49694 lines
2.9 MiB
49694 lines
2.9 MiB
; --------------------------------------------------------------------------------
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; @Title: STM32G0 On-Chip Peripherals
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; @Props: Released
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; @Author: STR, TRJ, KMB, DAB, PIW, KRZ, NEJ
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; @Changelog: 2018-07-11 STR
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; 2019-10-04 TRJ
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; 2021-08-12 KMB
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; 2022-01-28 DAB
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; 2022-02-17 PIW
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; 2022-06-28 KRZ
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; 2024-01-18 NEJ
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; @Manufacturer: STM - ST Microelectronics N.V.
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; @Doc: Generated (TRACE32, build: 166062.), based on:
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; STM32G030.svd (Ver. 1.5), STM32G031.svd (Ver. 1.5),
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; STM32G041.svd (Ver. 1.4), STM32G050.svd (Ver. 1.2),
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; STM32G051.svd (Ver. 1.3), STM32G061.svd (Ver. 1.3),
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; STM32G070.svd (Ver. 1.8), STM32G071.svd (Ver. 2.4),
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; STM32G081.svd (Ver. 1.7), STM32G0B0.svd (Ver. 1.5),
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; STM32G0B1.svd (Ver. 1.7), STM32G0C1.svd (Ver. 1.7)
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; @Core: Cortex-M0+
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; @Chip: STM32G030C6, STM32G030C8, STM32G030F6, STM32G030J6,
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; STM32G030K6, STM32G030K8, STM32G031C4, STM32G031C6,
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; STM32G031C8, STM32G031F4, STM32G031F6, STM32G031F8,
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; STM32G031G4, STM32G031G6, STM32G031G8, STM32G031J4,
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; STM32G031J6, STM32G031K4, STM32G031K6, STM32G031K8,
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; STM32G031Y8, STM32G041C6, STM32G041C8, STM32G041F6,
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; STM32G041F8, STM32G041G6, STM32G041G8, STM32G041J6,
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; STM32G041K6, STM32G041K8, STM32G050C6, STM32G050C8,
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; STM32G050F6, STM32G050K6, STM32G050K8, STM32G051C6,
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; STM32G051C8, STM32G051F6, STM32G051F8, STM32G051G6,
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; STM32G051G8, STM32G051K6, STM32G051K8, STM32G061C6,
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; STM32G061C8, STM32G061F6, STM32G061F8, STM32G061G6,
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; STM32G061G8, STM32G061K6, STM32G061K8, STM32G070CB,
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; STM32G070KB, STM32G070RB, STM32G071C8, STM32G071CB,
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; STM32G071EB, STM32G071G8, STM32G071GB, STM32G071K8,
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; STM32G071KB, STM32G071R8, STM32G071RB, STM32G081C8,
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; STM32G081CB, STM32G081EB, STM32G081G8, STM32G081GB,
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; STM32G081K8, STM32G081KB, STM32G081R8, STM32G081RB,
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; STM32G0B0CE, STM32G0B0KE, STM32G0B0RE, STM32G0B0VE,
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; STM32G0B1CB, STM32G0B1CC, STM32G0B1CE, STM32G0B1KB,
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; STM32G0B1KC, STM32G0B1KC, STM32G0B1KE, STM32G0B1MB,
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; STM32G0B1MC, STM32G0B1ME, STM32G0B1RB, STM32G0B1RC,
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; STM32G0B1RE, STM32G0B1VB, STM32G0B1VC, STM32G0B1VE,
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; STM32G0C1CC, STM32G0C1CE, STM32G0C1KC, STM32G0C1KE,
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; STM32G0C1MC, STM32G0C1ME, STM32G0C1RC, STM32G0C1RE,
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; STM32G0C1VC, STM32G0C1VE
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perstm32g0.per 17390 2024-01-25 14:08:42Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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|
hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40012400
|
|
sif (cpuis("STM32G030*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
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|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELR_0,ADC channel selection register [alternate]"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ISR,ADC interrupt and status"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready" "0,1"
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1"
|
|
bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1"
|
|
bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1"
|
|
line.long 0x4 "IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt" "0,1"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1"
|
|
line.long 0x8 "CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1"
|
|
bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADC enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ISR,ADC interrupt and status"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready" "0,1"
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,ADC analog watchdog 3 flag" "0,1"
|
|
bitfld.long 0x0 8. "AWD2,ADC analog watchdog 2 flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,ADC analog watchdog 1 flag" "0,1"
|
|
bitfld.long 0x0 4. "OVR,ADC group regular overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,ADC group regular end of sequence" "0,1"
|
|
bitfld.long 0x0 2. "EOC,ADC group regular end of unitary" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,ADC group regular end of sampling" "0,1"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready flag" "0,1"
|
|
line.long 0x4 "IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt" "0,1"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,ADC analog watchdog 3" "0,1"
|
|
bitfld.long 0x4 8. "AWD2IE,ADC analog watchdog 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,ADC analog watchdog 1" "0,1"
|
|
bitfld.long 0x4 4. "OVRIE,ADC group regular overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,ADC group regular end of sequence" "0,1"
|
|
bitfld.long 0x4 2. "EOCIE,ADC group regular end of unitary" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,ADC group regular end of sampling" "0,1"
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt" "0,1"
|
|
line.long 0x8 "CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0,1"
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC voltage regulator" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC group regular conversion" "0,1"
|
|
bitfld.long 0x8 2. "ADSTART,ADC group regular conversion" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable" "0,1"
|
|
bitfld.long 0x8 0. "ADEN,ADC enable" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SMPR,ADC sampling time register"
|
|
hexmask.long.tbyte 0x0 8.--26. 1. "SMPSEL,Channel sampling time"
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "AWD1TR,watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold"
|
|
line.long 0x4 "AWD2TR,watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,ADC analog watchdog 2 threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,ADC analog watchdog 2 threshold"
|
|
line.long 0x8 "CHSELR,channel selection register"
|
|
hexmask.long.tbyte 0x8 0.--18. 1. "CHSEL,Channel-x selection"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELR_0,ADC channel selection register [alternate]"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
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bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
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|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELR_0,ADC channel selection register [alternate]"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELRMOD0,ADC channel selection register"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELR_0,ADC channel selection register [alternate]"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELR,ADC channel selection register [alternate]"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "ADC_ISR,ADC interrupt and status register"
|
|
bitfld.long 0x0 13. "CCRDY,Channel Configuration Ready flag" "0: Channel configuration update not applied.,1: Channel configuration update is applied."
|
|
bitfld.long 0x0 11. "EOCAL,End Of Calibration flag" "0: Calibration is not complete,1: Calibration is complete"
|
|
newline
|
|
bitfld.long 0x0 9. "AWD3,Analog watchdog 3 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 8. "AWD2,Analog watchdog 2 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
newline
|
|
bitfld.long 0x0 7. "AWD1,Analog watchdog 1 flag" "0: No analog watchdog event occurred (or the flag..,1: Analog watchdog event occurred"
|
|
bitfld.long 0x0 4. "OVR,ADC overrun" "0: No overrun occurred (or the flag event was..,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "EOS,End of sequence flag" "0: Conversion sequence not complete (or the flag..,1: Conversion sequence complete"
|
|
bitfld.long 0x0 2. "EOC,End of conversion flag" "0: Channel conversion not complete (or the flag..,1: Channel conversion complete"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSMP,End of sampling flag" "0: Not at the end of the sampling phase (or the..,1: End of sampling phase reached"
|
|
bitfld.long 0x0 0. "ADRDY,ADC ready" "0: ADC not yet ready to start conversion (or the..,1: ADC is ready to start conversion"
|
|
line.long 0x4 "ADC_IER,ADC interrupt enable register"
|
|
bitfld.long 0x4 13. "CCRDYIE,Channel Configuration Ready Interrupt enable" "0: Channel configuration ready interrupt disabled,1: Channel configuration ready interrupt enabled"
|
|
bitfld.long 0x4 11. "EOCALIE,End of calibration interrupt enable" "0: End of calibration interrupt disabled,1: End of calibration interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "AWD3IE,Analog watchdog 3 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 8. "AWD2IE,Analog watchdog 2 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "AWD1IE,Analog watchdog 1 interrupt enable" "0: Analog watchdog interrupt disabled,1: Analog watchdog interrupt enabled"
|
|
bitfld.long 0x4 4. "OVRIE,Overrun interrupt enable" "0: Overrun interrupt disabled,1: Overrun interrupt enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x4 3. "EOSIE,End of conversion sequence interrupt enable" "0: EOS interrupt disabled,1: EOS interrupt enabled. An interrupt is generated.."
|
|
bitfld.long 0x4 2. "EOCIE,End of conversion interrupt enable" "0: EOC interrupt disabled,1: EOC interrupt enabled. An interrupt is generated.."
|
|
newline
|
|
bitfld.long 0x4 1. "EOSMPIE,End of sampling flag interrupt enable" "0: EOSMP interrupt disabled.,1: EOSMP interrupt enabled. An interrupt is.."
|
|
bitfld.long 0x4 0. "ADRDYIE,ADC ready interrupt enable" "0: ADRDY interrupt disabled.,1: ADRDY interrupt enabled. An interrupt is.."
|
|
line.long 0x8 "ADC_CR,ADC control register"
|
|
bitfld.long 0x8 31. "ADCAL,ADC calibration" "0: Calibration complete,1: Write 1 to calibrate the ADC. Read at 1 means.."
|
|
bitfld.long 0x8 28. "ADVREGEN,ADC Voltage Regulator Enable" "0: ADC voltage regulator disabled,1: ADC voltage regulator enabled"
|
|
newline
|
|
bitfld.long 0x8 4. "ADSTP,ADC stop conversion command" "0: No ADC stop conversion command ongoing,1: Write 1 to stop the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 2. "ADSTART,ADC start conversion command" "0: No ADC conversion is ongoing.,1: Write 1 to start the ADC. Read 1 means that the.."
|
|
newline
|
|
bitfld.long 0x8 1. "ADDIS,ADC disable command" "0: No ADDIS command ongoing,1: Write 1 to disable the ADC. Read 1 means that an.."
|
|
bitfld.long 0x8 0. "ADEN,ADC enable command" "0: ADC is disabled (OFF state),1: Write 1 to enable the ADC."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ADC_SMPR,ADC sampling time register"
|
|
bitfld.long 0x0 26. "SMPSEL18,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 25. "SMPSEL17,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 24. "SMPSEL16,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 23. "SMPSEL15,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 22. "SMPSEL14,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 21. "SMPSEL13,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 20. "SMPSEL12,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 19. "SMPSEL11,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 18. "SMPSEL10,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 17. "SMPSEL9,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 16. "SMPSEL8,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 15. "SMPSEL7,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 14. "SMPSEL6,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 13. "SMPSEL5,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 12. "SMPSEL4,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 11. "SMPSEL3,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 10. "SMPSEL2,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 9. "SMPSEL1,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
newline
|
|
bitfld.long 0x0 8. "SMPSEL0,Channel-x sampling time selection" "0: Sampling time of CHANNELx use the setting of..,1: Sampling time of CHANNELx use the setting of.."
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection 2" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection 1" "0: 1.5 ADC clock cycles,1: 3.5 ADC clock cycles,2: 7.5 ADC clock cycles,3: 12.5 ADC clock cycles,4: 19.5 ADC clock cycles,5: 39.5 ADC clock cycles,6: 79.5 ADC clock cycles,7: 160.5 ADC clock cycles"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "ADC_AWD1TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,Analog watchdog 1 higher threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,Analog watchdog 1 lower threshold"
|
|
line.long 0x4 "ADC_AWD2TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,Analog watchdog 2 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,Analog watchdog 2 lower threshold"
|
|
line.long 0x8 "ADC_CHSELR,ADC channel selection register [alternate]"
|
|
bitfld.long 0x8 18. "CHSEL18,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 17. "CHSEL17,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 16. "CHSEL16,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 15. "CHSEL15,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 14. "CHSEL14,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 13. "CHSEL13,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 12. "CHSEL12,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 11. "CHSEL11,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 10. "CHSEL10,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 9. "CHSEL9,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 8. "CHSEL8,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 7. "CHSEL7,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 6. "CHSEL6,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 5. "CHSEL5,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 4. "CHSEL4,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 3. "CHSEL3,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 2. "CHSEL2,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
bitfld.long 0x8 1. "CHSEL1,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
newline
|
|
bitfld.long 0x8 0. "CHSEL0,Channel-x selection" "0: Input Channel-x is not selected for conversion,1: Input Channel-x is selected for conversion"
|
|
endif
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "ADC_CFGR1,ADC configuration register 1"
|
|
sif (cpuis("STM32G030*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWDCH1CH,ADC analog watchdog 1 monitored channel"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x0 26.--30. 1. "AWD1CH,Analog watchdog channel selection"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 23. "AWD1EN,ADC analog watchdog 1 enable on scope" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
newline
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
newline
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
newline
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
newline
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 23. "AWD1EN,Analog watchdog enable" "0: Analog watchdog 1 disabled,1: Analog watchdog 1 enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "AWD1SGL,Enable the watchdog on a single channel or on all channels" "0: Analog watchdog 1 enabled on all channels,1: Analog watchdog 1 enabled on a single channel"
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR register" "0: Each bit of the ADC_CHSELR register enables an..,1: ADC_CHSELR register is able to sequence up to 8.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 22. "AWD1SGL,ADC analog watchdog 1 monitoring a" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 21. "CHSELRMOD,Mode selection of the ADC_CHSELR" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "DISCEN,ADC group regular sequencer" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
newline
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 16. "DISCEN,Discontinuous mode" "0: Discontinuous mode disabled,1: Discontinuous mode enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0: Auto-off mode disabled,1: Auto-off mode enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0: Wait conversion mode off,1: Wait conversion mode on"
|
|
bitfld.long 0x0 13. "CONT,Single / continuous conversion mode" "0: Single conversion mode,1: Continuous conversion mode"
|
|
newline
|
|
bitfld.long 0x0 12. "OVRMOD,Overrun management mode" "0: ADC_DR register is preserved with the old data..,1: ADC_DR register is overwritten with the last.."
|
|
bitfld.long 0x0 10.--11. "EXTEN,External trigger enable and polarity selection" "0: Hardware trigger detection disabled (conversions..,1: Hardware trigger detection on the rising edge,2: Hardware trigger detection on the falling edge,3: Hardware trigger detection on both the rising.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 15. "AUTOFF,Auto-off mode" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 14. "WAIT,Wait conversion mode" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 13. "CONT,ADC group regular continuous conversion" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 12. "OVRMOD,ADC group regular overrun" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 10.--11. "EXTEN,ADC group regular external trigger" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,ADC group regular external trigger" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,ADC group regular external trigger" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
newline
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
newline
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
newline
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 6.--8. "EXTSEL,External trigger selection" "0: TRG0,1: TRG1,2: TRG2,3: TRG3,4: TRG4,5: TRG5,6: TRG6,7: TRG7"
|
|
bitfld.long 0x0 5. "ALIGN,Data alignment" "0: Right alignment,1: Left alignment"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "RES,Data resolution" "0: 12 bits,1: 10 bits,2: 8 bits,3: 6 bits"
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0: Upward scan (from CHSEL0 to CHSEL18),1: Backward scan (from CHSEL18 to CHSEL0)"
|
|
newline
|
|
bitfld.long 0x0 1. "DMACFG,Direct memory access configuration" "0: DMA one shot mode selected,1: DMA circular mode selected"
|
|
bitfld.long 0x0 0. "DMAEN,Direct memory access enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 5. "ALIGN,ADC data alignement" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 3.--4. "RES,ADC data resolution" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 2. "SCANDIR,Scan sequence direction" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 1. "DMACFG,ADC DMA transfer" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 0. "DMAEN,ADC DMA transfer enable" "0,1"
|
|
endif
|
|
line.long 0x4 "ADC_CFGR2,ADC configuration register 2"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
newline
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 30.--31. "CKMODE,ADC clock mode" "0: ADCCLK (Asynchronous clock mode) generated at..,1: PCLK/2 (Synchronous clock mode),2: PCLK/4 (Synchronous clock mode),3: PCLK (Synchronous clock mode). This.."
|
|
newline
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode enable" "0: Low Frequency Trigger Mode disabled,1: Low Frequency Trigger Mode enabled"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 29. "LFTRIG,Low frequency trigger mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 9. "TOVS,ADC oversampling discontinuous mode" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "TOVS,ADC oversampling discontinuous mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 9. "TOVS,Triggered Oversampling" "0: All oversampled conversions for a channel are..,1: Each oversampled conversion for a channel needs.."
|
|
newline
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,Oversampling shift"
|
|
bitfld.long 0x4 2.--4. "OVSR,Oversampling ratio" "0: 2x,1: 4x,2: 8x,3: 16x,4: 32x,5: 64x,6: 128x,7: 256x"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 5.--8. 1. "OVSS,ADC oversampling shift"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 2.--4. "OVSR,ADC oversampling ratio" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 0. "OVSE,ADC oversampler enable on scope ADC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 0. "OVSE,ADC oversampler enable on scope ADC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 0. "OVSE,Oversampler Enable" "0: Oversampler disabled,1: Oversampler enabled"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "SMPR,ADC sampling time register"
|
|
hexmask.long.tbyte 0x0 8.--26. 1. "SMPSEL,Channel sampling time"
|
|
bitfld.long 0x0 4.--6. "SMP2,Sampling time selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SMP1,Sampling time selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "AWD1TR,watchdog threshold register"
|
|
hexmask.long.word 0x0 16.--27. 1. "HT1,ADC analog watchdog 1 threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "LT1,ADC analog watchdog 1 threshold"
|
|
line.long 0x4 "AWD2TR,watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT2,ADC analog watchdog 2 threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT2,ADC analog watchdog 2 threshold"
|
|
line.long 0x8 "CHSELR,channel selection register"
|
|
hexmask.long.tbyte 0x8 0.--18. 1. "CHSEL,Channel-x selection"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,conversion of the sequence"
|
|
line.long 0x4 "AWD3TR,watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,ADC analog watchdog 3 threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,ADC analog watchdog 3 threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data"
|
|
hexmask.long.word 0x0 0.--15. 1. "regularDATA,ADC group regular conversion"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "CALFACT,ADC calibration factors"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,ADC calibration factor in single-ended"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "CCR,ADC common control register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,conversion of the sequence"
|
|
line.long 0x4 "AWD3TR,watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,ADC analog watchdog 3 threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,ADC analog watchdog 3 threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "DR,ADC group regular conversion data"
|
|
hexmask.long.word 0x0 0.--15. 1. "regularDATA,ADC group regular conversion"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "AWD2CR,ADC analog watchdog 2 configuration"
|
|
hexmask.long.tbyte 0x0 0.--18. 1. "AWD2CH,ADC analog watchdog 2 monitored channel"
|
|
line.long 0x4 "AWD3CR,ADC analog watchdog 3 configuration"
|
|
hexmask.long.tbyte 0x4 0.--18. 1. "AWD3CH,ADC analog watchdog 3 monitored channel"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "CALFACT,ADC calibration factors"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,ADC calibration factor in single-ended"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "CCR,ADC common control register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0,1"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0,1"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled DAC_OUT2 connected to ADC..,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled DAC_OUT1 connected..,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled DAC_OUT2 connected to ADC..,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled DAC_OUT1 connected..,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled DAC_OUT2 connected to ADC..,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled DAC_OUT1 connected..,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELRMOD1,ADC channel selection register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled DAC_OUT2 connected to ADC..,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled DAC_OUT1 connected..,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "ADC_CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled DAC_OUT2 connected to ADC..,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled DAC_OUT1 connected..,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "CHSELR_1,channel selection register CHSELRMOD = 1 in"
|
|
hexmask.long.byte 0x0 28.--31. 1. "SQ8,8th conversion of the sequence"
|
|
hexmask.long.byte 0x0 24.--27. 1. "SQ7,7th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SQ6,6th conversion of the sequence"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SQ5,5th conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "SQ4,4th conversion of the sequence"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SQ3,3rd conversion of the sequence"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "SQ2,2nd conversion of the sequence"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SQ1,1st conversion of the sequence"
|
|
line.long 0x4 "ADC_AWD3TR,ADC watchdog threshold register"
|
|
hexmask.long.word 0x4 16.--27. 1. "HT3,Analog watchdog 3 higher threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "LT3,Analog watchdog 3lower threshold"
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x0 "ADC_DR,ADC data register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted data"
|
|
group.long 0xA0++0x7
|
|
line.long 0x0 "ADC_AWD2CR,ADC Analog Watchdog 2 Configuration register"
|
|
bitfld.long 0x0 18. "AWD2CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 17. "AWD2CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 16. "AWD2CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 15. "AWD2CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 14. "AWD2CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 13. "AWD2CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 12. "AWD2CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 11. "AWD2CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 10. "AWD2CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 9. "AWD2CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 8. "AWD2CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 7. "AWD2CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 6. "AWD2CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 5. "AWD2CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 4. "AWD2CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 3. "AWD2CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 2. "AWD2CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
bitfld.long 0x0 1. "AWD2CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
newline
|
|
bitfld.long 0x0 0. "AWD2CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD2,1: ADC analog channel-x is monitored by AWD2"
|
|
line.long 0x4 "ADC_AWD3CR,ADC Analog Watchdog 3 Configuration register"
|
|
bitfld.long 0x4 18. "AWD3CH18,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 17. "AWD3CH17,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 16. "AWD3CH16,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 15. "AWD3CH15,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 14. "AWD3CH14,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 13. "AWD3CH13,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 12. "AWD3CH12,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 11. "AWD3CH11,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 10. "AWD3CH10,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 9. "AWD3CH9,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 8. "AWD3CH8,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 7. "AWD3CH7,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 6. "AWD3CH6,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 5. "AWD3CH5,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 4. "AWD3CH4,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 3. "AWD3CH3,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 2. "AWD3CH2,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
bitfld.long 0x4 1. "AWD3CH1,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
newline
|
|
bitfld.long 0x4 0. "AWD3CH0,Analog watchdog channel selection" "0: ADC analog channel-x is not monitored by AWD3,1: ADC analog channel-x is monitored by AWD3"
|
|
group.long 0xB4++0x3
|
|
line.long 0x0 "ADC_CALFACT,ADC Calibration factor"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CALFACT,Calibration factor"
|
|
group.long 0x308++0x3
|
|
line.long 0x0 "ADC_CCR,ADC common configuration register"
|
|
bitfld.long 0x0 24. "VBATEN,VBAT enable" "0: VBAT channel disabled DAC_OUT2 connected to ADC..,1: VBAT channel enabled"
|
|
bitfld.long 0x0 23. "TSEN,Temperature sensor enable" "0: Temperature sensor disabled DAC_OUT1 connected..,1: Temperature sensor enabled"
|
|
newline
|
|
bitfld.long 0x0 22. "VREFEN,VREFINT enable" "0: VREFINT disabled,1: VREFINT enabled"
|
|
hexmask.long.byte 0x0 18.--21. 1. "PRESC,ADC prescaler"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G041*")||cpuis("STM32G061*")||cpuis("STM32G081*")||cpuis("STM32G0C1*"))
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0x40026000
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key"
|
|
line.long 0x10 "IVR0,initialization vector register"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR"
|
|
line.long 0x14 "IVR1,initialization vector register"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR"
|
|
line.long 0x18 "IVR2,initialization vector register"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR"
|
|
line.long 0x1C "IVR3,initialization vector register"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AES_CR,AES control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128,1: 256"
|
|
newline
|
|
bitfld.long 0x0 16. "CHMOD2,Chaining mode selection bit [2]" "0: Electronic codebook (ECB),1: Cipher-Block Chaining (CBC)"
|
|
bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Init phase,1: Header phase,2: Payload phase,3: Final phase"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0: Disable (mask),1: Enable"
|
|
bitfld.long 0x0 9. "CCFIE,CCF interrupt enable" "0: Disable (mask),1: Enable"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error flag clear" "0: No effect,1: Clear RDERR and WRERR flags"
|
|
bitfld.long 0x0 7. "CCFC,Computation complete flag clear" "0: No effect,1: Clear CCF"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "CHMOD1,Chaining mode selection bit [2]" "0: Electronic codebook (ECB),1: Cipher-Block Chaining (CBC),2: Counter Mode (CTR),3: Galois Counter Mode (GCM) and Galois Message.."
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0: Mode 1: encryption,1: Mode 2: key derivation (or key preparation for..,2: Mode 3: decryption,3: Mode 4: key derivation then single decryption"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection" "0: None,1: Half-word (16-bit),2: Byte (8-bit),3: Bit"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "AES_SR,AES control register"
|
|
bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy"
|
|
bitfld.long 0x0 2. "WRERR,Write error" "0: Not detected,1: Detected"
|
|
newline
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0: Not detected,1: Detected"
|
|
bitfld.long 0x0 0. "CCF,Computation completed flag" "0: Not completed,1: Completed"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "AES_DINR,AES data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DIN,Input data word"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "AES_DOUTR,AES data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DOUT,Output data word"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "AES_KEYR0,AES key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]"
|
|
line.long 0x4 "AES_KEYR1,AES key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]"
|
|
line.long 0x8 "AES_KEYR2,AES key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]"
|
|
line.long 0xC "AES_KEYR3,AES key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]"
|
|
line.long 0x10 "AES_IVR0,AES initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "IVI,Initialization vector input bits [31:0]"
|
|
line.long 0x14 "AES_IVR1,AES initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "IVI,Initialization vector input bits [63:32]"
|
|
line.long 0x18 "AES_IVR2,AES initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "IVI,Initialization vector input bits [95:64]"
|
|
line.long 0x1C "AES_IVR3,AES initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "IVI,Initialization vector input bits [127:96]"
|
|
line.long 0x20 "AES_KEYR4,AES key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "KEY,Cryptographic key bits [159:128]"
|
|
line.long 0x24 "AES_KEYR5,AES key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "KEY,Cryptographic key bits [191:160]"
|
|
line.long 0x28 "AES_KEYR6,AES key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "KEY,Cryptographic key bits [223:192]"
|
|
line.long 0x2C "AES_KEYR7,AES key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "KEY,Cryptographic key bits [255:224]"
|
|
line.long 0x30 "AES_SUSP0R,AES suspend registers"
|
|
hexmask.long 0x30 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x34 "AES_SUSP1R,AES suspend registers"
|
|
hexmask.long 0x34 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x38 "AES_SUSP2R,AES suspend registers"
|
|
hexmask.long 0x38 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x3C "AES_SUSP3R,AES suspend registers"
|
|
hexmask.long 0x3C 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x40 "AES_SUSP4R,AES suspend registers"
|
|
hexmask.long 0x40 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x44 "AES_SUSP5R,AES suspend registers"
|
|
hexmask.long 0x44 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x48 "AES_SUSP6R,AES suspend registers"
|
|
hexmask.long 0x48 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x4C "AES_SUSP7R,AES suspend registers"
|
|
hexmask.long 0x4C 0.--31. 1. "SUSP,AES suspend"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR,control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block of"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CHMOD2,AES chaining mode Bit2" "0,1"
|
|
bitfld.long 0x0 13.--14. "GCMPH,Used only for GCM CCM and GMAC" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAOUTEN,Enable DMA management of data output" "0,1"
|
|
bitfld.long 0x0 11. "DMAINEN,Enable DMA management of data input" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x0 9. "CCFIE,CCF flag interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error clear" "0,1"
|
|
bitfld.long 0x0 7. "CCFC,Computation Complete Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "CHMOD10,AES chaining mode Bit1" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection (for data in and" "0,1,2,3"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy flag" "0,1"
|
|
bitfld.long 0x0 2. "WRERR,Write error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0,1"
|
|
bitfld.long 0x0 0. "CCF,Computation complete flag" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "DINR,data input register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DINR,Data Input Register"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "DOUTR,data output register"
|
|
hexmask.long 0x0 0.--31. 1. "AES_DOUTR,Data output register"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "KEYR0,key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "AES_KEYR0,Data Output Register (LSB key"
|
|
line.long 0x4 "KEYR1,key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "AES_KEYR1,AES key register (key"
|
|
line.long 0x8 "KEYR2,key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "AES_KEYR2,AES key register (key"
|
|
line.long 0xC "KEYR3,key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "AES_KEYR3,AES key register (MSB key"
|
|
line.long 0x10 "IVR0,initialization vector register"
|
|
hexmask.long 0x10 0.--31. 1. "AES_IVR0,initialization vector register (LSB IVR"
|
|
line.long 0x14 "IVR1,initialization vector register"
|
|
hexmask.long 0x14 0.--31. 1. "AES_IVR1,Initialization Vector Register (IVR"
|
|
line.long 0x18 "IVR2,initialization vector register"
|
|
hexmask.long 0x18 0.--31. 1. "AES_IVR2,Initialization Vector Register (IVR"
|
|
line.long 0x1C "IVR3,initialization vector register"
|
|
hexmask.long 0x1C 0.--31. 1. "AES_IVR3,Initialization Vector Register (MSB IVR"
|
|
line.long 0x20 "KEYR4,key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "AES_KEYR4,AES key register (MSB key"
|
|
line.long 0x24 "KEYR5,key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "AES_KEYR5,AES key register (MSB key"
|
|
line.long 0x28 "KEYR6,key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "AES_KEYR6,AES key register (MSB key"
|
|
line.long 0x2C "KEYR7,key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "AES_KEYR7,AES key register (MSB key"
|
|
line.long 0x30 "SUSP0R,AES suspend register 0"
|
|
hexmask.long 0x30 0.--31. 1. "AES_SUSP0R,AES suspend register 0"
|
|
line.long 0x34 "SUSP1R,AES suspend register 1"
|
|
hexmask.long 0x34 0.--31. 1. "AES_SUSP1R,AES suspend register 1"
|
|
line.long 0x38 "SUSP2R,AES suspend register 2"
|
|
hexmask.long 0x38 0.--31. 1. "AES_SUSP2R,AES suspend register 2"
|
|
line.long 0x3C "SUSP3R,AES suspend register 3"
|
|
hexmask.long 0x3C 0.--31. 1. "AES_SUSP3R,AES suspend register 3"
|
|
line.long 0x40 "SUSP4R,AES suspend register 4"
|
|
hexmask.long 0x40 0.--31. 1. "AES_SUSP4R,AES suspend register 4"
|
|
line.long 0x44 "SUSP5R,AES suspend register 5"
|
|
hexmask.long 0x44 0.--31. 1. "AES_SUSP5R,AES suspend register 5"
|
|
line.long 0x48 "SUSP6R,AES suspend register 6"
|
|
hexmask.long 0x48 0.--31. 1. "AES_SUSP6R,AES suspend register 6"
|
|
line.long 0x4C "SUSP7R,AES suspend register 7"
|
|
hexmask.long 0x4C 0.--31. 1. "AES_SUSP7R,AES suspend register 7"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFR,AES hardware configuration"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CFG4,HW Generic 4"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CFG3,HW Generic 3"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,HW Generic 2"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,HW Generic 1"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "AES_CR,AES control register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "NPBLB,Number of padding bytes in last block"
|
|
bitfld.long 0x0 18. "KEYSIZE,Key size selection" "0: 128,1: 256"
|
|
newline
|
|
bitfld.long 0x0 16. "CHMOD2,Chaining mode selection bit [2]" "0: Electronic codebook (ECB),1: Cipher-Block Chaining (CBC)"
|
|
bitfld.long 0x0 13.--14. "GCMPH,GCM or CCM phase selection" "0: Init phase,1: Header phase,2: Payload phase,3: Final phase"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAOUTEN,DMA output enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 11. "DMAINEN,DMA input enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 10. "ERRIE,Error interrupt enable" "0: Disable (mask),1: Enable"
|
|
bitfld.long 0x0 9. "CCFIE,CCF interrupt enable" "0: Disable (mask),1: Enable"
|
|
newline
|
|
bitfld.long 0x0 8. "ERRC,Error flag clear" "0: No effect,1: Clear RDERR and WRERR flags"
|
|
bitfld.long 0x0 7. "CCFC,Computation complete flag clear" "0: No effect,1: Clear CCF"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "CHMOD1,Chaining mode selection bit [2]" "0: Electronic codebook (ECB),1: Cipher-Block Chaining (CBC),2: Counter Mode (CTR),3: Galois Counter Mode (GCM) and Galois Message.."
|
|
bitfld.long 0x0 3.--4. "MODE,AES operating mode" "0: Mode 1: encryption,1: Mode 2: key derivation (or key preparation for..,2: Mode 3: decryption,3: Mode 4: key derivation then single decryption"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATATYPE,Data type selection" "0: None,1: Half-word (16-bit),2: Byte (8-bit),3: Bit"
|
|
bitfld.long 0x0 0. "EN,AES enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "AES_SR,AES status register"
|
|
bitfld.long 0x0 3. "BUSY,Busy" "0: Idle,1: Busy"
|
|
bitfld.long 0x0 2. "WRERR,Write error" "0: Not detected,1: Detected"
|
|
newline
|
|
bitfld.long 0x0 1. "RDERR,Read error flag" "0: Not detected,1: Detected"
|
|
bitfld.long 0x0 0. "CCF,Computation completed flag" "0: Not completed,1: Completed"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "AES_DINR,AES data input register"
|
|
hexmask.long 0x0 0.--31. 1. "DIN,Input data word"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "AES_DOUTR,AES data output register"
|
|
hexmask.long 0x0 0.--31. 1. "DOUT,Output data word"
|
|
group.long 0x10++0x4F
|
|
line.long 0x0 "AES_KEYR0,AES key register 0"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Cryptographic key bits [31:0]"
|
|
line.long 0x4 "AES_KEYR1,AES key register 1"
|
|
hexmask.long 0x4 0.--31. 1. "KEY,Cryptographic key bits [63:32]"
|
|
line.long 0x8 "AES_KEYR2,AES key register 2"
|
|
hexmask.long 0x8 0.--31. 1. "KEY,Cryptographic key bits [95:64]"
|
|
line.long 0xC "AES_KEYR3,AES key register 3"
|
|
hexmask.long 0xC 0.--31. 1. "KEY,Cryptographic key bits [127:96]"
|
|
line.long 0x10 "AES_IVR0,AES initialization vector register 0"
|
|
hexmask.long 0x10 0.--31. 1. "IVI,Initialization vector input bits [31:0]"
|
|
line.long 0x14 "AES_IVR1,AES initialization vector register 1"
|
|
hexmask.long 0x14 0.--31. 1. "IVI,Initialization vector input bits [63:32]"
|
|
line.long 0x18 "AES_IVR2,AES initialization vector register 2"
|
|
hexmask.long 0x18 0.--31. 1. "IVI,Initialization vector input bits [95:64]"
|
|
line.long 0x1C "AES_IVR3,AES initialization vector register 3"
|
|
hexmask.long 0x1C 0.--31. 1. "IVI,Initialization vector input bits [127:96]"
|
|
line.long 0x20 "AES_KEYR4,AES key register 4"
|
|
hexmask.long 0x20 0.--31. 1. "KEY,Cryptographic key bits [159:128]"
|
|
line.long 0x24 "AES_KEYR5,AES key register 5"
|
|
hexmask.long 0x24 0.--31. 1. "KEY,Cryptographic key bits [191:160]"
|
|
line.long 0x28 "AES_KEYR6,AES key register 6"
|
|
hexmask.long 0x28 0.--31. 1. "KEY,Cryptographic key bits [223:192]"
|
|
line.long 0x2C "AES_KEYR7,AES key register 7"
|
|
hexmask.long 0x2C 0.--31. 1. "KEY,Cryptographic key bits [255:224]"
|
|
line.long 0x30 "AES_SUSP0R,AES suspend registers"
|
|
hexmask.long 0x30 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x34 "AES_SUSP1R,AES suspend registers"
|
|
hexmask.long 0x34 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x38 "AES_SUSP2R,AES suspend registers"
|
|
hexmask.long 0x38 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x3C "AES_SUSP3R,AES suspend registers"
|
|
hexmask.long 0x3C 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x40 "AES_SUSP4R,AES suspend registers"
|
|
hexmask.long 0x40 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x44 "AES_SUSP5R,AES suspend registers"
|
|
hexmask.long 0x44 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x48 "AES_SUSP6R,AES suspend registers"
|
|
hexmask.long 0x48 0.--31. 1. "SUSP,AES suspend"
|
|
line.long 0x4C "AES_SUSP7R,AES suspend registers"
|
|
hexmask.long 0x4C 0.--31. 1. "SUSP,AES suspend"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "CEC (HDMI-CEC Controller)"
|
|
base ad:0x40007800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CEC_CR,CEC control register"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x0 2. "TXEOM,Tx end of message" "0: TXDR data byte is transmitted with EOM = 0,1: TXDR data byte is transmitted with EOM = 1"
|
|
bitfld.long 0x0 1. "TXSOM,Tx start of message" "0: No CEC transmission is on-going,1: CEC transmission command"
|
|
newline
|
|
bitfld.long 0x0 0. "CECEN,CEC enable" "0: CEC peripheral is off.,1: CEC peripheral is on."
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1"
|
|
bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 2. "TXEOM,Tx End Of Message The TXEOM bit is set" "0,1"
|
|
bitfld.long 0x0 1. "TXSOM,Tx Start Of Message TXSOM is set by" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CECEN,CEC Enable The CECEN bit is set and" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 2. "TXEOM,Tx end of message" "0: TXDR data byte is transmitted with EOM = 0,1: TXDR data byte is transmitted with EOM = 1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXSOM,Tx start of message" "0: No CEC transmission is on-going,1: CEC transmission command"
|
|
bitfld.long 0x0 0. "CECEN,CEC enable" "0: CEC peripheral is off.,1: CEC peripheral is on."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 2. "TXEOM,Tx end of message" "0: TXDR data byte is transmitted with EOM = 0,1: TXDR data byte is transmitted with EOM = 1"
|
|
bitfld.long 0x0 1. "TXSOM,Tx start of message" "0: No CEC transmission is on-going,1: CEC transmission command"
|
|
newline
|
|
bitfld.long 0x0 0. "CECEN,CEC enable" "0: CEC peripheral is off.,1: CEC peripheral is on."
|
|
endif
|
|
line.long 0x4 "CEC_CFGR,This register is used to configure the"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x4 31. "LSTN,Listen mode" "0: CEC peripheral receives only message addressed..,1: CEC peripheral receives messages addressed to.."
|
|
bitfld.long 0x4 8. "SFTOP,SFT option bit" "0: SFT timer starts when TXSOM is set by software.,1: SFT timer starts automatically at the end of.."
|
|
newline
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid error-bit generation in broadcast" "0: BRE detection with BRESTP = 1 and BREGEN = 0 on..,1: Error-bit is not generated in the same condition.."
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate error-bit on long bit period error" "0: LBPE detection does not generate an error-bit on..,1: LBPE detection generates an error-bit on the CEC.."
|
|
newline
|
|
bitfld.long 0x4 5. "BREGEN,Generate error-bit on bit rising error" "0: BRE detection does not generate an error-bit on..,1: BRE detection generates an error-bit on the CEC.."
|
|
bitfld.long 0x4 4. "BRESTP,Rx-stop on bit rising error" "0: BRE detection does not stop reception of the CEC..,1: BRE detection stops message reception."
|
|
newline
|
|
bitfld.long 0x4 3. "RXTOL,Rx-tolerance" "0: Standard tolerance margin:,1: Extended tolerance"
|
|
bitfld.long 0x4 0.--2. "SFT,Signal free time" "?,1: 0.5 nominal data bit periods,2: 1.5 nominal data bit periods,3: 2.5 nominal data bit periods,4: 3.5 nominal data bit periods,5: 4.5 nominal data bit periods,6: 5.5 nominal data bit periods,7: 6.5 nominal data bit periods"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 31. "LSTN,Listen mode LSTN bit is set and cleared" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 31. "LSTN,Listen mode" "0: CEC peripheral receives only message addressed..,1: CEC peripheral receives messages addressed to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 31. "LSTN,Listen mode" "0: CEC peripheral receives only message addressed..,1: CEC peripheral receives messages addressed to.."
|
|
endif
|
|
hexmask.long.word 0x4 16.--30. 1. "OAR,Own addresses configuration"
|
|
newline
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1"
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1"
|
|
bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1"
|
|
bitfld.long 0x4 3. "RXTOL,Rx-Tolerance" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1"
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1"
|
|
bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1"
|
|
bitfld.long 0x4 3. "RXTOL,Rx-Tolerance" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 8. "SFTOPT,SFT Option Bit The SFTOPT bit is set and" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid Error-Bit Generation in Broadcast" "0,1"
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate Error-Bit on Long Bit Period" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BREGEN,Generate Error-Bit on Bit Rising Error" "0,1"
|
|
bitfld.long 0x4 4. "BRESTP,Rx-Stop on Bit Rising Error The BRESTP" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXTOL,Rx-Tolerance" "0,1"
|
|
bitfld.long 0x4 0.--2. "SFT,Signal Free Time SFT bits are set by" "?,1: 0,2: 1,3: 2,4: 3,5: 4,6: 5,7: 6"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 8. "SFTOP,SFT option bit" "0: SFT timer starts when TXSOM is set by software.,1: SFT timer starts automatically at the end of.."
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid error-bit generation in broadcast" "0: BRE detection with BRESTP = 1 and BREGEN = 0 on..,1: Error-bit is not generated in the same condition.."
|
|
newline
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate error-bit on long bit period error" "0: LBPE detection does not generate an error-bit on..,1: LBPE detection generates an error-bit on the CEC.."
|
|
bitfld.long 0x4 5. "BREGEN,Generate error-bit on bit rising error" "0: BRE detection does not generate an error-bit on..,1: BRE detection generates an error-bit on the CEC.."
|
|
newline
|
|
bitfld.long 0x4 4. "BRESTP,Rx-stop on bit rising error" "0: BRE detection does not stop reception of the CEC..,1: BRE detection stops message reception."
|
|
bitfld.long 0x4 3. "RXTOL,Rx-tolerance" "0: Standard tolerance margin:,1: Extended tolerance"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "SFT,Signal free time" "?,1: 0.5 nominal data bit periods,2: 1.5 nominal data bit periods,3: 2.5 nominal data bit periods,4: 3.5 nominal data bit periods,5: 4.5 nominal data bit periods,6: 5.5 nominal data bit periods,7: 6.5 nominal data bit periods"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 8. "SFTOP,SFT option bit" "0: SFT timer starts when TXSOM is set by software.,1: SFT timer starts automatically at the end of.."
|
|
newline
|
|
bitfld.long 0x4 7. "BRDNOGEN,Avoid error-bit generation in broadcast" "0: BRE detection with BRESTP = 1 and BREGEN = 0 on..,1: Error-bit is not generated in the same condition.."
|
|
bitfld.long 0x4 6. "LBPEGEN,Generate error-bit on long bit period error" "0: LBPE detection does not generate an error-bit on..,1: LBPE detection generates an error-bit on the CEC.."
|
|
newline
|
|
bitfld.long 0x4 5. "BREGEN,Generate error-bit on bit rising error" "0: BRE detection does not generate an error-bit on..,1: BRE detection generates an error-bit on the CEC.."
|
|
bitfld.long 0x4 4. "BRESTP,Rx-stop on bit rising error" "0: BRE detection does not stop reception of the CEC..,1: BRE detection stops message reception."
|
|
newline
|
|
bitfld.long 0x4 3. "RXTOL,Rx-tolerance" "0: Standard tolerance margin:,1: Extended tolerance"
|
|
bitfld.long 0x4 0.--2. "SFT,Signal free time" "?,1: 0.5 nominal data bit periods,2: 1.5 nominal data bit periods,3: 2.5 nominal data bit periods,4: 3.5 nominal data bit periods,5: 4.5 nominal data bit periods,6: 5.5 nominal data bit periods,7: 6.5 nominal data bit periods"
|
|
endif
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CEC_TXDR,CEC Tx data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXD,Tx Data register. TXD is a write-only"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CEC_RXDR,CEC Rx Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXD,Rx Data register. RXD is read-only and"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CEC_ISR,CEC Interrupt and Status"
|
|
bitfld.long 0x0 12. "TXACKE,Tx-Missing Acknowledge Error In" "0,1"
|
|
bitfld.long 0x0 11. "TXERR,Tx-Error In transmission mode TXERR is" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TXUDR,Tx-Buffer Underrun In transmission mode " "0,1"
|
|
bitfld.long 0x0 9. "TXEND,End of Transmission TXEND is set by" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXBR,Tx-Byte Request TXBR is set by hardware" "0,1"
|
|
bitfld.long 0x0 7. "ARBLST,Arbitration Lost ARBLST is set by" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXACKE,Rx-Missing Acknowledge In receive mode " "0,1"
|
|
bitfld.long 0x0 5. "LBPE,Rx-Long Bit Period Error LBPE is set by" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SBPE,Rx-Short Bit Period Error SBPE is set by" "0,1"
|
|
bitfld.long 0x0 3. "BRE,Rx-Bit Rising Error BRE is set by" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXOVR,Rx-Overrun RXOVR is set by hardware if" "0,1"
|
|
bitfld.long 0x0 1. "RXEND,End Of Reception RXEND is set by" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXBR,Rx-Byte Received The RXBR bit is set by" "0,1"
|
|
line.long 0x4 "CEC_IER,CEC interrupt enable register"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-missing acknowledge error interrupt enable" "0: TXACKE interrupt disabled,1: TXACKE interrupt enabled"
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-error interrupt enable" "0: TXERR interrupt disabled,1: TXERR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-underrun interrupt enable" "0: TXUDR interrupt disabled,1: TXUDR interrupt enabled"
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-end of message interrupt enable" "0: TXEND interrupt disabled,1: TXEND interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-byte request interrupt enable" "0: TXBR interrupt disabled,1: TXBR interrupt enabled"
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration lost interrupt enable" "0: ARBLST interrupt disabled,1: ARBLST interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-missing acknowledge error interrupt enable" "0: RXACKE interrupt disabled,1: RXACKE interrupt enabled"
|
|
bitfld.long 0x4 5. "LBPEIE,Long bit period error interrupt enable" "0: LBPE interrupt disabled,1: LBPE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "SBPEIE,Short bit period error interrupt enable" "0: SBPE interrupt disabled,1: SBPE interrupt enabled"
|
|
bitfld.long 0x4 3. "BREIE,Bit rising error interrupt enable" "0: BRE interrupt disabled,1: BRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-buffer overrun interrupt enable" "0: RXOVR interrupt disabled,1: RXOVR interrupt enabled"
|
|
bitfld.long 0x4 1. "RXENDIE,End of reception interrupt enable" "0: RXEND interrupt disabled,1: RXEND interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "RXBRIE,Rx-byte received interrupt enable" "0: RXBR interrupt disabled,1: RXBR interrupt enabled"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1"
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1"
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-Missing Acknowledge Error Interrupt" "0,1"
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-Error Interrupt Enable The TXERRIE" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-Underrun Interrupt Enable The TXUDRIE" "0,1"
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-End Of Message Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-Byte Request Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration Lost Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-Missing Acknowledge Error Interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBPEIE,Long Bit Period Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SBPEIE,Short Bit Period Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 3. "BREIE,Bit Rising Error Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-Buffer Overrun Interrupt Enable The" "0,1"
|
|
bitfld.long 0x4 1. "RXENDIE,End Of Reception Interrupt Enable The" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXBRIE,Rx-Byte Received Interrupt Enable The" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-missing acknowledge error interrupt enable" "0: TXACKE interrupt disabled,1: TXACKE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-error interrupt enable" "0: TXERR interrupt disabled,1: TXERR interrupt enabled"
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-underrun interrupt enable" "0: TXUDR interrupt disabled,1: TXUDR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-end of message interrupt enable" "0: TXEND interrupt disabled,1: TXEND interrupt enabled"
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-byte request interrupt enable" "0: TXBR interrupt disabled,1: TXBR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration lost interrupt enable" "0: ARBLST interrupt disabled,1: ARBLST interrupt enabled"
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-missing acknowledge error interrupt enable" "0: RXACKE interrupt disabled,1: RXACKE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "LBPEIE,Long bit period error interrupt enable" "0: LBPE interrupt disabled,1: LBPE interrupt enabled"
|
|
bitfld.long 0x4 4. "SBPEIE,Short bit period error interrupt enable" "0: SBPE interrupt disabled,1: SBPE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "BREIE,Bit rising error interrupt enable" "0: BRE interrupt disabled,1: BRE interrupt enabled"
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-buffer overrun interrupt enable" "0: RXOVR interrupt disabled,1: RXOVR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RXENDIE,End of reception interrupt enable" "0: RXEND interrupt disabled,1: RXEND interrupt enabled"
|
|
bitfld.long 0x4 0. "RXBRIE,Rx-byte received interrupt enable" "0: RXBR interrupt disabled,1: RXBR interrupt enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 12. "TXACKIE,Tx-missing acknowledge error interrupt enable" "0: TXACKE interrupt disabled,1: TXACKE interrupt enabled"
|
|
bitfld.long 0x4 11. "TXERRIE,Tx-error interrupt enable" "0: TXERR interrupt disabled,1: TXERR interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "TXUDRIE,Tx-underrun interrupt enable" "0: TXUDR interrupt disabled,1: TXUDR interrupt enabled"
|
|
bitfld.long 0x4 9. "TXENDIE,Tx-end of message interrupt enable" "0: TXEND interrupt disabled,1: TXEND interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 8. "TXBRIE,Tx-byte request interrupt enable" "0: TXBR interrupt disabled,1: TXBR interrupt enabled"
|
|
bitfld.long 0x4 7. "ARBLSTIE,Arbitration lost interrupt enable" "0: ARBLST interrupt disabled,1: ARBLST interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 6. "RXACKIE,Rx-missing acknowledge error interrupt enable" "0: RXACKE interrupt disabled,1: RXACKE interrupt enabled"
|
|
bitfld.long 0x4 5. "LBPEIE,Long bit period error interrupt enable" "0: LBPE interrupt disabled,1: LBPE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 4. "SBPEIE,Short bit period error interrupt enable" "0: SBPE interrupt disabled,1: SBPE interrupt enabled"
|
|
bitfld.long 0x4 3. "BREIE,Bit rising error interrupt enable" "0: BRE interrupt disabled,1: BRE interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 2. "RXOVRIE,Rx-buffer overrun interrupt enable" "0: RXOVR interrupt disabled,1: RXOVR interrupt enabled"
|
|
bitfld.long 0x4 1. "RXENDIE,End of reception interrupt enable" "0: RXEND interrupt disabled,1: RXEND interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 0. "RXBRIE,Rx-byte received interrupt enable" "0: RXBR interrupt disabled,1: RXBR interrupt enabled"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "COMP (Comparator)"
|
|
base ad:0x40010200
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "COMP1_CSR,Comparator 1 control and status register"
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 31. "LOCK,COMP1_CSR register lock" "0: COMP1_CSR[31:0] register read/write bits can be..,1: COMP1_CSR[31:0] register bits can be read but.."
|
|
rbitfld.long 0x0 30. "VALUE,Comparator 1 output status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 1 blanking source selector"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 1 power mode selector" "0: High speed,1: others: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 1 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 1 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 1 output selector" "0: COMP1_VALUE,1: COMP1_VALUE XOR COMP2_VALUE (required for window.."
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 1 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP2_INP signal of the comparator 2 (required.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 1 signal selector for non-inverting input" "0: PC5,1: PB2,2: PA1,3: None (open)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 1 signal selector for inverting input INM"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Comparator 1 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 31. "LOCK,COMP2_CSR register lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 31. "LOCK,COMP2_CSR register lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 31. "LOCK,COMP2_CSR register lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 31. "LOCK,COMP1_CSR register lock" "0: COMP1_CSR[31:0] register read/write bits can be..,1: COMP1_CSR[31:0] register bits can be read but.."
|
|
newline
|
|
rbitfld.long 0x0 30. "VALUE,Comparator 1 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 31. "LOCK,COMP1_CSR register lock" "0: COMP1_CSR[31:0] register read/write bits can be..,1: COMP1_CSR[31:0] register bits can be read but.."
|
|
newline
|
|
rbitfld.long 0x0 30. "VALUE,Comparator 1 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 2 blanking source"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 2 power mode" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 2 hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 2 polarity" "0,1"
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 2 output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 2 blanking source"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 2 power mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 2 hysteresis" "0,1,2,3"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 2 polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 2 output" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 2 blanking source"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 2 power mode" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 2 hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 2 polarity" "0,1"
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 2 output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 1 blanking source selector"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 1 power mode selector" "0: High speed,1: others: Reserved,?,?"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 1 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 1 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 1 output selector" "0: COMP1_VALUE,1: COMP1_VALUE XOR COMP2_VALUE (required for window.."
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 1 blanking source selector"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 1 power mode selector" "0: High speed,1: others: Reserved,?,?"
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 1 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
newline
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 1 polarity selector" "0: Non-inverted,1: Inverted"
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 1 output selector" "0: COMP1_VALUE,1: COMP1_VALUE XOR COMP2_VALUE (required for window.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 2 non-inverting input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 2 non-inverting input" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 2 non-inverting input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 1 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP2_INP signal of the comparator 2 (required.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 1 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP2_INP signal of the comparator 2 (required.."
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 2 signal selector for" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 2 signal selector for"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 2 signal selector for" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 2 signal selector for"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 2 signal selector for" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 2 signal selector for"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 1 signal selector for non-inverting input" "0: PC5,1: PB2,2: PA1,3: None (open)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 1 signal selector for inverting input INM"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 1 signal selector for non-inverting input" "0: PC5,1: PB2,2: PA1,3: None (open)"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 1 signal selector for inverting input INM"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 0. "EN,COMP channel 1 enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 0. "EN,COMP channel 1 enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 0. "EN,Comparator 1 enable bit" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 0. "EN,Comparator 1 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
line.long 0x4 "COMP2_CSR,Comparator 2 control and status register"
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 31. "LOCK,COMP2_CSR register lock" "0: COMP2_CSR[31:0] register read/write bits can be..,1: COMP2_CSR[31:0] register bits can be read but.."
|
|
rbitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source selector"
|
|
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode selector" "0: High speed,1: Medium speed,2: others: Reserved,?"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x4 14. "WINOUT,Comparator 2 output selector" "0: COMP2_VALUE,1: COMP1_VALUE XOR COMP2_VALUE (required for window.."
|
|
bitfld.long 0x4 11. "WINMODE,Comparator 2 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP1_INP signal of the comparator 1 (required.."
|
|
newline
|
|
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for non-inverting input" "0: PB4,1: PB6,2: PA3,3: None (open)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for inverting input INM"
|
|
newline
|
|
bitfld.long 0x4 0. "EN,Comparator 2 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 31. "LOCK,COMP2_CSR register lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 31. "LOCK,COMP2_CSR register lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 31. "LOCK,COMP2_CSR register lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 31. "LOCK,COMP2_CSR register lock" "0: COMP2_CSR[31:0] register read/write bits can be..,1: COMP2_CSR[31:0] register bits can be read but.."
|
|
newline
|
|
rbitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 31. "LOCK,COMP2_CSR register lock" "0: COMP2_CSR[31:0] register read/write bits can be..,1: COMP2_CSR[31:0] register bits can be read but.."
|
|
newline
|
|
rbitfld.long 0x4 30. "VALUE,Comparator 2 output status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity" "0,1"
|
|
bitfld.long 0x4 14. "WINOUT,Comparator 2 output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source"
|
|
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis" "0,1,2,3"
|
|
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "WINOUT,Comparator 2 output" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode" "0,1,2,3"
|
|
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity" "0,1"
|
|
bitfld.long 0x4 14. "WINOUT,Comparator 2 output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source selector"
|
|
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode selector" "0: High speed,1: Medium speed,2: others: Reserved,?"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x4 14. "WINOUT,Comparator 2 output selector" "0: COMP2_VALUE,1: COMP1_VALUE XOR COMP2_VALUE (required for window.."
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x4 20.--24. 1. "BLANKSEL,Comparator 2 blanking source selector"
|
|
newline
|
|
bitfld.long 0x4 18.--19. "PWRMODE,Comparator 2 power mode selector" "0: High speed,1: Medium speed,2: others: Reserved,?"
|
|
bitfld.long 0x4 16.--17. "HYST,Comparator 2 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
newline
|
|
bitfld.long 0x4 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
|
|
bitfld.long 0x4 14. "WINOUT,Comparator 2 output selector" "0: COMP2_VALUE,1: COMP1_VALUE XOR COMP2_VALUE (required for window.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 11. "WINMODE,Comparator 2 non-inverting input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 11. "WINMODE,Comparator 2 non-inverting input" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 11. "WINMODE,Comparator 2 non-inverting input" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 11. "WINMODE,Comparator 2 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP1_INP signal of the comparator 1 (required.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 11. "WINMODE,Comparator 2 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP1_INP signal of the comparator 1 (required.."
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for non-inverting input" "0: PB4,1: PB6,2: PA3,3: None (open)"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for inverting input INM"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 8.--9. "INPSEL,Comparator 2 signal selector for non-inverting input" "0: PB4,1: PB6,2: PA3,3: None (open)"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "INMSEL,Comparator 2 signal selector for inverting input INM"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 0. "EN,COMP channel 1 enable bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 0. "EN,Comparator 2 enable bit" "0: Disable,1: Enable"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 0. "EN,Comparator 2 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "COMP3_CSR,Comparator 2 control and status register"
|
|
bitfld.long 0x0 31. "LOCK,COMP3_CSR register lock" "0: COMP3_CSR[31:0] register read/write bits can be..,1: COMP3_CSR[31:0] register bits can be read but.."
|
|
rbitfld.long 0x0 30. "VALUE,Comparator 3 output status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 3 blanking source selector"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 3 power mode selector" "0: High speed,1: Medium speed,?,3: others: Reserved"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 3 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 3 output selector" "0: COMP2_VALUE,1: COMP1_VALUE XOR COMP3_VALUE (required for window.."
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 3 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP1_INP signal of the comparator 1 (required.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 3 signal selector for non-inverting input" "0: PB4,1: PB6,2: PA3,3: None (open)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 3 signal selector for inverting input INM"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Comparator 3 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "COMP3_CSR,Comparator 2 control and status register"
|
|
bitfld.long 0x0 31. "LOCK,COMP3_CSR register lock" "0: COMP3_CSR[31:0] register read/write bits can be..,1: COMP3_CSR[31:0] register bits can be read but.."
|
|
rbitfld.long 0x0 30. "VALUE,Comparator 3 output status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 3 blanking source selector"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 3 power mode selector" "0: High speed,1: Medium speed,?,3: others: Reserved"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 3 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 3 output selector" "0: COMP2_VALUE,1: COMP1_VALUE XOR COMP3_VALUE (required for window.."
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 3 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP1_INP signal of the comparator 1 (required.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 3 signal selector for non-inverting input" "0: PB4,1: PB6,2: PA3,3: None (open)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 3 signal selector for inverting input INM"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Comparator 3 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "COMP3_CSR,Comparator 2 control and status register"
|
|
bitfld.long 0x0 31. "LOCK,COMP3_CSR register lock" "0: COMP3_CSR[31:0] register read/write bits can be..,1: COMP3_CSR[31:0] register bits can be read but.."
|
|
rbitfld.long 0x0 30. "VALUE,Comparator 3 output status" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--24. 1. "BLANKSEL,Comparator 3 blanking source selector"
|
|
bitfld.long 0x0 18.--19. "PWRMODE,Comparator 3 power mode selector" "0: High speed,1: Medium speed,?,3: others: Reserved"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "HYST,Comparator 3 hysteresis selector" "0: None,1: Low,2: Medium,3: High"
|
|
bitfld.long 0x0 15. "POLARITY,Comparator 2 polarity selector" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.long 0x0 14. "WINOUT,Comparator 3 output selector" "0: COMP2_VALUE,1: COMP1_VALUE XOR COMP3_VALUE (required for window.."
|
|
bitfld.long 0x0 11. "WINMODE,Comparator 3 non-inverting input selector for window mode" "0: Signal selected with INPSEL[1:0] bitfield of..,1: COMP1_INP signal of the comparator 1 (required.."
|
|
newline
|
|
bitfld.long 0x0 8.--9. "INPSEL,Comparator 3 signal selector for non-inverting input" "0: PB4,1: PB6,2: PA3,3: None (open)"
|
|
hexmask.long.byte 0x0 4.--7. 1. "INMSEL,Comparator 3 signal selector for inverting input INM"
|
|
newline
|
|
bitfld.long 0x0 0. "EN,Comparator 3 enable bit" "0: Disable,1: Enable"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "CRC (Cyclic Redundancy Check Calculation Unit)"
|
|
base ad:0x40023000
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CRC_CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "CRC_POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CRC_CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "CRC_POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CRC_CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "CRC_POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0,1"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0,1,2,3"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CRC_CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "CRC_POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CRC_CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "CRC_POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_DR,Data register"
|
|
hexmask.long 0x0 0.--31. 1. "DR,Data register bits"
|
|
line.long 0x4 "CRC_IDR,Independent data register"
|
|
hexmask.long 0x4 0.--31. 1. "IDR,General-purpose 32-bit data register"
|
|
line.long 0x8 "CRC_CR,Control register"
|
|
bitfld.long 0x8 7. "REV_OUT,Reverse output data" "0: Bit order not affected,1: Bit-reversed output format"
|
|
bitfld.long 0x8 5.--6. "REV_IN,Reverse input data" "0: Bit order not affected,1: Bit reversal done by byte,2: Bit reversal done by half-word,3: Bit reversal done by word"
|
|
newline
|
|
bitfld.long 0x8 3.--4. "POLYSIZE,Polynomial size" "0: 32 bit polynomial,1: 16 bit polynomial,2: 8 bit polynomial,3: 7 bit polynomial"
|
|
bitfld.long 0x8 0. "RESET,RESET bit" "0,1"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "CRC_INIT,Initial CRC value"
|
|
hexmask.long 0x0 0.--31. 1. "CRC_INIT,Programmable initial CRC"
|
|
line.long 0x4 "CRC_POL,polynomial"
|
|
hexmask.long 0x4 0.--31. 1. "POL,Programmable polynomial"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "DAC (Digital-to-Analog Converter)"
|
|
base ad:0x40007400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DAC_CR,DAC control register"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x0 30. "CEN2,DAC channel2 calibration enable" "0: DAC channel2 in Normal operating mode,1: DAC channel2 in calibration mode"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable" "0: DAC channel2 DMA underrun interrupt disabled,1: DAC channel2 DMA underrun interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable" "0: DAC channel2 DMA mode disabled,1: DAC channel2 DMA mode enabled"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection"
|
|
newline
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0: DAC channel2 trigger disabled and data written..,1: DAC channel2 trigger enabled and data from the.."
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable" "0: DAC channel2 disabled,1: DAC channel2 enabled"
|
|
newline
|
|
bitfld.long 0x0 14. "CEN1,DAC channel1 calibration enable" "0: DAC channel1 in Normal operating mode,1: DAC channel1 in calibration mode"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable" "0: DAC channel1 DMA Underrun Interrupt disabled,1: DAC channel1 DMA Underrun Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable" "0: DAC channel1 DMA mode disabled,1: DAC channel1 DMA mode enabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection"
|
|
newline
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0: DAC channel1 trigger disabled and data written..,1: DAC channel1 trigger enabled and data from the.."
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable" "0: DAC channel1 disabled,1: DAC channel1 enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These"
|
|
newline
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1"
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These"
|
|
newline
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1"
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 30. "CEN2,DAC Channel 2 calibration enable This" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable This bit is set" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave" "0,1,2,3"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection These"
|
|
newline
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger" "0,1"
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable This bit is set and" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 30. "CEN2,DAC channel2 calibration enable" "0: DAC channel2 in Normal operating mode,1: DAC channel2 in calibration mode"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable" "0: DAC channel2 DMA underrun interrupt disabled,1: DAC channel2 DMA underrun interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable" "0: DAC channel2 DMA mode disabled,1: DAC channel2 DMA mode enabled"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection"
|
|
newline
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0: DAC channel2 trigger disabled and data written..,1: DAC channel2 trigger enabled and data from the.."
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable" "0: DAC channel2 disabled,1: DAC channel2 enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 30. "CEN2,DAC channel2 calibration enable" "0: DAC channel2 in Normal operating mode,1: DAC channel2 in calibration mode"
|
|
bitfld.long 0x0 29. "DMAUDRIE2,DAC channel2 DMA underrun interrupt enable" "0: DAC channel2 DMA underrun interrupt disabled,1: DAC channel2 DMA underrun interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 28. "DMAEN2,DAC channel2 DMA enable" "0: DAC channel2 DMA mode disabled,1: DAC channel2 DMA mode enabled"
|
|
hexmask.long.byte 0x0 24.--27. 1. "MAMP2,DAC channel2 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "WAVE2,DAC channel2 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
|
|
hexmask.long.byte 0x0 18.--21. 1. "TSEL2,DAC channel2 trigger selection"
|
|
newline
|
|
bitfld.long 0x0 17. "TEN2,DAC channel2 trigger enable" "0: DAC channel2 trigger disabled and data written..,1: DAC channel2 trigger enabled and data from the.."
|
|
bitfld.long 0x0 16. "EN2,DAC channel2 enable" "0: DAC channel2 disabled,1: DAC channel2 enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1"
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3"
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These"
|
|
newline
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These"
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 14. "CEN1,DAC Channel 1 calibration enable This" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt" "0,1"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable This bit is set" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection These"
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable This bit is set and" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 14. "CEN1,DAC channel1 calibration enable" "0: DAC channel1 in Normal operating mode,1: DAC channel1 in calibration mode"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable" "0: DAC channel1 DMA Underrun Interrupt disabled,1: DAC channel1 DMA Underrun Interrupt enabled"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable" "0: DAC channel1 DMA mode disabled,1: DAC channel1 DMA mode enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection"
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0: DAC channel1 trigger disabled and data written..,1: DAC channel1 trigger enabled and data from the.."
|
|
newline
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable" "0: DAC channel1 disabled,1: DAC channel1 enabled"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 14. "CEN1,DAC channel1 calibration enable" "0: DAC channel1 in Normal operating mode,1: DAC channel1 in calibration mode"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDRIE1,DAC channel1 DMA Underrun Interrupt enable" "0: DAC channel1 DMA Underrun Interrupt disabled,1: DAC channel1 DMA Underrun Interrupt enabled"
|
|
bitfld.long 0x0 12. "DMAEN1,DAC channel1 DMA enable" "0: DAC channel1 DMA mode disabled,1: DAC channel1 DMA mode enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MAMP1,DAC channel1 mask/amplitude selector"
|
|
bitfld.long 0x0 6.--7. "WAVE1,DAC channel1 noise/triangle wave generation enable" "0: wave generation disabled,1: Noise wave generation enabled,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 2.--5. 1. "TSEL1,DAC channel1 trigger selection"
|
|
bitfld.long 0x0 1. "TEN1,DAC channel1 trigger enable" "0: DAC channel1 trigger disabled and data written..,1: DAC channel1 trigger enabled and data from the.."
|
|
newline
|
|
bitfld.long 0x0 0. "EN1,DAC channel1 enable" "0: DAC channel1 disabled,1: DAC channel1 enabled"
|
|
endif
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DAC_SWTRGR,DAC software trigger register"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger" "0: No trigger,1: Trigger"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger" "0: No trigger,1: Trigger"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger This bit" "0,1"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger This bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger" "0: No trigger,1: Trigger"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger" "0: No trigger,1: Trigger"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 1. "SWTRIG2,DAC channel2 software trigger" "0: No trigger,1: Trigger"
|
|
bitfld.long 0x0 0. "SWTRIG1,DAC channel1 software trigger" "0: No trigger,1: Trigger"
|
|
endif
|
|
group.long 0x8++0x23
|
|
line.long 0x0 "DAC_DHR12R1,DAC channel1 12-bit right-aligned data"
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data"
|
|
line.long 0x4 "DAC_DHR12L1,DAC channel1 12-bit left aligned data"
|
|
hexmask.long.word 0x4 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data"
|
|
line.long 0x8 "DAC_DHR8R1,DAC channel1 8-bit right aligned data"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data"
|
|
line.long 0xC "DAC_DHR12R2,DAC channel2 12-bit right aligned data"
|
|
hexmask.long.word 0xC 0.--11. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data"
|
|
line.long 0x10 "DAC_DHR12L2,DAC channel2 12-bit left aligned data"
|
|
hexmask.long.word 0x10 4.--15. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data"
|
|
line.long 0x14 "DAC_DHR8R2,DAC channel2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x14 0.--7. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data"
|
|
line.long 0x18 "DAC_DHR12RD,Dual DAC 12-bit right-aligned data holding"
|
|
hexmask.long.word 0x18 16.--27. 1. "DACC2DHR,DAC channel2 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. "DACC1DHR,DAC channel1 12-bit right-aligned data"
|
|
line.long 0x1C "DAC_DHR12LD,DUAL DAC 12-bit left aligned data holding"
|
|
hexmask.long.word 0x1C 20.--31. 1. "DACC2DHR,DAC channel2 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. "DACC1DHR,DAC channel1 12-bit left-aligned data"
|
|
line.long 0x20 "DAC_DHR8RD,DUAL DAC 8-bit right aligned data holding"
|
|
hexmask.long.byte 0x20 8.--15. 1. "DACC2DHR,DAC channel2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. "DACC1DHR,DAC channel1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "DAC_DOR1,DAC channel1 data output"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output These bits are"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DACC1DOR,DAC channel1 data output"
|
|
endif
|
|
line.long 0x4 "DAC_DOR2,DAC channel2 data output"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output These bits are"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.word 0x4 0.--11. 1. "DACC2DOR,DAC channel2 data output"
|
|
endif
|
|
group.long 0x34++0x1B
|
|
line.long 0x0 "DAC_SR,DAC status register"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
rbitfld.long 0x0 31. "BWST2,DAC channel2 busy writing sample time flag" "0: There is no write operation of DAC_SHSR2..,1: There is a write operation of DAC_SHSR2 ongoing:.."
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC channel2 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
|
|
newline
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
|
|
rbitfld.long 0x0 15. "BWST1,DAC channel1 busy writing sample time flag" "0: There is no write operation of DAC_SHSR1..,1: There is a write operation of DAC_SHSR1 ongoing:.."
|
|
newline
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC channel1 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1"
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1"
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rbitfld.long 0x0 31. "BWST2,DAC Channel 2 busy writing sample time" "0,1"
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC Channel 2 calibration offset status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag This bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 31. "BWST2,DAC channel2 busy writing sample time flag" "0: There is no write operation of DAC_SHSR2..,1: There is a write operation of DAC_SHSR2 ongoing:.."
|
|
newline
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC channel2 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 31. "BWST2,DAC channel2 busy writing sample time flag" "0: There is no write operation of DAC_SHSR2..,1: There is a write operation of DAC_SHSR2 ongoing:.."
|
|
rbitfld.long 0x0 30. "CAL_FLAG2,DAC channel2 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
|
|
newline
|
|
bitfld.long 0x0 29. "DMAUDR2,DAC channel2 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1"
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rbitfld.long 0x0 15. "BWST1,DAC Channel 1 busy writing sample time" "0,1"
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC Channel 1 calibration offset status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag This bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 15. "BWST1,DAC channel1 busy writing sample time flag" "0: There is no write operation of DAC_SHSR1..,1: There is a write operation of DAC_SHSR1 ongoing:.."
|
|
newline
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC channel1 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 15. "BWST1,DAC channel1 busy writing sample time flag" "0: There is no write operation of DAC_SHSR1..,1: There is a write operation of DAC_SHSR1 ongoing:.."
|
|
newline
|
|
rbitfld.long 0x0 14. "CAL_FLAG1,DAC channel1 calibration offset status" "0: calibration trimming value is lower than the..,1: calibration trimming value is equal or greater.."
|
|
bitfld.long 0x0 13. "DMAUDR1,DAC channel1 DMA underrun flag" "0: No DMA underrun error condition occurred for DAC..,1: DMA underrun error condition occurred for DAC.."
|
|
endif
|
|
line.long 0x4 "DAC_CCR,DAC calibration control"
|
|
hexmask.long.byte 0x4 16.--20. 1. "OTRIM2,DAC channel2 offset trimming value"
|
|
hexmask.long.byte 0x4 0.--4. 1. "OTRIM1,DAC channel1 offset trimming value"
|
|
line.long 0x8 "DAC_MCR,DAC mode control register"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC channel2 mode" "0: DAC channel2 is connected to external pin with..,1: DAC channel2 is connected to external pin and to..,2: DAC channel2 is connected to external pin with..,3: DAC channel2 is connected to on chip peripherals..,4: DAC channel2 is connected to external pin with..,5: DAC channel2 is connected to external pin and to..,6: DAC channel2 is connected to external pin and to..,7: DAC channel2 is connected to on chip peripherals.."
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC channel1 mode" "0: DAC channel1 is connected to external pin with..,1: DAC channel1 is connected to external pin and to..,2: DAC channel1 is connected to external pin with..,3: DAC channel1 is connected to on chip peripherals..,4: DAC channel1 is connected to external pin with..,5: DAC channel1 is connected to external pin and to..,6: DAC channel1 is connected to external pin and to..,7: DAC channel1 is connected to on chip peripherals.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC Channel 2 mode These bits can be" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC channel2 mode" "0: DAC channel2 is connected to external pin with..,1: DAC channel2 is connected to external pin and to..,2: DAC channel2 is connected to external pin with..,3: DAC channel2 is connected to on chip peripherals..,4: DAC channel2 is connected to external pin with..,5: DAC channel2 is connected to external pin and to..,6: DAC channel2 is connected to external pin and to..,7: DAC channel2 is connected to on chip peripherals.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 16.--18. "MODE2,DAC channel2 mode" "0: DAC channel2 is connected to external pin with..,1: DAC channel2 is connected to external pin and to..,2: DAC channel2 is connected to external pin with..,3: DAC channel2 is connected to on chip peripherals..,4: DAC channel2 is connected to external pin with..,5: DAC channel2 is connected to external pin and to..,6: DAC channel2 is connected to external pin and to..,7: DAC channel2 is connected to on chip peripherals.."
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC Channel 1 mode These bits can be" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC channel1 mode" "0: DAC channel1 is connected to external pin with..,1: DAC channel1 is connected to external pin and to..,2: DAC channel1 is connected to external pin with..,3: DAC channel1 is connected to on chip peripherals..,4: DAC channel1 is connected to external pin with..,5: DAC channel1 is connected to external pin and to..,6: DAC channel1 is connected to external pin and to..,7: DAC channel1 is connected to on chip peripherals.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 0.--2. "MODE1,DAC channel1 mode" "0: DAC channel1 is connected to external pin with..,1: DAC channel1 is connected to external pin and to..,2: DAC channel1 is connected to external pin with..,3: DAC channel1 is connected to on chip peripherals..,4: DAC channel1 is connected to external pin with..,5: DAC channel1 is connected to external pin and to..,6: DAC channel1 is connected to external pin and to..,7: DAC channel1 is connected to on chip peripherals.."
|
|
endif
|
|
line.long 0xC "DAC_SHSR1,DAC Sample and Hold sample time register"
|
|
hexmask.long.word 0xC 0.--9. 1. "TSAMPLE1,DAC channel1 sample time (only valid in Sample and hold mode)"
|
|
line.long 0x10 "DAC_SHSR2,DAC Sample and Hold sample time register"
|
|
hexmask.long.word 0x10 0.--9. 1. "TSAMPLE2,DAC channel2 sample time (only valid in Sample and hold mode)"
|
|
line.long 0x14 "DAC_SHHR,DAC Sample and Hold hold time"
|
|
hexmask.long.word 0x14 16.--25. 1. "THOLD2,DAC channel2 hold time (only valid in Sample and hold mode)."
|
|
hexmask.long.word 0x14 0.--9. 1. "THOLD1,DAC channel1 hold time (only valid in Sample and hold mode)"
|
|
line.long 0x18 "DAC_SHRR,DAC Sample and Hold refresh time"
|
|
hexmask.long.byte 0x18 16.--23. 1. "TREFRESH2,DAC channel2 refresh time (only valid in Sample and hold mode)"
|
|
hexmask.long.byte 0x18 0.--7. 1. "TREFRESH1,DAC channel1 refresh time (only valid in Sample and hold mode)"
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "IP_HWCFGR0,DAC IP Hardware Configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OR_CFG,option register bit width"
|
|
hexmask.long.byte 0x0 12.--15. 1. "SAMPLE,Sample and hold mode"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRIANGLE,Triangle wave generation"
|
|
hexmask.long.byte 0x0 4.--7. 1. "LFSR,Pseudonoise wave generation"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DUAL,Dual DAC capability"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "IP_HWCFGR0,DAC IP Hardware Configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OR_CFG,option register bit width"
|
|
hexmask.long.byte 0x0 12.--15. 1. "SAMPLE,Sample and hold mode"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRIANGLE,Triangle wave generation"
|
|
hexmask.long.byte 0x0 4.--7. 1. "LFSR,Pseudonoise wave generation"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DUAL,Dual DAC capability"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "IP_HWCFGR0,DAC IP Hardware Configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OR_CFG,option register bit width"
|
|
hexmask.long.byte 0x0 12.--15. 1. "SAMPLE,Sample and hold mode"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRIANGLE,Triangle wave generation"
|
|
hexmask.long.byte 0x0 4.--7. 1. "LFSR,Pseudonoise wave generation"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DUAL,Dual DAC capability"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "DBG (Debug Support)"
|
|
base ad:0x40015800
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "IDCODE,DBGMCU_IDCODE"
|
|
hexmask.long.word 0x0 16.--31. 1. "REV_ID,Revision identifie"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device identifier"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Device Identifier"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Device Identifier"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device Identifier"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device Identifier"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.word 0x0 0.--11. 1. "DEV_ID,Device Identifier"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.word 0x0 0.--15. 1. "DEV_ID,Device Identifier"
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "CR,Debug MCU configuration"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby mode" "0,1"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0,1"
|
|
line.long 0x4 "APB_FZ1,Debug MCU APB1 freeze"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,LPTIM1 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,LPTIM2 counter stopped when core is" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout counter stopped when" "0,1"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Independent watchdog counter stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Window watchdog counter stopped when" "0,1"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,RTC counter stopped when core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,TIM2 counter stopped when core is" "0,1"
|
|
line.long 0x8 "APB_FZ2,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,DBG_TIM17_STOP" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,DBG_TIM16_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,DBG_TIM14_STOP" "0,1"
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,TIM1 counter stopped when core is" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 22. "DBG_I2C2_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0,1"
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
newline
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,Clocking of TIM7 counter when the core is halted." "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 4. "DBG_TIM6_STOP,Clocking of TIM6 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,Clocking of TIM15 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,Clocking of TIM7 counter when the core is halted." "0: Enable,1: Disable"
|
|
bitfld.long 0x4 4. "DBG_TIM6_STOP,Clocking of TIM6 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,Clocking of TIM15 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,Clocking of TIM7 counter when the core is halted." "0: Enable,1: Disable"
|
|
bitfld.long 0x4 4. "DBG_TIM6_STOP,Clocking of TIM6 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,Clocking of TIM15 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "CR,Debug MCU Configuration"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby Mode" "0,1"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
line.long 0x4 "APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the" "0,1"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout mode stopped when" "0,1"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Debug Independent Wachdog stopped when" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Debug Window Wachdog stopped when Core" "0,1"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Debug RTC stopped when Core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,TIM7 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 4. "DBG_TIMER6_STOP,Debug Timer 6 stopped when Core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is" "0,1"
|
|
line.long 0x8 "APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,DBG_TIM17_STOP" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,DBG_TIM16_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,DBG_TIM15_STOP" "0,1"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,DBG_TIM14_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,DBG_TIM1_STOP" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "CR,Debug MCU Configuration"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby Mode" "0,1"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
line.long 0x4 "APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the" "0,1"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout mode stopped when" "0,1"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Debug Independent Wachdog stopped when" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Debug Window Wachdog stopped when Core" "0,1"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Debug RTC stopped when Core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,TIM7 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 4. "DBG_TIMER6_STOP,Debug Timer 6 stopped when Core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is" "0,1"
|
|
line.long 0x8 "APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,DBG_TIM17_STOP" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,DBG_TIM16_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,DBG_TIM15_STOP" "0,1"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,DBG_TIM14_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,DBG_TIM1_STOP" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "CR,Debug MCU Configuration"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby Mode" "0,1"
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop Mode" "0,1"
|
|
line.long 0x4 "APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the" "0,1"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_STOP,I2C1 SMBUS timeout mode stopped when" "0,1"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Debug Independent Wachdog stopped when" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Debug Window Wachdog stopped when Core" "0,1"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Debug RTC stopped when Core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,TIM7 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 4. "DBG_TIMER6_STOP,Debug Timer 6 stopped when Core is" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,TIM3 counter stopped when core is" "0,1"
|
|
bitfld.long 0x4 0. "DBG_TIMER2_STOP,Debug Timer 2 stopped when Core is" "0,1"
|
|
line.long 0x8 "APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,DBG_TIM17_STOP" "0,1"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,DBG_TIM16_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,DBG_TIM15_STOP" "0,1"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,DBG_TIM14_STOP" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,DBG_TIM1_STOP" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,Clocking of TIM7 counter when the core is halted." "0: Enable,1: Disable"
|
|
bitfld.long 0x4 4. "DBG_TIM6_STOP,Clocking of TIM6 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,Clocking of TIM15 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,Clocking of TIM7 counter when the core is halted." "0: Enable,1: Disable"
|
|
bitfld.long 0x4 4. "DBG_TIM6_STOP,Clocking of TIM6 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,Clocking of TIM15 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "DBG_CR,DBG configuration register"
|
|
bitfld.long 0x0 2. "DBG_STANDBY,Debug Standby and Shutdown modes" "0: Digital part powered. From software point of..,1: Digital part powered and FCLK and HCLK running.."
|
|
bitfld.long 0x0 1. "DBG_STOP,Debug Stop mode" "0: All clocks disabled including FCLK and HCLK.,1: FCLK and HCLK running derived from the internal.."
|
|
line.long 0x4 "DBG_APB_FZ1,DBG APB freeze register 1"
|
|
bitfld.long 0x4 31. "DBG_LPTIM1_STOP,Clocking of LPTIMER1 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 30. "DBG_LPTIM2_STOP,Clocking of LPTIMER2 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 21. "DBG_I2C1_SMBUS_TIMEOUT,SMBUS timeout when core is halted" "0: Same behavior as in normal mode,1: The SMBUS timeout is frozen"
|
|
bitfld.long 0x4 12. "DBG_IWDG_STOP,Clocking of IWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 11. "DBG_WWDG_STOP,Clocking of WWDG counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 10. "DBG_RTC_STOP,Clocking of RTC counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 5. "DBG_TIM7_STOP,Clocking of TIM7 counter when the core is halted." "0: Enable,1: Disable"
|
|
bitfld.long 0x4 4. "DBG_TIM6_STOP,Clocking of TIM6 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x4 1. "DBG_TIM3_STOP,Clocking of TIM3 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x4 0. "DBG_TIM2_STOP,Clocking of TIM2 counter when the core is halted" "0: Enable,1: Disable"
|
|
line.long 0x8 "DBG_APB_FZ2,DBG APB freeze register 2"
|
|
bitfld.long 0x8 18. "DBG_TIM17_STOP,Clocking of TIM17 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 17. "DBG_TIM16_STOP,Clocking of TIM16 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 16. "DBG_TIM15_STOP,Clocking of TIM15 counter when the core is halted" "0: Enable,1: Disable"
|
|
bitfld.long 0x8 15. "DBG_TIM14_STOP,Clocking of TIM14 counter when the core is halted" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0x8 11. "DBG_TIM1_STOP,Clocking of TIM1 counter when the core is halted" "0: Enable,1: Disable"
|
|
endif
|
|
tree.end
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "DMA1"
|
|
base ad:0x40020000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,transfer error (TE) flag for channel 7" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 26. "HTIF7,half transfer (HT) flag for channel 7" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 25. "TCIF7,transfer complete (TC) flag for channel 7" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 24. "GIF7,global interrupt flag for channel 7" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 23. "TEIF6,transfer error (TE) flag for channel 6" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 22. "HTIF6,half transfer (HT) flag for channel 6" "0: no HT event,1: a HT event occurred"
|
|
newline
|
|
bitfld.long 0x0 21. "TCIF6,transfer complete (TC) flag for channel 6" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 20. "GIF6,global interrupt flag for channel 6" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 19. "TEIF5,transfer error (TE) flag for channel 5" "0: no TE event,1: a TE event occurred"
|
|
newline
|
|
bitfld.long 0x0 18. "HTIF5,half transfer (HT) flag for channel 5" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 17. "TCIF5,transfer complete (TC) flag for channel 5" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 15. "TEIF4,transfer error (TE) flag for channel 4" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 14. "HTIF4,half transfer (HT) flag for channel 4" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 13. "TCIF4,transfer complete (TC) flag for channel 4" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 11. "TEIF3,transfer error (TE) flag for channel 3" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 10. "HTIF3,half transfer (HT) flag for channel 3" "0: no HT event,1: a HT event occurred"
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,transfer complete (TC) flag for channel 3" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 8. "GIF3,global interrupt flag for channel 3" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 7. "TEIF2,transfer error (TE) flag for channel 2" "0: no TE event,1: a TE event occurred"
|
|
newline
|
|
bitfld.long 0x0 6. "HTIF2,half transfer (HT) flag for channel 2" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 5. "TCIF2,transfer complete (TC) flag for channel 2" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 4. "GIF2,global interrupt flag for channel 2" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIF1,transfer error (TE) flag for channel 1" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 2. "HTIF1,half transfer (HT) flag for channel 1" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 1. "TCIF1,transfer complete (TC) flag for channel 1" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "GIF1,global interrupt flag for channel 1" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,transfer error flag clear for channel 7" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,half transfer flag clear for channel 7" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,transfer complete flag clear for channel 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CGIF7,global interrupt flag clear for channel 7" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,transfer error flag clear for channel 6" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,half transfer flag clear for channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CTCIF6,transfer complete flag clear for channel 6" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,global interrupt flag clear for channel 6" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,transfer error flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CHTIF5,half transfer flag clear for channel 5" "0,1"
|
|
bitfld.long 0x0 17. "CTCIF5,transfer complete flag clear for channel 5" "0,1"
|
|
bitfld.long 0x0 16. "CGIF5,global interrupt flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CTEIF4,transfer error flag clear for channel 4" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,half transfer flag clear for channel 4" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,transfer complete flag clear for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CGIF4,global interrupt flag clear for channel 4" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,transfer error flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,half transfer flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTCIF3,transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,global interrupt flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 7. "CTEIF2,transfer error flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CHTIF2,half transfer flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 5. "CTCIF2,transfer complete flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,global interrupt flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTEIF1,transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,half transfer flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,transfer complete flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CGIF1,global interrupt flag clear for channel 1" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR1,DMA channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR1,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR1,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR2,DMA channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR2,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR2,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR3,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR3,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR3,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR4,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR4,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR4,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR5,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR5,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR5,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR6,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR6,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR6,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR7,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR7,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR7,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
tree.end
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x0 27. "TEIF7,transfer error (TE) flag for channel 7" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 26. "HTIF7,half transfer (HT) flag for channel 7" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 25. "TCIF7,transfer complete (TC) flag for channel 7" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 24. "GIF7,global interrupt flag for channel 7" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 23. "TEIF6,transfer error (TE) flag for channel 6" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 22. "HTIF6,half transfer (HT) flag for channel 6" "0: no HT event,1: a HT event occurred"
|
|
newline
|
|
bitfld.long 0x0 21. "TCIF6,transfer complete (TC) flag for channel 6" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 20. "GIF6,global interrupt flag for channel 6" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 19. "TEIF5,transfer error (TE) flag for channel 5" "0: no TE event,1: a TE event occurred"
|
|
newline
|
|
bitfld.long 0x0 18. "HTIF5,half transfer (HT) flag for channel 5" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 17. "TCIF5,transfer complete (TC) flag for channel 5" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 16. "GIF5,global interrupt flag for channel 5" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 15. "TEIF4,transfer error (TE) flag for channel 4" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 14. "HTIF4,half transfer (HT) flag for channel 4" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 13. "TCIF4,transfer complete (TC) flag for channel 4" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 12. "GIF4,global interrupt flag for channel 4" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 11. "TEIF3,transfer error (TE) flag for channel 3" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 10. "HTIF3,half transfer (HT) flag for channel 3" "0: no HT event,1: a HT event occurred"
|
|
newline
|
|
bitfld.long 0x0 9. "TCIF3,transfer complete (TC) flag for channel 3" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 8. "GIF3,global interrupt flag for channel 3" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
bitfld.long 0x0 7. "TEIF2,transfer error (TE) flag for channel 2" "0: no TE event,1: a TE event occurred"
|
|
newline
|
|
bitfld.long 0x0 6. "HTIF2,half transfer (HT) flag for channel 2" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 5. "TCIF2,transfer complete (TC) flag for channel 2" "0: no TC event,1: a TC event occurred"
|
|
bitfld.long 0x0 4. "GIF2,global interrupt flag for channel 2" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 3. "TEIF1,transfer error (TE) flag for channel 1" "0: no TE event,1: a TE event occurred"
|
|
bitfld.long 0x0 2. "HTIF1,half transfer (HT) flag for channel 1" "0: no HT event,1: a HT event occurred"
|
|
bitfld.long 0x0 1. "TCIF1,transfer complete (TC) flag for channel 1" "0: no TC event,1: a TC event occurred"
|
|
newline
|
|
bitfld.long 0x0 0. "GIF1,global interrupt flag for channel 1" "0: no TE HT or TC event,1: a TE HT or TC event occurred"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x0 27. "CTEIF7,transfer error flag clear for channel 7" "0,1"
|
|
bitfld.long 0x0 26. "CHTIF7,half transfer flag clear for channel 7" "0,1"
|
|
bitfld.long 0x0 25. "CTCIF7,transfer complete flag clear for channel 7" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "CGIF7,global interrupt flag clear for channel 7" "0,1"
|
|
bitfld.long 0x0 23. "CTEIF6,transfer error flag clear for channel 6" "0,1"
|
|
bitfld.long 0x0 22. "CHTIF6,half transfer flag clear for channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CTCIF6,transfer complete flag clear for channel 6" "0,1"
|
|
bitfld.long 0x0 20. "CGIF6,global interrupt flag clear for channel 6" "0,1"
|
|
bitfld.long 0x0 19. "CTEIF5,transfer error flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CHTIF5,half transfer flag clear for channel 5" "0,1"
|
|
bitfld.long 0x0 17. "CTCIF5,transfer complete flag clear for channel 5" "0,1"
|
|
bitfld.long 0x0 16. "CGIF5,global interrupt flag clear for channel 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CTEIF4,transfer error flag clear for channel 4" "0,1"
|
|
bitfld.long 0x0 14. "CHTIF4,half transfer flag clear for channel 4" "0,1"
|
|
bitfld.long 0x0 13. "CTCIF4,transfer complete flag clear for channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CGIF4,global interrupt flag clear for channel 4" "0,1"
|
|
bitfld.long 0x0 11. "CTEIF3,transfer error flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 10. "CHTIF3,half transfer flag clear for channel 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTCIF3,transfer complete flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 8. "CGIF3,global interrupt flag clear for channel 3" "0,1"
|
|
bitfld.long 0x0 7. "CTEIF2,transfer error flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CHTIF2,half transfer flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 5. "CTCIF2,transfer complete flag clear for channel 2" "0,1"
|
|
bitfld.long 0x0 4. "CGIF2,global interrupt flag clear for channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTEIF1,transfer error flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 2. "CHTIF1,half transfer flag clear for channel 1" "0,1"
|
|
bitfld.long 0x0 1. "CTCIF1,transfer complete flag clear for channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CGIF1,global interrupt flag clear for channel 1" "0,1"
|
|
group.long 0x8++0xF
|
|
line.long 0x0 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR1,DMA channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR1,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR1,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x1C++0xF
|
|
line.long 0x0 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR2,DMA channel x number of data register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR2,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR2,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x30++0xF
|
|
line.long 0x0 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR3,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR3,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR3,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x44++0xF
|
|
line.long 0x0 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR4,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR4,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR4,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x58++0xF
|
|
line.long 0x0 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR5,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR5,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR5,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR6,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR6,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR6,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x0 14. "MEM2MEM,memory-to-memory mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 12.--13. "PL,priority level" "0: low,1: medium,2: high,3: very high"
|
|
bitfld.long 0x0 10.--11. "MSIZE,memory size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "PSIZE,peripheral size" "0: 8 bits,1: 16 bits,2: 32 bits,?"
|
|
bitfld.long 0x0 7. "MINC,memory increment mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 6. "PINC,peripheral increment mode" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CIRC,circular mode" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 4. "DIR,data transfer direction" "0: read from peripheral,1: read from memory"
|
|
bitfld.long 0x0 3. "TEIE,transfer error interrupt enable" "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "HTIE,half transfer interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 1. "TCIE,transfer complete interrupt enable" "0: disabled,1: enabled"
|
|
bitfld.long 0x0 0. "EN,channel enable" "0: disabled,1: enabled"
|
|
line.long 0x4 "DMA_CNDTR7,DMA channel x configuration register"
|
|
hexmask.long.word 0x4 0.--15. 1. "NDT,number of data to transfer (0 to 216-1)"
|
|
line.long 0x8 "DMA_CPAR7,DMA channel x peripheral address register"
|
|
hexmask.long 0x8 0.--31. 1. "PA,peripheral address"
|
|
line.long 0xC "DMA_CMAR7,DMA channel x memory address register"
|
|
hexmask.long 0xC 0.--31. 1. "MA,peripheral address"
|
|
tree.end
|
|
tree.end
|
|
tree "DMAMUX (Direct Memory Access Multiplexer)"
|
|
base ad:0x40020800
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "C0CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x4 "C1CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x8 "C2CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0xC "C3CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x10 "C4CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x14 "C5CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x18 "C6CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "RG0CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x4 "RG1CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x8 "RG2CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0xC "RG3CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "RGSR,DMAMux - DMA request generator status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OF,Trigger event overrun flag The flag is"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "RGCFR,DMAMux - DMA request generator clear flag"
|
|
hexmask.long.byte 0x0 0.--3. 1. "COF,Clear trigger event overrun flag Upon"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x2F
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x1C "DMAMUX_C7CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x1C 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x1C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x1C 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x1C 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x1C 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x1C 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x20 "DMAMUX_C8CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x20 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x20 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x20 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x20 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x20 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x20 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x24 "DMAMUX_C9CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x24 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x24 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x24 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x24 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x24 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x24 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x24 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x28 "DMAMUX_C10CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x28 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x28 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x28 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x28 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x28 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x28 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x2C "DMAMUX_C11CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x2C 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x2C 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x2C 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x2C 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x2C 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x2C 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 11. "SOF11,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 10. "SOF10,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SOF9,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 8. "SOF8,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SOF7,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
rbitfld.long 0x0 11. "CSOF11,Clear synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 10. "CSOF10,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 9. "CSOF9,Clear synchronization overrun event flag" "0,1"
|
|
rbitfld.long 0x0 8. "CSOF8,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 7. "CSOF7,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMux - DMA request generator status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OF,Trigger event overrun flag The flag is"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMux - DMA request generator clear flag"
|
|
hexmask.long.byte 0x0 0.--3. 1. "COF,Clear trigger event overrun flag Upon"
|
|
rgroup.long 0x3F8++0x3
|
|
line.long 0x0 "DMAMUX_IPIDR,DMAMUX IP identification"
|
|
hexmask.long 0x0 0.--31. 1. "ID,IP identification"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SOF,Synchronization overrun event"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CSOF,Clear synchronization overrun event"
|
|
rgroup.long 0x3FC++0x3
|
|
line.long 0x0 "DMAMUX_SIDR,DMAMUX size identification"
|
|
hexmask.long 0x0 0.--31. 1. "SID,Size identification"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rgroup.long 0x3F4++0x3
|
|
line.long 0x0 "DMAMUX_VERR,DMAMUX version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major IP revision"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor IP revision"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rgroup.long 0x3F0++0x3
|
|
line.long 0x0 "DMAMUX_HWCFGR1,DMAMUX hardware configuration 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NUM_DMA_REQGEN,number of DMA request generator"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NUM_DMA_TRIG,number of synchronization"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "NUM_DMA_PERIPH_REQ,number of DMA request lines from"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_STREAMS,number of DMA request line multiplexer"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rgroup.long 0x3EC++0x3
|
|
line.long 0x0 "DMAMUX_HWCFGR2,DMAMUX hardware configuration 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_EXT_REQ,Number of DMA request trigger"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMux - DMA request generator status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OF,Trigger event overrun flag The flag is"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMux - DMA request generator clear flag"
|
|
hexmask.long.byte 0x0 0.--3. 1. "COF,Clear trigger event overrun flag Upon"
|
|
rgroup.long 0x3F8++0x3
|
|
line.long 0x0 "DMAMUX_IPIDR,DMAMUX IP identification"
|
|
hexmask.long 0x0 0.--31. 1. "ID,IP identification"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SOF,Synchronization overrun event"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CSOF,Clear synchronization overrun event"
|
|
rgroup.long 0x3FC++0x3
|
|
line.long 0x0 "DMAMUX_SIDR,DMAMUX size identification"
|
|
hexmask.long 0x0 0.--31. 1. "SID,Size identification"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0x3F4++0x3
|
|
line.long 0x0 "DMAMUX_VERR,DMAMUX version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major IP revision"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor IP revision"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0x3F0++0x3
|
|
line.long 0x0 "DMAMUX_HWCFGR1,DMAMUX hardware configuration 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NUM_DMA_REQGEN,number of DMA request generator"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NUM_DMA_TRIG,number of synchronization"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "NUM_DMA_PERIPH_REQ,number of DMA request lines from"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_STREAMS,number of DMA request line multiplexer"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0x3EC++0x3
|
|
line.long 0x0 "DMAMUX_HWCFGR2,DMAMUX hardware configuration 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_EXT_REQ,Number of DMA request trigger"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x0 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x0 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x4 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x4 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x8 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0xC 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0xC 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x10 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x10 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x14 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x14 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMux - DMA request line multiplexer"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization input"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization event type selector" "0,1,2,3"
|
|
bitfld.long 0x18 16. "SE,Synchronous operating mode" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation" "0,1"
|
|
bitfld.long 0x18 8. "SOIE,Interrupt enable at synchronization" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--7. 1. "DMAREQ_ID,Input DMA request line"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x0 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x4 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0x8 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMux - DMA request generator channel x"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to generate"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger event type" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel" "0,1"
|
|
bitfld.long 0xC 8. "OIE,Interrupt enable at trigger event" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,DMA request trigger input"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMux - DMA request generator status"
|
|
hexmask.long.byte 0x0 0.--3. 1. "OF,Trigger event overrun flag The flag is"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMux - DMA request generator clear flag"
|
|
hexmask.long.byte 0x0 0.--3. 1. "COF,Clear trigger event overrun flag Upon"
|
|
rgroup.long 0x3F8++0x3
|
|
line.long 0x0 "DMAMUX_IPIDR,DMAMUX IP identification"
|
|
hexmask.long 0x0 0.--31. 1. "ID,IP identification"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SOF,Synchronization overrun event"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt"
|
|
hexmask.long.byte 0x0 0.--6. 1. "CSOF,Clear synchronization overrun event"
|
|
rgroup.long 0x3FC++0x3
|
|
line.long 0x0 "DMAMUX_SIDR,DMAMUX size identification"
|
|
hexmask.long 0x0 0.--31. 1. "SID,Size identification"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0x3F4++0x3
|
|
line.long 0x0 "DMAMUX_VERR,DMAMUX version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major IP revision"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor IP revision"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0x3F0++0x3
|
|
line.long 0x0 "DMAMUX_HWCFGR1,DMAMUX hardware configuration 1"
|
|
hexmask.long.byte 0x0 24.--31. 1. "NUM_DMA_REQGEN,number of DMA request generator"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NUM_DMA_TRIG,number of synchronization"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "NUM_DMA_PERIPH_REQ,number of DMA request lines from"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_STREAMS,number of DMA request line multiplexer"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0x3EC++0x3
|
|
line.long 0x0 "DMAMUX_HWCFGR2,DMAMUX hardware configuration 2"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NUM_DMA_EXT_REQ,Number of DMA request trigger"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "DMAMUX_C0CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x0 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x0 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x0 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x0 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x4 "DMAMUX_C1CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x4 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x4 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x4 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x4 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x8 "DMAMUX_C2CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x8 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x8 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x8 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x8 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x8 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x8 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0xC "DMAMUX_C3CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0xC 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0xC 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0xC 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0xC 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0xC 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0xC 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x10 "DMAMUX_C4CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x10 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x10 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x10 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x10 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x10 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x10 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x14 "DMAMUX_C5CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x14 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x14 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x14 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x14 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x14 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x14 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
line.long 0x18 "DMAMUX_C6CR,DMAMUX request line multiplexer channel x configuration register"
|
|
hexmask.long.byte 0x18 24.--28. 1. "SYNC_ID,Synchronization identification"
|
|
hexmask.long.byte 0x18 19.--23. 1. "NBREQ,Number of DMA requests minus 1 to forward"
|
|
newline
|
|
bitfld.long 0x18 17.--18. "SPOL,Synchronization polarity" "0: no event i.e. no synchronization nor detection.,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
bitfld.long 0x18 16. "SE,Synchronization enable" "0: synchronization disabled,1: synchronization enabled"
|
|
newline
|
|
bitfld.long 0x18 9. "EGE,Event generation enable" "0: event generation disabled,1: event generation enabled"
|
|
bitfld.long 0x18 8. "SOIE,Synchronization overrun interrupt enable" "0: interrupt disabled,1: interrupt enabled"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--5. 1. "DMAREQ_ID,DMA request identification"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "DMAMUX_CSR,DMAMUX request line multiplexer interrupt channel status register"
|
|
bitfld.long 0x0 6. "SOF6,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "SOF5,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SOF4,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "SOF3,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SOF2,Synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "SOF1,Synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SOF0,Synchronization overrun event flag" "0,1"
|
|
wgroup.long 0x84++0x3
|
|
line.long 0x0 "DMAMUX_CFR,DMAMUX request line multiplexer interrupt clear flag register"
|
|
bitfld.long 0x0 6. "CSOF6,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 5. "CSOF5,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CSOF4,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 3. "CSOF3,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSOF2,Clear synchronization overrun event flag" "0,1"
|
|
bitfld.long 0x0 1. "CSOF1,Clear synchronization overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CSOF0,Clear synchronization overrun event flag" "0,1"
|
|
group.long 0x100++0xF
|
|
line.long 0x0 "DMAMUX_RG0CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x0 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x0 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x0 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x0 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x4 "DMAMUX_RG1CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x4 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x4 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x4 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x4 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0x8 "DMAMUX_RG2CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0x8 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0x8 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0x8 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0x8 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--4. 1. "SIG_ID,Signal identification"
|
|
line.long 0xC "DMAMUX_RG3CR,DMAMUX request generator channel x configuration register"
|
|
hexmask.long.byte 0xC 19.--23. 1. "GNBREQ,Number of DMA requests to be generated (minus 1)"
|
|
bitfld.long 0xC 17.--18. "GPOL,DMA request generator trigger polarity" "0: no event. I.e. none trigger detection nor..,1: rising edge,2: falling edge,3: rising and falling edge"
|
|
newline
|
|
bitfld.long 0xC 16. "GE,DMA request generator channel x enable" "0: DMA request generator channel x disabled,1: DMA request generator channel x enabled"
|
|
bitfld.long 0xC 8. "OIE,Trigger overrun interrupt enable" "0: interrupt on a trigger overrun event occurrence..,1: interrupt on a trigger overrun event occurrence.."
|
|
newline
|
|
hexmask.long.byte 0xC 0.--4. 1. "SIG_ID,Signal identification"
|
|
rgroup.long 0x140++0x3
|
|
line.long 0x0 "DMAMUX_RGSR,DMAMUX request generator interrupt status register"
|
|
bitfld.long 0x0 3. "OF3,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "OF2,Trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OF1,Trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "OF0,Trigger overrun event flag" "0,1"
|
|
wgroup.long 0x144++0x3
|
|
line.long 0x0 "DMAMUX_RGCFR,DMAMUX request generator interrupt clear flag register"
|
|
bitfld.long 0x0 3. "COF3,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 2. "COF2,Clear trigger overrun event flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "COF1,Clear trigger overrun event flag" "0,1"
|
|
bitfld.long 0x0 0. "COF0,Clear trigger overrun event flag" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "EXTI (Extended Interrupt and Event Controller)"
|
|
base ad:0x40021800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "RTSR1,EXTI rising trigger selection"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 20. "RT20,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 18. "TR18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 17. "TR17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 18. "TR18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 17. "TR17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 16. "RT16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 18. "RT18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 17. "RT17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 16. "RT16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 15. "RT15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 14. "RT14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 13. "RT13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 12. "RT12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RT11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 10. "RT10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 9. "RT9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 8. "RT8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 7. "RT7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 6. "RT6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 5. "RT5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 4. "RT4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 3. "RT3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 1. "RT1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x0 0. "RT0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
line.long 0x4 "FTSR1,EXTI falling trigger selection"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 20. "FT20,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 20. "FT20,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 18. "TR18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 17. "TR17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 18. "TR18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 17. "TR17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 16. "FT16,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 18. "FT18,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 17. "FT17,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 16. "FT16,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 16. "TR16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 15. "TR15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 14. "TR14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 13. "TR13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 12. "TR12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 11. "TR11,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TR10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 9. "TR9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 8. "TR8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 7. "TR7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 6. "TR6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 5. "TR5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 4. "TR4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 3. "TR3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 2. "TR2,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TR1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x4 0. "TR0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 15. "FT15,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 14. "FT14,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 13. "FT13,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 12. "FT12,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "FT11,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 10. "FT10,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 9. "FT9,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 8. "FT8,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 7. "FT7,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 6. "FT6,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 5. "FT5,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 4. "FT4,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 3. "FT3,Falling trigger event configuration bit of configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 1. "FT1,Falling trigger event configuration bit of configurable line" "0,1"
|
|
bitfld.long 0x4 0. "FT0,Falling trigger event configuration bit of configurable line" "0,1"
|
|
endif
|
|
line.long 0x8 "SWIER1,EXTI software interrupt event"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 20. "SWI20,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 20. "SWI20,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 18. "SWIER18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 17. "SWIER17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 18. "SWIER18,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 17. "SWIER17,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 18. "SWI18,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 17. "SWI17,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 16. "SWI16,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 18. "SWI18,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 17. "SWI17,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 16. "SWI16,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 16. "SWIER16,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 15. "SWIER15,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 14. "SWIER14,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 13. "SWIER13,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 12. "SWIER12,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 11. "SWIER11,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "SWIER10,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 9. "SWIER9,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 8. "SWIER8,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 7. "SWIER7,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 6. "SWIER6,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 5. "SWIER5,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 4. "SWIER4,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 3. "SWIER3,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 2. "SWIER2,Rising trigger event configuration bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "SWIER1,Rising trigger event configuration bit" "0,1"
|
|
bitfld.long 0x8 0. "SWIER0,Rising trigger event configuration bit" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 15. "SWI15,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 14. "SWI14,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 13. "SWI13,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 12. "SWI12,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "SWI11,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 10. "SWI10,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 9. "SWI9,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 8. "SWI8,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 7. "SWI7,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 6. "SWI6,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 5. "SWI5,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 4. "SWI4,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 3. "SWI3,Software rising edge event trigger on line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 1. "SWI1,Software rising edge event trigger on line" "0,1"
|
|
bitfld.long 0x8 0. "SWI0,Software rising edge event trigger on line" "0,1"
|
|
endif
|
|
line.long 0xC "RPR1,EXTI rising edge pending"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0xC 20. "RPIF20,Rising edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0xC 20. "RPIF20,Rising edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0xC 18. "RPIF18,configurable event inputs x rising edge" "0,1"
|
|
bitfld.long 0xC 17. "RPIF17,configurable event inputs x rising edge" "0,1"
|
|
bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0xC 18. "RPIF18,configurable event inputs x rising edge" "0,1"
|
|
bitfld.long 0xC 17. "RPIF17,configurable event inputs x rising edge" "0,1"
|
|
bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0xC 18. "RPIF18,Rising edge event pending for configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "RPIF17,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 16. "RPIF16,Rising edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0xC 18. "RPIF18,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 17. "RPIF17,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 16. "RPIF16,Rising edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0xC 16. "RPIF16,configurable event inputs x rising edge" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 15. "RPIF15,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 14. "RPIF14,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 13. "RPIF13,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 12. "RPIF12,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 11. "RPIF11,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 10. "RPIF10,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 9. "RPIF9,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 8. "RPIF8,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 7. "RPIF7,Rising edge event pending for configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "RPIF6,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 5. "RPIF5,configurable event inputs x rising edge" "0,1"
|
|
bitfld.long 0xC 4. "RPIF4,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 3. "RPIF3,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 2. "RPIF2,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 1. "RPIF1,Rising edge event pending for configurable line" "0,1"
|
|
bitfld.long 0xC 0. "RPIF0,Rising edge event pending for configurable line" "0,1"
|
|
line.long 0x10 "FPR1,EXTI falling edge pending"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x10 20. "FPIF20,Falling edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x10 20. "FPIF20,Falling edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x10 18. "FPIF18,configurable event inputs x falling edge" "0,1"
|
|
bitfld.long 0x10 17. "FPIF17,configurable event inputs x falling edge" "0,1"
|
|
bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x10 18. "FPIF18,configurable event inputs x falling edge" "0,1"
|
|
bitfld.long 0x10 17. "FPIF17,configurable event inputs x falling edge" "0,1"
|
|
bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x10 18. "FPIF18,Falling edge event pending for configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "FPIF17,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 16. "FPIF16,Falling edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x10 18. "FPIF18,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 17. "FPIF17,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 16. "FPIF16,Falling edge event pending for configurable line" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x10 16. "FPIF16,configurable event inputs x falling edge" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 15. "FPIF15,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 14. "FPIF14,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 13. "FPIF13,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 12. "FPIF12,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 11. "FPIF11,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 10. "FPIF10,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 9. "FPIF9,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 8. "FPIF8,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 7. "FPIF7,Falling edge event pending for configurable line" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "FPIF6,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 5. "FPIF5,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 4. "FPIF4,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 3. "FPIF3,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 2. "FPIF2,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 1. "FPIF1,Falling edge event pending for configurable line" "0,1"
|
|
bitfld.long 0x10 0. "FPIF0,Falling edge event pending for configurable line" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x28++0x13
|
|
line.long 0x0 "RTSR2,EXTI rising trigger selection register 2"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable line 34" "0,1"
|
|
line.long 0x4 "FTSR2,EXTI falling trigger selection register 2"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line 34" "0,1"
|
|
line.long 0x8 "SWIER2,EXTI software interrupt event register 2"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line 34" "0,1"
|
|
line.long 0xC "RPR2,EXTI rising edge pending register 2"
|
|
bitfld.long 0xC 2. "RPIF2,Rising edge event pending for configurable line 34" "0,1"
|
|
line.long 0x10 "FPR2,EXTI falling edge pending register 2"
|
|
bitfld.long 0x10 2. "FPIF2,Falling edge event pending for configurable line 34" "0,1"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "IMR2,EXTI CPU wakeup with interrupt mask"
|
|
bitfld.long 0x0 3. "IM35,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 2. "IM34,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IM33,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 0. "IM32,CPU wakeup with interrupt mask on event" "0,1"
|
|
line.long 0x4 "EMR2,EXTI CPU wakeup with event mask"
|
|
bitfld.long 0x4 3. "EM35,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 2. "EM34,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EM33,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 0. "EM32,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x28++0x13
|
|
line.long 0x0 "RTSR2,EXTI rising trigger selection register 2"
|
|
bitfld.long 0x0 2. "RT2,Rising trigger event configuration bit of configurable line 34" "0,1"
|
|
line.long 0x4 "FTSR2,EXTI falling trigger selection register 2"
|
|
bitfld.long 0x4 2. "FT2,Falling trigger event configuration bit of configurable line 34" "0,1"
|
|
line.long 0x8 "SWIER2,EXTI software interrupt event register 2"
|
|
bitfld.long 0x8 2. "SWI2,Software rising edge event trigger on line 34" "0,1"
|
|
line.long 0xC "RPR2,EXTI rising edge pending register 2"
|
|
bitfld.long 0xC 2. "RPIF2,Rising edge event pending for configurable line 34" "0,1"
|
|
line.long 0x10 "FPR2,EXTI falling edge pending register 2"
|
|
bitfld.long 0x10 2. "FPIF2,Falling edge event pending for configurable line 34" "0,1"
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "IMR2,EXTI CPU wakeup with interrupt mask"
|
|
bitfld.long 0x0 3. "IM35,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 2. "IM34,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IM33,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 0. "IM32,CPU wakeup with interrupt mask on event" "0,1"
|
|
line.long 0x4 "EMR2,EXTI CPU wakeup with event mask"
|
|
bitfld.long 0x4 3. "EM35,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 2. "EM34,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EM33,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 0. "EM32,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
group.long 0x60++0xF
|
|
line.long 0x0 "EXTICR1,EXTI external interrupt selection"
|
|
hexmask.long.byte 0x0 24.--31. 1. "EXTI24_31,GPIO port selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "EXTI16_23,GPIO port selection"
|
|
hexmask.long.byte 0x0 8.--15. 1. "EXTI8_15,GPIO port selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "EXTI0_7,GPIO port selection"
|
|
line.long 0x4 "EXTICR2,EXTI external interrupt selection"
|
|
hexmask.long.byte 0x4 24.--31. 1. "EXTI24_31,GPIO port selection"
|
|
hexmask.long.byte 0x4 16.--23. 1. "EXTI16_23,GPIO port selection"
|
|
hexmask.long.byte 0x4 8.--15. 1. "EXTI8_15,GPIO port selection"
|
|
hexmask.long.byte 0x4 0.--7. 1. "EXTI0_7,GPIO port selection"
|
|
line.long 0x8 "EXTICR3,EXTI external interrupt selection"
|
|
hexmask.long.byte 0x8 24.--31. 1. "EXTI24_31,GPIO port selection"
|
|
hexmask.long.byte 0x8 16.--23. 1. "EXTI16_23,GPIO port selection"
|
|
hexmask.long.byte 0x8 8.--15. 1. "EXTI8_15,GPIO port selection"
|
|
hexmask.long.byte 0x8 0.--7. 1. "EXTI0_7,GPIO port selection"
|
|
line.long 0xC "EXTICR4,EXTI external interrupt selection"
|
|
hexmask.long.byte 0xC 24.--31. 1. "EXTI24_31,GPIO port selection"
|
|
hexmask.long.byte 0xC 16.--23. 1. "EXTI16_23,GPIO port selection"
|
|
hexmask.long.byte 0xC 8.--15. 1. "EXTI8_15,GPIO port selection"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXTI0_7,GPIO port selection"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "IMR1,EXTI CPU wakeup with interrupt mask"
|
|
bitfld.long 0x0 31. "IM31,CPU wakeup with interrupt mask on event" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 27. "IM27,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 27. "IM27,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 27. "IM27,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 30. "IM30,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 29. "IM29,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "IM28,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 27. "IM27,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
bitfld.long 0x0 26. "IM26,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 25. "IM25,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 24. "IM24,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 23. "IM23,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 22. "IM22,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 21. "IM21,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 20. "IM20,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
bitfld.long 0x0 19. "IM19,CPU wakeup with interrupt mask on event" "0,1"
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 18. "IM18,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "IM17,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 18. "IM18,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 17. "IM17,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 18. "IM18,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 17. "IM17,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 18. "IM18,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "IM17,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 16. "IM16,CPU wakeup with interrupt mask on event" "0,1"
|
|
endif
|
|
bitfld.long 0x0 15. "IM15,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 14. "IM14,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 13. "IM13,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "IM12,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 11. "IM11,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 10. "IM10,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 9. "IM9,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 8. "IM8,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 7. "IM7,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 6. "IM6,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 5. "IM5,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 4. "IM4,CPU wakeup with interrupt mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "IM3,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 2. "IM2,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 1. "IM1,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 0. "IM0,CPU wakeup with interrupt mask on event" "0,1"
|
|
line.long 0x4 "EMR1,EXTI CPU wakeup with event mask"
|
|
bitfld.long 0x4 31. "EM31,CPU wakeup with event mask on event" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 27. "EM27,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 27. "EM27,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 27. "EM27,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 30. "EM30,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 29. "EM29,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "EM28,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 27. "EM27,CPU wakeup with event mask on event" "0,1"
|
|
endif
|
|
bitfld.long 0x4 26. "EM26,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 25. "EM25,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 23. "EM23,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 21. "EM21,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 19. "EM19,CPU wakeup with event mask on event" "0,1"
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 18. "EM18,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 17. "EM17,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 18. "EM18,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 17. "EM17,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 18. "EM18,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 17. "EM17,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 18. "EM18,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 17. "EM17,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 16. "EM16,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 15. "EM15,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 14. "EM14,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 13. "EM13,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 12. "EM12,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EM11,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 10. "EM10,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 9. "EM9,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 8. "EM8,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 7. "EM7,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 6. "EM6,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 5. "EM5,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 4. "EM4,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 3. "EM3,CPU wakeup with event mask on event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "EM2,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 1. "EM1,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 0. "EM0,CPU wakeup with event mask on event" "0,1"
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "IMR2,EXTI CPU wakeup with interrupt mask"
|
|
bitfld.long 0x0 1. "IM33,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 0. "IM32,CPU wakeup with interrupt mask on event" "0,1"
|
|
line.long 0x4 "EMR2,EXTI CPU wakeup with event mask"
|
|
bitfld.long 0x4 1. "EM33,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 0. "EM32,CPU wakeup with event mask on event" "0,1"
|
|
group.long 0x3D8++0x17
|
|
line.long 0x0 "HWCFGR7,Hardware configuration"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event"
|
|
line.long 0x4 "HWCFGR6,Hardware configuration"
|
|
hexmask.long 0x4 0.--31. 1. "CPUEVENT,HW configuration CPU event"
|
|
line.long 0x8 "HWCFGR5,Hardware configuration"
|
|
hexmask.long 0x8 0.--31. 1. "CPUEVENT,HW configuration CPU event"
|
|
line.long 0xC "HWCFGR4,Hardware configuration"
|
|
hexmask.long 0xC 0.--31. 1. "EVENT_TRG,HW configuration event trigger"
|
|
line.long 0x10 "HWCFGR3,Hardware configuration"
|
|
hexmask.long 0x10 0.--31. 1. "EVENT_TRG,HW configuration event trigger"
|
|
line.long 0x14 "HWCFGR2,Hardware configuration"
|
|
hexmask.long 0x14 0.--31. 1. "EVENT_TRG,HW configuration event trigger"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR1,Hardware configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NBIOPORT,HW configuration of number of IO"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CPUEVTEN,HW configuration of CPU event output"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBCPUS,configuration number of"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NBEVENTS,configuration number of"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x90++0x7
|
|
line.long 0x0 "IMR2,EXTI CPU wakeup with interrupt mask"
|
|
bitfld.long 0x0 1. "IM33,CPU wakeup with interrupt mask on event" "0,1"
|
|
bitfld.long 0x0 0. "IM32,CPU wakeup with interrupt mask on event" "0,1"
|
|
line.long 0x4 "EMR2,EXTI CPU wakeup with event mask"
|
|
bitfld.long 0x4 1. "EM33,CPU wakeup with event mask on event" "0,1"
|
|
bitfld.long 0x4 0. "EM32,CPU wakeup with event mask on event" "0,1"
|
|
group.long 0x3D8++0x17
|
|
line.long 0x0 "HWCFGR7,Hardware configuration"
|
|
hexmask.long 0x0 0.--31. 1. "CPUEVENT,HW configuration CPU event"
|
|
line.long 0x4 "HWCFGR6,Hardware configuration"
|
|
hexmask.long 0x4 0.--31. 1. "CPUEVENT,HW configuration CPU event"
|
|
line.long 0x8 "HWCFGR5,Hardware configuration"
|
|
hexmask.long 0x8 0.--31. 1. "CPUEVENT,HW configuration CPU event"
|
|
line.long 0xC "HWCFGR4,Hardware configuration"
|
|
hexmask.long 0xC 0.--31. 1. "EVENT_TRG,HW configuration event trigger"
|
|
line.long 0x10 "HWCFGR3,Hardware configuration"
|
|
hexmask.long 0x10 0.--31. 1. "EVENT_TRG,HW configuration event trigger"
|
|
line.long 0x14 "HWCFGR2,Hardware configuration"
|
|
hexmask.long 0x14 0.--31. 1. "EVENT_TRG,HW configuration event trigger"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR1,Hardware configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NBIOPORT,HW configuration of number of IO"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CPUEVTEN,HW configuration of CPU event output"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBCPUS,configuration number of"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NBEVENTS,configuration number of"
|
|
line.long 0x4 "VERR,AES version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major revision"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor revision"
|
|
line.long 0x8 "IPIDR,AES identification register"
|
|
hexmask.long 0x8 0.--31. 1. "ID,Identification code"
|
|
line.long 0xC "SIDR,AES size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "ID,Size Identification code"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "FDCAN (FD Controller Area Network)"
|
|
base ad:0x0
|
|
tree "FDCAN1"
|
|
base ad:0x40006400
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,BERR" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RxFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RxFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
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bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
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|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
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hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
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bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
tree "FDCAN2"
|
|
base ad:0x40006800
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "FDCAN_CREL,FDCAN core release register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,2"
|
|
newline
|
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hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "YEAR,4"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "MON,12"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DAY,18"
|
|
line.long 0x4 "FDCAN_ENDN,FDCAN endian register"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness test value"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "FDCAN_DBTP,FDCAN data bit timing and prescaler register"
|
|
bitfld.long 0x0 23. "TDC,Transceiver delay compensation" "0: Transceiver delay compensation disabled,1: Transceiver delay compensation enabled"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DBRP,Data bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "DSJW,Synchronization jump width"
|
|
line.long 0x4 "FDCAN_TEST,FDCAN test register"
|
|
rbitfld.long 0x4 7. "RX,Receive pin" "0: The CAN bus is dominant (FDCANx_RX = 0),1: The CAN bus is recessive (FDCANx_RX = 1)"
|
|
bitfld.long 0x4 5.--6. "TX,Control of transmit pin" "0: Reset value FDCANx_TX TX is controlled by the..,1: Sample point can be monitored at pin FDCANx_TX,2: Dominant (0) level at pin FDCANx_TX,3: Recessive (1) at pin FDCANx_TX"
|
|
newline
|
|
bitfld.long 0x4 4. "LBCK,Loop back mode" "0: Reset value Loop Back mode is disabled,1: Loop Back mode is enabled (see Power down (Sleep.."
|
|
line.long 0x8 "FDCAN_RWD,FDCAN RAM watchdog register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "WDV,Watchdog value"
|
|
hexmask.long.byte 0x8 0.--7. 1. "WDC,Watchdog configuration"
|
|
line.long 0xC "FDCAN_CCCR,FDCAN CC control register"
|
|
bitfld.long 0xC 15. "NISO,Non ISO operation" "0: CAN FD frame format according to ISO11898-1,1: CAN FD frame format according to Bosch CAN FD.."
|
|
bitfld.long 0xC 14. "TXP,If this bit is set the FDCAN pauses for two CAN bit times before starting the next transmission after successfully transmitting a frame." "0: disabled,1: enabled"
|
|
newline
|
|
bitfld.long 0xC 13. "EFBI,Edge filtering during bus integration" "0: Edge filtering disabled,1: Two consecutive dominant tq required to detect.."
|
|
bitfld.long 0xC 12. "PXHD,Protocol exception handling disable" "0: Protocol exception handling enabled,1: Protocol exception handling disabled"
|
|
newline
|
|
bitfld.long 0xC 9. "BRSE,FDCAN bit rate switching" "0: Bit rate switching for transmissions disabled,1: Bit rate switching for transmissions enabled"
|
|
bitfld.long 0xC 8. "FDOE,FD operation enable" "0: FD operation disabled,1: FD operation enabled"
|
|
newline
|
|
bitfld.long 0xC 7. "TEST,Test mode enable" "0: Normal operation register TEST holds reset values,1: Test Mode write access to register TEST enabled"
|
|
bitfld.long 0xC 6. "DAR,Disable automatic retransmission" "0: Automatic retransmission of messages not..,1: Automatic retransmission disabled"
|
|
newline
|
|
bitfld.long 0xC 5. "MON,Bus monitoring mode" "0: Bus monitoring mode disabled,1: Bus monitoring mode enabled"
|
|
bitfld.long 0xC 4. "CSR,Clock stop request" "0: No clock stop requested,1: Clock stop requested. When clock stop is.."
|
|
newline
|
|
rbitfld.long 0xC 3. "CSA,Clock stop acknowledge" "0: No clock stop acknowledged,1: FDCAN may be set in power down by stopping APB.."
|
|
bitfld.long 0xC 2. "ASM,ASM restricted operation mode" "0: Normal CAN operation,1: Restricted Operation Mode active"
|
|
newline
|
|
bitfld.long 0xC 1. "CCE,Configuration change enable" "0: The CPU has no write access to the protected..,1: The CPU has write access to the protected.."
|
|
bitfld.long 0xC 0. "INIT,Initialization" "0: Normal operation,1: Initialization started"
|
|
line.long 0x10 "FDCAN_NBTP,FDCAN nominal bit timing and prescaler register"
|
|
hexmask.long.byte 0x10 25.--31. 1. "NSJW,Nominal (re)synchronization jump width"
|
|
hexmask.long.word 0x10 16.--24. 1. "NBRP,Bit rate prescaler"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "NTSEG1,Nominal time segment before sample point"
|
|
hexmask.long.byte 0x10 0.--6. 1. "NTSEG2,Nominal time segment after sample point"
|
|
line.long 0x14 "FDCAN_TSCC,FDCAN timestamp counter configuration register"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TCP,Timestamp counter prescaler"
|
|
bitfld.long 0x14 0.--1. "TSS,Timestamp select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented according to..,2: External timestamp counter from TIM3 value..,3: Same as 00."
|
|
line.long 0x18 "FDCAN_TSCV,FDCAN timestamp counter value register"
|
|
hexmask.long.word 0x18 0.--15. 1. "TSC,Timestamp counter"
|
|
line.long 0x1C "FDCAN_TOCC,FDCAN timeout counter configuration register"
|
|
hexmask.long.word 0x1C 16.--31. 1. "TOP,Timeout period"
|
|
bitfld.long 0x1C 1.--2. "TOS,Timeout select" "0: Continuous operation,1: Timeout controlled by Tx Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ETOC,Timeout counter enable" "0: Timeout counter disabled,1: Timeout counter enabled"
|
|
line.long 0x20 "FDCAN_TOCV,FDCAN timeout counter value register"
|
|
hexmask.long.word 0x20 0.--15. 1. "TOC,Timeout counter"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "FDCAN_ECR,FDCAN error counter register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN error logging"
|
|
rbitfld.long 0x0 15. "RP,Receive error passive" "0: The receive error counter is below the error..,1: The receive error counter has reached the error.."
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive error counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit error counter"
|
|
line.long 0x4 "FDCAN_PSR,FDCAN protocol status register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter delay compensation value"
|
|
bitfld.long 0x4 14. "PXE,Protocol exception event" "0: No protocol exception event occurred since last..,1: Protocol exception event occurred"
|
|
newline
|
|
bitfld.long 0x4 13. "REDL,Received FDCAN message" "0: Since this bit was reset by the CPU no FDCAN..,1: Message in FDCAN format with EDL flag set has.."
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received FDCAN message" "0: Last received FDCAN message did not have its BRS..,1: Last received FDCAN message had its BRS flag set."
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received FDCAN message" "0: Last received FDCAN message did not have its ESI..,1: Last received FDCAN message had its ESI flag set."
|
|
bitfld.long 0x4 8.--10. "DLEC,Data last error code" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
rbitfld.long 0x4 7. "BO,Bus_Off status" "0: The FDCAN is not Bus_Off.,1: The FDCAN is in Bus_Off state."
|
|
rbitfld.long 0x4 6. "EW,Warning Sstatus" "0: Both error counters are below the Error_Warning..,1: At least one of error counter has reached the.."
|
|
newline
|
|
rbitfld.long 0x4 5. "EP,Error passive" "0: The FDCAN is in the Error_Active state. It..,1: The FDCAN is in the Error_Passive state."
|
|
rbitfld.long 0x4 3.--4. "ACT,Activity" "0: Synchronizing: node is synchronizing on CAN..,1: Idle: node is neither receiver nor transmitter.,2: Receiver: node is operating as receiver.,3: Transmitter: node is operating as transmitter."
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last error code" "0: No Error: No error occurred since LEC has been..,1: Stuff Error: More than 5 equal bits in a..,2: Form Error: A fixed format part of a received..,3: AckError: The message transmitted by the FDCAN..,4: Bit1Error: During the transmission of a message..,5: Bit0Error: During the transmission of a message..,6: CRCError: The CRC check sum of a received..,7: NoChange: Any read access to the Protocol status.."
|
|
line.long 0x8 "FDCAN_TDCR,FDCAN transmitter delay compensation register"
|
|
hexmask.long.byte 0x8 8.--14. 1. "TDCO,Transmitter delay compensation offset"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TDCF,Transmitter delay compensation filter window length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "FDCAN_IR,FDCAN interrupt register"
|
|
bitfld.long 0x0 23. "ARA,Access to reserved address" "0: No access to reserved address occurred,1: Access to reserved address occurred"
|
|
bitfld.long 0x0 22. "PED,Protocol error in data phase (data bit time is used)" "0: No protocol error in data phase,1: Protocol error in data phase detected (PSR.DLEC.."
|
|
newline
|
|
bitfld.long 0x0 21. "PEA,Protocol error in arbitration phase (nominal bit time is used)" "0: No protocol error in arbitration phase,1: Protocol error in arbitration phase detected.."
|
|
bitfld.long 0x0 20. "WDI,Watchdog interrupt" "0: No message RAM watchdog event occurred,1: Message RAM watchdog event due to missing READY"
|
|
newline
|
|
bitfld.long 0x0 19. "BO,Bus_Off status" "0: Bus_Off status unchanged,1: Bus_Off status changed"
|
|
bitfld.long 0x0 18. "EW,Warning status" "0: Error_Warning status unchanged,1: Error_Warning status changed"
|
|
newline
|
|
bitfld.long 0x0 17. "EP,Error passive" "0: Error_Passive status unchanged,1: Error_Passive status changed"
|
|
bitfld.long 0x0 16. "ELO,Error logging overflow" "0: CAN error logging counter did not overflow.,1: Overflow of CAN error logging counter occurred."
|
|
newline
|
|
bitfld.long 0x0 15. "TOO,Timeout occurred" "0: No timeout,1: Timeout reached"
|
|
bitfld.long 0x0 14. "MRAF,Message RAM access failure" "0: No Message RAM access failure occurred,1: Message RAM access failure occurred"
|
|
newline
|
|
bitfld.long 0x0 13. "TSW,Timestamp wraparound" "0: No timestamp counter wrap-around,1: Timestamp counter wrapped around"
|
|
bitfld.long 0x0 12. "TEFL,Tx event FIFO element lost" "0: No Tx event FIFO element lost,1: Tx event FIFO element lost"
|
|
newline
|
|
bitfld.long 0x0 11. "TEFF,Tx event FIFO full" "0: Tx event FIFO Not full,1: Tx event FIFO full"
|
|
bitfld.long 0x0 10. "TEFN,Tx event FIFO New Entry" "0: Tx event FIFO unchanged,1: Tx handler wrote Tx event FIFO element."
|
|
newline
|
|
bitfld.long 0x0 9. "TFE,Tx FIFO empty" "0: Tx FIFO non-empty,1: Tx FIFO empty"
|
|
bitfld.long 0x0 8. "TCF,Transmission cancellation finished" "0: No transmission cancellation finished,1: Transmission cancellation finished"
|
|
newline
|
|
bitfld.long 0x0 7. "TC,Transmission completed" "0: No transmission completed,1: Transmission completed"
|
|
bitfld.long 0x0 6. "HPM,High-priority message" "0: No high-priority message received,1: High-priority message received"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost"
|
|
bitfld.long 0x0 4. "RF1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 3. "RF1N,Rx FIFO 1 new message" "0: No new message written to Rx FIFO 1,1: New message written to Rx FIFO 1"
|
|
bitfld.long 0x0 2. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 new message" "0: No new message written to Rx FIFO 0,1: New message written to Rx FIFO 0"
|
|
line.long 0x4 "FDCAN_IE,FDCAN interrupt enable register"
|
|
bitfld.long 0x4 23. "ARAE,Access to reserved address enable" "0,1"
|
|
bitfld.long 0x4 22. "PEDE,Protocol error in data phase enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "PEAE,Protocol error in arbitration phase enable" "0,1"
|
|
bitfld.long 0x4 20. "WDIE,Watchdog interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 19. "BOE,Bus_Off status" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 18. "EWE,Warning status interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 17. "EPE,Error passive interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 16. "ELOE,Error logging overflow interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 15. "TOOE,Timeout occurred interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 14. "MRAFE,Message RAM access failure interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 13. "TSWE,Timestamp wraparound interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 12. "TEFLE,Tx event FIFO element lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 11. "TEFFE,Tx event FIFO full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 10. "TEFNE,Tx event FIFO new entry interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "TFEE,Tx FIFO empty interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 8. "TCFE,Transmission cancellation finished interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 7. "TCE,Transmission completed interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 6. "HPME,High-priority message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1LE,Rx FIFO 1 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 4. "RF1FE,Rx FIFO 1 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "RF1NE,Rx FIFO 1 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 2. "RF0LE,Rx FIFO 0 message lost interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0FE,Rx FIFO 0 full interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 new message interrupt enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "FDCAN_ILS,FDCAN interrupt line select register"
|
|
bitfld.long 0x8 6. "PERR,Protocol error grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 5. "BERR,BERR" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "MISC,Interrupt regrouping the following interruption" "0,1"
|
|
bitfld.long 0x8 3. "TFERR,Tx FIFO ERROR grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "SMSG,Status message bit grouping the following interruption" "0,1"
|
|
bitfld.long 0x8 1. "RxFIFO1,RX FIFO bit grouping the following interruption" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "RxFIFO0,RX FIFO bit grouping the following interruption" "0,1"
|
|
line.long 0xC "FDCAN_ILE,FDCAN interrupt line enable register"
|
|
bitfld.long 0xC 1. "EINT1,Enable interrupt line 1" "0: Interrupt line fdcan_intr0_it disabled,1: Interrupt line fdcan_intr0_it enabled"
|
|
bitfld.long 0xC 0. "EINT0,Enable interrupt line 0" "0: Interrupt line fdcan_intr1_it disabled,1: Interrupt line fdcan_intr1_it enabled"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "FDCAN_RXGFC,FDCAN global filter configuration register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LSE,List size extended"
|
|
hexmask.long.byte 0x0 16.--20. 1. "LSS,List size standard"
|
|
newline
|
|
bitfld.long 0x0 9. "F0OM,FIFO 0 operation mode (overwrite or blocking)" "0,1"
|
|
bitfld.long 0x0 8. "F1OM,FIFO 1 operation mode (overwrite or blocking)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching frames standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept non-matching frames extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,3: Reject"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject remote frames standard" "0: Filter remote frames with 11-bit standard IDs,1: Reject all remote frames with 11-bit standard IDs"
|
|
bitfld.long 0x0 0. "RRFE,Reject remote frames extended" "0: Filter remote frames with 29-bit standard IDs,1: Reject all remote frames with 29-bit standard IDs"
|
|
line.long 0x4 "FDCAN_XIDAM,FDCAN extended ID and mask register"
|
|
hexmask.long 0x4 0.--28. 1. "EIDM,Extended ID mask"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "FDCAN_HPMS,FDCAN high-priority message status register"
|
|
bitfld.long 0x0 15. "FLST,Filter list" "0: Standard filter list,1: Extended filter list"
|
|
hexmask.long.byte 0x0 8.--12. 1. "FIDX,Filter index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message storage indicator" "0: No FIFO selected,1: FIFO overrun,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
bitfld.long 0x0 0.--2. "BIDX,Buffer index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x90++0x3
|
|
line.long 0x0 "FDCAN_RXF0S,FDCAN Rx FIFO 0 status register"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 message lost" "0: No Rx FIFO 0 message lost,1: Rx FIFO 0 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 full" "0: Rx FIFO 0 not full,1: Rx FIFO 0 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F0PI,Rx FIFO 0 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F0GI,Rx FIFO 0 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F0FL,Rx FIFO 0 fill level"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "FDCAN_RXF0A,CAN Rx FIFO 0 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F0AI,Rx FIFO 0 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "FDCAN_RXF1S,FDCAN Rx FIFO 1 status register"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 message lost" "0: No Rx FIFO 1 message lost,1: Rx FIFO 1 message lost also set after write.."
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 full" "0: Rx FIFO 1 not full,1: Rx FIFO 1 full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "F1PI,Rx FIFO 1 put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "F1GI,Rx FIFO 1 get index" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "F1FL,Rx FIFO 1 fill level"
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "FDCAN_RXF1A,FDCAN Rx FIFO 1 acknowledge register"
|
|
bitfld.long 0x0 0.--2. "F1AI,Rx FIFO 1 acknowledge index" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FDCAN_TXBC,FDCAN Tx buffer configuration register"
|
|
bitfld.long 0x0 24. "TFQM,Tx FIFO/queue mode" "0: Tx FIFO operation,1: Tx queue operation."
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x0 "FDCAN_TXFQS,FDCAN Tx FIFO/queue status register"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/queue full" "0: Tx FIFO/queue not full,1: Tx FIFO/queue full"
|
|
bitfld.long 0x0 16.--17. "TFQPI,Tx FIFO/queue put index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "TFGI,Tx FIFO get index" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TFFL,Tx FIFO free level" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "FDCAN_TXBRP,FDCAN Tx buffer request pending register"
|
|
bitfld.long 0x4 0.--2. "TRP,Transmission request pending" "0: No transmission request pending,1: Transmission request pending,?,?,?,?,?,?"
|
|
group.long 0xCC++0x7
|
|
line.long 0x0 "FDCAN_TXBAR,FDCAN Tx buffer add request register"
|
|
bitfld.long 0x0 0.--2. "AR,Add request" "0: No transmission request added,1: Transmission requested added.,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCR,FDCAN Tx buffer cancellation request register"
|
|
bitfld.long 0x4 0.--2. "CR,Cancellation request" "0: No cancellation pending,1: Cancellation pending,?,?,?,?,?,?"
|
|
rgroup.long 0xD4++0x7
|
|
line.long 0x0 "FDCAN_TXBTO,FDCAN Tx buffer transmission occurred register"
|
|
bitfld.long 0x0 0.--2. "TO,Transmission occurred." "0: No transmission occurred,1: Transmission occurred,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCF,FDCAN Tx buffer cancellation finished register"
|
|
bitfld.long 0x4 0.--2. "CF,Cancellation finished" "0: No transmit buffer cancellation,1: Transmit buffer cancellation finished,?,?,?,?,?,?"
|
|
group.long 0xDC++0x7
|
|
line.long 0x0 "FDCAN_TXBTIE,FDCAN Tx buffer transmission interrupt enable register"
|
|
bitfld.long 0x0 0.--2. "TIE,Transmission interrupt enable" "0: Transmission interrupt disabled,1: Transmission interrupt enable,?,?,?,?,?,?"
|
|
line.long 0x4 "FDCAN_TXBCIE,FDCAN Tx buffer cancellation finished interrupt enable register"
|
|
bitfld.long 0x4 0.--2. "CFIE,Cancellation finished interrupt enable." "0: Cancellation finished interrupt disabled,1: Cancellation finished interrupt enabled,?,?,?,?,?,?"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "FDCAN_TXEFS,FDCAN Tx event FIFO status register"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO element lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO full" "0: Tx event FIFO not full,1: Tx event FIFO full"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "EFPI,Event FIFO put index" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "EFGI,Event FIFO get index" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "EFFL,Event FIFO fill level" "0,1,2,3,4,5,6,7"
|
|
group.long 0xE8++0x3
|
|
line.long 0x0 "FDCAN_TXEFA,FDCAN Tx event FIFO acknowledge register"
|
|
bitfld.long 0x0 0.--1. "EFAI,Event FIFO acknowledge index" "0,1,2,3"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "FDCAN_CKDIV,FDCAN CFG clock divider register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PDIV,input clock divider"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "FLASH (Embedded Flash Memory)"
|
|
base ad:0x40022000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "ACR,Access control register"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 18. "DBG_SWEN,Debug access software" "0,1"
|
|
endif
|
|
bitfld.long 0x0 16. "EMPTY,Flash User area empty" "0,1"
|
|
bitfld.long 0x0 11. "ICRST,Instruction cache reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ICEN,Instruction cache enable" "0,1"
|
|
bitfld.long 0x0 8. "PRFTEN,Prefetch enable" "0,1"
|
|
bitfld.long 0x0 0.--2. "LATENCY,Latency" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "KEYR,Flash key register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYR,KEYR"
|
|
line.long 0x4 "OPTKEYR,Option byte key register"
|
|
hexmask.long 0x4 0.--31. 1. "OPTKEYR,Option byte key"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 18. "CFGBSY,Programming or erase configuration" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x0 17. "BSY2,BSY2" "0,1"
|
|
bitfld.long 0x0 16. "BSY1,BSY1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 17. "BSY2,BSY2" "0,1"
|
|
bitfld.long 0x0 16. "BSY1,BSY1" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 17. "BSY2,BSY2" "0,1"
|
|
bitfld.long 0x0 16. "BSY1,BSY1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 17. "BSY2,BSY2" "0,1"
|
|
bitfld.long 0x0 16. "BSY1,BSY1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 16. "BSY,Busy" "0,1"
|
|
endif
|
|
bitfld.long 0x0 15. "OPTVERR,Option and Engineering bits loading" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 14. "RDERR,PCROP read error" "0,1"
|
|
endif
|
|
bitfld.long 0x0 9. "FASTERR,Fast programming error" "0,1"
|
|
bitfld.long 0x0 8. "MISERR,Fast programming data miss" "0,1"
|
|
bitfld.long 0x0 7. "PGSERR,Programming sequence error" "0,1"
|
|
bitfld.long 0x0 6. "SIZERR,Size error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PGAERR,Programming alignment" "0,1"
|
|
bitfld.long 0x0 4. "WRPERR,Write protected error" "0,1"
|
|
bitfld.long 0x0 3. "PROGERR,Programming error" "0,1"
|
|
bitfld.long 0x0 1. "OPERR,Operation error" "0,1"
|
|
bitfld.long 0x0 0. "EOP,End of operation" "0,1"
|
|
line.long 0x4 "CR,Flash control register"
|
|
bitfld.long 0x4 31. "LOCK,FLASH_CR Lock" "0,1"
|
|
bitfld.long 0x4 30. "OPTLOCK,Options Lock" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 28. "SEC_PROT,Securable memory area protection" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 27. "OBL_LAUNCH,Force the option byte" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 26. "RDERRIE,PCROP read error interrupt" "0,1"
|
|
endif
|
|
bitfld.long 0x4 25. "ERRIE,Error interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "EOPIE,End of operation interrupt" "0,1"
|
|
bitfld.long 0x4 18. "FSTPG,Fast programming" "0,1"
|
|
bitfld.long 0x4 17. "OPTSTRT,Options modification start" "0,1"
|
|
bitfld.long 0x4 16. "STRT,Start" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x4 15. "MER2,MER2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "BKER,BKER" "0,1"
|
|
hexmask.long.word 0x4 3.--12. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER1,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 15. "MER2,MER2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 15. "MER2,MER2" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 15. "MER2,MER2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 13. "BKER,BKER" "0,1"
|
|
hexmask.long.word 0x4 3.--12. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER1,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 13. "BKER,BKER" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 3.--12. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER1,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 13. "BKER,BKER" "0,1"
|
|
hexmask.long.word 0x4 3.--12. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER1,Mass erase" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
newline
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x4 3.--8. 1. "PNB,Page number"
|
|
newline
|
|
bitfld.long 0x4 2. "MER,Mass erase" "0,1"
|
|
endif
|
|
bitfld.long 0x4 1. "PER,Page erase" "0,1"
|
|
bitfld.long 0x4 0. "PG,Programming" "0,1"
|
|
line.long 0x8 "ECCR,Flash ECC register"
|
|
bitfld.long 0x8 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x8 30. "ECCC,ECC correction" "0,1"
|
|
bitfld.long 0x8 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x8 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
hexmask.long.word 0x8 0.--13. 1. "ADDR_ECC,ECC fail address"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.word 0x8 0.--13. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.word 0x8 0.--13. 1. "ADDR_ECC,ECC fail address"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.word 0x8 0.--13. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.word 0x8 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
line.long 0x4 "PCROP1BER,Flash PCROP zone B End address"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
line.long 0x4 "PCROP1BER,Flash PCROP zone B End address"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PCROP1BER,Flash PCROP area B End address"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PCROP2ASR,Flash PCROP2 area A start address register"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP2A_STRT,PCROP2A area start offset bank2"
|
|
line.long 0x4 "PCROP2AER,Flash PCROP2 area A end address register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP2A_END,PCROP2A area end offset bank2"
|
|
line.long 0x8 "WRP2AR,Flash WRP2 area A address register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "WRP2A_END,WRP area A end offset Bank 2"
|
|
hexmask.long.byte 0x8 0.--6. 1. "WRP2A_STRT,WRP area A start offset Bank 2"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PCROP1BER,Flash PCROP area B End address"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
group.long 0x44++0x17
|
|
line.long 0x0 "PCROP2ASR,Flash PCROP2 area A start address register"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP2A_STRT,PCROP2A area start offset bank2"
|
|
line.long 0x4 "PCROP2AER,Flash PCROP2 area A end address register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP2A_END,PCROP2A area end offset bank2"
|
|
line.long 0x8 "WRP2AR,Flash WRP2 area A address register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "WRP2A_END,WRP area A end offset Bank 2"
|
|
hexmask.long.byte 0x8 0.--6. 1. "WRP2A_STRT,WRP area A start offset Bank 2"
|
|
line.long 0xC "WRP2BR,Flash WRP2 area B address register"
|
|
hexmask.long.byte 0xC 16.--22. 1. "WRP2B_END,WRP area B end offset Bank 2"
|
|
hexmask.long.byte 0xC 0.--6. 1. "WRP2B_STRT,WRP area B start offset Bank 2"
|
|
line.long 0x10 "PCROP2BSR,FLASH PCROP2 area B start address register"
|
|
hexmask.long.word 0x10 0.--8. 1. "PCROP2B_STRT,PCROP2B area start offset Bank 2"
|
|
line.long 0x14 "PCROP2BER,FLASH PCROP2 area B end address register"
|
|
hexmask.long.word 0x14 0.--8. 1. "PCROP2B_END,PCROP2B area end offset Bank 2"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
line.long 0x4 "PCROP1BER,Flash PCROP zone B End address"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x7
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
line.long 0x4 "PCROP1BER,Flash PCROP zone B End address"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PCROP1BER,Flash PCROP area B End address"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "PCROP2ASR,Flash PCROP2 area A start address register"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP2A_STRT,PCROP2A area start offset bank2"
|
|
line.long 0x4 "PCROP2AER,Flash PCROP2 area A end address register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP2A_END,PCROP2A area end offset bank2"
|
|
line.long 0x8 "WRP2AR,Flash WRP2 area A address register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "WRP2A_END,WRP area A end offset Bank 2"
|
|
hexmask.long.byte 0x8 0.--6. 1. "WRP2A_STRT,WRP area A start offset Bank 2"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "ECCR2,Flash ECC register 2"
|
|
bitfld.long 0x0 31. "ECCD,ECC detection" "0,1"
|
|
bitfld.long 0x0 30. "ECCC,ECC correction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "ECCIE,ECC correction interrupt" "0,1"
|
|
rbitfld.long 0x0 20. "SYSF_ECC,ECC fail for Corrected ECC Error or" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--14. 1. "ADDR_ECC,ECC fail address"
|
|
rgroup.long 0x24++0x7
|
|
line.long 0x0 "PCROP1ASR,Flash PCROP zone A Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1A_STRT,PCROP1A area start offset"
|
|
line.long 0x4 "PCROP1AER,Flash PCROP zone A End address"
|
|
bitfld.long 0x4 31. "PCROP_RDP,PCROP area preserved when RDP level" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "PCROP1A_END,PCROP1A area end offset"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "PCROP1BSR,Flash PCROP zone B Start address"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PCROP1B_STRT,PCROP1B area start offset"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PCROP1BER,Flash PCROP area B End address"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP1B_END,PCROP1B area end offset"
|
|
group.long 0x44++0x17
|
|
line.long 0x0 "PCROP2ASR,Flash PCROP2 area A start address register"
|
|
hexmask.long.word 0x0 0.--8. 1. "PCROP2A_STRT,PCROP2A area start offset bank2"
|
|
line.long 0x4 "PCROP2AER,Flash PCROP2 area A end address register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP2A_END,PCROP2A area end offset bank2"
|
|
line.long 0x8 "WRP2AR,Flash WRP2 area A address register"
|
|
hexmask.long.byte 0x8 16.--22. 1. "WRP2A_END,WRP area A end offset Bank 2"
|
|
hexmask.long.byte 0x8 0.--6. 1. "WRP2A_STRT,WRP area A start offset Bank 2"
|
|
line.long 0xC "WRP2BR,Flash WRP2 area B address register"
|
|
hexmask.long.byte 0xC 16.--22. 1. "WRP2B_END,WRP area B end offset Bank 2"
|
|
hexmask.long.byte 0xC 0.--6. 1. "WRP2B_STRT,WRP area B start offset Bank 2"
|
|
line.long 0x10 "PCROP2BSR,FLASH PCROP2 area B start address register"
|
|
hexmask.long.word 0x10 0.--8. 1. "PCROP2B_STRT,PCROP2B area start offset Bank 2"
|
|
line.long 0x14 "PCROP2BER,FLASH PCROP2 area B end address register"
|
|
hexmask.long.word 0x14 0.--8. 1. "PCROP2B_END,PCROP2B area end offset Bank 2"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "OPTR,Flash option register"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 29. "IRHEN,Internal reset holder enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27.--28. "NRST_MODE,NRST_MODE" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x0 26. "nBOOT0,nBOOT0 option bit" "0,1"
|
|
bitfld.long 0x0 25. "nBOOT1,Boot configuration" "0,1"
|
|
bitfld.long 0x0 24. "nBOOT_SEL,nBOOT_SEL" "0,1"
|
|
bitfld.long 0x0 22. "RAM_PARITY_CHECK,SRAM parity check control" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x0 21. "DUAL_BANK,DUAL_BANK" "0,1"
|
|
bitfld.long 0x0 20. "nSWAP_BANK,nSWAP_BANK" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 21. "DUAL_BANK,DUAL_BANK" "0,1"
|
|
bitfld.long 0x0 20. "nSWAP_BANK,nSWAP_BANK" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 21. "DUAL_BANK,DUAL_BANK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "nSWAP_BANK,nSWAP_BANK" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 21. "DUAL_BANK,DUAL_BANK" "0,1"
|
|
bitfld.long 0x0 20. "nSWAP_BANK,nSWAP_BANK" "0,1"
|
|
endif
|
|
bitfld.long 0x0 19. "WWDG_SW,Window watchdog selection" "0,1"
|
|
bitfld.long 0x0 18. "IWDG_STDBY,Independent watchdog counter freeze in" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "IWDG_STOP,Independent watchdog counter freeze in" "0,1"
|
|
bitfld.long 0x0 16. "IDWG_SW,Independent watchdog" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 15. "nRSTS_HDW,nRSTS_HDW" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 14. "nRST_STDBY,nRST_STDBY" "0,1"
|
|
bitfld.long 0x0 13. "nRST_STOP,nRST_STOP" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 11.--12. "BORR_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
bitfld.long 0x0 9.--10. "BORF_LEV,These bits contain the VDD supply level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "BOREN,BOR reset Level" "0,1"
|
|
endif
|
|
hexmask.long.byte 0x0 0.--7. 1. "RDP,Read protection level"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "WRP1AR,Flash WRP area A address"
|
|
sif (cpuis("STM32G030*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x0 16.--21. 1. "WRP1A_END,WRP area A end offset"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x0 0.--5. 1. "WRP1A_STRT,WRP area A start offset"
|
|
endif
|
|
line.long 0x4 "WRP1BR,Flash WRP area B address"
|
|
sif (cpuis("STM32G030*"))
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x4 16.--21. 1. "WRP1B_END,WRP area B end offset"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x4 0.--5. 1. "WRP1B_STRT,WRP area B start offset"
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "WRP2AR,FLASH WRP2 area A address register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP2A_END,WRP2A_END"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP2A_STRT,WRP2A_STRT"
|
|
line.long 0x4 "WRP2BR,FLASH WRP2 area B address register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP2B_END,WRP2B_END"
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP2B_STRT,WRP2B_STRT"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "WRP2AR,FLASH WRP2 area A address register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP2A_END,WRP2A_END"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP2A_STRT,WRP2A_STRT"
|
|
line.long 0x4 "WRP2BR,FLASH WRP2 area B address register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP2B_END,WRP2B_END"
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP2B_STRT,WRP2B_STRT"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "WRP2BR,Flash WRP2 area B address register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP2B_END,WRP area B end offset Bank 2"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP2B_STRT,WRP area B start offset Bank 2"
|
|
line.long 0x4 "PCROP2BSR,FLASH PCROP2 area B start address register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP2B_STRT,PCROP2B area start offset Bank 2"
|
|
line.long 0x8 "PCROP2BER,FLASH PCROP2 area B end address register"
|
|
hexmask.long.word 0x8 0.--8. 1. "PCROP2B_END,PCROP2B area end offset Bank 2"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
hexmask.long.byte 0x0 20.--27. 1. "SEC_SIZE2,Securable memory area size"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
hexmask.long.byte 0x0 20.--27. 1. "SEC_SIZE2,Securable memory area size"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "WRP2AR,FLASH WRP2 area A address register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP2A_END,WRP2A_END"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP2A_STRT,WRP2A_STRT"
|
|
line.long 0x4 "WRP2BR,FLASH WRP2 area B address register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP2B_END,WRP2B_END"
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP2B_STRT,WRP2B_STRT"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x4C++0x7
|
|
line.long 0x0 "WRP2AR,FLASH WRP2 area A address register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP2A_END,WRP2A_END"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP2A_STRT,WRP2A_STRT"
|
|
line.long 0x4 "WRP2BR,FLASH WRP2 area B address register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "WRP2B_END,WRP2B_END"
|
|
hexmask.long.byte 0x4 0.--6. 1. "WRP2B_STRT,WRP2B_STRT"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "WRP2BR,Flash WRP2 area B address register"
|
|
hexmask.long.byte 0x0 16.--22. 1. "WRP2B_END,WRP area B end offset Bank 2"
|
|
hexmask.long.byte 0x0 0.--6. 1. "WRP2B_STRT,WRP area B start offset Bank 2"
|
|
line.long 0x4 "PCROP2BSR,FLASH PCROP2 area B start address register"
|
|
hexmask.long.word 0x4 0.--8. 1. "PCROP2B_STRT,PCROP2B area start offset Bank 2"
|
|
line.long 0x8 "PCROP2BER,FLASH PCROP2 area B end address register"
|
|
hexmask.long.word 0x8 0.--8. 1. "PCROP2B_END,PCROP2B area end offset Bank 2"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
hexmask.long.byte 0x0 20.--27. 1. "SEC_SIZE2,Securable memory area size"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "SECR,Flash Security register"
|
|
hexmask.long.byte 0x0 20.--27. 1. "SEC_SIZE2,Securable memory area size"
|
|
bitfld.long 0x0 16. "BOOT_LOCK,used to force boot from user" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "SEC_SIZE,Securable memory area size"
|
|
endif
|
|
tree.end
|
|
tree "GPIO (General-Purpose I/Os)"
|
|
base ad:0x0
|
|
tree "GPIOA"
|
|
base ad:0x50000000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOB"
|
|
base ad:0x50000400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOC"
|
|
base ad:0x50000800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree "GPIOD"
|
|
base ad:0x50000C00
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
sif (cpuis("STM32G050*"))
|
|
tree "GPIOE"
|
|
base ad:0x50001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "GPIOE"
|
|
base ad:0x50001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "GPIOE"
|
|
base ad:0x50001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "GPIOE"
|
|
base ad:0x50001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "GPIOE"
|
|
base ad:0x50001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "GPIOE"
|
|
base ad:0x50001000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "GPIOF"
|
|
base ad:0x50001400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "MODER,GPIO port mode register"
|
|
bitfld.long 0x0 30.--31. "MODER15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 28.--29. "MODER14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "MODER13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "MODER12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 22.--23. "MODER11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "MODER10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 18.--19. "MODER9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 16.--17. "MODER8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 14.--15. "MODER7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 12.--13. "MODER6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "MODER5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "MODER4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 6.--7. "MODER3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "MODER2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "MODER1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "MODER0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0x4 "OTYPER,GPIO port output type register"
|
|
bitfld.long 0x4 15. "OT15,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 14. "OT14,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 13. "OT13,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 12. "OT12,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 11. "OT11,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 10. "OT10,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 9. "OT9,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 8. "OT8,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 7. "OT7,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 6. "OT6,Port x configuration bits (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OT5,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 4. "OT4,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 3. "OT3,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 2. "OT2,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 1. "OT1,Port x configuration bits (y =" "0,1"
|
|
bitfld.long 0x4 0. "OT0,Port x configuration bits (y =" "0,1"
|
|
line.long 0x8 "OSPEEDR,GPIO port output speed"
|
|
bitfld.long 0x8 30.--31. "OSPEEDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 28.--29. "OSPEEDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 26.--27. "OSPEEDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 24.--25. "OSPEEDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 22.--23. "OSPEEDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 20.--21. "OSPEEDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 18.--19. "OSPEEDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 16.--17. "OSPEEDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 14.--15. "OSPEEDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 12.--13. "OSPEEDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 10.--11. "OSPEEDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 8.--9. "OSPEEDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 6.--7. "OSPEEDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 4.--5. "OSPEEDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 2.--3. "OSPEEDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0x8 0.--1. "OSPEEDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
line.long 0xC "PUPDR,GPIO port pull-up/pull-down"
|
|
bitfld.long 0xC 30.--31. "PUPDR15,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 28.--29. "PUPDR14,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 26.--27. "PUPDR13,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 24.--25. "PUPDR12,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 22.--23. "PUPDR11,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 20.--21. "PUPDR10,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 18.--19. "PUPDR9,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 16.--17. "PUPDR8,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 14.--15. "PUPDR7,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 12.--13. "PUPDR6,Port x configuration bits (y =" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "PUPDR5,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 8.--9. "PUPDR4,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 6.--7. "PUPDR3,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 4.--5. "PUPDR2,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 2.--3. "PUPDR1,Port x configuration bits (y =" "0,1,2,3"
|
|
bitfld.long 0xC 0.--1. "PUPDR0,Port x configuration bits (y =" "0,1,2,3"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "IDR,GPIO port input data register"
|
|
bitfld.long 0x0 15. "IDR15,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 14. "IDR14,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 13. "IDR13,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 12. "IDR12,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 11. "IDR11,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 10. "IDR10,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 9. "IDR9,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 8. "IDR8,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 7. "IDR7,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 6. "IDR6,Port input data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "IDR5,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 4. "IDR4,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 3. "IDR3,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 2. "IDR2,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 1. "IDR1,Port input data (y =" "0,1"
|
|
bitfld.long 0x0 0. "IDR0,Port input data (y =" "0,1"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "ODR,GPIO port output data register"
|
|
bitfld.long 0x0 15. "ODR15,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 14. "ODR14,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 13. "ODR13,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 12. "ODR12,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 11. "ODR11,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 10. "ODR10,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 9. "ODR9,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 8. "ODR8,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 7. "ODR7,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 6. "ODR6,Port output data (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ODR5,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 4. "ODR4,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 3. "ODR3,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 2. "ODR2,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 1. "ODR1,Port output data (y =" "0,1"
|
|
bitfld.long 0x0 0. "ODR0,Port output data (y =" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "BSRR,GPIO port bit set/reset"
|
|
bitfld.long 0x0 31. "BR15,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 30. "BR14,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 29. "BR13,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 28. "BR12,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 27. "BR11,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 26. "BR10,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 25. "BR9,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 24. "BR8,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 23. "BR7,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 22. "BR6,Port x reset bit y (y =" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "BR5,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 20. "BR4,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 19. "BR3,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 18. "BR2,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 17. "BR1,Port x reset bit y (y =" "0,1"
|
|
bitfld.long 0x0 16. "BR0,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "BS15,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "BS14,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "BS13,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "BS12,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "BS11,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "BS10,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "BS9,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "BS8,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "BS7,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 6. "BS6,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "BS5,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "BS4,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "BS3,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "BS2,Port x set bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "BS1,Port x set bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "BS0,Port x set bit y (y=" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "LCKR,GPIO port configuration lock"
|
|
bitfld.long 0x0 16. "LCKK,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 15. "LCK15,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 14. "LCK14,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 13. "LCK13,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 12. "LCK12,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 11. "LCK11,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 10. "LCK10,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 9. "LCK9,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 8. "LCK8,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 7. "LCK7,Port x lock bit y (y=" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LCK6,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 5. "LCK5,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 4. "LCK4,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 3. "LCK3,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 2. "LCK2,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 1. "LCK1,Port x lock bit y (y=" "0,1"
|
|
bitfld.long 0x0 0. "LCK0,Port x lock bit y (y=" "0,1"
|
|
line.long 0x4 "AFRL,GPIO alternate function low"
|
|
hexmask.long.byte 0x4 28.--31. 1. "AFSEL7,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 24.--27. 1. "AFSEL6,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 20.--23. 1. "AFSEL5,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 16.--19. 1. "AFSEL4,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 12.--15. 1. "AFSEL3,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 8.--11. 1. "AFSEL2,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 4.--7. 1. "AFSEL1,Alternate function selection for port x"
|
|
hexmask.long.byte 0x4 0.--3. 1. "AFSEL0,Alternate function selection for port x"
|
|
line.long 0x8 "AFRH,GPIO alternate function high"
|
|
hexmask.long.byte 0x8 28.--31. 1. "AFSEL15,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 24.--27. 1. "AFSEL14,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 20.--23. 1. "AFSEL13,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 16.--19. 1. "AFSEL12,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 12.--15. 1. "AFSEL11,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 8.--11. 1. "AFSEL10,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 4.--7. 1. "AFSEL9,Alternate function selection for port x"
|
|
hexmask.long.byte 0x8 0.--3. 1. "AFSEL8,Alternate function selection for port x"
|
|
wgroup.long 0x28++0x3
|
|
line.long 0x0 "BRR,port bit reset register"
|
|
bitfld.long 0x0 15. "BR15,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 14. "BR14,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 13. "BR13,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 12. "BR12,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 11. "BR11,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 10. "BR10,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 9. "BR9,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 8. "BR8,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 7. "BR7,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 6. "BR6,Port Reset bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "BR5,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 4. "BR4,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 3. "BR3,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 2. "BR2,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 1. "BR1,Port Reset bit" "0,1"
|
|
bitfld.long 0x0 0. "BR0,Port Reset bit" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "I2C (Inter-Integrated Circuit)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
newline
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
newline
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0,1"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBUS alert enable" "0,1"
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default address" "0,1"
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host address enable" "0,1"
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0,1"
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from STOP enable" "0,1"
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0,1"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0,1"
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests" "0,1"
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "STOPIE,STOP detection Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received interrupt" "0,1"
|
|
bitfld.long 0x0 3. "ADDRIE,Address match interrupt enable (slave" "0,1"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0,1"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master" "0,1"
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave" "0,1"
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master" "0,1"
|
|
bitfld.long 0x4 13. "START,Start generation" "0,1"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read" "0,1"
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address bit (master"
|
|
line.long 0x8 "OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0,1"
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0,1"
|
|
bitfld.long 0x8 8.--9. "OA1_8_9,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x8 1.--7. 1. "OA1_7_1,Interface address"
|
|
bitfld.long 0x8 0. "OA1_0,Interface address" "0,1"
|
|
line.long 0xC "OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0,1"
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout" "0,1"
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0,1"
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout" "0,1"
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus timeout A"
|
|
line.long 0x18 "ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave" "0,1"
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40008800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40008800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40008800
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "I2C_CR1,Control register 1"
|
|
bitfld.long 0x0 23. "PECEN,PEC enable" "0: PEC calculation disabled,1: PEC calculation enabled"
|
|
bitfld.long 0x0 22. "ALERTEN,SMBus alert enable" "0: The SMBus alert pin (SMBA) is not supported in..,1: The SMBus alert pin is supported in host mode.."
|
|
newline
|
|
bitfld.long 0x0 21. "SMBDEN,SMBus Device Default Address enable" "0: Device Default Address disabled. Address..,1: Device Default Address enabled. Address.."
|
|
bitfld.long 0x0 20. "SMBHEN,SMBus Host Address enable" "0: Host Address disabled. Address 0b0001000x is..,1: Host Address enabled. Address 0b0001000x is ACKed."
|
|
newline
|
|
bitfld.long 0x0 19. "GCEN,General call enable" "0: General call disabled. Address 0b00000000 is..,1: General call enabled. Address 0b00000000 is ACKed."
|
|
bitfld.long 0x0 18. "WUPEN,Wakeup from Stop mode enable" "0: Wakeup from Stop mode disable.,1: Wakeup from Stop mode enable."
|
|
newline
|
|
bitfld.long 0x0 17. "NOSTRETCH,Clock stretching disable" "0: Clock stretching enabled,1: Clock stretching disabled"
|
|
bitfld.long 0x0 16. "SBC,Slave byte control" "0: Slave byte control disabled,1: Slave byte control enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "RXDMAEN,DMA reception requests enable" "0: DMA mode disabled for reception,1: DMA mode enabled for reception"
|
|
bitfld.long 0x0 14. "TXDMAEN,DMA transmission requests enable" "0: DMA mode disabled for transmission,1: DMA mode enabled for transmission"
|
|
newline
|
|
bitfld.long 0x0 12. "ANFOFF,Analog noise filter OFF" "0: Analog noise filter enabled,1: Analog noise filter disabled"
|
|
hexmask.long.byte 0x0 8.--11. 1. "DNF,Digital noise filter"
|
|
newline
|
|
bitfld.long 0x0 7. "ERRIE,Error interrupts enable" "0: Error detection interrupts disabled,1: Error detection interrupts enabled"
|
|
bitfld.long 0x0 6. "TCIE,Transfer Complete interrupt enable" "0: Transfer Complete interrupt disabled,1: Transfer Complete interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPIE,Stop detection Interrupt enable" "0: Stop detection (STOPF) interrupt disabled,1: Stop detection (STOPF) interrupt enabled"
|
|
bitfld.long 0x0 4. "NACKIE,Not acknowledge received Interrupt enable" "0: Not acknowledge (NACKF) received interrupts..,1: Not acknowledge (NACKF) received interrupts.."
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRIE,Address match Interrupt enable (slave only)" "0: Address match (ADDR) interrupts disabled,1: Address match (ADDR) interrupts enabled"
|
|
bitfld.long 0x0 2. "RXIE,RX Interrupt enable" "0: Receive (RXNE) interrupt disabled,1: Receive (RXNE) interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "TXIE,TX Interrupt enable" "0: Transmit (TXIS) interrupt disabled,1: Transmit (TXIS) interrupt enabled"
|
|
bitfld.long 0x0 0. "PE,Peripheral enable" "0: Peripheral disable,1: Peripheral enable"
|
|
line.long 0x4 "I2C_CR2,Control register 2"
|
|
bitfld.long 0x4 26. "PECBYTE,Packet error checking byte" "0: No PEC transfer.,1: PEC transmission/reception is requested"
|
|
bitfld.long 0x4 25. "AUTOEND,Automatic end mode (master mode)" "0: software end mode: TC flag is set when NBYTES..,1: Automatic end mode: a STOP condition is.."
|
|
newline
|
|
bitfld.long 0x4 24. "RELOAD,NBYTES reload mode" "0: The transfer is completed after the NBYTES data..,1: The transfer is not completed after the NBYTES.."
|
|
hexmask.long.byte 0x4 16.--23. 1. "NBYTES,Number of bytes"
|
|
newline
|
|
bitfld.long 0x4 15. "NACK,NACK generation (slave mode)" "0: an ACK is sent after current received byte.,1: a NACK is sent after current received byte."
|
|
bitfld.long 0x4 14. "STOP,Stop generation (master mode)" "0: No Stop generation.,1: Stop generation after current byte transfer."
|
|
newline
|
|
bitfld.long 0x4 13. "START,Start generation" "0: No Start generation.,1: Restart/Start generation:"
|
|
bitfld.long 0x4 12. "HEAD10R,10-bit address header only read direction (master receiver mode)" "0: The master sends the complete 10 bit slave..,1: The master only sends the 1st 7 bits of the 10.."
|
|
newline
|
|
bitfld.long 0x4 11. "ADD10,10-bit addressing mode (master mode)" "0: The master operates in 7-bit addressing mode,1: The master operates in 10-bit addressing mode"
|
|
bitfld.long 0x4 10. "RD_WRN,Transfer direction (master mode)" "0: Master requests a write transfer.,1: Master requests a read transfer."
|
|
newline
|
|
hexmask.long.word 0x4 0.--9. 1. "SADD,Slave address (master mode)"
|
|
line.long 0x8 "I2C_OAR1,Own address register 1"
|
|
bitfld.long 0x8 15. "OA1EN,Own Address 1 enable" "0: Own address 1 disabled. The received slave..,1: Own address 1 enabled. The received slave.."
|
|
bitfld.long 0x8 10. "OA1MODE,Own Address 1 10-bit mode" "0: Own address 1 is a 7-bit address.,1: Own address 1 is a 10-bit address."
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "OA1,Interface own slave address"
|
|
line.long 0xC "I2C_OAR2,Own address register 2"
|
|
bitfld.long 0xC 15. "OA2EN,Own Address 2 enable" "0: Own address 2 disabled. The received slave..,1: Own address 2 enabled. The received slave.."
|
|
bitfld.long 0xC 8.--10. "OA2MSK,Own Address 2 masks" "0: No mask,1: OA2[1] is masked and don't care. Only OA2[7:2]..,2: OA2[2:1] are masked and don't care. Only..,3: OA2[3:1] are masked and don't care. Only..,4: OA2[4:1] are masked and don't care. Only..,5: OA2[5:1] are masked and don't care. Only..,6: OA2[6:1] are masked and don't care. Only OA2[7]..,7: OA2[7:1] are masked and don't care. No.."
|
|
newline
|
|
hexmask.long.byte 0xC 1.--7. 1. "OA2,Interface address"
|
|
line.long 0x10 "I2C_TIMINGR,Timing register"
|
|
hexmask.long.byte 0x10 28.--31. 1. "PRESC,Timing prescaler"
|
|
hexmask.long.byte 0x10 20.--23. 1. "SCLDEL,Data setup time"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--19. 1. "SDADEL,Data hold time"
|
|
hexmask.long.byte 0x10 8.--15. 1. "SCLH,SCL high period (master"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "SCLL,SCL low period (master"
|
|
line.long 0x14 "I2C_TIMEOUTR,Status register 1"
|
|
bitfld.long 0x14 31. "TEXTEN,Extended clock timeout enable" "0: Extended clock timeout detection is disabled,1: Extended clock timeout detection is enabled."
|
|
hexmask.long.word 0x14 16.--27. 1. "TIMEOUTB,Bus timeout B"
|
|
newline
|
|
bitfld.long 0x14 15. "TIMOUTEN,Clock timeout enable" "0: SCL timeout detection is disabled,1: SCL timeout detection is enabled: when SCL is.."
|
|
bitfld.long 0x14 12. "TIDLE,Idle clock timeout detection" "0: TIMEOUTA is used to detect SCL low timeout,1: TIMEOUTA is used to detect both SCL and SDA high.."
|
|
newline
|
|
hexmask.long.word 0x14 0.--11. 1. "TIMEOUTA,Bus Timeout A"
|
|
line.long 0x18 "I2C_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. "ADDCODE,Address match code (Slave"
|
|
rbitfld.long 0x18 16. "DIR,Transfer direction (Slave mode)" "0: Write transfer slave enters receiver mode.,1: Read transfer slave enters transmitter mode."
|
|
newline
|
|
rbitfld.long 0x18 15. "BUSY,Bus busy" "0,1"
|
|
rbitfld.long 0x18 13. "ALERT,SMBus alert" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 12. "TIMEOUT,Timeout or t_low detection" "0,1"
|
|
rbitfld.long 0x18 11. "PECERR,PEC Error in reception" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 10. "OVR,Overrun/Underrun (slave" "0,1"
|
|
rbitfld.long 0x18 9. "ARLO,Arbitration lost" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 8. "BERR,Bus error" "0,1"
|
|
rbitfld.long 0x18 7. "TCR,Transfer Complete Reload" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 6. "TC,Transfer Complete (master" "0,1"
|
|
rbitfld.long 0x18 5. "STOPF,Stop detection flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 4. "NACKF,Not acknowledge received" "0,1"
|
|
rbitfld.long 0x18 3. "ADDR,Address matched (slave" "0,1"
|
|
newline
|
|
rbitfld.long 0x18 2. "RXNE,Receive data register not empty" "0,1"
|
|
bitfld.long 0x18 1. "TXIS,Transmit interrupt status" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "TXE,Transmit data register empty" "0,1"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "I2C_ICR,Interrupt clear register"
|
|
bitfld.long 0x0 13. "ALERTCF,Alert flag clear" "0,1"
|
|
bitfld.long 0x0 12. "TIMOUTCF,Timeout detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PECCF,PEC Error flag clear" "0,1"
|
|
bitfld.long 0x0 10. "OVRCF,Overrun/Underrun flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARLOCF,Arbitration lost flag" "0,1"
|
|
bitfld.long 0x0 8. "BERRCF,Bus error flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "STOPCF,Stop detection flag clear" "0,1"
|
|
bitfld.long 0x0 4. "NACKCF,Not Acknowledge flag clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ADDRCF,Address Matched flag clear" "0,1"
|
|
rgroup.long 0x20++0x7
|
|
line.long 0x0 "I2C_PECR,PEC register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PEC,Packet error checking"
|
|
line.long 0x4 "I2C_RXDR,Receive data register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,8-bit receive data"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "I2C_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,8-bit transmit data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "IWDG (Independent Watchdog)"
|
|
base ad:0x40003000
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,Prescaler default value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WINDOW,Support of Window function"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,Prescaler default value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WINDOW,Support of Window function"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PR_DEFAULT,Prescaler default value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "WINDOW,Support of Window function"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x0 0.--15. 1. "KEY,Key value (write only read"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x0 0.--2. "PR,Prescaler divider" "0: divider /4,1: divider /8,2: divider /16,3: divider /32,4: divider /64,5: divider /128,6: divider /256,7: divider /256"
|
|
line.long 0x4 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x4 0.--11. 1. "RL,Watchdog counter reload"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "IWDG_SR,Status register"
|
|
bitfld.long 0x0 2. "WVU,Watchdog counter window value update" "0,1"
|
|
bitfld.long 0x0 1. "RVU,Watchdog counter reload value update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PVU,Watchdog prescaler value update" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x0 0.--11. 1. "WIN,Watchdog counter window"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "LPTIM (Low-Power Timer)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G051*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
sif (cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G051*"))
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
sif (cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to" "0,1"
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down Clear" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP Clear" "0,1"
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK Clear" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK Clear" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge Clear" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match Clear" "0,1"
|
|
bitfld.long 0x0 0. "CMPMCF,compare match Clear Flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt" "0,1"
|
|
line.long 0x4 "CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0,1"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0,1"
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0,1"
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0,1"
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0,1"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0,1"
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and" "0,1,2,3"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external" "0,1,2,3"
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0,1,2,3"
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0,1"
|
|
line.long 0x8 "CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in continuous" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in single mode" "0,1"
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM Enable" "0,1"
|
|
line.long 0xC "CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM1 Input 2 selection" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIMx Input 1 selection" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "LPTIM1"
|
|
base ad:0x40007C00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
tree.end
|
|
tree "LPTIM2"
|
|
base ad:0x40009400
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "LPTIM_ISR,Interrupt and Status Register"
|
|
bitfld.long 0x0 6. "DOWN,Counter direction change up to down" "0,1"
|
|
bitfld.long 0x0 5. "UP,Counter direction change down to up" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROK,Autoreload register update OK" "0,1"
|
|
bitfld.long 0x0 3. "CMPOK,Compare register update OK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIG,External trigger edge event" "0,1"
|
|
bitfld.long 0x0 1. "ARRM,Autoreload match" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPM,Compare match" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "LPTIM_ICR,Interrupt Clear Register"
|
|
bitfld.long 0x0 6. "DOWNCF,Direction change to down clear flag" "0,1"
|
|
bitfld.long 0x0 5. "UPCF,Direction change to UP clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKCF,Autoreload register update OK clear flag" "0,1"
|
|
bitfld.long 0x0 3. "CMPOKCF,Compare register update OK clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGCF,External trigger valid edge clear flag" "0,1"
|
|
bitfld.long 0x0 1. "ARRMCF,Autoreload match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMCF,Compare match clear flag" "0,1"
|
|
group.long 0x8++0x13
|
|
line.long 0x0 "LPTIM_IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 6. "DOWNIE,Direction change to down Interrupt Enable" "0: DOWN interrupt disabled,1: DOWN interrupt enabled"
|
|
bitfld.long 0x0 5. "UPIE,Direction change to UP Interrupt Enable" "0: UP interrupt disabled,1: UP interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "ARROKIE,Autoreload register update OK Interrupt Enable" "0: ARROK interrupt disabled,1: ARROK interrupt enabled"
|
|
bitfld.long 0x0 3. "CMPOKIE,Compare register update OK Interrupt Enable" "0: CMPOK interrupt disabled,1: CMPOK interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "EXTTRIGIE,External trigger valid edge Interrupt Enable" "0: EXTTRIG interrupt disabled,1: EXTTRIG interrupt enabled"
|
|
bitfld.long 0x0 1. "ARRMIE,Autoreload match Interrupt Enable" "0: ARRM interrupt disabled,1: ARRM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "CMPMIE,Compare match Interrupt Enable" "0: CMPM interrupt disabled,1: CMPM interrupt enabled"
|
|
line.long 0x4 "LPTIM_CFGR,Configuration Register"
|
|
bitfld.long 0x4 24. "ENC,Encoder mode enable" "0: Encoder mode disabled,1: Encoder mode enabled"
|
|
bitfld.long 0x4 23. "COUNTMODE,counter mode enabled" "0: the counter is incremented following each..,1: the counter is incremented following each valid.."
|
|
newline
|
|
bitfld.long 0x4 22. "PRELOAD,Registers update mode" "0: Registers are updated after each APB bus write..,1: Registers are updated at the end of the current.."
|
|
bitfld.long 0x4 21. "WAVPOL,Waveform shape polarity" "0: The LPTIM output reflects the compare results..,1: The LPTIM output reflects the inverse of the.."
|
|
newline
|
|
bitfld.long 0x4 20. "WAVE,Waveform shape" "0: Deactivate Set-once mode PWM or One Pulse..,1: Activate the Set-once mode"
|
|
bitfld.long 0x4 19. "TIMOUT,Timeout enable" "0: A trigger event arriving when the timer is..,1: A trigger event arriving when the timer is.."
|
|
newline
|
|
bitfld.long 0x4 17.--18. "TRIGEN,Trigger enable and polarity" "0: software trigger (counting start is initiated by..,1: rising edge is the active edge,2: falling edge is the active edge,3: both edges are active edges"
|
|
bitfld.long 0x4 13.--15. "TRIGSEL,Trigger selector" "0: lptim_ext_trig0,1: lptim_ext_trig1,2: lptim_ext_trig2,3: lptim_ext_trig3,4: lptim_ext_trig4,5: lptim_ext_trig5,6: lptim_ext_trig6,7: lptim_ext_trig7"
|
|
newline
|
|
bitfld.long 0x4 9.--11. "PRESC,Clock prescaler" "0: /1,1: /2,2: /4,3: /8,4: /16,5: /32,6: /64,7: /128"
|
|
bitfld.long 0x4 6.--7. "TRGFLT,Configurable digital filter for trigger" "0: any trigger active level change is considered as..,1: trigger active level change must be stable for..,2: trigger active level change must be stable for..,3: trigger active level change must be stable for.."
|
|
newline
|
|
bitfld.long 0x4 3.--4. "CKFLT,Configurable digital filter for external clock" "0: any external clock signal level change is..,1: external clock signal level change must be..,2: external clock signal level change must be..,3: external clock signal level change must be.."
|
|
bitfld.long 0x4 1.--2. "CKPOL,Clock Polarity" "0: the rising edge is the active edge used for..,1: the falling edge is the active edge used for..,2: both edges are active edges. When both external..,3: not allowed"
|
|
newline
|
|
bitfld.long 0x4 0. "CKSEL,Clock selector" "0: LPTIM is clocked by internal clock source (APB..,1: LPTIM is clocked by an external clock source.."
|
|
line.long 0x8 "LPTIM_CR,Control Register"
|
|
bitfld.long 0x8 4. "RSTARE,Reset after read enable" "0,1"
|
|
bitfld.long 0x8 3. "COUNTRST,Counter reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "CNTSTRT,Timer start in Continuous mode" "0,1"
|
|
bitfld.long 0x8 1. "SNGSTRT,LPTIM start in Single mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "ENABLE,LPTIM enable" "0: LPTIM is disabled,1: LPTIM is enabled"
|
|
line.long 0xC "LPTIM_CMP,Compare Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "CMP,Compare value"
|
|
line.long 0x10 "LPTIM_ARR,Autoreload Register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto reload value"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPTIM_CNT,Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "LPTIM_CFGR2,LPTIM configuration register 2"
|
|
bitfld.long 0x0 4.--5. "IN2SEL,LPTIM input 2 selection" "0: lptim_in2_mux0,1: lptim_in2_mux1,2: lptim_in2_mux2,3: lptim_in2_mux3"
|
|
bitfld.long 0x0 0.--1. "IN1SEL,LPTIM input 1 selection" "0: lptim_in1_mux0,1: lptim_in1_mux1,2: lptim_in1_mux2,3: lptim_in1_mux3"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "LPUART (Low-Power Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G0B1*"))
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "LPUART_CR1_enabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
endif
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LPUART_CR1_disabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
endif
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
endif
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
|
|
endif
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "LPUART_CR2,LPUART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
newline
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD = 0/mark.."
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD = 0/mark.."
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,?,2: 2 stop bits,?"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
line.long 0x8 "LPUART_CR3,LPUART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
|
|
newline
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever WUF =.."
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on Start bit detection,3: WUF active on RXNE."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
newline
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
newline
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
newline
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE = 1 or ORE = 1.."
|
|
line.long 0xC "LPUART_BRR,LPUART baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "LPUART_RQR,LPUART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_enabled,LPUART interrupt and status register [alternate]"
|
|
rbitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
rbitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
rbitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
rbitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
rbitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
newline
|
|
rbitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
rbitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
newline
|
|
rbitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
endif
|
|
rbitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
rbitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
rbitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
rbitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
rbitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
rbitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
rbitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
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rbitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
rbitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
newline
|
|
rbitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
rbitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
rbitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
rbitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
rbitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
rbitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
rbitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
rbitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_disabled,LPUART interrupt and status register [alternate]"
|
|
sif (cpuis("STM32G051*")||cpuis("STM32G061*"))
|
|
rbitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
rbitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
rbitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
newline
|
|
rbitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
rbitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
newline
|
|
rbitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
rbitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
newline
|
|
rbitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
endif
|
|
rbitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
rbitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
rbitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
rbitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
rbitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
rbitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
rbitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
newline
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
endif
|
|
rbitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
endif
|
|
rbitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
rbitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
rbitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
rbitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
rbitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "LPUART_RDR,LPUART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "LPUART2"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "LPUART_CR1_enabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF = 1.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE = 1.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
newline
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE = 1.."
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC = 1.."
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE =.."
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
bitfld.long 0x0 1. "UESM,LPUART enable in Stop mode" "0: LPUART not able to wake up the MCU from..,1: LPUART able to wake up the MCU from low-power.."
|
|
newline
|
|
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LPUART_CR1_disabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
newline
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE = 1.."
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC = 1.."
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE =.."
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
bitfld.long 0x0 1. "UESM,LPUART enable in Stop mode" "0: LPUART not able to wake up the MCU from..,1: LPUART able to wake up the MCU from low-power.."
|
|
newline
|
|
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
|
|
line.long 0x4 "LPUART_CR2,LPUART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
newline
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD = 0/mark.."
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD = 0/mark.."
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,?,2: 2 stop bits,?"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
line.long 0x8 "LPUART_CR3,LPUART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
|
|
newline
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever WUF =.."
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on Start bit detection,3: WUF active on RXNE."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
newline
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
newline
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
newline
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE = 1 or ORE = 1.."
|
|
line.long 0xC "LPUART_BRR,LPUART baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "LPUART_RQR,LPUART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_enabled,LPUART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO is not full,1: RXFIFO is full"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO is not empty,1: TXFIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
newline
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
newline
|
|
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_disabled,LPUART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
newline
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
newline
|
|
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "LPUART_RDR,LPUART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "LPUART1"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "LPUART_CR1_enabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF = 1.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE = 1.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
newline
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE = 1.."
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC = 1.."
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
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|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE =.."
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
bitfld.long 0x0 1. "UESM,LPUART enable in Stop mode" "0: LPUART not able to wake up the MCU from..,1: LPUART able to wake up the MCU from low-power.."
|
|
newline
|
|
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LPUART_CR1_disabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
newline
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE = 1.."
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC = 1.."
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE =.."
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
bitfld.long 0x0 1. "UESM,LPUART enable in Stop mode" "0: LPUART not able to wake up the MCU from..,1: LPUART able to wake up the MCU from low-power.."
|
|
newline
|
|
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
|
|
line.long 0x4 "LPUART_CR2,LPUART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
newline
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD = 0/mark.."
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD = 0/mark.."
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,?,2: 2 stop bits,?"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
line.long 0x8 "LPUART_CR3,LPUART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
|
|
newline
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever WUF =.."
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on Start bit detection,3: WUF active on RXNE."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
newline
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
newline
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
newline
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE = 1 or ORE = 1.."
|
|
line.long 0xC "LPUART_BRR,LPUART baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "LPUART_RQR,LPUART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_enabled,LPUART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO is not full,1: RXFIFO is full"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO is not empty,1: TXFIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
newline
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
newline
|
|
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_disabled,LPUART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
newline
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
newline
|
|
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "LPUART_RDR,LPUART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "LPUART2"
|
|
base ad:0x40008400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "LPUART_CR1_enabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when RXFF = 1.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when TXFE = 1.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
newline
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE = 1.."
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC = 1.."
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE =.."
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
bitfld.long 0x0 1. "UESM,LPUART enable in Stop mode" "0: LPUART not able to wake up the MCU from..,1: LPUART able to wake up the MCU from low-power.."
|
|
newline
|
|
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LPUART_CR1_disabled,LPUART control register 1 [alternate]"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 Start bit,1: 1 Start bit"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when the CMF bit.."
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
newline
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever PE = 1.."
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever.."
|
|
newline
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever TC = 1.."
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated whenever ORE = 1.."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever IDLE =.."
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
bitfld.long 0x0 1. "UESM,LPUART enable in Stop mode" "0: LPUART not able to wake up the MCU from..,1: LPUART able to wake up the MCU from low-power.."
|
|
newline
|
|
bitfld.long 0x0 0. "UE,LPUART enable" "0: LPUART prescaler and outputs disabled low-power..,1: LPUART enabled"
|
|
line.long 0x4 "LPUART_CR2,LPUART control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the LPUART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
newline
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD = 0/mark.."
|
|
newline
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD = 0/mark.."
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0: 1 stop bit,?,2: 2 stop bits,?"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
line.long 0x8 "LPUART_CR3,LPUART control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth.,1: TXFIFO reaches 1/4 of its depth.,?,3: TXFIFO reaches 3/4 of its depth.,4: TXFIFO reaches 7/8 of its depth.,5: TXFIFO becomes empty.,6: TXFIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated when Receive.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth.,1: Receive FIFO reaches 1/4 of its depth.,?,3: Receive FIFO reaches 3/4 of its depth.,4: Receive FIFO reaches 7/8 of its depth.,5: Receive FIFO becomes full.,6: Receive FIFO reaches 1/2 of its depth.,?"
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt is inhibited,1: A LPUART interrupt is generated when TXFIFO.."
|
|
newline
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt is inhibited,1: An LPUART interrupt is generated whenever WUF =.."
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on Start bit detection,3: WUF active on RXNE."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
newline
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
newline
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
newline
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated when FE = 1 or ORE = 1.."
|
|
line.long 0xC "LPUART_BRR,LPUART baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,LPUART baud rate"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "LPUART_RQR,LPUART request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_enabled,LPUART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO is not full,1: RXFIFO is full"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO is not empty,1: TXFIFO is empty"
|
|
newline
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
newline
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
newline
|
|
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "LPUART_ISR_disabled,LPUART interrupt and status register [alternate]"
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in Active mode,1: Receiver in Mute mode"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: LPUART is idle (no reception),1: Reception on going"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Data register is full/Transmit FIFO is full.,1: Data register/Transmit FIFO is not full."
|
|
newline
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
newline
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
newline
|
|
bitfld.long 0x0 2. "NE,Start bit noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "LPUART_ICR,LPUART interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "LPUART_RDR,LPUART receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "LPUART_TDR,LPUART transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "LPUART_PRESC,LPUART prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "PWR (Power Control)"
|
|
base ad:0x40007000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Power control register 1"
|
|
bitfld.long 0x0 14. "LPR,Low-power run" "0,1"
|
|
bitfld.long 0x0 9.--10. "VOS,Voltage scaling range" "0,1,2,3"
|
|
bitfld.long 0x0 8. "DBP,Disable backup domain write" "0,1"
|
|
bitfld.long 0x0 5. "FPD_LPSLP,Flash memory powered down during" "0,1"
|
|
bitfld.long 0x0 4. "FPD_LPRUN,Flash memory powered down during" "0,1"
|
|
bitfld.long 0x0 3. "FPD_STOP,Flash memory powered down during Stop" "0,1"
|
|
bitfld.long 0x0 0.--2. "LPMS,Low-power mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0x4 "CR2,Power control register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x4 10. "USV,USV" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 10. "USV,USV" "0,1"
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 10. "USV,USV" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 10. "USV,USV" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 10. "USV,USV" "0,1"
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 9. "IOSV,IOSV" "0,1"
|
|
bitfld.long 0x4 8. "PVMENUSB,PVMENUSB" "0,1"
|
|
bitfld.long 0x4 7. "PVMENDAC,PVMENDAC" "0,1"
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 4.--6. "PVDRT,Power voltage detector rising threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 1.--3. "PVDFT,Power voltage detector falling threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0. "PVDE,Power voltage detector" "0,1"
|
|
endif
|
|
line.long 0x8 "CR3,Power control register 3"
|
|
bitfld.long 0x8 15. "EIWUL,Enable internal wakeup" "0,1"
|
|
bitfld.long 0x8 10. "APC,Apply pull-up and pull-down" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 9. "ULPEN,Enable the periodical sampling mode for" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 9. "ENB_ULP,Ultra-low-power enable" "0,1"
|
|
bitfld.long 0x8 8. "RRS,SRAM retention in Standby" "0,1"
|
|
endif
|
|
bitfld.long 0x8 5. "EWUP6,Enable WKUP6 wakeup pin" "0,1"
|
|
bitfld.long 0x8 4. "EWUP5,Enable WKUP5 wakeup pin" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "EWUP4,Enable Wakeup pin WKUP4" "0,1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 2. "EWUP3,Enable Wakeup pin WKUP3" "0,1"
|
|
endif
|
|
bitfld.long 0x8 1. "EWUP2,Enable Wakeup pin WKUP2" "0,1"
|
|
bitfld.long 0x8 0. "EWUP1,Enable Wakeup pin WKUP1" "0,1"
|
|
line.long 0xC "CR4,Power control register 4"
|
|
bitfld.long 0xC 9. "VBRS,VBAT battery charging resistor" "0,1"
|
|
bitfld.long 0xC 8. "VBE,VBAT battery charging" "0,1"
|
|
bitfld.long 0xC 5. "WP6,WKUP6 wakeup pin polarity" "0,1"
|
|
bitfld.long 0xC 4. "WP5,Wakeup pin WKUP5 polarity" "0,1"
|
|
bitfld.long 0xC 3. "WP4,Wakeup pin WKUP4 polarity" "0,1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0xC 2. "WP3,Wakeup pin WKUP3 polarity" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 1. "WP2,Wakeup pin WKUP2 polarity" "0,1"
|
|
bitfld.long 0xC 0. "WP1,Wakeup pin WKUP1 polarity" "0,1"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "SR1,Power status register 1"
|
|
bitfld.long 0x0 15. "WUFI,Wakeup flag internal" "0,1"
|
|
bitfld.long 0x0 8. "SBF,Standby flag" "0,1"
|
|
bitfld.long 0x0 5. "WUF6,Wakeup flag 6" "0,1"
|
|
bitfld.long 0x0 4. "WUF5,Wakeup flag 5" "0,1"
|
|
bitfld.long 0x0 3. "WUF4,Wakeup flag 4" "0,1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 2. "WUF3,Wakeup flag 3" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 1. "WUF2,Wakeup flag 2" "0,1"
|
|
bitfld.long 0x0 0. "WUF1,Wakeup flag 1" "0,1"
|
|
line.long 0x4 "SR2,Power status register 2"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 15. "PVMODAC,VDDA monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 12. "PVMOUSB,USB supply voltage monitoring output flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 11. "PVDO,Power voltage detector" "0,1"
|
|
endif
|
|
bitfld.long 0x4 10. "VOSF,Voltage scaling flag" "0,1"
|
|
bitfld.long 0x4 9. "REGLPF,Low-power regulator flag" "0,1"
|
|
bitfld.long 0x4 8. "REGLPS,Low-power regulator" "0,1"
|
|
bitfld.long 0x4 7. "FLASH_RDY,Flash ready flag" "0,1"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "SCR,Power status clear register"
|
|
bitfld.long 0x0 8. "CSBF,Clear standby flag" "0,1"
|
|
bitfld.long 0x0 5. "CWUF6,Clear wakeup flag 6" "0,1"
|
|
bitfld.long 0x0 4. "CWUF5,Clear wakeup flag 5" "0,1"
|
|
bitfld.long 0x0 3. "CWUF4,Clear wakeup flag 4" "0,1"
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x0 2. "CWUF3,Clear wakeup flag 3" "0,1"
|
|
endif
|
|
bitfld.long 0x0 1. "CWUF2,Clear wakeup flag 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CWUF1,Clear wakeup flag 1" "0,1"
|
|
group.long 0x20++0x2F
|
|
line.long 0x0 "PUCRA,Power Port A pull-up control"
|
|
bitfld.long 0x0 15. "PU15,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 14. "PU14,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 13. "PU13,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 12. "PU12,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 11. "PU11,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 10. "PU10,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 9. "PU9,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 8. "PU8,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 7. "PU7,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 6. "PU6,Port A pull-up bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PU5,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 4. "PU4,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 3. "PU3,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 2. "PU2,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 1. "PU1,Port A pull-up bit y" "0,1"
|
|
bitfld.long 0x0 0. "PU0,Port A pull-up bit y" "0,1"
|
|
line.long 0x4 "PDCRA,Power Port A pull-down control"
|
|
bitfld.long 0x4 15. "PD15,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 14. "PD14,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 13. "PD13,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 12. "PD12,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 11. "PD11,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 10. "PD10,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 9. "PD9,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 8. "PD8,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 7. "PD7,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 6. "PD6,Port A pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PD5,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 4. "PD4,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 3. "PD3,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 2. "PD2,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 1. "PD1,Port A pull-down bit y" "0,1"
|
|
bitfld.long 0x4 0. "PD0,Port A pull-down bit y" "0,1"
|
|
line.long 0x8 "PUCRB,Power Port B pull-up control"
|
|
bitfld.long 0x8 15. "PU15,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 14. "PU14,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 13. "PU13,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 12. "PU12,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 11. "PU11,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 10. "PU10,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 9. "PU9,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 8. "PU8,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 7. "PU7,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 6. "PU6,Port B pull-up bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "PU5,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 4. "PU4,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 3. "PU3,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 2. "PU2,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 1. "PU1,Port B pull-up bit y" "0,1"
|
|
bitfld.long 0x8 0. "PU0,Port B pull-up bit y" "0,1"
|
|
line.long 0xC "PDCRB,Power Port B pull-down control"
|
|
bitfld.long 0xC 15. "PD15,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 14. "PD14,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 13. "PD13,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 12. "PD12,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 11. "PD11,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 10. "PD10,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 9. "PD9,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 8. "PD8,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 7. "PD7,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 6. "PD6,Port B pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "PD5,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 4. "PD4,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 3. "PD3,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 2. "PD2,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 1. "PD1,Port B pull-down bit y" "0,1"
|
|
bitfld.long 0xC 0. "PD0,Port B pull-down bit y" "0,1"
|
|
line.long 0x10 "PUCRC,Power Port C pull-up control"
|
|
bitfld.long 0x10 15. "PU15,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 14. "PU14,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 13. "PU13,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 12. "PU12,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 11. "PU11,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 10. "PU10,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 9. "PU9,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 8. "PU8,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 7. "PU7,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 6. "PU6,Port C pull-up bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "PU5,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 4. "PU4,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 3. "PU3,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 2. "PU2,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 1. "PU1,Port C pull-up bit y" "0,1"
|
|
bitfld.long 0x10 0. "PU0,Port C pull-up bit y" "0,1"
|
|
line.long 0x14 "PDCRC,Power Port C pull-down control"
|
|
bitfld.long 0x14 15. "PD15,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 14. "PD14,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 13. "PD13,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 12. "PD12,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 11. "PD11,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 10. "PD10,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 9. "PD9,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 8. "PD8,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 7. "PD7,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 6. "PD6,Port C pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "PD5,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 4. "PD4,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 3. "PD3,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 2. "PD2,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 1. "PD1,Port C pull-down bit y" "0,1"
|
|
bitfld.long 0x14 0. "PD0,Port C pull-down bit y" "0,1"
|
|
line.long 0x18 "PUCRD,Power Port D pull-up control"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x18 15. "PU15,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 14. "PU14,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 13. "PU13,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 12. "PU12,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 11. "PU11,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 10. "PU10,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 7. "PU7,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 15. "PU15,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 15. "PU15,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 15. "PU15,Port D pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 15. "PU15,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 14. "PU14,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 14. "PU14,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 14. "PU14,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 14. "PU14,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 13. "PU13,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 13. "PU13,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 13. "PU13,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 13. "PU13,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 12. "PU12,Port D pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 12. "PU12,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 12. "PU12,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 12. "PU12,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 11. "PU11,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 11. "PU11,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 11. "PU11,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 11. "PU11,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 10. "PU10,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 10. "PU10,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 10. "PU10,Port D pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 10. "PU10,Port D pull-up bit y" "0,1"
|
|
endif
|
|
bitfld.long 0x18 9. "PU9,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 8. "PU8,Port D pull-up bit y" "0,1"
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 7. "PU7,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 7. "PU7,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 7. "PU7,Port D pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 7. "PU7,Port D pull-up bit y" "0,1"
|
|
endif
|
|
bitfld.long 0x18 6. "PU6,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 5. "PU5,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 4. "PU4,Port D pull-up bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "PU3,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 2. "PU2,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 1. "PU1,Port D pull-up bit y" "0,1"
|
|
bitfld.long 0x18 0. "PU0,Port D pull-up bit y" "0,1"
|
|
line.long 0x1C "PDCRD,Power Port D pull-down control"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x1C 15. "PD15,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 14. "PD14,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 7. "PD7,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 15. "PD15,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 15. "PD15,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 15. "PD15,Port D pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 15. "PD15,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 14. "PD14,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 14. "PD14,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 14. "PD14,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 14. "PD14,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 13. "PD13,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 12. "PD12,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 11. "PD11,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 10. "PD10,Port D pull-down bit y" "0,1"
|
|
endif
|
|
bitfld.long 0x1C 9. "PD9,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 8. "PD8,Port D pull-down bit y" "0,1"
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 7. "PD7,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 7. "PD7,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 7. "PD7,Port D pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 7. "PD7,Port D pull-down bit y" "0,1"
|
|
endif
|
|
bitfld.long 0x1C 6. "PD6,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 5. "PD5,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 4. "PD4,Port D pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "PD3,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 2. "PD2,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 1. "PD1,Port D pull-down bit y" "0,1"
|
|
bitfld.long 0x1C 0. "PD0,Port D pull-down bit y" "0,1"
|
|
line.long 0x20 "PUCRE,Power Port E pull-UP control"
|
|
bitfld.long 0x20 15. "PU15,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 14. "PU14,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 13. "PU13,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 12. "PU12,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 11. "PU11,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 10. "PU10,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 9. "PU9,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 8. "PU8,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 7. "PU7,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 6. "PU6,Port E pull-up bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x20 5. "PU5,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 4. "PU4,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 3. "PU3,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 2. "PU2,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 1. "PU1,Port E pull-up bit y" "0,1"
|
|
bitfld.long 0x20 0. "PU0,Port E pull-up bit y" "0,1"
|
|
line.long 0x24 "PDCRE,Power Port E pull-down control"
|
|
bitfld.long 0x24 15. "PD15,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 14. "PD14,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 13. "PD13,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 12. "PD12,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 11. "PD11,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 10. "PD10,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 9. "PD9,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 8. "PD8,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 7. "PD7,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 6. "PD6,Port E pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x24 5. "PD5,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 4. "PD4,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 3. "PD3,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 2. "PD2,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 1. "PD1,Port E pull-down bit y" "0,1"
|
|
bitfld.long 0x24 0. "PD0,Port E pull-down bit y" "0,1"
|
|
line.long 0x28 "PUCRF,Power Port F pull-up control"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x28 13. "PU13,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 12. "PU12,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 11. "PU11,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 10. "PU10,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 9. "PU9,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 8. "PU8,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 7. "PU7,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 6. "PU6,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 5. "PU5,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 4. "PU4,Port F pull-up bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x28 3. "PU3,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 13. "PU13,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 13. "PU13,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 13. "PU13,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 13. "PU13,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 12. "PU12,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 12. "PU12,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 12. "PU12,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 12. "PU12,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 11. "PU11,Port F pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 11. "PU11,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 11. "PU11,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 11. "PU11,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 10. "PU10,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 10. "PU10,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 10. "PU10,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 10. "PU10,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 9. "PU9,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 9. "PU9,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 9. "PU9,Port F pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 9. "PU9,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 8. "PU8,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 8. "PU8,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 8. "PU8,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 8. "PU8,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 7. "PU7,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 7. "PU7,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 7. "PU7,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 7. "PU7,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 6. "PU6,Port F pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 6. "PU6,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 6. "PU6,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 6. "PU6,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 5. "PU5,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 5. "PU5,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 5. "PU5,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 5. "PU5,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 4. "PU4,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 4. "PU4,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 4. "PU4,Port F pull-up bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 4. "PU4,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 3. "PU3,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 3. "PU3,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 3. "PU3,Port F pull-up bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 3. "PU3,Port F pull-up bit y" "0,1"
|
|
endif
|
|
bitfld.long 0x28 2. "PU2,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 1. "PU1,Port F pull-up bit y" "0,1"
|
|
bitfld.long 0x28 0. "PU0,Port F pull-up bit y" "0,1"
|
|
line.long 0x2C "PDCRF,Power Port F pull-down control"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*"))
|
|
bitfld.long 0x2C 13. "PD13,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 12. "PD12,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 11. "PD11,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 10. "PD10,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 9. "PD9,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 8. "PD8,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 7. "PD7,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 6. "PD6,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 5. "PD5,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 4. "PD4,Port F pull-down bit y" "0,1"
|
|
newline
|
|
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 13. "PD13,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 13. "PD13,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 13. "PD13,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 13. "PD13,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 12. "PD12,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 12. "PD12,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 12. "PD12,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 12. "PD12,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 11. "PD11,Port F pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 11. "PD11,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 11. "PD11,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 11. "PD11,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 10. "PD10,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 10. "PD10,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 10. "PD10,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 10. "PD10,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 9. "PD9,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 9. "PD9,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 9. "PD9,Port F pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 9. "PD9,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 8. "PD8,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 8. "PD8,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 8. "PD8,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 8. "PD8,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 7. "PD7,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 7. "PD7,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 7. "PD7,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 7. "PD7,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 6. "PD6,Port F pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 6. "PD6,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 6. "PD6,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 6. "PD6,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 5. "PD5,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 5. "PD5,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 5. "PD5,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 5. "PD5,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 4. "PD4,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 4. "PD4,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 4. "PD4,Port F pull-down bit y" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 4. "PD4,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 3. "PD3,Port F pull-down bit y" "0,1"
|
|
endif
|
|
bitfld.long 0x2C 2. "PD2,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 1. "PD1,Port F pull-down bit y" "0,1"
|
|
bitfld.long 0x2C 0. "PD0,Port F pull-down bit y" "0,1"
|
|
tree.end
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Clock control register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 25. "PLLRDY,PLL clock ready flag" "0,1"
|
|
bitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 25. "PLLRDY,PLL clock ready flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 25. "PLLRDY,PLL clock ready flag" "0,1"
|
|
endif
|
|
bitfld.long 0x0 24. "PLLON,PLL enable" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 23. "HSI48RDY,HSI48RDY" "0,1"
|
|
bitfld.long 0x0 22. "HSI48ON,HSI48ON" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 23. "HSI48RDY,HSI48RDY" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "HSI48ON,HSI48ON" "0,1"
|
|
endif
|
|
bitfld.long 0x0 19. "CSSON,Clock security system" "0,1"
|
|
bitfld.long 0x0 18. "HSEBYP,HSE crystal oscillator" "0,1"
|
|
bitfld.long 0x0 17. "HSERDY,HSE clock ready flag" "0,1"
|
|
bitfld.long 0x0 16. "HSEON,HSE clock enable" "0,1"
|
|
bitfld.long 0x0 11.--13. "HSIDIV,HSI16 clock division" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 10. "HSIRDY,HSI16 clock ready flag" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 9. "HSIKERON,HSI16 always enable for peripheral" "0,1"
|
|
bitfld.long 0x0 8. "HSION,HSI16 clock enable" "0,1"
|
|
line.long 0x4 "ICSCR,Internal clock sources calibration"
|
|
hexmask.long.byte 0x4 8.--14. 1. "HSITRIM,HSI16 clock trimming"
|
|
hexmask.long.byte 0x4 0.--7. 1. "HSICAL,HSI16 clock calibration"
|
|
line.long 0x8 "CFGR,Clock configuration register"
|
|
sif (cpuis("STM32G030*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output"
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock"
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,MCO2PRE"
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,MCO2SEL"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
rbitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
rbitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
rbitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
rbitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rbitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rbitfld.long 0x8 28.--30. "MCOPRE,Microcontroller clock output" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x8 28.--31. 1. "MCOPRE,Microcontroller clock output"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 24.--26. "MCOSEL,Microcontroller clock" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x8 24.--27. 1. "MCOSEL,Microcontroller clock"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,MCO2PRE"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,MCO2PRE"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,MCO2PRE"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,MCO2PRE"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x8 20.--23. 1. "MCO2PRE,MCO2PRE"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,MCO2SEL"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,MCO2SEL"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,MCO2SEL"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,MCO2SEL"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
hexmask.long.byte 0x8 16.--19. 1. "MCO2SEL,MCO2SEL"
|
|
endif
|
|
bitfld.long 0x8 12.--14. "PPRE,APB prescaler" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 8.--11. 1. "HPRE,AHB prescaler"
|
|
rbitfld.long 0x8 3.--5. "SWS,System clock switch status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 0.--2. "SW,System clock switch" "0,1,2,3,4,5,6,7"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B0*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PLLSYSCFGR,PLL configuration register"
|
|
bitfld.long 0x0 29.--31. "PLLR,PLL VCO division factor R for PLLRCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 28. "PLLREN,PLLRCLK clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "PLLQ,PLL VCO division factor Q for PLLQCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24. "PLLQEN,PLLQCLK clock output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--21. 1. "PLLP,PLL VCO division factor P for PLLPCLK"
|
|
bitfld.long 0x0 16. "PLLPEN,PLLPCLK clock output" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G030*"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "PLLN,PLL frequency multiplication factor"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLLN,PLL frequency multiplication factor"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLLN,PLL frequency multiplication factor"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "PLLN,PLL frequency multiplication factor"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLLN,PLL frequency multiplication factor"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLLN,PLL frequency multiplication factor"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "PLLN,PLL frequency multiplication factor"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLLN,PLL frequency multiplication factor"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
hexmask.long.byte 0x0 8.--14. 1. "PLLN,PLL frequency multiplication factor"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
hexmask.long.byte 0x0 8.--15. 1. "PLLN,PLL frequency multiplication factor"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 4.--6. "PLLM,Division factor M of the PLL input clock" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0.--1. "PLLSRC,PLL input clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PLLCFGR,PLL configuration register"
|
|
bitfld.long 0x0 29.--31. "PLLR,PLL VCO division factor R for PLLRCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 28. "PLLREN,PLLRCLK clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "PLLQ,PLL VCO division factor Q for PLLQCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24. "PLLQEN,PLLQCLK clock output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--21. 1. "PLLP,PLL VCO division factor P for PLLPCLK"
|
|
bitfld.long 0x0 16. "PLLPEN,PLLPCLK clock output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PLLN,PLL frequency multiplication factor"
|
|
bitfld.long 0x0 4.--6. "PLLM,Division factor M of the PLL input clock" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PLLSRC,PLL input clock source" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CRRCR,RCC clock recovery RC register"
|
|
hexmask.long.word 0x0 0.--8. 1. "HSI48CAL,HSI48 clock calibration"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCIPR2,Peripherals independent clock configuration register 2"
|
|
bitfld.long 0x0 12.--13. "USBSEL,USBSEL" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "FDCANSEL,FDCANSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "I2S2SEL,I2S2SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "I2S1SEL,2S1SEL" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PLLCFGR,PLL configuration register"
|
|
bitfld.long 0x0 29.--31. "PLLR,PLL VCO division factor R for PLLRCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 28. "PLLREN,PLLRCLK clock output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25.--27. "PLLQ,PLL VCO division factor Q for PLLQCLK" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 24. "PLLQEN,PLLQCLK clock output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--21. 1. "PLLP,PLL VCO division factor P for PLLPCLK"
|
|
bitfld.long 0x0 16. "PLLPEN,PLLPCLK clock output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PLLN,PLL frequency multiplication factor"
|
|
bitfld.long 0x0 4.--6. "PLLM,Division factor M of the PLL input clock" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PLLSRC,PLL input clock source" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "CRRCR,RCC clock recovery RC register"
|
|
hexmask.long.word 0x0 0.--8. 1. "HSI48CAL,HSI48 clock calibration"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCIPR2,Peripherals independent clock configuration register 2"
|
|
bitfld.long 0x0 12. "USBSEL,USBSEL" "0,1"
|
|
bitfld.long 0x0 8.--9. "FDCANSEL,FDCANSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "I2S2SEL,I2S2SEL" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "I2S1SEL,2S1SEL" "0,1,2,3"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CIER,Clock interrupt enable"
|
|
bitfld.long 0x0 5. "PLLSYSRDYIE,PLL ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYIE,HSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYIE,HSI ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "LSERDYIE,LSE ready interrupt enable" "0,1"
|
|
bitfld.long 0x0 0. "LSIRDYIE,LSI ready interrupt enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "CIFR,Clock interrupt flag register"
|
|
bitfld.long 0x0 9. "LSECSSF,LSE Clock security system interrupt" "0,1"
|
|
bitfld.long 0x0 8. "CSSF,Clock security system interrupt" "0,1"
|
|
bitfld.long 0x0 5. "PLLSYSRDYF,PLL ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYF,HSE ready interrupt flag" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYF,HSI ready interrupt flag" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 2. "HSI48RDYF,HSI48RDYF" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 2. "HSI48RDYF,HSI48RDYF" "0,1"
|
|
endif
|
|
bitfld.long 0x0 1. "LSERDYF,LSE ready interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LSIRDYF,LSI ready interrupt flag" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "CICR,Clock interrupt clear register"
|
|
bitfld.long 0x0 9. "LSECSSC,LSE Clock security system interrupt" "0,1"
|
|
bitfld.long 0x0 8. "CSSC,Clock security system interrupt" "0,1"
|
|
bitfld.long 0x0 5. "PLLSYSRDYC,PLL ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 4. "HSERDYC,HSE ready interrupt clear" "0,1"
|
|
bitfld.long 0x0 3. "HSIRDYC,HSI ready interrupt clear" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 2. "HSI48RDYC,HSI48RDYC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 2. "HSI48RDYC,HSI48RDYC" "0,1"
|
|
endif
|
|
bitfld.long 0x0 1. "LSERDYC,LSE ready interrupt clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LSIRDYC,LSI ready interrupt clear" "0,1"
|
|
group.long 0x24++0x33
|
|
line.long 0x0 "IOPRSTR,I/O port reset register"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x0 5. "GPIOFRST,GPIOFRST" "0,1"
|
|
bitfld.long 0x0 4. "GPIOERST,GPIOERST" "0,1"
|
|
bitfld.long 0x0 3. "GPIODRST,GPIODRST" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,GPIOCRST" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,GPIOBRST" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,GPIOARST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 5. "IOPFRST,I/O port F reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 5. "IOPFRST,I/O port F reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 5. "GPIOFRST,GPIOFRST" "0,1"
|
|
bitfld.long 0x0 4. "GPIOERST,GPIOERST" "0,1"
|
|
bitfld.long 0x0 3. "GPIODRST,GPIODRST" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,GPIOCRST" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,GPIOBRST" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,GPIOARST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 5. "IOPFRST,I/O port F reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 5. "IOPFRST,I/O port F reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x0 5. "GPIOFRST,GPIOFRST" "0,1"
|
|
bitfld.long 0x0 4. "GPIOERST,GPIOERST" "0,1"
|
|
bitfld.long 0x0 3. "GPIODRST,GPIODRST" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,GPIOCRST" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,GPIOBRST" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,GPIOARST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 5. "IOPFRST,I/O port F reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 5. "IOPFRST,I/O port F reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 5. "GPIOFRST,GPIOFRST" "0,1"
|
|
bitfld.long 0x0 4. "GPIOERST,GPIOERST" "0,1"
|
|
bitfld.long 0x0 3. "GPIODRST,GPIODRST" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,GPIOCRST" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,GPIOBRST" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,GPIOARST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 5. "GPIOFRST,GPIOFRST" "0,1"
|
|
bitfld.long 0x0 4. "GPIOERST,GPIOERST" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "GPIODRST,GPIODRST" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,GPIOCRST" "0,1"
|
|
bitfld.long 0x0 1. "GPIOBRST,GPIOBRST" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,GPIOARST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 5. "GPIOFRST,GPIOFRST" "0,1"
|
|
bitfld.long 0x0 4. "GPIOERST,GPIOERST" "0,1"
|
|
bitfld.long 0x0 3. "GPIODRST,GPIODRST" "0,1"
|
|
bitfld.long 0x0 2. "GPIOCRST,GPIOCRST" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "GPIOBRST,GPIOBRST" "0,1"
|
|
bitfld.long 0x0 0. "GPIOARST,GPIOARST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 3. "IOPDRST,I/O port D reset" "0,1"
|
|
bitfld.long 0x0 2. "IOPCRST,I/O port C reset" "0,1"
|
|
bitfld.long 0x0 1. "IOPBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "IOPARST,I/O port A reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 3. "IOPDRST,I/O port D reset" "0,1"
|
|
bitfld.long 0x0 2. "IOPCRST,I/O port C reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOPBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "IOPARST,I/O port A reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 3. "IOPDRST,I/O port D reset" "0,1"
|
|
bitfld.long 0x0 2. "IOPCRST,I/O port C reset" "0,1"
|
|
bitfld.long 0x0 1. "IOPBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "IOPARST,I/O port A reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 3. "IOPDRST,I/O port D reset" "0,1"
|
|
bitfld.long 0x0 2. "IOPCRST,I/O port C reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOPBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "IOPARST,I/O port A reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 3. "IOPDRST,I/O port D reset" "0,1"
|
|
bitfld.long 0x0 2. "IOPCRST,I/O port C reset" "0,1"
|
|
bitfld.long 0x0 1. "IOPBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "IOPARST,I/O port A reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 3. "IOPDRST,I/O port D reset" "0,1"
|
|
bitfld.long 0x0 2. "IOPCRST,I/O port C reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "IOPBRST,I/O port B reset" "0,1"
|
|
bitfld.long 0x0 0. "IOPARST,I/O port A reset" "0,1"
|
|
endif
|
|
line.long 0x4 "AHBRSTR,AHB peripheral reset register"
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 18. "RNGRST,Random number generator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 18. "RNGRST,Random number generator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 18. "RNGRST,Random number generator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 18. "RNGRST,Random number generator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 18. "RNGRST,Random number generator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 18. "RNGRST,Random number generator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 16. "AESRST,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 16. "AESRST,AES hardware accelerator" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 16. "AESRST,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 16. "AESRST,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 16. "AESRST,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 16. "AESRST,AES hardware accelerator" "0,1"
|
|
endif
|
|
bitfld.long 0x4 12. "CRCRST,CRC reset" "0,1"
|
|
bitfld.long 0x4 8. "FLASHRST,FLITF reset" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x4 1. "DMA2RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 1. "DMA2RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x4 1. "DMA2RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 1. "DMA2RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 1. "DMA2RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 1. "DMA2RST,DMA1 reset" "0,1"
|
|
bitfld.long 0x4 0. "DMA1RST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 0. "DMARST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 0. "DMARST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 0. "DMARST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 0. "DMARST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 0. "DMARST,DMA1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 0. "DMARST,DMA1 reset" "0,1"
|
|
endif
|
|
line.long 0x8 "APBRSTR1,APB peripheral reset register"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
bitfld.long 0x8 29. "DAC1RST,DAC1 interface reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
bitfld.long 0x8 29. "DAC1RST,DAC1 interface reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "DAC1RST,DAC1 interface reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 31. "LPTIM1RST,Low Power Timer 1 reset" "0,1"
|
|
bitfld.long 0x8 30. "LPTIM2RST,Low Power Timer 2 reset" "0,1"
|
|
bitfld.long 0x8 29. "DAC1RST,DAC1 interface reset" "0,1"
|
|
endif
|
|
bitfld.long 0x8 28. "PWRRST,Power interface reset" "0,1"
|
|
bitfld.long 0x8 27. "DBGRST,Debug support reset" "0,1"
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 26. "UCPD2RST,UCPD2 reset" "0,1"
|
|
bitfld.long 0x8 25. "UCPD1RST,UCPD1 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "CECRST,HDMI CEC reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 26. "UCPD2RST,UCPD2 reset" "0,1"
|
|
bitfld.long 0x8 25. "UCPD1RST,UCPD1 reset" "0,1"
|
|
bitfld.long 0x8 24. "CECRST,HDMI CEC reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 26. "UCPD2RST,UCPD2 reset" "0,1"
|
|
bitfld.long 0x8 25. "UCPD1RST,UCPD1 reset" "0,1"
|
|
bitfld.long 0x8 24. "CECRST,HDMI CEC reset" "0,1"
|
|
bitfld.long 0x8 23. "I2C3RST,I2C3RST reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 26. "UCPD2RST,UCPD2 reset" "0,1"
|
|
bitfld.long 0x8 25. "UCPD1RST,UCPD1 reset" "0,1"
|
|
bitfld.long 0x8 24. "CECRST,HDMI CEC reset" "0,1"
|
|
bitfld.long 0x8 23. "I2C3RST,I2C3RST reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x8 23. "I2C3RST,I2C3RST reset" "0,1"
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
bitfld.long 0x8 15. "SPI3RST,SPI3 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "USBRST,USBRST" "0,1"
|
|
bitfld.long 0x8 9. "USART6RST,USART6RST" "0,1"
|
|
bitfld.long 0x8 8. "USART5RST,USART5RST" "0,1"
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
bitfld.long 0x8 2. "TIM4RST,TIM4 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 23. "I2C3RST,I2C3RST reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 23. "I2C3RST,I2C3RST reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 23. "I2C3RST,I2C3RST reset" "0,1"
|
|
endif
|
|
bitfld.long 0x8 22. "I2C2RST,I2C2 reset" "0,1"
|
|
bitfld.long 0x8 21. "I2C1RST,I2C1 reset" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 20. "LPUART1RST,LPUART1 reset" "0,1"
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 19. "USART4RST,USART4 reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 18. "USART3RST,USART3 reset" "0,1"
|
|
endif
|
|
bitfld.long 0x8 17. "USART2RST,USART2 reset" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 16. "CRSRST,CRSRST" "0,1"
|
|
bitfld.long 0x8 15. "SPI3RST,SPI3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 16. "CRSRST,CRSRST" "0,1"
|
|
bitfld.long 0x8 15. "SPI3RST,SPI3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 15. "SPI3RST,SPI3 reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 15. "SPI3RST,SPI3 reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 15. "SPI3RST,SPI3 reset" "0,1"
|
|
endif
|
|
bitfld.long 0x8 14. "SPI2RST,SPI2 reset" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 13. "USBRST,USBRST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 13. "USBRST,USBRST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 13. "USBRST,USBRST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 13. "USBRST,USBRST" "0,1"
|
|
bitfld.long 0x8 12. "FDCANRST,FDCANRST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 13. "USBRST,USBRST" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "FDCANRST,FDCANRST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 9. "USART6RST,USART6RST" "0,1"
|
|
bitfld.long 0x8 8. "USART5RST,USART5RST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 9. "USART6RST,USART6RST" "0,1"
|
|
bitfld.long 0x8 8. "USART5RST,USART5RST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 9. "USART6RST,USART6RST" "0,1"
|
|
bitfld.long 0x8 8. "USART5RST,USART5RST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 9. "USART6RST,USART6RST" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "USART5RST,USART5RST" "0,1"
|
|
bitfld.long 0x8 7. "LPUART2RST,LPUART2RST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 9. "USART6RST,USART6RST" "0,1"
|
|
bitfld.long 0x8 8. "USART5RST,USART5RST" "0,1"
|
|
bitfld.long 0x8 7. "LPUART2RST,LPUART2RST" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 5. "TIM7RST,TIM7 timer reset" "0,1"
|
|
bitfld.long 0x8 4. "TIM6RST,TIM6 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 2. "TIM4RST,TIM4 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x8 2. "TIM4RST,TIM4 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 2. "TIM4RST,TIM4 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 2. "TIM4RST,TIM4 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 2. "TIM4RST,TIM4 timer reset" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 1. "TIM3RST,TIM3 timer reset" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 0. "TIM2RST,TIM2 timer reset" "0,1"
|
|
endif
|
|
line.long 0xC "APBRSTR2,APB peripheral reset register"
|
|
bitfld.long 0xC 20. "ADCRST,ADC reset" "0,1"
|
|
bitfld.long 0xC 18. "TIM17RST,TIM17 timer reset" "0,1"
|
|
bitfld.long 0xC 17. "TIM16RST,TIM16 timer reset" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0xC 16. "TIM15RST,TIM15 timer reset" "0,1"
|
|
endif
|
|
bitfld.long 0xC 15. "TIM14RST,TIM14 timer reset" "0,1"
|
|
bitfld.long 0xC 14. "USART1RST,USART1 reset" "0,1"
|
|
bitfld.long 0xC 12. "SPI1RST,SPI1 reset" "0,1"
|
|
bitfld.long 0xC 11. "TIM1RST,TIM1 timer reset" "0,1"
|
|
bitfld.long 0xC 0. "SYSCFGRST,SYSCFG COMP and VREFBUF" "0,1"
|
|
line.long 0x10 "IOPENR,GPIO clock enable register"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 4. "GPIOEEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x10 5. "IOPFEN,I/O port F clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x10 5. "IOPFEN,I/O port F clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 4. "GPIOEEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x10 5. "IOPFEN,I/O port F clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x10 5. "IOPFEN,I/O port F clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 4. "GPIOEEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x10 5. "IOPFEN,I/O port F clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x10 5. "IOPFEN,I/O port F clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 4. "GPIOEEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 4. "GPIOEEN,I/O port E clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x10 5. "GPIOFEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 4. "GPIOEEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 3. "GPIODEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 2. "GPIOCEN,I/O port C clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "GPIOBEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x10 0. "GPIOAEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x10 3. "IOPDEN,I/O port D clock enable" "0,1"
|
|
bitfld.long 0x10 2. "IOPCEN,I/O port C clock enable" "0,1"
|
|
bitfld.long 0x10 1. "IOPBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "IOPAEN,I/O port A clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x10 3. "IOPDEN,I/O port D clock enable" "0,1"
|
|
bitfld.long 0x10 2. "IOPCEN,I/O port C clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IOPBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "IOPAEN,I/O port A clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x10 3. "IOPDEN,I/O port D clock enable" "0,1"
|
|
bitfld.long 0x10 2. "IOPCEN,I/O port C clock enable" "0,1"
|
|
bitfld.long 0x10 1. "IOPBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "IOPAEN,I/O port A clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x10 3. "IOPDEN,I/O port D clock enable" "0,1"
|
|
bitfld.long 0x10 2. "IOPCEN,I/O port C clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IOPBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "IOPAEN,I/O port A clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x10 3. "IOPDEN,I/O port D clock enable" "0,1"
|
|
bitfld.long 0x10 2. "IOPCEN,I/O port C clock enable" "0,1"
|
|
bitfld.long 0x10 1. "IOPBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "IOPAEN,I/O port A clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x10 3. "IOPDEN,I/O port D clock enable" "0,1"
|
|
bitfld.long 0x10 2. "IOPCEN,I/O port C clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "IOPBEN,I/O port B clock enable" "0,1"
|
|
bitfld.long 0x10 0. "IOPAEN,I/O port A clock enable" "0,1"
|
|
endif
|
|
line.long 0x14 "AHBENR,AHB peripheral clock enable"
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x14 18. "RNGEN,Random number generator clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x14 18. "RNGEN,Random number generator clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x14 18. "RNGEN,Random number generator clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x14 18. "RNGEN,Random number generator clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x14 18. "RNGEN,Random number generator clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x14 18. "RNGEN,Random number generator clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x14 16. "AESEN,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x14 16. "AESEN,AES hardware accelerator" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x14 16. "AESEN,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x14 16. "AESEN,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x14 16. "AESEN,AES hardware accelerator" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x14 16. "AESEN,AES hardware accelerator" "0,1"
|
|
endif
|
|
bitfld.long 0x14 12. "CRCEN,CRC clock enable" "0,1"
|
|
bitfld.long 0x14 8. "FLASHEN,Flash memory interface clock" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x14 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x14 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x14 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x14 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x14 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x14 1. "DMA2EN,DMA2 clock enable" "0,1"
|
|
bitfld.long 0x14 0. "DMA1EN,DMA1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x14 0. "DMAEN,DMA clock enable" "0,1"
|
|
endif
|
|
line.long 0x18 "APBENR1,APB peripheral clock enable register"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
bitfld.long 0x18 29. "DAC1EN,DAC1 interface clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
bitfld.long 0x18 29. "DAC1EN,DAC1 interface clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "DAC1EN,DAC1 interface clock" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 31. "LPTIM1EN,LPTIM1 clock enable" "0,1"
|
|
bitfld.long 0x18 30. "LPTIM2EN,LPTIM2 clock enable" "0,1"
|
|
bitfld.long 0x18 29. "DAC1EN,DAC1 interface clock" "0,1"
|
|
endif
|
|
bitfld.long 0x18 28. "PWREN,Power interface clock" "0,1"
|
|
bitfld.long 0x18 27. "DBGEN,Debug support clock enable" "0,1"
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 26. "UCPD2EN,UCPD2 clock enable" "0,1"
|
|
bitfld.long 0x18 25. "UCPD1EN,UCPD1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "CECEN,HDMI CEC clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 26. "UCPD2EN,UCPD2 clock enable" "0,1"
|
|
bitfld.long 0x18 25. "UCPD1EN,UCPD1 clock enable" "0,1"
|
|
bitfld.long 0x18 24. "CECEN,HDMI CEC clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 26. "UCPD2EN,UCPD2 clock enable" "0,1"
|
|
bitfld.long 0x18 25. "UCPD1EN,UCPD1 clock enable" "0,1"
|
|
bitfld.long 0x18 24. "CECEN,HDMI CEC clock enable" "0,1"
|
|
bitfld.long 0x18 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 26. "UCPD2EN,UCPD2 clock enable" "0,1"
|
|
bitfld.long 0x18 25. "UCPD1EN,UCPD1 clock enable" "0,1"
|
|
bitfld.long 0x18 24. "CECEN,HDMI CEC clock enable" "0,1"
|
|
bitfld.long 0x18 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x18 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
bitfld.long 0x18 15. "SPI3EN,SPI3 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "USBEN,USBEN" "0,1"
|
|
bitfld.long 0x18 9. "USART6EN,USART6EN" "0,1"
|
|
bitfld.long 0x18 8. "USART5EN,USART5EN" "0,1"
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
bitfld.long 0x18 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 23. "I2C3EN,I2C3 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x18 22. "I2C2EN,I2C2 clock enable" "0,1"
|
|
bitfld.long 0x18 21. "I2C1EN,I2C1 clock enable" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 20. "LPUART1EN,LPUART1 clock enable" "0,1"
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 19. "USART4EN,USART4 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 18. "USART3EN,USART3 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x18 17. "USART2EN,USART2 clock enable" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 16. "CRSEN,CRSEN" "0,1"
|
|
bitfld.long 0x18 15. "SPI3EN,SPI3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 16. "CRSEN,CRSEN" "0,1"
|
|
bitfld.long 0x18 15. "SPI3EN,SPI3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 15. "SPI3EN,SPI3 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 15. "SPI3EN,SPI3 clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 15. "SPI3EN,SPI3 clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x18 14. "SPI2EN,SPI2 clock enable" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 13. "USBEN,USBEN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 13. "USBEN,USBEN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 13. "USBEN,USBEN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 13. "USBEN,USBEN" "0,1"
|
|
bitfld.long 0x18 12. "FDCANEN,USBEN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 13. "USBEN,USBEN" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12. "FDCANEN,USBEN" "0,1"
|
|
endif
|
|
bitfld.long 0x18 11. "WWDGEN,WWDG clock enable" "0,1"
|
|
bitfld.long 0x18 10. "RTCAPBEN,RTC APB clock enable" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 9. "USART6EN,USART6EN" "0,1"
|
|
bitfld.long 0x18 8. "USART5EN,USART5EN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 9. "USART6EN,USART6EN" "0,1"
|
|
bitfld.long 0x18 8. "USART5EN,USART5EN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 9. "USART6EN,USART6EN" "0,1"
|
|
newline
|
|
bitfld.long 0x18 8. "USART5EN,USART5EN" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 9. "USART6EN,USART6EN" "0,1"
|
|
bitfld.long 0x18 8. "USART5EN,USART5EN" "0,1"
|
|
bitfld.long 0x18 7. "LPUART2EN,LPUART2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 9. "USART6EN,USART6EN" "0,1"
|
|
bitfld.long 0x18 8. "USART5EN,USART5EN" "0,1"
|
|
bitfld.long 0x18 7. "LPUART2EN,LPUART2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 5. "TIM7EN,TIM7 timer clock enable" "0,1"
|
|
bitfld.long 0x18 4. "TIM6EN,TIM6 timer clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x18 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x18 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 2. "TIM4EN,TIM4 timer clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x18 1. "TIM3EN,TIM3 timer clock enable" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 0. "TIM2EN,TIM2 timer clock enable" "0,1"
|
|
endif
|
|
line.long 0x1C "APBENR2,APB peripheral clock enable register"
|
|
bitfld.long 0x1C 20. "ADCEN,ADC clock enable" "0,1"
|
|
bitfld.long 0x1C 18. "TIM17EN,TIM16 timer clock enable" "0,1"
|
|
bitfld.long 0x1C 17. "TIM16EN,TIM16 timer clock enable" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x1C 16. "TIM15EN,TIM15 timer clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x1C 15. "TIM14EN,TIM14 timer clock enable" "0,1"
|
|
bitfld.long 0x1C 14. "USART1EN,USART1 clock enable" "0,1"
|
|
bitfld.long 0x1C 12. "SPI1EN,SPI1 clock enable" "0,1"
|
|
bitfld.long 0x1C 11. "TIM1EN,TIM1 timer clock enable" "0,1"
|
|
bitfld.long 0x1C 0. "SYSCFGEN,SYSCFG COMP and VREFBUF clock" "0,1"
|
|
line.long 0x20 "IOPSMENR,GPIO in Sleep mode clock enable"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 4. "GPIOESMEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x20 5. "IOPFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x20 5. "IOPFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 4. "GPIOESMEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x20 5. "IOPFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x20 5. "IOPFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 4. "GPIOESMEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x20 5. "IOPFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x20 5. "IOPFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 4. "GPIOESMEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 4. "GPIOESMEN,I/O port E clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x20 5. "GPIOFSMEN,I/O port F clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 4. "GPIOESMEN,I/O port E clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 3. "GPIODSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "GPIOCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "GPIOBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "GPIOASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x20 3. "IOPDSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "IOPCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "IOPBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "IOPASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x20 3. "IOPDSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "IOPCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "IOPBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "IOPASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x20 3. "IOPDSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "IOPCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "IOPBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "IOPASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x20 3. "IOPDSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "IOPCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "IOPBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "IOPASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x20 3. "IOPDSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "IOPCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 1. "IOPBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "IOPASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x20 3. "IOPDSMEN,I/O port D clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 2. "IOPCSMEN,I/O port C clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "IOPBSMEN,I/O port B clock enable during Sleep" "0,1"
|
|
bitfld.long 0x20 0. "IOPASMEN,I/O port A clock enable during Sleep" "0,1"
|
|
endif
|
|
line.long 0x24 "AHBSMENR,AHB peripheral clock enable in Sleep mode"
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x24 18. "RNGSMEN,Random number generator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x24 18. "RNGSMEN,Random number generator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x24 18. "RNGSMEN,Random number generator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x24 18. "RNGSMEN,Random number generator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x24 18. "RNGSMEN,Random number generator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x24 18. "RNGSMEN,Random number generator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x24 16. "AESSMEN,AES hardware accelerator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x24 16. "AESSMEN,AES hardware accelerator clock enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x24 16. "AESSMEN,AES hardware accelerator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x24 16. "AESSMEN,AES hardware accelerator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x24 16. "AESSMEN,AES hardware accelerator clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x24 16. "AESSMEN,AES hardware accelerator clock enable" "0,1"
|
|
endif
|
|
bitfld.long 0x24 12. "CRCSMEN,CRC clock enable during Sleep" "0,1"
|
|
bitfld.long 0x24 9. "SRAMSMEN,SRAM clock enable during Sleep" "0,1"
|
|
bitfld.long 0x24 8. "FLASHSMEN,Flash memory interface clock enable" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x24 1. "DMA2SMEN,DMA2 clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x24 1. "DMA2SMEN,DMA2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x24 1. "DMA2SMEN,DMA2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x24 1. "DMA2SMEN,DMA2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x24 1. "DMA2SMEN,DMA2 clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x24 1. "DMA2SMEN,DMA2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x24 0. "DMA1SMEN,DMA1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x24 0. "DMASMEN,DMA clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x24 0. "DMASMEN,DMA clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x24 0. "DMASMEN,DMA clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x24 0. "DMASMEN,DMA clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x24 0. "DMASMEN,DMA clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x24 0. "DMASMEN,DMA clock enable during Sleep" "0,1"
|
|
endif
|
|
line.long 0x28 "APBSMENR1,APB peripheral clock enable in Sleep mode"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
bitfld.long 0x28 29. "DAC1SMEN,DAC1 interface clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
bitfld.long 0x28 29. "DAC1SMEN,DAC1 interface clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
newline
|
|
bitfld.long 0x28 29. "DAC1SMEN,DAC1 interface clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 31. "LPTIM1SMEN,Low Power Timer 1 clock enable during" "0,1"
|
|
bitfld.long 0x28 30. "LPTIM2SMEN,Low Power Timer 2 clock enable during" "0,1"
|
|
bitfld.long 0x28 29. "DAC1SMEN,DAC1 interface clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x28 28. "PWRSMEN,Power interface clock enable during" "0,1"
|
|
bitfld.long 0x28 27. "DBGSMEN,Debug support clock enable during Sleep" "0,1"
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x28 26. "UCPD2SMEN,UCPD2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 25. "UCPD1SMEN,UCPD1 clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 24. "CECSMEN,HDMI CEC clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 26. "UCPD2SMEN,UCPD2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 25. "UCPD1SMEN,UCPD1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 24. "CECSMEN,HDMI CEC clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 26. "UCPD2SMEN,UCPD2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 25. "UCPD1SMEN,UCPD1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 24. "CECSMEN,HDMI CEC clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 23. "I2C3SMEN,I2C3 clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 26. "UCPD2SMEN,UCPD2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 25. "UCPD1SMEN,UCPD1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 24. "CECSMEN,HDMI CEC clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 23. "I2C3SMEN,I2C3 clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x28 23. "I2C3SMEN,I2C3 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 15. "SPI3SMEN,SPI3 clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 9. "USART6SMEN,USART6 clock enable" "0,1"
|
|
bitfld.long 0x28 8. "USART5SMEN,USART5 clock enable" "0,1"
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 2. "TIM4SMEN,TIM4 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 23. "I2C3SMEN,I2C3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 23. "I2C3SMEN,I2C3 clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 23. "I2C3SMEN,I2C3 clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x28 22. "I2C2SMEN,I2C2 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 21. "I2C1SMEN,I2C1 clock enable during Sleep" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 20. "LPUART1SMEN,LPUART1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 19. "USART4SMEN,USART4 clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 18. "USART3SMEN,USART3 clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x28 17. "USART2SMEN,USART2 clock enable during Sleep" "0,1"
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 16. "CRSSSMEN,CRSS clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 15. "SPI3SMEN,SPI3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 16. "CRSSSMEN,CRSS clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 15. "SPI3SMEN,SPI3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 15. "SPI3SMEN,SPI3 clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 15. "SPI3SMEN,SPI3 clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 15. "SPI3SMEN,SPI3 clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x28 14. "SPI2SMEN,SPI2 clock enable during Sleep" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 12. "FDCANSMEN,FDCAN clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 13. "USBSMEN,USB clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 12. "FDCANSMEN,FDCAN clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x28 11. "WWDGSMEN,WWDG clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 10. "RTCAPBSMEN,RTC APB clock enable during Sleep" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 9. "USART6SMEN,USART6 clock enable" "0,1"
|
|
bitfld.long 0x28 8. "USART5SMEN,USART5 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 9. "USART6SMEN,USART6 clock enable" "0,1"
|
|
bitfld.long 0x28 8. "USART5SMEN,USART5 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 9. "USART6SMEN,USART6 clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x28 8. "USART5SMEN,USART5 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 9. "USART6SMEN,USART6 clock enable" "0,1"
|
|
bitfld.long 0x28 8. "USART5SMEN,USART5 clock enable" "0,1"
|
|
bitfld.long 0x28 7. "LPUART2SMEN,LPUART2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 9. "USART6SMEN,USART6 clock enable" "0,1"
|
|
bitfld.long 0x28 8. "USART5SMEN,USART5 clock enable" "0,1"
|
|
bitfld.long 0x28 7. "LPUART2SMEN,LPUART2 clock enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 5. "TIM7SMEN,TIM7 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x28 4. "TIM6SMEN,TIM6 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x28 2. "TIM4SMEN,TIM4 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x28 2. "TIM4SMEN,TIM4 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x28 2. "TIM4SMEN,TIM4 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 2. "TIM4SMEN,TIM4 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 2. "TIM4SMEN,TIM4 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x28 1. "TIM3SMEN,TIM3 timer clock enable during Sleep" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 0. "TIM2SMEN,TIM2 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
line.long 0x2C "APBSMENR2,APB peripheral clock enable in Sleep mode"
|
|
bitfld.long 0x2C 20. "ADCSMEN,ADC clock enable during Sleep" "0,1"
|
|
bitfld.long 0x2C 18. "TIM17SMEN,TIM16 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x2C 17. "TIM16SMEN,TIM16 timer clock enable during Sleep" "0,1"
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x2C 16. "TIM15SMEN,TIM15 timer clock enable during Sleep" "0,1"
|
|
endif
|
|
bitfld.long 0x2C 15. "TIM14SMEN,TIM14 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x2C 14. "USART1SMEN,USART1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x2C 12. "SPI1SMEN,SPI1 clock enable during Sleep" "0,1"
|
|
bitfld.long 0x2C 11. "TIM1SMEN,TIM1 timer clock enable during Sleep" "0,1"
|
|
bitfld.long 0x2C 0. "SYSCFGSMEN,SYSCFG COMP and VREFBUF clock enable" "0,1"
|
|
line.long 0x30 "CCIPR,Peripherals independent clock configuration"
|
|
bitfld.long 0x30 30.--31. "ADCSEL,ADCs clock source" "0,1,2,3"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x30 28.--29. "RNGDIV,Division factor of RNG clock" "0,1,2,3"
|
|
bitfld.long 0x30 26.--27. "RNGSEL,RNG clock source selection" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G030*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
newline
|
|
bitfld.long 0x30 4.--5. "USART3SEL,USART3 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x30 24. "TIM15SEL,TIM15 clock source" "0,1"
|
|
endif
|
|
bitfld.long 0x30 22. "TIM1SEL,TIM1 clock source" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x30 20.--21. "LPTIM2SEL,LPTIM2 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 18.--19. "LPTIM1SEL,LPTIM1 clock source" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x30 14.--15. "I2S2SEL,I2S1 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 12.--13. "I2C1SEL,I2C1 clock source" "0,1,2,3"
|
|
newline
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 8.--9. "LPUART2SEL,LPUART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x30 10.--11. "LPUART1SEL,LPUART1 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 8.--9. "LPUART2SEL,LPUART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 6. "CECSEL,HDMI CEC clock source" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 6. "CECSEL,HDMI CEC clock source" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x30 6. "CECSEL,HDMI CEC clock source" "0,1"
|
|
bitfld.long 0x30 4.--5. "USART3SEL,USART3 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x30 6. "CECSEL,HDMI CEC clock source" "0,1"
|
|
bitfld.long 0x30 4.--5. "USART3SEL,USART3 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x30 4.--5. "USART3SEL,USART3 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
bitfld.long 0x30 4.--5. "USART3SEL,USART3 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x30 4.--5. "USART3SEL,USART3 clock source" "0,1,2,3"
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 2.--3. "USART2SEL,USART2 clock source" "0,1,2,3"
|
|
endif
|
|
bitfld.long 0x30 0.--1. "USART1SEL,USART1 clock source" "0,1,2,3"
|
|
sif (cpuis("STM32G030*"))
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCIPR2,Peripherals independent clock configuration register 2"
|
|
bitfld.long 0x0 12.--13. "USBSEL,USBSEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "I2S2SEL,I2S2SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "I2S1SEL,2S1SEL" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCIPR2,Peripherals independent clock configuration register 2"
|
|
bitfld.long 0x0 12.--13. "USBSEL,USBSEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "I2S2SEL,I2S2SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "I2S1SEL,2S1SEL" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCIPR2,Peripherals independent clock configuration register 2"
|
|
bitfld.long 0x0 12.--13. "USBSEL,USBSEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "I2S2SEL,I2S2SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "I2S1SEL,2S1SEL" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "CCIPR2,Peripherals independent clock configuration register 2"
|
|
bitfld.long 0x0 12.--13. "USBSEL,USBSEL" "0,1,2,3"
|
|
bitfld.long 0x0 2.--3. "I2S2SEL,I2S2SEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "I2S1SEL,2S1SEL" "0,1,2,3"
|
|
endif
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "BDCR,RTC domain control register"
|
|
bitfld.long 0x0 25. "LSCOSEL,Low-speed clock output" "0,1"
|
|
bitfld.long 0x0 24. "LSCOEN,Low-speed clock output (LSCO)" "0,1"
|
|
bitfld.long 0x0 16. "BDRST,RTC domain software reset" "0,1"
|
|
bitfld.long 0x0 15. "RTCEN,RTC clock enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "RTCSEL,RTC clock source selection" "0,1,2,3"
|
|
sif (cpuis("STM32G030*"))
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 6. "LSECSSD,CSS on LSE failure" "0,1"
|
|
endif
|
|
bitfld.long 0x0 5. "LSECSSON,CSS on LSE enable" "0,1"
|
|
bitfld.long 0x0 3.--4. "LSEDRV,LSE oscillator drive" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LSEBYP,LSE oscillator bypass" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x0 1. "LSERDY,LSE oscillator ready" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 0. "LSEON,LSE oscillator enable" "0,1"
|
|
line.long 0x4 "CSR,Control/status register"
|
|
sif (cpuis("STM32G030*"))
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
bitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
bitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
bitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
bitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
bitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
bitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x4 31. "LPWRRSTF,Low-power reset flag" "0,1"
|
|
rbitfld.long 0x4 30. "WWDGRSTF,Window watchdog reset flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 29. "IWDGRSTF,Independent window watchdog reset" "0,1"
|
|
rbitfld.long 0x4 28. "SFTRSTF,Software reset flag" "0,1"
|
|
rbitfld.long 0x4 27. "PWRRSTF,BOR or POR/PDR flag" "0,1"
|
|
rbitfld.long 0x4 26. "PINRSTF,Pin reset flag" "0,1"
|
|
rbitfld.long 0x4 25. "OBLRSTF,Option byte loader reset" "0,1"
|
|
endif
|
|
bitfld.long 0x4 23. "RMVF,Remove reset flags" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rbitfld.long 0x4 1. "LSIRDY,LSI oscillator ready" "0,1"
|
|
endif
|
|
bitfld.long 0x4 0. "LSION,LSI oscillator enable" "0,1"
|
|
tree.end
|
|
sif (cpuis("STM32G041*")||cpuis("STM32G061*")||cpuis("STM32G081*")||cpuis("STM32G0C1*"))
|
|
tree "RNG (True Random Number Generator)"
|
|
base ad:0x40025000
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,control register"
|
|
bitfld.long 0x0 6. "BYP,Bypass mode enable" "0,1"
|
|
bitfld.long 0x0 5. "CED,Clock error detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "IE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt" "0,1"
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1"
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 0. "DRDY,Data ready" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DR,data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RNG_CR,control register"
|
|
bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection is enable,1: Clock error detection is disable"
|
|
bitfld.long 0x0 3. "IE,Interrupt Enable" "0: RNG Interrupt is disabled,1: RNG Interrupt is enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled."
|
|
line.long 0x4 "RNG_SR,status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence has been detected."
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (fRNGCLK fHCLK/32),1: The RNG has been detected too slow (fRNGCLK.."
|
|
newline
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequence.."
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (fRNGCLK fHCLK/32). If..,1: The RNG clock is too slow (fRNGCLK fHCLK/32)."
|
|
newline
|
|
rbitfld.long 0x4 0. "DRDY,Data Ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RNG_DR,RNG data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR,control register"
|
|
bitfld.long 0x0 6. "BYP,Bypass mode enable" "0,1"
|
|
bitfld.long 0x0 5. "CED,Clock error detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "IE,Interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "RNGEN,Random number generator" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt" "0,1"
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0,1"
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 0. "DRDY,Data ready" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "DR,data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RNG_CR,control register"
|
|
bitfld.long 0x0 5. "CED,Clock error detection" "0: Clock error detection is enable,1: Clock error detection is disable"
|
|
bitfld.long 0x0 3. "IE,Interrupt Enable" "0: RNG Interrupt is disabled,1: RNG Interrupt is enabled. An interrupt is.."
|
|
newline
|
|
bitfld.long 0x0 2. "RNGEN,True random number generator enable" "0: True random number generator is disabled. Analog..,1: True random number generator is enabled."
|
|
line.long 0x4 "RNG_SR,status register"
|
|
bitfld.long 0x4 6. "SEIS,Seed error interrupt status" "0: No faulty sequence detected,1: At least one faulty sequence has been detected."
|
|
bitfld.long 0x4 5. "CEIS,Clock error interrupt status" "0: The RNG clock is correct (fRNGCLK> fHCLK/32),1: The RNG has been detected too slow (fRNGCLK>.."
|
|
newline
|
|
rbitfld.long 0x4 2. "SECS,Seed error current status" "0: No faulty sequence has currently been detected.,1: At least one of the following faulty sequence.."
|
|
rbitfld.long 0x4 1. "CECS,Clock error current status" "0: The RNG clock is correct (fRNGCLK> fHCLK/32). If..,1: The RNG clock is too slow (fRNGCLK> fHCLK/32)."
|
|
newline
|
|
rbitfld.long 0x4 0. "DRDY,Data Ready" "0: The RNG_DR register is not yet valid no random..,1: The RNG_DR register contains valid random data."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RNG_DR,data register"
|
|
hexmask.long 0x0 0.--31. 1. "RNDATA,Random data"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "RTC (Real-Time Clock)"
|
|
base ad:0x40002800
|
|
sif (cpuis("STM32G030*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512Hz,1: Calibration output is 1Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TR,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "DR,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SSR,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "ICSR,initialization and status"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
line.long 0x4 "PRER,prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler"
|
|
line.long 0x8 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value"
|
|
line.long 0xC "CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0xC 24. "ITSE,ITSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,COE" "0,1"
|
|
bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,POL" "0,1"
|
|
bitfld.long 0xC 19. "COSEL,COSEL" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,BKP" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1"
|
|
bitfld.long 0xC 15. "TSIE,TSIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1"
|
|
bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1"
|
|
bitfld.long 0xC 11. "TSE,TSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,WUTE" "0,1"
|
|
bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1"
|
|
bitfld.long 0xC 6. "FMT,FMT" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1"
|
|
bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1"
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CALR,calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5" "0,1"
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTR,shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TSTR,time stamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "TSDR,time stamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "ALRMAR,alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "ALRMASSR,alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "ALRMBR,alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "ALRMBSSR,alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,WUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1"
|
|
line.long 0x4 "MISR,masked interrupt status"
|
|
bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "SCR,status clear register"
|
|
bitfld.long 0x0 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TR,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "DR,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SSR,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "ICSR,initialization and status"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
line.long 0x4 "PRER,prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler"
|
|
line.long 0x8 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value"
|
|
line.long 0xC "CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0xC 24. "ITSE,ITSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,COE" "0,1"
|
|
bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,POL" "0,1"
|
|
bitfld.long 0xC 19. "COSEL,COSEL" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,BKP" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1"
|
|
bitfld.long 0xC 15. "TSIE,TSIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1"
|
|
bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1"
|
|
bitfld.long 0xC 11. "TSE,TSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,WUTE" "0,1"
|
|
bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1"
|
|
bitfld.long 0xC 6. "FMT,FMT" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1"
|
|
bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1"
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CALR,calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5" "0,1"
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTR,shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TSTR,time stamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "TSDR,time stamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "ALRMAR,alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "ALRMASSR,alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "ALRMBR,alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "ALRMBSSR,alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,WUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1"
|
|
line.long 0x4 "MISR,masked interrupt status"
|
|
bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "SCR,status clear register"
|
|
bitfld.long 0x0 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512Hz,1: Calibration output is 1Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,RTC control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,RTC control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512Hz,1: Calibration output is 1Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TR,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "DR,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SSR,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "ICSR,initialization and status"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
line.long 0x4 "PRER,prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler"
|
|
line.long 0x8 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value"
|
|
line.long 0xC "CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0xC 24. "ITSE,ITSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,COE" "0,1"
|
|
bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,POL" "0,1"
|
|
bitfld.long 0xC 19. "COSEL,COSEL" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,BKP" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1"
|
|
bitfld.long 0xC 15. "TSIE,TSIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1"
|
|
bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1"
|
|
bitfld.long 0xC 11. "TSE,TSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,WUTE" "0,1"
|
|
bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1"
|
|
bitfld.long 0xC 6. "FMT,FMT" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1"
|
|
bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1"
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CALR,calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5" "0,1"
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTR,shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TSTR,time stamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "TSDR,time stamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "ALRMAR,alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "ALRMASSR,alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "ALRMBR,alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "ALRMBSSR,alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,WUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1"
|
|
line.long 0x4 "MISR,masked interrupt status"
|
|
bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "SCR,status clear register"
|
|
bitfld.long 0x0 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRUST_ZONE,TRUST_ZONE"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OPTIONREG_OUT,OPTIONREG_OUT"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "TIMESTAMP,TIMESTAMP"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SMOOTH_CALIB,SMOOTH_CALIB"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "WAKEUP,WAKEUP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ALARMB,ALARMB"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TR,time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "DR,date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SSR,sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "ICSR,initialization and status"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0,1"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0,1"
|
|
bitfld.long 0x0 3. "SHPF,Shift operation pending" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0,1"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0,1"
|
|
line.long 0x4 "PRER,prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler"
|
|
line.long 0x8 "WUTR,wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value"
|
|
line.long 0xC "CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,OUT2EN" "0,1"
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM_TYPE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM_PU" "0,1"
|
|
bitfld.long 0xC 26. "TAMPOE,TAMPOE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,TAMPTS" "0,1"
|
|
bitfld.long 0xC 24. "ITSE,ITSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,COE" "0,1"
|
|
bitfld.long 0xC 21.--22. "OSEL,OSEL" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,POL" "0,1"
|
|
bitfld.long 0xC 19. "COSEL,COSEL" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,BKP" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,SUB1H" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,ADD1H" "0,1"
|
|
bitfld.long 0xC 15. "TSIE,TSIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,WUTIE" "0,1"
|
|
bitfld.long 0xC 13. "ALRBIE,ALRBIE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,ALRAIE" "0,1"
|
|
bitfld.long 0xC 11. "TSE,TSE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,WUTE" "0,1"
|
|
bitfld.long 0xC 9. "ALRBE,ALRBE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,ALRAE" "0,1"
|
|
bitfld.long 0xC 6. "FMT,FMT" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,BYPSHAD" "0,1"
|
|
bitfld.long 0xC 4. "REFCKON,REFCKON" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,TSEDGE" "0,1"
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,WUCKSEL" "0,1,2,3,4,5,6,7"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CALR,calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5" "0,1"
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "SHIFTR,shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0,1"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "TSTR,time stamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "TSDR,time stamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "TSSSR,timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "ALRMAR,alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0,1"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0,1"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0,1"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "ALRMASSR,alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "ALRMBR,alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0,1"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0,1"
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0,1"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0,1"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0,1"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "ALRMBSSR,alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "SR,status register"
|
|
bitfld.long 0x0 5. "ITSF,ITSF" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,TSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,TSF" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,WUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,ALRBF" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,ALRAF" "0,1"
|
|
line.long 0x4 "MISR,masked interrupt status"
|
|
bitfld.long 0x4 5. "ITSMF,ITSMF" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,TSOVMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,TSMF" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,WUTMF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,ALRBMF" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,ALRAMF" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "SCR,status clear register"
|
|
bitfld.long 0x0 5. "CITSF,CITSF" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,CTSOVF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,CTSF" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,CWUTF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,CALRBF" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,CALRAF" "0,1"
|
|
group.long 0x3F0++0x3
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRUST_ZONE,TRUST_ZONE"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OPTIONREG_OUT,OPTIONREG_OUT"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "TIMESTAMP,TIMESTAMP"
|
|
hexmask.long.byte 0x0 8.--11. 1. "SMOOTH_CALIB,SMOOTH_CALIB"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "WAKEUP,WAKEUP"
|
|
hexmask.long.byte 0x0 0.--3. 1. "ALARMB,ALARMB"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512Hz,1: Calibration output is 1Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,RTC control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "RTC_TR,RTC time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0x4 "RTC_DR,RTC date register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "YT,Year tens in BCD format"
|
|
hexmask.long.byte 0x4 16.--19. 1. "YU,Year units in BCD format"
|
|
newline
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0: forbidden,1: Monday,?,?,?,?,?,7: Sunday"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SS,Sub second value"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "RTC_ICSR,RTC initialization control and status register"
|
|
rbitfld.long 0x0 16. "RECALPF,Recalibration pending Flag" "0,1"
|
|
bitfld.long 0x0 7. "INIT,Initialization mode" "0: Free running mode,1: Initialization mode used to program time and.."
|
|
newline
|
|
rbitfld.long 0x0 6. "INITF,Initialization flag" "0: Calendar registers update is not allowed,1: Calendar registers update is allowed"
|
|
bitfld.long 0x0 5. "RSF,Registers synchronization flag" "0: Calendar shadow registers not yet synchronized,1: Calendar shadow registers synchronized"
|
|
newline
|
|
rbitfld.long 0x0 4. "INITS,Initialization status flag" "0: Calendar has not been initialized,1: Calendar has been initialized"
|
|
rbitfld.long 0x0 3. "SHPF,Shift operation pending" "0: No shift operation is pending,1: A shift operation is pending"
|
|
newline
|
|
rbitfld.long 0x0 2. "WUTWF,Wakeup timer write flag" "0: Wakeup timer configuration update not allowed..,1: Wakeup timer configuration update allowed"
|
|
rbitfld.long 0x0 1. "ALRBWF,Alarm B write flag" "0: Alarm B update not allowed,1: Alarm B update allowed"
|
|
newline
|
|
rbitfld.long 0x0 0. "ALRAWF,Alarm A write flag" "0: Alarm A update not allowed,1: Alarm A update allowed"
|
|
line.long 0x4 "RTC_PRER,RTC prescaler register"
|
|
hexmask.long.byte 0x4 16.--22. 1. "PREDIV_A,Asynchronous prescaler factor"
|
|
hexmask.long.word 0x4 0.--14. 1. "PREDIV_S,Synchronous prescaler factor"
|
|
line.long 0x8 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x8 0.--15. 1. "WUT,Wakeup auto-reload value bits"
|
|
line.long 0xC "RTC_CR,RTC control register"
|
|
bitfld.long 0xC 31. "OUT2EN,RTC_OUT2 output enable" "0: TAMPALRM is output on RTC_OUT2,1: CALIB is output on RTC_OUT2 and TAMPALRM is.."
|
|
bitfld.long 0xC 30. "TAMPALRM_TYPE,TAMPALRM output type" "0: TAMPALRM is push-pull output,1: TAMPALRM is open-drain output"
|
|
newline
|
|
bitfld.long 0xC 29. "TAMPALRM_PU,TAMPALRM pull-up enable" "0: No pull-up is applied on TAMPALRM output,1: A pull-up is applied on TAMPALRM output"
|
|
bitfld.long 0xC 26. "TAMPOE,Tamper detection output enable on TAMPALRM" "0: The tamper flag is not routed on TAMPALRM,1: The tamper flag is routed on TAMPALRM combined.."
|
|
newline
|
|
bitfld.long 0xC 25. "TAMPTS,Activate timestamp on tamper detection event" "0: Tamper detection event does not cause a RTC..,1: Save RTC timestamp on tamper detection event"
|
|
bitfld.long 0xC 24. "ITSE,timestamp on internal event enable" "0: internal event timestamp disabled,1: internal event timestamp enabled"
|
|
newline
|
|
bitfld.long 0xC 23. "COE,Calibration output enable" "0: Calibration output disabled,1: Calibration output enabled"
|
|
bitfld.long 0xC 21.--22. "OSEL,Output selection" "0: Output disabled,1: Alarm A output enabled,2: Alarm B output enabled,3: Wakeup output enabled"
|
|
newline
|
|
bitfld.long 0xC 20. "POL,Output polarity" "0: The pin is high when ALRAF/ALRBF/WUTF is..,1: The pin is low when ALRAF/ALRBF/WUTF is asserted.."
|
|
bitfld.long 0xC 19. "COSEL,Calibration output selection" "0: Calibration output is 512 Hz,1: Calibration output is 1 Hz"
|
|
newline
|
|
bitfld.long 0xC 18. "BKP,Backup" "0,1"
|
|
bitfld.long 0xC 17. "SUB1H,Subtract 1 hour (winter time change)" "0: No effect,1: Subtracts 1 hour to the current time. This can.."
|
|
newline
|
|
bitfld.long 0xC 16. "ADD1H,Add 1 hour (summer time change)" "0: No effect,1: Adds 1 hour to the current time. This can be.."
|
|
bitfld.long 0xC 15. "TSIE,Timestamp interrupt enable" "0: Timestamp interrupt disable,1: Timestamp interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 14. "WUTIE,Wakeup timer interrupt enable" "0: Wakeup timer interrupt disabled,1: Wakeup timer interrupt enabled"
|
|
bitfld.long 0xC 13. "ALRBIE,Alarm B interrupt enable" "0: Alarm B interrupt disable,1: Alarm B interrupt enable"
|
|
newline
|
|
bitfld.long 0xC 12. "ALRAIE,Alarm A interrupt enable" "0: Alarm A interrupt disabled,1: Alarm A interrupt enabled"
|
|
bitfld.long 0xC 11. "TSE,timestamp enable" "0: timestamp disable,1: timestamp enable"
|
|
newline
|
|
bitfld.long 0xC 10. "WUTE,Wakeup timer enable" "0: Wakeup timer disabled,1: Wakeup timer enabled"
|
|
bitfld.long 0xC 9. "ALRBE,Alarm B enable" "0: Alarm B disabled,1: Alarm B enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "ALRAE,Alarm A enable" "0: Alarm A disabled,1: Alarm A enabled"
|
|
bitfld.long 0xC 6. "FMT,Hour format" "0: 24 hour/day format,1: AM/PM hour format"
|
|
newline
|
|
bitfld.long 0xC 5. "BYPSHAD,Bypass the shadow registers" "0: Calendar values (when reading from RTC_SSR..,1: Calendar values (when reading from RTC_SSR.."
|
|
bitfld.long 0xC 4. "REFCKON,RTC_REFIN reference clock detection enable (50 or 60Hz)" "0: RTC_REFIN detection disabled,1: RTC_REFIN detection enabled"
|
|
newline
|
|
bitfld.long 0xC 3. "TSEDGE,Timestamp event active edge" "0: RTC_TS input rising edge generates a timestamp..,1: RTC_TS input falling edge generates a timestamp.."
|
|
bitfld.long 0xC 0.--2. "WUCKSEL,ck_wut wakeup clock selection" "0: RTC/16 clock is selected,1: RTC/8 clock is selected,2: RTC/4 clock is selected,3: RTC/2 clock is selected,?,?,?,?"
|
|
wgroup.long 0x24++0x3
|
|
line.long 0x0 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "KEY,Write protection key"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x0 15. "CALP,Increase frequency of RTC by 488.5ppm" "0: No RTCCLK pulses are added.,1: One RTCCLK pulse is effectively inserted every.."
|
|
bitfld.long 0x0 14. "CALW8,Use an 8-second calibration cycle period" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CALW16,Use a 16-second calibration cycle period" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "CALM,Calibration minus"
|
|
wgroup.long 0x2C++0x3
|
|
line.long 0x0 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x0 31. "ADD1S,Add one second" "0: No effect,1: Add one second to the clock/calendar"
|
|
hexmask.long.word 0x0 0.--14. 1. "SUBFS,Subtract a fraction of a second"
|
|
rgroup.long 0x30++0xB
|
|
line.long 0x0 "RTC_TSTR,RTC timestamp time register"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format." "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format."
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format."
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_TSDR,RTC timestamp date register"
|
|
bitfld.long 0x4 13.--15. "WDU,Week day units" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 12. "MT,Month tens in BCD format" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "MU,Month units in BCD format"
|
|
bitfld.long 0x4 4.--5. "DT,Date tens in BCD format" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DU,Date units in BCD format"
|
|
line.long 0x8 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SS,Sub second value"
|
|
group.long 0x40++0xF
|
|
line.long 0x0 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x0 31. "MSK4,Alarm A date mask" "0: Alarm A set if the date/day match,1: Date/day don't care in alarm A comparison"
|
|
bitfld.long 0x0 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x0 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x0 23. "MSK3,Alarm A hours mask" "0: Alarm A set if the hours match,1: Hours don't care in alarm A comparison"
|
|
bitfld.long 0x0 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x0 15. "MSK2,Alarm A minutes mask" "0: Alarm A set if the minutes match,1: Minutes don't care in alarm A comparison"
|
|
bitfld.long 0x0 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x0 7. "MSK1,Alarm A seconds mask" "0: Alarm A set if the seconds match,1: Seconds don't care in alarm A comparison"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "ST,Second tens in BCD format." "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SU,Second units in BCD format."
|
|
line.long 0x4 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
hexmask.long.byte 0x4 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0x4 0.--14. 1. "SS,Sub seconds value"
|
|
line.long 0x8 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x8 31. "MSK4,Alarm B date mask" "0: Alarm B set if the date and day match,1: Date and day don't care in alarm B comparison"
|
|
bitfld.long 0x8 30. "WDSEL,Week day selection" "0: DU[3:0] represents the date units,1: DU[3:0] represents the week day. DT[1:0] is.."
|
|
newline
|
|
bitfld.long 0x8 28.--29. "DT,Date tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 24.--27. 1. "DU,Date units or day in BCD format"
|
|
newline
|
|
bitfld.long 0x8 23. "MSK3,Alarm B hours mask" "0: Alarm B set if the hours match,1: Hours don't care in alarm B comparison"
|
|
bitfld.long 0x8 22. "PM,AM/PM notation" "0: AM or 24-hour format,1: PM"
|
|
newline
|
|
bitfld.long 0x8 20.--21. "HT,Hour tens in BCD format" "0,1,2,3"
|
|
hexmask.long.byte 0x8 16.--19. 1. "HU,Hour units in BCD format"
|
|
newline
|
|
bitfld.long 0x8 15. "MSK2,Alarm B minutes mask" "0: Alarm B set if the minutes match,1: Minutes don't care in alarm B comparison"
|
|
bitfld.long 0x8 12.--14. "MNT,Minute tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--11. 1. "MNU,Minute units in BCD format"
|
|
bitfld.long 0x8 7. "MSK1,Alarm B seconds mask" "0: Alarm B set if the seconds match,1: Seconds don't care in alarm B comparison"
|
|
newline
|
|
bitfld.long 0x8 4.--6. "ST,Second tens in BCD format" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x8 0.--3. 1. "SU,Second units in BCD format"
|
|
line.long 0xC "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
hexmask.long.byte 0xC 24.--27. 1. "MASKSS,Mask the most-significant bits starting at this bit"
|
|
hexmask.long.word 0xC 0.--14. 1. "SS,Sub seconds value"
|
|
rgroup.long 0x50++0x7
|
|
line.long 0x0 "RTC_SR,RTC status register"
|
|
bitfld.long 0x0 5. "ITSF,Internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "TSOVF,Timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TSF,Timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "WUTF,Wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRBF,Alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "ALRAF,Alarm A flag" "0,1"
|
|
line.long 0x4 "RTC_MISR,RTC masked interrupt status register"
|
|
bitfld.long 0x4 5. "ITSMF,Internal timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 4. "TSOVMF,Timestamp overflow masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TSMF,Timestamp masked flag" "0,1"
|
|
bitfld.long 0x4 2. "WUTMF,Wakeup timer masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALRBMF,Alarm B masked flag" "0,1"
|
|
bitfld.long 0x4 0. "ALRAMF,Alarm A masked flag" "0,1"
|
|
wgroup.long 0x5C++0x3
|
|
line.long 0x0 "RTC_SCR,RTC status clear register"
|
|
bitfld.long 0x0 5. "CITSF,Clear internal timestamp flag" "0,1"
|
|
bitfld.long 0x0 4. "CTSOVF,Clear timestamp overflow flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CTSF,Clear timestamp flag" "0,1"
|
|
bitfld.long 0x0 2. "CWUTF,Clear wakeup timer flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CALRBF,Clear alarm B flag" "0,1"
|
|
bitfld.long 0x0 0. "CALRAF,Clear alarm A flag" "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*")||cpuis("STM32G051*")||cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B0*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2)+1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2)+1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NSSCFG,NSS pulse feature enhancement at SPI"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DSCFG,SPI data size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "I2SCKCFG,I2S master clock generator at I2S"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2SCFG,I2S mode implementation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CRCCFG,CRC capable at SPI mode"
|
|
line.long 0x4 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x8 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0xC "SIDR,EXTI Size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NSSCFG,NSS pulse feature enhancement at SPI"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DSCFG,SPI data size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "I2SCKCFG,I2S master clock generator at I2S"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2SCFG,I2S mode implementation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CRCCFG,CRC capable at SPI mode"
|
|
line.long 0x4 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x8 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0xC "SIDR,EXTI Size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NSSCFG,NSS pulse feature enhancement at SPI"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DSCFG,SPI data size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "I2SCKCFG,I2S master clock generator at I2S"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2SCFG,I2S mode implementation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CRCCFG,CRC capable at SPI mode"
|
|
line.long 0x4 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x8 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0xC "SIDR,EXTI Size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NSSCFG,NSS pulse feature enhancement at SPI"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DSCFG,SPI data size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "I2SCKCFG,I2S master clock generator at I2S"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2SCFG,I2S mode implementation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CRCCFG,CRC capable at SPI mode"
|
|
line.long 0x4 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x8 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0xC "SIDR,EXTI Size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NSSCFG,NSS pulse feature enhancement at SPI"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DSCFG,SPI data size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "I2SCKCFG,I2S master clock generator at I2S"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2SCFG,I2S mode implementation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CRCCFG,CRC capable at SPI mode"
|
|
line.long 0x4 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x8 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0xC "SIDR,EXTI Size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 15. "BIDIMODE,Bidirectional data mode" "0,1"
|
|
bitfld.long 0x0 14. "BIDIOE,Output enable in bidirectional" "0,1"
|
|
bitfld.long 0x0 13. "CRCEN,Hardware CRC calculation" "0,1"
|
|
bitfld.long 0x0 12. "CRCNEXT,CRC transfer next" "0,1"
|
|
bitfld.long 0x0 11. "DFF,Data frame format" "0,1"
|
|
bitfld.long 0x0 10. "RXONLY,Receive only" "0,1"
|
|
bitfld.long 0x0 9. "SSM,Software slave management" "0,1"
|
|
bitfld.long 0x0 8. "SSI,Internal slave select" "0,1"
|
|
bitfld.long 0x0 7. "LSBFIRST,Frame format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "SPE,SPI enable" "0,1"
|
|
bitfld.long 0x0 3.--5. "BR,Baud rate control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "MSTR,Master selection" "0,1"
|
|
bitfld.long 0x0 1. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x0 0. "CPHA,Clock phase" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 14. "LDMA_TX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 13. "LDMA_RX,Last DMA transfer for" "0,1"
|
|
bitfld.long 0x4 12. "FRXTH,FIFO reception threshold" "0,1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "DS,Data size"
|
|
bitfld.long 0x4 7. "TXEIE,Tx buffer empty interrupt" "0,1"
|
|
bitfld.long 0x4 6. "RXNEIE,RX buffer not empty interrupt" "0,1"
|
|
bitfld.long 0x4 5. "ERRIE,Error interrupt enable" "0,1"
|
|
bitfld.long 0x4 4. "FRF,Frame format" "0,1"
|
|
bitfld.long 0x4 3. "NSSP,NSS pulse management" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SSOE,SS output enable" "0,1"
|
|
bitfld.long 0x4 1. "TXDMAEN,Tx buffer DMA enable" "0,1"
|
|
bitfld.long 0x4 0. "RXDMAEN,Rx buffer DMA enable" "0,1"
|
|
line.long 0x8 "SR,status register"
|
|
rbitfld.long 0x8 11.--12. "FTLVL,FIFO transmission level" "0,1,2,3"
|
|
rbitfld.long 0x8 9.--10. "FRLVL,FIFO reception level" "0,1,2,3"
|
|
rbitfld.long 0x8 8. "TIFRFE,TI frame format error" "0,1"
|
|
rbitfld.long 0x8 7. "BSY,Busy flag" "0,1"
|
|
rbitfld.long 0x8 6. "OVR,Overrun flag" "0,1"
|
|
rbitfld.long 0x8 5. "MODF,Mode fault" "0,1"
|
|
bitfld.long 0x8 4. "CRCERR,CRC error flag" "0,1"
|
|
rbitfld.long 0x8 3. "UDR,Underrun flag" "0,1"
|
|
rbitfld.long 0x8 2. "CHSIDE,Channel side" "0,1"
|
|
newline
|
|
rbitfld.long 0x8 1. "TXE,Transmit buffer empty" "0,1"
|
|
rbitfld.long 0x8 0. "RXNE,Receive buffer not empty" "0,1"
|
|
line.long 0xC "DR,data register"
|
|
hexmask.long.word 0xC 0.--15. 1. "DR,Data register"
|
|
line.long 0x10 "CRCPR,CRC polynomial register"
|
|
hexmask.long.word 0x10 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.long 0x14++0x7
|
|
line.long 0x0 "RXCRCR,RX CRC register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RxCRC,Rx CRC register"
|
|
line.long 0x4 "TXCRCR,TX CRC register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TxCRC,Tx CRC register"
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "I2SCFGR,configuration register"
|
|
bitfld.long 0x0 11. "I2SMOD,I2S mode selection" "0,1"
|
|
bitfld.long 0x0 10. "SE2,I2S enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "I2SCFG,I2S configuration mode" "0,1,2,3"
|
|
bitfld.long 0x0 7. "PCMSYNC,PCM frame synchronization" "0,1"
|
|
bitfld.long 0x0 4.--5. "I2SSTD,standard selection" "0,1,2,3"
|
|
bitfld.long 0x0 3. "CKPOL,Inactive state clock" "0,1"
|
|
bitfld.long 0x0 1.--2. "DATLEN,Data length to be" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CHLEN,Channel length (number of bits per audio" "0,1"
|
|
line.long 0x4 "I2SPR,prescaler register"
|
|
bitfld.long 0x4 9. "MCKOE,Master clock output enable" "0,1"
|
|
bitfld.long 0x4 8. "ODD,Odd factor for the" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "I2SDIV,linear prescaler"
|
|
rgroup.long 0x3F0++0xF
|
|
line.long 0x0 "HWCFGR,hardware configuration"
|
|
hexmask.long.byte 0x0 16.--19. 1. "NSSCFG,NSS pulse feature enhancement at SPI"
|
|
hexmask.long.byte 0x0 12.--15. 1. "DSCFG,SPI data size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "I2SCKCFG,I2S master clock generator at I2S"
|
|
hexmask.long.byte 0x0 4.--7. 1. "I2SCFG,I2S mode implementation"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CRCCFG,CRC capable at SPI mode"
|
|
line.long 0x4 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x8 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0xC "SIDR,EXTI Size ID register"
|
|
hexmask.long 0xC 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2)+1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2)+1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40003C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPIx_RXCRCR value,1: CRC value received does not match the.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2)+1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40003C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "SPI2"
|
|
base ad:0x40003800
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
tree "SPI3"
|
|
base ad:0x40003C00
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x0 15. "BIDIMODE,Bidirectional data mode enable." "0: 2-line unidirectional data mode selected,1: 1-line bidirectional data mode selected"
|
|
bitfld.word 0x0 14. "BIDIOE,Output enable in bidirectional mode" "0: Output disabled (receive-only mode),1: Output enabled (transmit-only mode)"
|
|
newline
|
|
bitfld.word 0x0 13. "CRCEN,Hardware CRC calculation enable" "0: CRC calculation disabled,1: CRC calculation enabled"
|
|
bitfld.word 0x0 12. "CRCNEXT,Transmit CRC next" "0: Next transmit value is from Tx buffer.,1: Next transmit value is from Tx CRC register."
|
|
newline
|
|
bitfld.word 0x0 11. "CRCL,CRC length" "0: 8-bit CRC length,1: 16-bit CRC length"
|
|
bitfld.word 0x0 10. "RXONLY,Receive only mode enabled." "0: Full-duplex (Transmit and receive),1: Output disabled (Receive-only mode)"
|
|
newline
|
|
bitfld.word 0x0 9. "SSM,Software slave management" "0: Software slave management disabled,1: Software slave management enabled"
|
|
bitfld.word 0x0 8. "SSI,Internal slave select" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "LSBFIRST,Frame format" "0: data is transmitted / received with the MSB first,1: data is transmitted / received with the LSB first"
|
|
bitfld.word 0x0 6. "SPE,SPI enable" "0: Peripheral disabled,1: Peripheral enabled"
|
|
newline
|
|
bitfld.word 0x0 3.--5. "BR,Baud rate control" "0: fPCLK/2,1: fPCLK/4,2: fPCLK/8,3: fPCLK/16,4: fPCLK/32,5: fPCLK/64,6: fPCLK/128,7: fPCLK/256"
|
|
bitfld.word 0x0 2. "MSTR,Master selection" "0: Slave configuration,1: Master configuration"
|
|
newline
|
|
bitfld.word 0x0 1. "CPOL,Clock polarity" "0: CK to 0 when idle,1: CK to 1 when idle"
|
|
bitfld.word 0x0 0. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x0 14. "LDMA_TX,Last DMA transfer for transmission" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
bitfld.word 0x0 13. "LDMA_RX,Last DMA transfer for reception" "0: Number of data to transfer is even,1: Number of data to transfer is odd"
|
|
newline
|
|
bitfld.word 0x0 12. "FRXTH,FIFO reception threshold" "0: RXNE event is generated if the FIFO level is..,1: RXNE event is generated if the FIFO level is.."
|
|
hexmask.word.byte 0x0 8.--11. 1. "DS,Data size"
|
|
newline
|
|
bitfld.word 0x0 7. "TXEIE,Tx buffer empty interrupt enable" "0: TXE interrupt masked,1: TXE interrupt not masked. Used to generate an.."
|
|
bitfld.word 0x0 6. "RXNEIE,RX buffer not empty interrupt enable" "0: RXNE interrupt masked,1: RXNE interrupt not masked. Used to generate an.."
|
|
newline
|
|
bitfld.word 0x0 5. "ERRIE,Error interrupt enable" "0: Error interrupt is masked,1: Error interrupt is enabled"
|
|
bitfld.word 0x0 4. "FRF,Frame format" "0: SPI Motorola mode,?"
|
|
newline
|
|
bitfld.word 0x0 3. "NSSP,NSS pulse management" "0: No NSS pulse,1: NSS pulse generated"
|
|
bitfld.word 0x0 2. "SSOE,SS output enable" "0: SS output is disabled in master mode and the SPI..,1: SS output is enabled in master mode and when the.."
|
|
newline
|
|
bitfld.word 0x0 1. "TXDMAEN,Tx buffer DMA enable" "0: Tx buffer DMA disabled,1: Tx buffer DMA enabled"
|
|
bitfld.word 0x0 0. "RXDMAEN,Rx buffer DMA enable" "0: Rx buffer DMA disabled,1: Rx buffer DMA enabled"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x0 11.--12. "FTLVL,FIFO transmission level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full (considered as FULL when the FIFO.."
|
|
rbitfld.word 0x0 9.--10. "FRLVL,FIFO reception level" "0: FIFO empty,1: 1/4 FIFO,2: 1/2 FIFO,3: FIFO full"
|
|
newline
|
|
rbitfld.word 0x0 8. "FRE,Frame format error" "0: No frame format error,1: A frame format error occurred"
|
|
rbitfld.word 0x0 7. "BSY,Busy flag" "0: SPI (or I2S) not busy,1: SPI (or I2S) is busy in communication or Tx.."
|
|
newline
|
|
rbitfld.word 0x0 6. "OVR,Overrun flag" "0: No overrun occurred,1: Overrun occurred"
|
|
rbitfld.word 0x0 5. "MODF,Mode fault" "0: No mode fault occurred,1: Mode fault occurred"
|
|
newline
|
|
bitfld.word 0x0 4. "CRCERR,CRC error flag" "0: CRC value received matches the SPI_RXCRCR value,1: CRC value received does not match the SPI_RXCRCR.."
|
|
rbitfld.word 0x0 3. "UDR,Underrun flag" "0: No underrun occurred,1: Underrun occurred"
|
|
newline
|
|
rbitfld.word 0x0 2. "CHSIDE,Channel side" "0: Channel Left has to be transmitted or has been..,1: Channel Right has to be transmitted or has been.."
|
|
rbitfld.word 0x0 1. "TXE,Transmit buffer empty" "0: Tx buffer not empty,1: Tx buffer empty"
|
|
newline
|
|
rbitfld.word 0x0 0. "RXNE,Receive buffer not empty" "0: Rx buffer empty,1: Rx buffer not empty"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SPI_DR,SPI data register"
|
|
hexmask.word 0x0 0.--15. 1. "DR,Data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPI_CRCPR,SPI CRC polynomial register"
|
|
hexmask.word 0x0 0.--15. 1. "CRCPOLY,CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x0 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "RXCRC,Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x0 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x0 0.--15. 1. "TXCRC,Tx CRC register"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x0 12. "ASTRTEN,Asynchronous start enable." "0: The Asynchronous start is disabled.,1: The Asynchronous start is enabled."
|
|
bitfld.word 0x0 11. "I2SMOD,I2S mode selection" "0: SPI mode is selected,1: I2S mode is selected"
|
|
newline
|
|
bitfld.word 0x0 10. "I2SE,I2S enable" "0: I2S peripheral is disabled,1: I2S peripheral is enabled"
|
|
bitfld.word 0x0 8.--9. "I2SCFG,I2S configuration mode" "0: Slave - transmit,1: Slave - receive,2: Master - transmit,3: Master - receive"
|
|
newline
|
|
bitfld.word 0x0 7. "PCMSYNC,PCM frame synchronization" "0: Short frame synchronization,1: Long frame synchronization"
|
|
bitfld.word 0x0 4.--5. "I2SSTD,I2S standard selection" "0: I2S Philips standard,1: MSB justified standard (left justified),2: LSB justified standard (right justified),3: PCM standard"
|
|
newline
|
|
bitfld.word 0x0 3. "CKPOL,Inactive state clock polarity" "0: I2S clock inactive state is low level,1: I2S clock inactive state is high level"
|
|
bitfld.word 0x0 1.--2. "DATLEN,Data length to be transferred" "0: 16-bit data length,1: 24-bit data length,2: 32-bit data length,3: Not allowed"
|
|
newline
|
|
bitfld.word 0x0 0. "CHLEN,Channel length (number of bits per audio channel)" "0: 16-bit wide,1: 32-bit wide"
|
|
group.word 0x20++0x1
|
|
line.word 0x0 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x0 9. "MCKOE,Master clock output enable" "0: Master clock output is disabled,1: Master clock output is enabled"
|
|
bitfld.word 0x0 8. "ODD,Odd factor for the prescaler" "0: Real divider value is = I2SDIV *2,1: Real divider value is = (I2SDIV * 2) + 1"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--7. 1. "I2SDIV,I2S linear prescaler"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "SYSCFG (System Configuration Controller)"
|
|
base ad:0x40010000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFGR1,SYSCFG configuration register"
|
|
bitfld.long 0x0 24. "I2C3_FMP,I2C3_FMP" "0,1"
|
|
bitfld.long 0x0 23. "I2C_PA10_FMP,Fast Mode Plus (FM+) driving capability" "0,1"
|
|
bitfld.long 0x0 22. "I2C_PA9_FMP,Fast Mode Plus (FM+) driving capability" "0,1"
|
|
bitfld.long 0x0 21. "I2C2_FMP,FM+ driving capability activation for" "0,1"
|
|
bitfld.long 0x0 20. "I2C1_FMP,FM+ driving capability activation for" "0,1"
|
|
bitfld.long 0x0 19. "I2C_PB9_FMP,I2C_PB9_FMP" "0,1"
|
|
bitfld.long 0x0 18. "I2C_PB8_FMP,I2C_PB8_FMP" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "I2C_PB7_FMP,I2C_PB7_FMP" "0,1"
|
|
bitfld.long 0x0 16. "I2C_PBx_FMP,Fast Mode Plus (FM+) driving capability" "0,1"
|
|
bitfld.long 0x0 10. "UCPD2_STROBE,Strobe signal bit for" "0,1"
|
|
bitfld.long 0x0 9. "UCPD1_STROBE,Strobe signal bit for" "0,1"
|
|
bitfld.long 0x0 8. "BOOSTEN,I/O analog switch voltage booster" "0,1"
|
|
bitfld.long 0x0 6.--7. "IR_MOD,IR Modulation Envelope signal" "0,1,2,3"
|
|
bitfld.long 0x0 5. "IR_POL,IR output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PA12_RMP,PA11 and PA12 remapping" "0,1"
|
|
bitfld.long 0x0 3. "PA11_RMP,PA11_RMP" "0,1"
|
|
bitfld.long 0x0 0.--1. "MEM_MODE,Memory mapping selection" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CFGR2,SYSCFG configuration register"
|
|
bitfld.long 0x0 8. "SRAM_PEF,SRAM parity error flag" "0,1"
|
|
bitfld.long 0x0 3. "ECC_LOCK,ECC error lock bit" "0,1"
|
|
bitfld.long 0x0 1. "SRAM_PARITY_LOCK,SRAM parity lock bit" "0,1"
|
|
bitfld.long 0x0 0. "LOCKUP_LOCK,Cortex-M0+ LOCKUP bit enable" "0,1"
|
|
rgroup.long 0x80++0x3
|
|
line.long 0x0 "ITLINE0,interrupt line 0 status"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending" "0,1"
|
|
rgroup.long 0x88++0x33
|
|
line.long 0x0 "ITLINE2,interrupt line 2 status"
|
|
bitfld.long 0x0 1. "RTC,RTC" "0,1"
|
|
bitfld.long 0x0 0. "TAMP,TAMP" "0,1"
|
|
line.long 0x4 "ITLINE3,interrupt line 3 status"
|
|
bitfld.long 0x4 1. "FLASH_ECC,FLASH_ECC" "0,1"
|
|
bitfld.long 0x4 0. "FLASH_ITF,FLASH_ITF" "0,1"
|
|
line.long 0x8 "ITLINE4,interrupt line 4 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 1. "CRS,CRS" "0,1"
|
|
endif
|
|
bitfld.long 0x8 0. "RCC,RCC" "0,1"
|
|
line.long 0xC "ITLINE5,interrupt line 5 status"
|
|
bitfld.long 0xC 1. "EXTI1,EXTI1" "0,1"
|
|
bitfld.long 0xC 0. "EXTI0,EXTI0" "0,1"
|
|
line.long 0x10 "ITLINE6,interrupt line 6 status"
|
|
bitfld.long 0x10 1. "EXTI3,EXTI3" "0,1"
|
|
bitfld.long 0x10 0. "EXTI2,EXTI2" "0,1"
|
|
line.long 0x14 "ITLINE7,interrupt line 7 status"
|
|
bitfld.long 0x14 11. "EXTI15,EXTI15" "0,1"
|
|
bitfld.long 0x14 10. "EXTI14,EXTI14" "0,1"
|
|
bitfld.long 0x14 9. "EXTI13,EXTI13" "0,1"
|
|
bitfld.long 0x14 8. "EXTI12,EXTI12" "0,1"
|
|
bitfld.long 0x14 7. "EXTI11,EXTI11" "0,1"
|
|
bitfld.long 0x14 6. "EXTI10,EXTI10" "0,1"
|
|
bitfld.long 0x14 5. "EXTI9,EXTI9" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "EXTI8,EXTI8" "0,1"
|
|
bitfld.long 0x14 3. "EXTI7,EXTI7" "0,1"
|
|
bitfld.long 0x14 2. "EXTI6,EXTI6" "0,1"
|
|
bitfld.long 0x14 1. "EXTI5,EXTI5" "0,1"
|
|
bitfld.long 0x14 0. "EXTI4,EXTI4" "0,1"
|
|
line.long 0x18 "ITLINE8,interrupt line 8 status"
|
|
bitfld.long 0x18 2. "USB,USB" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 1. "UCPD2,UCPD2" "0,1"
|
|
bitfld.long 0x18 0. "UCPD1,UCPD1" "0,1"
|
|
endif
|
|
line.long 0x1C "ITLINE9,interrupt line 9 status"
|
|
bitfld.long 0x1C 0. "DMA1_CH1,DMA1_CH1" "0,1"
|
|
line.long 0x20 "ITLINE10,interrupt line 10 status"
|
|
bitfld.long 0x20 1. "DMA1_CH3,DMA1_CH3" "0,1"
|
|
bitfld.long 0x20 0. "DMA1_CH2,DMA1_CH1" "0,1"
|
|
line.long 0x24 "ITLINE11,interrupt line 11 status"
|
|
bitfld.long 0x24 9. "DMA2_CH5,DMA2_CH5" "0,1"
|
|
bitfld.long 0x24 8. "DMA2_CH4,DMA2_CH4" "0,1"
|
|
bitfld.long 0x24 7. "DMA2_CH3,DMA2_CH3" "0,1"
|
|
bitfld.long 0x24 6. "DMA2_CH2,DMA2_CH2" "0,1"
|
|
bitfld.long 0x24 5. "DMA2_CH1,DMA2_CH1" "0,1"
|
|
bitfld.long 0x24 4. "DMA1_CH7,DMA1_CH7" "0,1"
|
|
bitfld.long 0x24 3. "DMA1_CH6,DMA1_CH6" "0,1"
|
|
newline
|
|
bitfld.long 0x24 2. "DMA1_CH5,DMA1_CH5" "0,1"
|
|
bitfld.long 0x24 1. "DMA1_CH4,DMA1_CH4" "0,1"
|
|
bitfld.long 0x24 0. "DMAMUX,DMAMUX" "0,1"
|
|
line.long 0x28 "ITLINE12,interrupt line 12 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
newline
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x28 3. "COMP3,COMP3" "0,1"
|
|
bitfld.long 0x28 2. "COMP2,COMP2" "0,1"
|
|
bitfld.long 0x28 1. "COMP1,COMP1" "0,1"
|
|
endif
|
|
bitfld.long 0x28 0. "ADC,ADC" "0,1"
|
|
line.long 0x2C "ITLINE13,interrupt line 13 status"
|
|
bitfld.long 0x2C 3. "TIM1_BRK,TIM1_BRK" "0,1"
|
|
bitfld.long 0x2C 2. "TIM1_UPD,TIM1_UPD" "0,1"
|
|
bitfld.long 0x2C 1. "TIM1_TRG,TIM1_TRG" "0,1"
|
|
bitfld.long 0x2C 0. "TIM1_CCU,TIM1_CCU" "0,1"
|
|
line.long 0x30 "ITLINE14,interrupt line 14 status"
|
|
bitfld.long 0x30 0. "TIM1_CC,TIM1_CC" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rgroup.long 0xBC++0x3
|
|
line.long 0x0 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x0 0. "TIM2,TIM2" "0,1"
|
|
rgroup.long 0xF8++0x3
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
endif
|
|
rgroup.long 0xC0++0x37
|
|
line.long 0x0 "ITLINE16,interrupt line 16 status"
|
|
bitfld.long 0x0 1. "TIM4,TIM4" "0,1"
|
|
bitfld.long 0x0 0. "TIM3,TIM3" "0,1"
|
|
line.long 0x4 "ITLINE17,interrupt line 17 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x4 2. "LPTIM1,LPTIM1" "0,1"
|
|
bitfld.long 0x4 1. "DAC,DAC" "0,1"
|
|
endif
|
|
bitfld.long 0x4 0. "TIM6,TIM6" "0,1"
|
|
line.long 0x8 "ITLINE18,interrupt line 18 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x8 1. "LPTIM2,LPTIM2" "0,1"
|
|
endif
|
|
bitfld.long 0x8 0. "TIM7,TIM7" "0,1"
|
|
line.long 0xC "ITLINE19,interrupt line 19 status"
|
|
bitfld.long 0xC 0. "TIM14,TIM14" "0,1"
|
|
line.long 0x10 "ITLINE20,interrupt line 20 status"
|
|
bitfld.long 0x10 0. "TIM15,TIM15" "0,1"
|
|
line.long 0x14 "ITLINE21,interrupt line 21 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x14 2. "FDCAN2_IT0,FDCAN2_IT0" "0,1"
|
|
bitfld.long 0x14 1. "FDCAN1_IT0,FDCAN1_IT0" "0,1"
|
|
endif
|
|
bitfld.long 0x14 0. "TIM16,TIM16" "0,1"
|
|
line.long 0x18 "ITLINE22,interrupt line 22 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x18 2. "FDCAN2_IT1,FDCAN2_IT1" "0,1"
|
|
bitfld.long 0x18 1. "FDCAN1_IT1,FDCAN1_IT1" "0,1"
|
|
endif
|
|
bitfld.long 0x18 0. "TIM17,TIM17" "0,1"
|
|
line.long 0x1C "ITLINE23,interrupt line 23 status"
|
|
bitfld.long 0x1C 0. "I2C1,I2C1" "0,1"
|
|
line.long 0x20 "ITLINE24,interrupt line 24 status"
|
|
bitfld.long 0x20 1. "I2C3,I2C3" "0,1"
|
|
bitfld.long 0x20 0. "I2C2,I2C2" "0,1"
|
|
line.long 0x24 "ITLINE25,interrupt line 25 status"
|
|
bitfld.long 0x24 0. "SPI1,SPI1" "0,1"
|
|
line.long 0x28 "ITLINE26,interrupt line 26 status"
|
|
bitfld.long 0x28 14. "SPI3,SPI3" "0,1"
|
|
bitfld.long 0x28 0. "SPI2,SPI2" "0,1"
|
|
line.long 0x2C "ITLINE27,interrupt line 27 status"
|
|
bitfld.long 0x2C 0. "USART1,USART1" "0,1"
|
|
line.long 0x30 "ITLINE28,interrupt line 28 status"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x30 1. "LPUART2,LPUART2" "0,1"
|
|
endif
|
|
bitfld.long 0x30 0. "USART2,USART2" "0,1"
|
|
line.long 0x34 "ITLINE29,interrupt line 29 status"
|
|
bitfld.long 0x34 4. "USART6,USART6" "0,1"
|
|
bitfld.long 0x34 3. "USART5,USART5" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x34 2. "LPUART1,LPUART1" "0,1"
|
|
endif
|
|
bitfld.long 0x34 1. "USART4,USART4" "0,1"
|
|
bitfld.long 0x34 0. "USART3,USART3" "0,1"
|
|
sif (cpuis("STM32G031*"))
|
|
rgroup.long 0xF8++0x7
|
|
line.long 0x0 "ITLINE30,interrupt line 25 status"
|
|
bitfld.long 0x0 0. "CEC,CEC" "0,1"
|
|
line.long 0x4 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x4 1. "AES,AES" "0,1"
|
|
bitfld.long 0x4 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 25 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
tree "SYSCFG_ITLINE (System Configuration Controller (ITLINE))"
|
|
base ad:0x40010080
|
|
rgroup.long 0x80++0x1F
|
|
line.long 0x0 "ITLINE0,interrupt line 0 status"
|
|
bitfld.long 0x0 0. "WWDG,Window watchdog interrupt pending" "0,1"
|
|
line.long 0x4 "ITLINE1,interrupt line 1 status"
|
|
bitfld.long 0x4 0. "PVDOUT,PVD supply monitoring interrupt request" "0,1"
|
|
line.long 0x8 "ITLINE2,interrupt line 2 status"
|
|
bitfld.long 0x8 1. "RTC,RTC" "0,1"
|
|
bitfld.long 0x8 0. "TAMP,TAMP" "0,1"
|
|
line.long 0xC "ITLINE3,interrupt line 3 status"
|
|
bitfld.long 0xC 1. "FLASH_ECC,FLASH_ECC" "0,1"
|
|
bitfld.long 0xC 0. "FLASH_ITF,FLASH_ITF" "0,1"
|
|
line.long 0x10 "ITLINE4,interrupt line 4 status"
|
|
bitfld.long 0x10 0. "RCC,RCC" "0,1"
|
|
line.long 0x14 "ITLINE5,interrupt line 5 status"
|
|
bitfld.long 0x14 1. "EXTI1,EXTI1" "0,1"
|
|
bitfld.long 0x14 0. "EXTI0,EXTI0" "0,1"
|
|
line.long 0x18 "ITLINE6,interrupt line 6 status"
|
|
bitfld.long 0x18 1. "EXTI3,EXTI3" "0,1"
|
|
bitfld.long 0x18 0. "EXTI2,EXTI2" "0,1"
|
|
line.long 0x1C "ITLINE7,interrupt line 7 status"
|
|
bitfld.long 0x1C 11. "EXTI15,EXTI15" "0,1"
|
|
bitfld.long 0x1C 10. "EXTI14,EXTI14" "0,1"
|
|
bitfld.long 0x1C 9. "EXTI13,EXTI13" "0,1"
|
|
bitfld.long 0x1C 8. "EXTI12,EXTI12" "0,1"
|
|
bitfld.long 0x1C 7. "EXTI11,EXTI11" "0,1"
|
|
bitfld.long 0x1C 6. "EXTI10,EXTI10" "0,1"
|
|
bitfld.long 0x1C 5. "EXTI9,EXTI9" "0,1"
|
|
bitfld.long 0x1C 4. "EXTI8,EXTI8" "0,1"
|
|
bitfld.long 0x1C 3. "EXTI7,EXTI7" "0,1"
|
|
bitfld.long 0x1C 2. "EXTI6,EXTI6" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "EXTI5,EXTI5" "0,1"
|
|
bitfld.long 0x1C 0. "EXTI4,EXTI4" "0,1"
|
|
rgroup.long 0xA4++0x2B
|
|
line.long 0x0 "ITLINE9,interrupt line 9 status"
|
|
bitfld.long 0x0 0. "DMA1_CH1,DMA1_CH1" "0,1"
|
|
line.long 0x4 "ITLINE10,interrupt line 10 status"
|
|
bitfld.long 0x4 1. "DMA1_CH3,DMA1_CH3" "0,1"
|
|
bitfld.long 0x4 0. "DMA1_CH2,DMA1_CH1" "0,1"
|
|
line.long 0x8 "ITLINE11,interrupt line 11 status"
|
|
bitfld.long 0x8 2. "DMA1_CH5,DMA1_CH5" "0,1"
|
|
bitfld.long 0x8 1. "DMA1_CH4,DMA1_CH4" "0,1"
|
|
bitfld.long 0x8 0. "DMAMUX,DMAMUX" "0,1"
|
|
line.long 0xC "ITLINE12,interrupt line 12 status"
|
|
bitfld.long 0xC 0. "ADC,ADC" "0,1"
|
|
line.long 0x10 "ITLINE13,interrupt line 13 status"
|
|
bitfld.long 0x10 3. "TIM1_BRK,TIM1_BRK" "0,1"
|
|
bitfld.long 0x10 2. "TIM1_UPD,TIM1_UPD" "0,1"
|
|
bitfld.long 0x10 1. "TIM1_TRG,TIM1_TRG" "0,1"
|
|
bitfld.long 0x10 0. "TIM1_CCU,TIM1_CCU" "0,1"
|
|
line.long 0x14 "ITLINE14,interrupt line 14 status"
|
|
bitfld.long 0x14 0. "TIM1_CC,TIM1_CC" "0,1"
|
|
line.long 0x18 "ITLINE15,interrupt line 15 status"
|
|
bitfld.long 0x18 0. "TIM2,TIM2" "0,1"
|
|
line.long 0x1C "ITLINE16,interrupt line 16 status"
|
|
bitfld.long 0x1C 0. "TIM3,TIM3" "0,1"
|
|
line.long 0x20 "ITLINE17,interrupt line 17 status"
|
|
bitfld.long 0x20 2. "LPTIM1,LPTIM1" "0,1"
|
|
line.long 0x24 "ITLINE18,interrupt line 18 status"
|
|
bitfld.long 0x24 1. "LPTIM2,LPTIM2" "0,1"
|
|
line.long 0x28 "ITLINE19,interrupt line 19 status"
|
|
bitfld.long 0x28 0. "TIM14,TIM14" "0,1"
|
|
rgroup.long 0xD4++0x23
|
|
line.long 0x0 "ITLINE21,interrupt line 21 status"
|
|
bitfld.long 0x0 0. "TIM16,TIM16" "0,1"
|
|
line.long 0x4 "ITLINE22,interrupt line 22 status"
|
|
bitfld.long 0x4 0. "TIM17,TIM17" "0,1"
|
|
line.long 0x8 "ITLINE23,interrupt line 23 status"
|
|
bitfld.long 0x8 0. "I2C1,I2C1" "0,1"
|
|
line.long 0xC "ITLINE24,interrupt line 24 status"
|
|
bitfld.long 0xC 0. "I2C2,I2C2" "0,1"
|
|
line.long 0x10 "ITLINE25,interrupt line 25 status"
|
|
bitfld.long 0x10 0. "SPI1,SPI1" "0,1"
|
|
line.long 0x14 "ITLINE26,interrupt line 26 status"
|
|
bitfld.long 0x14 0. "SPI2,SPI2" "0,1"
|
|
line.long 0x18 "ITLINE27,interrupt line 27 status"
|
|
bitfld.long 0x18 0. "USART1,USART1" "0,1"
|
|
line.long 0x1C "ITLINE28,interrupt line 28 status"
|
|
bitfld.long 0x1C 0. "USART2,USART2" "0,1"
|
|
line.long 0x20 "ITLINE29,interrupt line 29 status"
|
|
bitfld.long 0x20 2. "USART5,USART5" "0,1"
|
|
sif (cpuis("STM32G041*"))
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "ITLINE31,interrupt line 31 status"
|
|
bitfld.long 0x0 1. "AES,AES" "0,1"
|
|
bitfld.long 0x0 0. "RNG,RNG" "0,1"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "TAMP (Tamper and Backup Registers)"
|
|
base ad:0x4000B000
|
|
sif (cpuis("STM32G030*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled."
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 3 input..,1: If TAMPFLT equal 00 Tamper 3 input staying high.."
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 2 input..,1: If TAMPFLT equal 00 Tamper 2 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 1 input..,1: If TAMPFLT equal 00 Tamper 1 input staying high.."
|
|
bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers.,1: Tamper 3 event does not erase the backup.."
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1Hz when RTCCLK = 32768Hz),1: RTCCLK / 16384 (2Hz when RTCCLK = 32768Hz),2: RTCCLK / 8192 (4Hz when RTCCLK = 32768Hz),3: RTCCLK / 4096 (8Hz when RTCCLK = 32768Hz),4: RTCCLK / 2048 (16Hz when RTCCLK = 32768Hz),5: RTCCLK / 1024 (32Hz when RTCCLK = 32768Hz),6: RTCCLK / 512 (64Hz when RTCCLK = 32768Hz),7: RTCCLK / 256 (128Hz when RTCCLK = 32768Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.."
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G031*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,ITAMP4E" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,ITAMP4IE" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SR,TAMP status register"
|
|
bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4F,ITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "ITAMP1F,ITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1"
|
|
line.long 0x4 "MISR,TAMP masked interrupt status"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,ITAMP4MF" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1MF:" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "SCR,TAMP status clear register"
|
|
bitfld.long 0x0 22. "CITAMP7F,CITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "CITAMP6F,CITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "CITAMP4F,CITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,BKP"
|
|
line.long 0x8 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,BKP"
|
|
line.long 0xC "BKP3R,TAMP backup register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,BKP"
|
|
line.long 0x10 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,BKP"
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,ITAMP4E" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,ITAMP4IE" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SR,TAMP status register"
|
|
bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4F,ITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "ITAMP1F,ITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1"
|
|
line.long 0x4 "MISR,TAMP masked interrupt status"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,ITAMP4MF" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1MF:" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "SCR,TAMP status clear register"
|
|
bitfld.long 0x0 22. "CITAMP7F,CITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "CITAMP6F,CITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "CITAMP4F,CITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,BKP"
|
|
line.long 0x8 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,BKP"
|
|
line.long 0xC "BKP3R,TAMP backup register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,BKP"
|
|
line.long 0x10 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,BKP"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled."
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 3 input staying..,1: If TAMPFLT = 00 Tamper 3 input staying high.."
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 2 input staying..,1: If TAMPFLT = 00 Tamper 2 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 1 input staying..,1: If TAMPFLT = 00 Tamper 1 input staying high.."
|
|
bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers.,1: Tamper 3 event does not erase the backup.."
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1Hz when RTCCLK = 32768Hz),1: RTCCLK / 16384 (2Hz when RTCCLK = 32768Hz),2: RTCCLK / 8192 (4Hz when RTCCLK = 32768Hz),3: RTCCLK / 4096 (8Hz when RTCCLK = 32768Hz),4: RTCCLK / 2048 (16Hz when RTCCLK = 32768Hz),5: RTCCLK / 1024 (32Hz when RTCCLK = 32768Hz),6: RTCCLK / 512 (64Hz when RTCCLK = 32768Hz),7: RTCCLK / 256 (128Hz when RTCCLK = 32768Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.."
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 2 input staying..,1: If TAMPFLT = 00 Tamper 2 input staying high.."
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 1 input staying..,1: If TAMPFLT = 00 Tamper 1 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT Tamper 2 input staying low triggers a..,1: If TAMPFLT Tamper 2 input staying high triggers.."
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT input staying low triggers a tamper..,1: If TAMPFLT Tamper 1 input staying high triggers.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled."
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 3 input staying..,1: If TAMPFLT=00 Tamper 3 input staying high.."
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 2 input..,1: If TAMPFLT equal 00 Tamper 2 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT different from 00 Tamper 1 input..,1: If TAMPFLT equal 00 Tamper 1 input staying high.."
|
|
bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers.,1: Tamper 3 event does not erase the backup.."
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1Hz when RTCCLK = 32768Hz),1: RTCCLK / 16384 (2Hz when RTCCLK = 32768Hz),2: RTCCLK / 8192 (4Hz when RTCCLK = 32768Hz),3: RTCCLK / 4096 (8Hz when RTCCLK = 32768Hz),4: RTCCLK / 2048 (16Hz when RTCCLK = 32768Hz),5: RTCCLK / 1024 (32Hz when RTCCLK = 32768Hz),6: RTCCLK / 512 (64Hz when RTCCLK = 32768Hz),7: RTCCLK / 256 (128Hz when RTCCLK = 32768Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.."
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,ITAMP4E" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,ITAMP4IE" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SR,TAMP status register"
|
|
bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4F,ITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "ITAMP1F,ITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1"
|
|
line.long 0x4 "MISR,TAMP masked interrupt status"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,ITAMP4MF" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1MF:" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "SCR,TAMP status clear register"
|
|
bitfld.long 0x0 22. "CITAMP7F,CITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "CITAMP6F,CITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "CITAMP4F,CITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,BKP"
|
|
line.long 0x8 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,BKP"
|
|
line.long 0xC "BKP3R,TAMP backup register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,BKP"
|
|
line.long 0x10 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,BKP"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,TAMP hardware configuration register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRUST_ZONE,TRUST_ZONE"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PTIONREG_OUT,PTIONREG_OUT"
|
|
line.long 0x4 "HWCFGR1,TAMP hardware configuration register"
|
|
hexmask.long.word 0x4 16.--31. 1. "INT_TAMPER,INT_TAMPER"
|
|
hexmask.long.byte 0x4 12.--15. 1. "ACTIVE_TAMPER,ACTIVE_TAMPER"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "TAMPER,TAMPER"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BACKUP_REGS,BACKUP_REGS"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,EXTI Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,ITAMP6E" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5E,ITAMP5E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,ITAMP4E" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3E,ITAMP3E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1E,ITAMP1E" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2E,TAMP2E" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,TAMP1E" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,TAMP2TRG" "0,1"
|
|
bitfld.long 0x4 24. "TAMP1TRG,TAMP1TRG" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,TAMP2MSK" "0,1"
|
|
bitfld.long 0x4 16. "TAMP1MSK,TAMP1MSK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,TAMP2NOER" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1NOER,TAMP1NOER" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMPPUDIS" "0,1"
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMPPRCH" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMPFLT" "0,1,2,3"
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,TAMPFREQ" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,ITAMP6IE" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5IE,ITAMP5IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,ITAMP4IE" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3IE,ITAMP3IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ITAMP1IE,ITAMP1IE" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2IE,TAMP2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,TAMP1IE" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "SR,TAMP status register"
|
|
bitfld.long 0x0 22. "ITAMP7F,ITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "ITAMP6F,ITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "ITAMP5F,ITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "ITAMP4F,ITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "ITAMP3F,ITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "ITAMP1F,ITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1F" "0,1"
|
|
line.long 0x4 "MISR,TAMP masked interrupt status"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ITAMP6MF" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,ITAMP5MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,ITAMP4MF" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,ITAMP3MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "ITAMP1MF,ITAMP1MF" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2MF" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1MF:" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "SCR,TAMP status clear register"
|
|
bitfld.long 0x0 22. "CITAMP7F,CITAMP7F" "0,1"
|
|
bitfld.long 0x0 21. "CITAMP6F,CITAMP6F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "CITAMP5F,CITAMP5F" "0,1"
|
|
bitfld.long 0x0 19. "CITAMP4F,CITAMP4F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CITAMP3F,CITAMP3F" "0,1"
|
|
bitfld.long 0x0 16. "CITAMP1F,CITAMP1F" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,CTAMP2F" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,CTAMP1F" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "BKP0R,TAMP backup register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,BKP"
|
|
line.long 0x4 "BKP1R,TAMP backup register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,BKP"
|
|
line.long 0x8 "BKP2R,TAMP backup register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,BKP"
|
|
line.long 0xC "BKP3R,TAMP backup register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,BKP"
|
|
line.long 0x10 "BKP4R,TAMP backup register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,BKP"
|
|
rgroup.long 0x3EC++0x13
|
|
line.long 0x0 "HWCFGR2,TAMP hardware configuration register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TRUST_ZONE,TRUST_ZONE"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PTIONREG_OUT,PTIONREG_OUT"
|
|
line.long 0x4 "HWCFGR1,TAMP hardware configuration register"
|
|
hexmask.long.word 0x4 16.--31. 1. "INT_TAMPER,INT_TAMPER"
|
|
hexmask.long.byte 0x4 12.--15. 1. "ACTIVE_TAMPER,ACTIVE_TAMPER"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "TAMPER,TAMPER"
|
|
hexmask.long.byte 0x4 0.--7. 1. "BACKUP_REGS,BACKUP_REGS"
|
|
line.long 0x8 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x8 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x8 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0xC "IPIDR,EXTI Identification register"
|
|
hexmask.long 0xC 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x10 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x10 0.--31. 1. "SID,Size Identification"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3E,Tamper detection on TAMP_IN3 enable" "0: Tamper detection on TAMP_IN3 is disabled.,1: Tamper detection on TAMP_IN3 is enabled."
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 26. "TAMP3TRG,Active level for tamper 3 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 3 input staying..,1: If TAMPFLT =00 Tamper 3 input staying high.."
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 2 input staying..,1: If TAMPFLT = 00 Tamper 2 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT different 00 Tamper 1 input staying..,1: If TAMPFLT = 00 Tamper 1 input staying high.."
|
|
bitfld.long 0x4 18. "TAMP3MSK,Tamper 3 mask" "0: Tamper 3 event generates a trigger event and..,1: Tamper 3 event generates a trigger event. TAMP3F.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3NOER,Tamper 3 no erase" "0: Tamper 3 event erases the backup registers.,1: Tamper 3 event does not erase the backup.."
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1Hz when RTCCLK = 32768Hz),1: RTCCLK / 16384 (2Hz when RTCCLK = 32768Hz),2: RTCCLK / 8192 (4Hz when RTCCLK = 32768Hz),3: RTCCLK / 4096 (8Hz when RTCCLK = 32768Hz),4: RTCCLK / 2048 (16Hz when RTCCLK = 32768Hz),5: RTCCLK / 1024 (32Hz when RTCCLK = 32768Hz),6: RTCCLK / 512 (64Hz when RTCCLK = 32768Hz),7: RTCCLK / 256 (128Hz when RTCCLK = 32768Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3IE,Tamper 3 interrupt enable" "0: Tamper 3 interrupt disabled.,1: Tamper 3 interrupt enabled.."
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMP3F,TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TAMP3MF,TAMP3 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTAMP3F,Clear TAMP3 detection flag" "0,1"
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT diferent 00 Tamper 2 input staying..,1: If TAMPFLT = 00 Tamper 2 input staying high.."
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT diferent 00 Tamper 1 input staying..,1: If TAMPFLT = 00 Tamper 1 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "TAMP_CR1,TAMP control register 1"
|
|
bitfld.long 0x0 21. "ITAMP6E,Internal tamper 6 enable: ST manufacturer readout" "0: Internal tamper 6 disabled.,1: Internal tamper 6 enabled: a tamper is generated.."
|
|
bitfld.long 0x0 20. "ITAMP5E,Internal tamper 5 enable: RTC calendar overflow" "0: Internal tamper 5 disabled.,1: Internal tamper 5 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4E,Internal tamper 4 enable: HSE monitoring" "0: Internal tamper 4 disabled.,1: Internal tamper 4 enabled. a tamper is generated.."
|
|
bitfld.long 0x0 18. "ITAMP3E,Internal tamper 3 enable: LSE monitoring" "0: Internal tamper 3 disabled.,1: Internal tamper 3 enabled: a tamper is generated.."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2E,Tamper detection on TAMP_IN2 enable" "0: Tamper detection on TAMP_IN2 is disabled.,1: Tamper detection on TAMP_IN2 is enabled."
|
|
bitfld.long 0x0 0. "TAMP1E,Tamper detection on TAMP_IN1 enable" "0: Tamper detection on TAMP_IN1 is disabled.,1: Tamper detection on TAMP_IN1 is enabled."
|
|
line.long 0x4 "TAMP_CR2,TAMP control register 2"
|
|
bitfld.long 0x4 25. "TAMP2TRG,Active level for tamper 2 input (active mode disabled)" "0: If TAMPFLT 00 Tamper 2 input staying low..,1: If TAMPFLT 00 Tamper 2 input staying high.."
|
|
bitfld.long 0x4 24. "TAMP1TRG,Active level for tamper 1 input (active mode disabled)" "0: If TAMPFLT 00 Tamper 1 input staying low..,1: If TAMPFLT 00 Tamper 1 input staying high.."
|
|
newline
|
|
bitfld.long 0x4 17. "TAMP2MSK,Tamper 2 mask" "0: Tamper 2 event generates a trigger event and..,1: Tamper 2 event generates a trigger event. TAMP2F.."
|
|
bitfld.long 0x4 16. "TAMP1MSK,Tamper 1 mask" "0: Tamper 1 event generates a trigger event and..,1: Tamper 1 event generates a trigger event. TAMP1F.."
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2NOER,Tamper 2 no erase" "0: Tamper 2 event erases the backup registers.,1: Tamper 2 event does not erase the backup.."
|
|
bitfld.long 0x4 0. "TAMP1NOER,Tamper 1 no erase" "0: Tamper 1 event erases the backup registers.,1: Tamper 1 event does not erase the backup.."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "TAMP_FLTCR,TAMP filter control register"
|
|
bitfld.long 0x0 7. "TAMPPUDIS,TAMP_INx pull-up disable" "0: Precharge TAMP_INx pins before sampling (enable..,1: Disable precharge of TAMP_INx pins."
|
|
bitfld.long 0x0 5.--6. "TAMPPRCH,TAMP_INx precharge duration" "0: 1 RTCCLK cycle,1: 2 RTCCLK cycles,2: 4 RTCCLK cycles,3: 8 RTCCLK cycles"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "TAMPFLT,TAMP_INx filter count" "0: Tamper event is activated on edge of TAMP_INx..,1: Tamper event is activated after 2 consecutive..,2: Tamper event is activated after 4 consecutive..,3: Tamper event is activated after 8 consecutive.."
|
|
bitfld.long 0x0 0.--2. "TAMPFREQ,Tamper sampling frequency" "0: RTCCLK / 32768 (1 Hz when RTCCLK = 32768 Hz),1: RTCCLK / 16384 (2 Hz when RTCCLK = 32768 Hz),2: RTCCLK / 8192 (4 Hz when RTCCLK = 32768 Hz),3: RTCCLK / 4096 (8 Hz when RTCCLK = 32768 Hz),4: RTCCLK / 2048 (16 Hz when RTCCLK = 32768 Hz),5: RTCCLK / 1024 (32 Hz when RTCCLK = 32768 Hz),6: RTCCLK / 512 (64 Hz when RTCCLK = 32768 Hz),7: RTCCLK / 256 (128 Hz when RTCCLK = 32768 Hz)"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "TAMP_IER,TAMP interrupt enable register"
|
|
bitfld.long 0x0 21. "ITAMP6IE,Internal tamper 6 interrupt enable: ST manufacturer readout" "0: Internal tamper 6 interrupt disabled.,1: Internal tamper 6 interrupt enabled."
|
|
bitfld.long 0x0 20. "ITAMP5IE,Internal tamper 5 interrupt enable: RTC calendar overflow" "0: Internal tamper 5 interrupt disabled.,1: Internal tamper 5 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4IE,Internal tamper 4 interrupt enable: HSE monitoring" "0: Internal tamper 4 interrupt disabled.,1: Internal tamper 4 interrupt enabled."
|
|
bitfld.long 0x0 18. "ITAMP3IE,Internal tamper 3 interrupt enable: LSE monitoring" "0: Internal tamper 3 interrupt disabled.,1: Internal tamper 3 interrupt enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2IE,Tamper 2 interrupt enable" "0: Tamper 2 interrupt disabled.,1: Tamper 2 interrupt enabled."
|
|
bitfld.long 0x0 0. "TAMP1IE,Tamper 1 interrupt enable" "0: Tamper 1 interrupt disabled.,1: Tamper 1 interrupt enabled."
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "TAMP_SR,TAMP status register"
|
|
bitfld.long 0x0 21. "ITAMP6F,ST manufacturer readout tamper detection flag" "0,1"
|
|
bitfld.long 0x0 20. "ITAMP5F,RTC calendar overflow tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ITAMP4F,HSE monitoring tamper detection flag" "0,1"
|
|
bitfld.long 0x0 18. "ITAMP3F,LSE monitoring tamper detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TAMP2F,TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "TAMP1F,TAMP1 detection flag" "0,1"
|
|
line.long 0x4 "TAMP_MISR,TAMP masked interrupt status register"
|
|
bitfld.long 0x4 21. "ITAMP6MF,ST manufacturer readout tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 20. "ITAMP5MF,RTC calendar overflow tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ITAMP4MF,HSE monitoring tamper interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 18. "ITAMP3MF,LSE monitoring tamper interrupt masked flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TAMP2MF,TAMP2 interrupt masked flag" "0,1"
|
|
bitfld.long 0x4 0. "TAMP1MF,TAMP1 interrupt masked flag" "0,1"
|
|
wgroup.long 0x3C++0x3
|
|
line.long 0x0 "TAMP_SCR,TAMP status clear register"
|
|
bitfld.long 0x0 21. "CITAMP6F,Clear ITAMP6 detection flag" "0,1"
|
|
bitfld.long 0x0 20. "CITAMP5F,Clear ITAMP5 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CITAMP4F,Clear ITAMP4 detection flag" "0,1"
|
|
bitfld.long 0x0 18. "CITAMP3F,Clear ITAMP3 detection flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CTAMP2F,Clear TAMP2 detection flag" "0,1"
|
|
bitfld.long 0x0 0. "CTAMP1F,Clear TAMP1 detection flag" "0,1"
|
|
group.long 0x100++0x13
|
|
line.long 0x0 "TAMP_BKP0R,TAMP backup 0 register"
|
|
hexmask.long 0x0 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x4 "TAMP_BKP1R,TAMP backup 1 register"
|
|
hexmask.long 0x4 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x8 "TAMP_BKP2R,TAMP backup 2 register"
|
|
hexmask.long 0x8 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0xC "TAMP_BKP3R,TAMP backup 3 register"
|
|
hexmask.long 0xC 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
line.long 0x10 "TAMP_BKP4R,TAMP backup 4 register"
|
|
hexmask.long 0x10 0.--31. 1. "BKP,The application can write or read data to and from these registers."
|
|
endif
|
|
tree.end
|
|
tree "TIM (Timers)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G050*"))
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
|
|
newline
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
newline
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
newline
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM15 alternate register 1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
endif
|
|
line.long 0x4 "CR2,control register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
endif
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
endif
|
|
line.long 0x4 "SR,status register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
endif
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
endif
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
endif
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
endif
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
endif
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
endif
|
|
line.long 0x4 "CR2,control register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
endif
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
endif
|
|
line.long 0x4 "SR,status register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
endif
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
endif
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
endif
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
endif
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
endif
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
endif
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS_4,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x20++0x33
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 21. "CC6P,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x0 20. "CC6E,Capture/Compare 6 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CC5P,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x0 16. "CC5E,Capture/Compare 5 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CC4NP,Capture/Compare 4 complementary output" "0,1"
|
|
bitfld.long 0x0 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x0 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CC3NE,Capture/Compare 3 complementary output" "0,1"
|
|
bitfld.long 0x0 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CC2NE,Capture/Compare 2 complementary output" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.word 0x10 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x1C "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x20 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x24 "BDTR,break and dead-time register"
|
|
bitfld.long 0x24 29. "BK2ID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x24 28. "BKBID,Break Bidirectional" "0,1"
|
|
newline
|
|
bitfld.long 0x24 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x24 26. "BKDSRM,Break Disarm" "0,1"
|
|
newline
|
|
bitfld.long 0x24 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x24 24. "BK2E,Break 2 enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x24 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x24 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x24 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x24 14. "AOE,Automatic output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x24 12. "BKE,Break enable" "0,1"
|
|
newline
|
|
bitfld.long 0x24 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x24 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x24 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x24 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x28 "DCR,DMA control register"
|
|
hexmask.long.byte 0x28 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x28 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x2C "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x2C 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x30 "OR1,option register 1"
|
|
bitfld.long 0x30 0. "OCREF_CLR,Ocref_clr source selection" "0,1"
|
|
group.long 0x58++0x13
|
|
line.long 0x0 "CCR5,capture/compare register 4"
|
|
bitfld.long 0x0 31. "GC5C3,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x0 30. "GC5C2,Group Channel 5 and Channel" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "GC5C1,Group Channel 5 and Channel" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x4 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x8 "AF1,DMA address for full transfer"
|
|
bitfld.long 0x8 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x8 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x8 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0xC "AF2,DMA address for full transfer"
|
|
bitfld.long 0xC 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0xC 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0xC 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0xC 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
line.long 0x10 "TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x10 24.--27. 1. "TI4SEL3_0,selects TI4[0] to TI4[15]"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TI3SEL3_0,selects TI3[0] to TI3[15]"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "TI2SEL3_0,selects TI2[0] to TI2[15]"
|
|
hexmask.long.byte 0x10 0.--3. 1. "TI1SEL3_0,selects TI1[0] to TI1[15]"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "TIM1_CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "TIM1_CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "TIM1_SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "TIM1_SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "TIM1_EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.long 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x20++0x2F
|
|
line.long 0x0 "TIM1_CCER,capture/compare enable"
|
|
bitfld.long 0x0 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x0 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x0 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x0 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x0 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
|
|
newline
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "TIM1_CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x8 "TIM1_PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "TIM1_ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "TIM1_RCR,repetition counter register"
|
|
hexmask.long.word 0x10 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "TIM1_CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "TIM1_CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x1C "TIM1_CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x20 "TIM1_CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x24 "TIM1_BDTR,break and dead-time register"
|
|
bitfld.long 0x24 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x24 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
|
bitfld.long 0x24 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x24 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
bitfld.long 0x24 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x24 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
|
hexmask.long.byte 0x24 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x24 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x24 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x24 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
newline
|
|
bitfld.long 0x24 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x24 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x24 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x24 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x24 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x24 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x28 "TIM1_DCR,DMA control register"
|
|
hexmask.long.byte 0x28 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x28 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x2C "TIM1_DMAR,DMA address for full transfer"
|
|
hexmask.long 0x2C 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
endif
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
endif
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
endif
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
endif
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
endif
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x0 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x0 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x58++0x13
|
|
line.long 0x0 "TIM1_CCR5,capture/compare register 4"
|
|
bitfld.long 0x0 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x0 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x0 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
line.long 0x4 "TIM1_CCR6,capture/compare register 6"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x8 "TIM1_AF1,TIM1 alternate function option register 1"
|
|
hexmask.long.byte 0x8 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x8 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x8 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0xC "TIM1_AF2,TIM1 alternate function option register 2"
|
|
bitfld.long 0xC 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0xC 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x10 "TIM1_TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x10 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x10 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
endif
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
endif
|
|
line.long 0x4 "SR,status register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
endif
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
endif
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
endif
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "TISEL,TI1[0] to TI1[15] input"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
endif
|
|
line.long 0x4 "CR2,control register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
newline
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
endif
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
endif
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
endif
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
endif
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
endif
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
endif
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
endif
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
endif
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
endif
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
endif
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long 0x10 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
endif
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
endif
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
endif
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
endif
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
endif
|
|
group.long 0x48++0x7
|
|
line.long 0x0 "DCR,DMA control register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
endif
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "OR1,TIM option register"
|
|
bitfld.long 0x0 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
endif
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
endif
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 16.--19. 1. "TI3SEL,TI3[0] to TI3[15] input selection"
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "TIM1_CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "TIM1_CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "TIM1_SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "TIM1_SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "TIM1_EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.long 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1"
|
|
bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x4F
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "TIM1_CCER,capture/compare enable"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "TIM1_CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
line.long 0xC "TIM1_PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "TIM1_ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "TIM1_RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "TIM1_CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "TIM1_CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "TIM1_CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "TIM1_CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "TIM1_BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
|
bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
newline
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "TIM1_DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "TIM1_DMAR,DMA address for full transfer"
|
|
hexmask.long 0x30 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x34 "TIM1_OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
newline
|
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bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
line.long 0x3C "TIM1_CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
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bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
line.long 0x40 "TIM1_CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "TIM1_AF1,DMA address for full transfer"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
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|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
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bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
newline
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x48 "TIM1_AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x4C "TIM1_TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x4C 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM6 (Basic Timer)"
|
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base ad:0x40001000
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
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newline
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bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
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newline
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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line.long 0x4 "SR,status register"
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
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group.long 0x24++0xB
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line.long 0x0 "CNT,counter"
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rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
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line.long 0x4 "PSC,prescaler"
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hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
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line.long 0x8 "ARR,auto-reload register"
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hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
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tree.end
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tree "TIM7 (Basic Timer)"
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base ad:0x40001400
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
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newline
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bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
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newline
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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line.long 0x4 "SR,status register"
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
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group.long 0x24++0xB
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line.long 0x0 "CNT,counter"
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rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
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line.long 0x4 "PSC,prescaler"
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hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
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line.long 0x8 "ARR,auto-reload register"
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hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
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tree.end
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tree "TIM14 (General Purpose Timer)"
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base ad:0x40002000
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group.long 0x0++0x3
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
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newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
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newline
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x4 "SR,status register"
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bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
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newline
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
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bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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newline
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bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x20++0xF
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line.long 0x0 "CCER,capture/compare enable"
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bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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newline
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x4 "CNT,counter"
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bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
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line.long 0x8 "PSC,prescaler"
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hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
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line.long 0xC "ARR,auto-reload register"
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hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
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group.long 0x34++0x3
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line.long 0x0 "CCR1,capture/compare register 1"
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hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
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group.long 0x68++0x3
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line.long 0x0 "TISEL,TIM timer input selection"
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hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
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tree.end
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tree "TIM15 (General Purpose Timer)"
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base ad:0x40014000
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group.long 0x0++0x13
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
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newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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newline
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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newline
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
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newline
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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newline
|
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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line.long 0x8 "SMCR,slave mode control register"
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bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
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newline
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bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
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newline
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bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0xC "DIER,DMA/Interrupt enable register"
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bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
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bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
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newline
|
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bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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newline
|
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bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
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bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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newline
|
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bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
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bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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newline
|
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bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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newline
|
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bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x10 "SR,status register"
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bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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newline
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bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
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newline
|
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bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
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bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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newline
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bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
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bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
|
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line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
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bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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|
newline
|
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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newline
|
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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newline
|
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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newline
|
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
|
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x3
|
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
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bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
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|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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|
newline
|
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
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|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
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|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
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|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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|
line.long 0x14 "CCR1,capture/compare register 1"
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|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
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|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0xB
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|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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|
newline
|
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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|
newline
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
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|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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|
newline
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bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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|
newline
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hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
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|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
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hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
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|
line.long 0x8 "DMAR,DMA address for full transfer"
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|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
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group.long 0x60++0x3
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line.long 0x0 "AF1,TIM15 alternate register 1"
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|
bitfld.long 0x0 12. "BKCMP3P,BRK COMP3 input polarity" "0: COMP3 input is active low,1: COMP3 input is active high"
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bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
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newline
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bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
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newline
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bitfld.long 0x0 3. "BKCMP3E,BRK COMP3 enable" "0: COMP3 input disabled,1: COMP3 input enabled"
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bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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newline
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
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bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
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group.long 0x68++0x3
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line.long 0x0 "TISEL,input selection register"
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hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
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hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
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tree.end
|
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tree "TIM16 (General Purpose Timer)"
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base ad:0x40014400
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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newline
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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newline
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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newline
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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newline
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bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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newline
|
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x4 "SR,status register"
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bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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newline
|
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bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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newline
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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|
newline
|
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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newline
|
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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newline
|
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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newline
|
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x20++0x17
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line.long 0x0 "CCER,capture/compare enable"
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bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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newline
|
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x4 "CNT,counter"
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rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
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|
line.long 0x8 "PSC,prescaler"
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hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
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hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
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line.long 0x10 "RCR,repetition counter register"
|
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hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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line.long 0x14 "CCR1,capture/compare register 1"
|
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hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
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group.long 0x44++0xB
|
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line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
newline
|
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "TIM1_CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "TIM1_CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
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|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "TIM1_SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "TIM1_SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "TIM1_EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.long 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1"
|
|
bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x4F
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "TIM1_CCER,capture/compare enable"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "TIM1_CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
line.long 0xC "TIM1_PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "TIM1_ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "TIM1_RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "TIM1_CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "TIM1_CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "TIM1_CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "TIM1_CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "TIM1_BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
|
bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
newline
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "TIM1_DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "TIM1_DMAR,DMA address for full transfer"
|
|
hexmask.long 0x30 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x34 "TIM1_OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
line.long 0x3C "TIM1_CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
line.long 0x40 "TIM1_CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "TIM1_AF1,DMA address for full transfer"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
newline
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x48 "TIM1_AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x4C "TIM1_TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x4C 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
|
|
newline
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
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|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
newline
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
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|
group.long 0x18++0x3
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|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
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|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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|
newline
|
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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|
newline
|
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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newline
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
group.long 0x18++0x3
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|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
group.long 0x20++0x1B
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|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
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|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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|
newline
|
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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|
newline
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
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|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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newline
|
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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|
newline
|
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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|
newline
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|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup."
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
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|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
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|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM15 alternate register 1"
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|
bitfld.long 0x0 12. "BKCMP3P,BRK COMP3 input polarity" "0: COMP3 input is active low,1: COMP3 input is active high"
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|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
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newline
|
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bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
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newline
|
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bitfld.long 0x0 3. "BKCMP3E,BRK COMP3 enable" "0: COMP3 input disabled,1: COMP3 input enabled"
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bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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newline
|
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
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bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
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|
group.long 0x68++0x3
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|
line.long 0x0 "TISEL,input selection register"
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|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
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hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
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tree.end
|
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tree "TIM16 (General Purpose Timer)"
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base ad:0x40014400
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
|
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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newline
|
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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|
line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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newline
|
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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newline
|
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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newline
|
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bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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|
newline
|
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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|
line.long 0x4 "SR,status register"
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|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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newline
|
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bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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|
newline
|
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
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|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match,?,?,?,?,?,?"
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|
newline
|
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
newline
|
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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|
newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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|
newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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|
newline
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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|
newline
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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|
group.long 0xC++0x7
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|
line.long 0x0 "DIER,DMA/Interrupt enable register"
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|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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|
newline
|
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bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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|
newline
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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|
line.long 0x4 "SR,status register"
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|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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|
newline
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bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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newline
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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|
wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
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|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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|
newline
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
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|
group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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|
group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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|
group.long 0x20++0x17
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|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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newline
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
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line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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|
newline
|
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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|
newline
|
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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|
newline
|
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
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bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
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|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
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|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
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|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
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|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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|
newline
|
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
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|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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|
newline
|
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
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|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
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|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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|
newline
|
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
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|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
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|
newline
|
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
newline
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
newline
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
tree.end
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS_4,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x30 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x34 "OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0,1"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
line.long 0x3C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel" "0,1"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x40 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "AF1,DMA address for full transfer"
|
|
bitfld.long 0x44 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TISEL,TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
|
|
newline
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
newline
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
newline
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM15 alternate register 1"
|
|
bitfld.long 0x0 12. "BKCMP3P,BRK COMP3 input polarity" "0: COMP3 input is active low,1: COMP3 input is active high"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
newline
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
newline
|
|
bitfld.long 0x0 3. "BKCMP3E,BRK COMP3 enable" "0: COMP3 input disabled,1: COMP3 input enabled"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS_4,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x30 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x34 "OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0,1"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
line.long 0x3C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel" "0,1"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x40 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "AF1,DMA address for full transfer"
|
|
bitfld.long 0x44 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TISEL,TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "TIM16 (General Purpose Timer)"
|
|
base ad:0x40014400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0,1"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M_2,Output Compare 1 mode" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarit" "0,1"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x0 8. "BKDFBK1E,BRK DFSDM_BREAK1 enable" "0,1"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
|
|
newline
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
newline
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = 1 then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
newline
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x20++0x1B
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
newline
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x18 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM15 alternate register 1"
|
|
bitfld.long 0x0 12. "BKCMP3P,BRK COMP3 input polarity" "0: COMP3 input is active low,1: COMP3 input is active high"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
newline
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
newline
|
|
bitfld.long 0x0 3. "BKCMP3E,BRK COMP3 enable" "0: COMP3 input disabled,1: COMP3 input enabled"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6" "0,1"
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4" "0,1"
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3" "0,1"
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1" "0,1"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update" "0,1"
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS_4,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt" "0,1"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0,1"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0,1"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,Output Compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x4B
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
bitfld.long 0x0 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output" "0,1"
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output" "0,1"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2ID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0,1"
|
|
bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0,1"
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0,1"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0,1"
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0,1"
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0,1"
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0,1"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0,1"
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run" "0,1"
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle" "0,1"
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0,1,2,3"
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x30 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x34 "OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0,1"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
line.long 0x3C "CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel" "0,1"
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel" "0,1"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare value"
|
|
line.long 0x40 "CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "AF1,DMA address for full transfer"
|
|
bitfld.long 0x44 14.--16. "ETRSEL,ETR source selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0,1"
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0,1"
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0,1"
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0,1"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0,1"
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0,1"
|
|
line.long 0x48 "AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0,1"
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0,1"
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN input polarity" "0,1"
|
|
bitfld.long 0x48 8. "BK2DFBK0E,BRK2 DFSDM_BREAK0 enable" "0,1"
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0,1"
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0,1"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 7. "OC1CE,OC1CE" "0,1"
|
|
bitfld.long 0x0 4.--6. "OC1M,OC1M" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,OC1PE" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,OC1FE" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,CC1S" "0,1,2,3"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "ICPCS,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TISEL,TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Low counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Low Auto-reload value"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0,1"
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0,1,2,3"
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0,1"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode" "0,1,2,3"
|
|
bitfld.long 0x0 4. "DIR,Direction" "0,1"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0,1"
|
|
bitfld.long 0x0 2. "URS,Update request source" "0,1"
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0,1"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0,1"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA" "0,1"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS_4_3,Trigger selection" "0,1,2,3"
|
|
bitfld.long 0x8 16. "SMS_3,Slave mode selection - bit" "0,1"
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0,1"
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0,1"
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0,1,2,3"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0,1"
|
|
bitfld.long 0x8 4.--6. "TS,Trigger selection" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0,1"
|
|
bitfld.long 0x8 0.--2. "SMS,Slave mode selection" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0,1"
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request" "0,1"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request" "0,1"
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request" "0,1"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request" "0,1"
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0,1"
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0,1"
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt" "0,1"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt" "0,1"
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0,1"
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture" "0,1"
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0,1"
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt" "0,1"
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt" "0,1"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0,1"
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0,1"
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1" "0,1"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2" "0,1,2,3"
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M,Output compare 1 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload" "0,1"
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0x13
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output" "0,1"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output" "0,1"
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
line.long 0xC "PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "ARR,auto-reload register"
|
|
hexmask.long.word 0x10 16.--31. 1. "ARR_H,High Auto-reload value (TIM2"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR_L,Low Auto-reload value"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 16.--31. 1. "CCR1_H,High Capture/Compare 1 value (TIM2"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1_L,Low Capture/Compare 1"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x4 16.--31. 1. "CCR2_H,High Capture/Compare 2 value (TIM2"
|
|
hexmask.long.word 0x4 0.--15. 1. "CCR2_L,Low Capture/Compare 2"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x8 16.--31. 1. "CCR3_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CCR3_L,Low Capture/Compare value"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long.word 0xC 16.--31. 1. "CCR4_H,High Capture/Compare value (TIM2"
|
|
hexmask.long.word 0xC 0.--15. 1. "CCR4_L,Low Capture/Compare value"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "IOCREF_CLR,IOCREF_CLR" "0,1"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,External trigger source"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2SEL"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1SEL"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "TIM1_CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "TIM1_CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "TIM1_SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "TIM1_SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "TIM1_EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.long 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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|
newline
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bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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|
newline
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x7
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
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bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1"
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bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1"
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newline
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bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
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bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
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bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
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newline
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
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newline
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bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
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newline
|
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bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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group.long 0x1C++0x4F
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line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
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hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
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bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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line.long 0x4 "TIM1_CCER,capture/compare enable"
|
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bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
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bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
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|
newline
|
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bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
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bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
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|
newline
|
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bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
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bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
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|
newline
|
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bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
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bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
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|
newline
|
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bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
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bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
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bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
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|
newline
|
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bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
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bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
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bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x8 "TIM1_CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
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hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
line.long 0xC "TIM1_PSC,prescaler"
|
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hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "TIM1_ARR,auto-reload register"
|
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hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
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line.long 0x14 "TIM1_RCR,repetition counter register"
|
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hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
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line.long 0x18 "TIM1_CCR1,capture/compare register 1"
|
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hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
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line.long 0x1C "TIM1_CCR2,capture/compare register 2"
|
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hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
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line.long 0x20 "TIM1_CCR3,capture/compare register 3"
|
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hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
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line.long 0x24 "TIM1_CCR4,capture/compare register 4"
|
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hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
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line.long 0x28 "TIM1_BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1"
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bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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|
newline
|
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bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
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|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
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bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
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bitfld.long 0x28 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
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hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
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hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
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bitfld.long 0x28 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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bitfld.long 0x28 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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|
newline
|
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bitfld.long 0x28 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "TIM1_DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "TIM1_DMAR,DMA address for full transfer"
|
|
hexmask.long 0x30 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x34 "TIM1_OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
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bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
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line.long 0x3C "TIM1_CCR5,capture/compare register 4"
|
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bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
line.long 0x40 "TIM1_CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "TIM1_AF1,DMA address for full transfer"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
newline
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x48 "TIM1_AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x4C "TIM1_TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x4C 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
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|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
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|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
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|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
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bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
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bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
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|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM4 (General Purpose Timer)"
|
|
base ad:0x40000800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2,2: tDTS = 4,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
newline
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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line.long 0x8 "SMCR,slave mode control register"
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bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
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bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
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bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0xC "DIER,DMA/Interrupt enable register"
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bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
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bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
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bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
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bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x10 "SR,status register"
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bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
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bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x20++0x1B
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line.long 0x0 "CCER,capture/compare enable"
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bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
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bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
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bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
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bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x4 "CNT,counter"
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rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
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line.long 0x8 "PSC,prescaler"
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hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
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line.long 0xC "ARR,auto-reload register"
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hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
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line.long 0x10 "RCR,repetition counter register"
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hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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line.long 0x14 "CCR1,capture/compare register 1"
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hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
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line.long 0x18 "CCR2,capture/compare register 2"
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hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
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group.long 0x44++0xB
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line.long 0x0 "BDTR,break and dead-time register"
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bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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newline
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
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bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
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line.long 0x4 "DCR,DMA control register"
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hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
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hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
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line.long 0x8 "DMAR,DMA address for full transfer"
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hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
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group.long 0x60++0x3
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line.long 0x0 "AF1,TIM15 alternate register 1"
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bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
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bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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newline
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
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bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
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bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
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group.long 0x68++0x3
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line.long 0x0 "TISEL,input selection register"
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hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
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hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
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tree.end
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tree "TIM16 (General Purpose Timer)"
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base ad:0x40014400
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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newline
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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newline
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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newline
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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newline
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bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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newline
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x4 "SR,status register"
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bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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newline
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bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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newline
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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newline
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
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|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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newline
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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|
group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x20++0x17
|
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line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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newline
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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|
line.long 0x4 "CNT,counter"
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|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
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|
line.long 0x8 "PSC,prescaler"
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|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "TIM1_CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "TIM1_CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "TIM1_SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
|
|
bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
newline
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
|
|
bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
newline
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x10 "TIM1_SR,status register"
|
|
bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
|
|
bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
|
|
newline
|
|
bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
newline
|
|
bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "TIM1_EGR,event generation register"
|
|
bitfld.long 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
|
|
newline
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
|
|
newline
|
|
bitfld.long 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
|
|
bitfld.long 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
newline
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
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|
bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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|
bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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|
newline
|
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
|
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1"
|
|
bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
group.long 0x1C++0x4F
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "TIM1_CCER,capture/compare enable"
|
|
bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
|
|
bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
|
|
bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
|
|
newline
|
|
bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "TIM1_CNT,counter"
|
|
rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
|
line.long 0xC "TIM1_PSC,prescaler"
|
|
hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "TIM1_ARR,auto-reload register"
|
|
hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x14 "TIM1_RCR,repetition counter register"
|
|
hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
|
|
line.long 0x18 "TIM1_CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "TIM1_CCR2,capture/compare register 2"
|
|
hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "TIM1_CCR3,capture/compare register 3"
|
|
hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
|
line.long 0x24 "TIM1_CCR4,capture/compare register 4"
|
|
hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "TIM1_BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
|
bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
|
hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
|
bitfld.long 0x28 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
bitfld.long 0x28 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
newline
|
|
bitfld.long 0x28 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
|
|
newline
|
|
bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "TIM1_DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "TIM1_DMAR,DMA address for full transfer"
|
|
hexmask.long 0x30 0.--31. 1. "DMAB,DMA register for burst accesses"
|
|
line.long 0x34 "TIM1_OR1,option register 1"
|
|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
|
|
line.long 0x3C "TIM1_CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
line.long 0x40 "TIM1_CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "TIM1_AF1,DMA address for full transfer"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
newline
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x48 "TIM1_AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x4C "TIM1_TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x4C 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
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|
newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
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newline
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bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
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bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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newline
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
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newline
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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line.long 0x8 "SMCR,slave mode control register"
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bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
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newline
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bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
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bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
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newline
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bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
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hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
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newline
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bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
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newline
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bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
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bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0xC "DIER,DMA/Interrupt enable register"
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bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
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bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
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newline
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bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
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bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
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newline
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bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
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bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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newline
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bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
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bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
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newline
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bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
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bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
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newline
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
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bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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line.long 0x10 "SR,status register"
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bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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newline
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bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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newline
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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newline
|
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bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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newline
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bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
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newline
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bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
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bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
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newline
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bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
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bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
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bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
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newline
|
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bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
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bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
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newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x7
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
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line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
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bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
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bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
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newline
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bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
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bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
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bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
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newline
|
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
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bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
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newline
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bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
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newline
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bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
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bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
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group.long 0x1C++0xB
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line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
|
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
|
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bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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line.long 0x4 "CCER,capture/compare enable"
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bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
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bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
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newline
|
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bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
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newline
|
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bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
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|
newline
|
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bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
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bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
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newline
|
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bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
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line.long 0x8 "CNT,counter"
|
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hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
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hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
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line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
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hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
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line.long 0x4 "PSC,prescaler"
|
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hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
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line.long 0x8 "ARR,auto-reload register"
|
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hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
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|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
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|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
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bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
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|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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|
line.long 0xC "DIER,DMA/Interrupt enable register"
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|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
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|
newline
|
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bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
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|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
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|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
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|
newline
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|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
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|
newline
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
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|
line.long 0x10 "SR,status register"
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|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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|
newline
|
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bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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|
newline
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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|
newline
|
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bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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|
newline
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bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
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|
wgroup.long 0x14++0x3
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|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
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newline
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bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
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bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
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|
newline
|
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bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
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|
group.long 0x18++0x3
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|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
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bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
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bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
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newline
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bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
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bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
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newline
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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newline
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
group.long 0x18++0x7
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
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|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
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bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
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|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
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|
newline
|
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bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
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|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
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|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
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|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
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|
newline
|
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bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
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|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
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group.long 0x1C++0xB
|
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line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
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|
newline
|
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bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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line.long 0x4 "CCER,capture/compare enable"
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bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
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bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
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|
newline
|
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bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
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|
newline
|
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bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
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|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM4 (General Purpose Timer)"
|
|
base ad:0x40000800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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line.long 0x8 "SMCR,slave mode control register"
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bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
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bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
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bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0xC "DIER,DMA/Interrupt enable register"
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bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
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bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
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bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
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bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x10 "SR,status register"
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bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
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bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x20++0x1B
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line.long 0x0 "CCER,capture/compare enable"
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bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
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bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
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bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
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bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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newline
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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newline
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x4 "CNT,counter"
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rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
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line.long 0x8 "PSC,prescaler"
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hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
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line.long 0xC "ARR,auto-reload register"
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hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
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line.long 0x10 "RCR,repetition counter register"
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hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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line.long 0x14 "CCR1,capture/compare register 1"
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hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
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line.long 0x18 "CCR2,capture/compare register 2"
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hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
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group.long 0x44++0xB
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line.long 0x0 "BDTR,break and dead-time register"
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bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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newline
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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newline
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
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bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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newline
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hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
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line.long 0x4 "DCR,DMA control register"
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hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
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hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
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line.long 0x8 "DMAR,DMA address for full transfer"
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hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
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group.long 0x60++0x3
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line.long 0x0 "AF1,TIM15 alternate register 1"
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bitfld.long 0x0 12. "BKCMP3P,BRK COMP3 input polarity" "0: COMP3 input is active low,1: COMP3 input is active high"
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bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
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newline
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bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
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bitfld.long 0x0 3. "BKCMP3E,BRK COMP3 enable" "0: COMP3 input disabled,1: COMP3 input enabled"
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bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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newline
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
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bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
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group.long 0x68++0x3
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line.long 0x0 "TISEL,input selection register"
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hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
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hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
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tree.end
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tree "TIM16 (General Purpose Timer)"
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base ad:0x40014400
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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newline
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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newline
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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newline
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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newline
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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newline
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bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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newline
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x4 "SR,status register"
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bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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newline
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bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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newline
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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newline
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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newline
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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group.long 0x20++0x17
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line.long 0x0 "CCER,capture/compare enable"
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bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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newline
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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|
newline
|
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "TIM1 (Advanced Control Timer)"
|
|
base ad:0x40012C00
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "TIM1_CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "TIM1_CR2,control register 2"
|
|
hexmask.long.byte 0x4 20.--23. 1. "MMS2,Master mode selection 2"
|
|
bitfld.long 0x4 18. "OIS6,Output Idle state 6 (OC6 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OIS5,Output Idle state 5 (OC5 output)" "0,1"
|
|
bitfld.long 0x4 14. "OIS4,Output Idle state 4 (OC4 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "OIS3N,Output Idle state 3 (OC3N output)" "0,1"
|
|
bitfld.long 0x4 12. "OIS3,Output Idle state 3 (OC3 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "OIS2N,Output Idle state 2 (OC2N output)" "0,1"
|
|
bitfld.long 0x4 10. "OIS2,Output Idle state 2 (OC2 output)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
line.long 0x8 "TIM1_SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
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bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
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bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled,1: CC4 DMA request enabled"
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bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled,1: CC3 DMA request enabled"
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|
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bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
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bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled,1: CC4 interrupt enabled"
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bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled,1: CC3 interrupt enabled"
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bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x10 "TIM1_SR,status register"
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bitfld.long 0x10 17. "CC6IF,Compare 6 interrupt flag" "0,1"
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bitfld.long 0x10 16. "CC5IF,Compare 5 interrupt flag" "0,1"
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bitfld.long 0x10 13. "SBIF,System Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the system.."
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bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
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bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x10 8. "B2IF,Break 2 interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break 2.."
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bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred.,1: An active level has been detected on the break.."
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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bitfld.long 0x10 5. "COMIF,COM interrupt flag" "0: No COM event occurred.,1: COM interrupt pending."
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bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
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bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
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bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
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bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "TIM1_EGR,event generation register"
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bitfld.long 0x0 8. "B2G,Break 2 generation" "0: No action,1: A break 2 event is generated. MOE bit is cleared.."
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bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When CCPC bit is set it allows CCxE CCxNE and.."
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bitfld.long 0x0 4. "CC4G,Capture/Compare 4 generation" "0,1"
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bitfld.long 0x0 3. "CC3G,Capture/Compare 3 generation" "0,1"
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bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
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bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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newline
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bitfld.long 0x0 15. "OC2CE,Output Compare 2 clear enable" "0,1"
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 7. "OC1CE,Output Compare 1 clear enable" "0: OC1Ref is not affected by the ocref_clr_int signal,1: OC1Ref is cleared as soon as a High level is.."
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newline
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,?,?,?,?,?,?"
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x7
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (output"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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newline
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
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bitfld.long 0x4 24. "OC4M2,Output compare 4 mode" "0,1"
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bitfld.long 0x4 16. "OC3M2,Output compare 3 mode" "0,1"
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bitfld.long 0x4 15. "OC4CE,Output compare 4 clear enable" "0,1"
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bitfld.long 0x4 12.--14. "OC4M1,Output compare 4 mode" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0x4 11. "OC4PE,Output compare 4 preload enable" "0,1"
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bitfld.long 0x4 10. "OC4FE,Output compare 4 fast enable" "0,1"
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newline
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bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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bitfld.long 0x4 7. "OC3CE,Output compare 3 clear enable" "0,1"
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newline
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bitfld.long 0x4 4.--6. "OC3M1,Output compare 3 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 3. "OC3PE,Output compare 3 preload enable" "0,1"
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newline
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bitfld.long 0x4 2. "OC3FE,Output compare 3 fast enable" "0,1"
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bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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group.long 0x1C++0x4F
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line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (output"
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hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
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bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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newline
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
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newline
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bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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bitfld.long 0x0 0.--1. "CC3S,Capture/compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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line.long 0x4 "TIM1_CCER,capture/compare enable"
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bitfld.long 0x4 21. "CC6P,Capture/Compare 6 output polarity" "0,1"
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bitfld.long 0x4 20. "CC6E,Capture/Compare 6 output enable" "0,1"
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newline
|
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bitfld.long 0x4 17. "CC5P,Capture/Compare 5 output polarity" "0,1"
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bitfld.long 0x4 16. "CC5E,Capture/Compare 5 output enable" "0,1"
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newline
|
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bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 complementary output polarity" "0,1"
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bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output polarity" "0,1"
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newline
|
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bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable" "0,1"
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bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 complementary output polarity" "0,1"
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newline
|
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bitfld.long 0x4 10. "CC3NE,Capture/Compare 3 complementary output enable" "0,1"
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bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output polarity" "0,1"
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newline
|
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bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable" "0,1"
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bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
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newline
|
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bitfld.long 0x4 6. "CC2NE,Capture/Compare 2 complementary output enable" "0,1"
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bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
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newline
|
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bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable" "0,1"
|
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bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high.,1: OC1N active low."
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|
newline
|
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bitfld.long 0x4 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output polarity" "0: The configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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|
newline
|
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bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x8 "TIM1_CNT,counter"
|
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rbitfld.long 0x8 31. "UIFCPY,UIF copy" "0,1"
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hexmask.long.word 0x8 0.--15. 1. "CNT,Counter value"
|
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line.long 0xC "TIM1_PSC,prescaler"
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hexmask.long.word 0xC 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x10 "TIM1_ARR,auto-reload register"
|
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hexmask.long.word 0x10 0.--15. 1. "ARR,Auto-reload value"
|
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line.long 0x14 "TIM1_RCR,repetition counter register"
|
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hexmask.long.word 0x14 0.--15. 1. "REP,Repetition counter value"
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line.long 0x18 "TIM1_CCR1,capture/compare register 1"
|
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hexmask.long.word 0x18 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
line.long 0x1C "TIM1_CCR2,capture/compare register 2"
|
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hexmask.long.word 0x1C 0.--15. 1. "CCR2,Capture/Compare 2 value"
|
|
line.long 0x20 "TIM1_CCR3,capture/compare register 3"
|
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hexmask.long.word 0x20 0.--15. 1. "CCR3,Capture/Compare value"
|
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line.long 0x24 "TIM1_CCR4,capture/compare register 4"
|
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hexmask.long.word 0x24 0.--15. 1. "CCR4,Capture/Compare value"
|
|
line.long 0x28 "TIM1_BDTR,break and dead-time register"
|
|
bitfld.long 0x28 29. "BK2BID,Break2 bidirectional" "0,1"
|
|
bitfld.long 0x28 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
newline
|
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bitfld.long 0x28 27. "BK2DSRM,Break2 Disarm" "0,1"
|
|
bitfld.long 0x28 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
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bitfld.long 0x28 25. "BK2P,Break 2 polarity" "0: Break input BRK2 is active low,1: Break input BRK2 is active high"
|
|
bitfld.long 0x28 24. "BK2E,Break 2 enable" "0: Break input BRK2 disabled,1: Break input BRK2 enabled"
|
|
newline
|
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hexmask.long.byte 0x28 20.--23. 1. "BK2F,Break 2 filter"
|
|
hexmask.long.byte 0x28 16.--19. 1. "BKF,Break filter"
|
|
newline
|
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bitfld.long 0x28 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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bitfld.long 0x28 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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newline
|
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bitfld.long 0x28 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
bitfld.long 0x28 12. "BKE,Break enable" "0: Break function disabled,1: Break function enabled"
|
|
newline
|
|
bitfld.long 0x28 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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|
bitfld.long 0x28 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are first forced.."
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|
newline
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bitfld.long 0x28 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected.,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
hexmask.long.byte 0x28 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x2C "TIM1_DCR,DMA control register"
|
|
hexmask.long.byte 0x2C 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x2C 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x30 "TIM1_DMAR,DMA address for full transfer"
|
|
hexmask.long 0x30 0.--31. 1. "DMAB,DMA register for burst accesses"
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|
line.long 0x34 "TIM1_OR1,option register 1"
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|
bitfld.long 0x34 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
line.long 0x38 "CCMR3_Output,capture/compare mode register 2 (output"
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|
bitfld.long 0x38 24. "OC6M_bit3,Output Compare 6 mode bit" "0,1"
|
|
bitfld.long 0x38 16. "OC5M_bit3,Output Compare 5 mode bit" "0,1"
|
|
newline
|
|
bitfld.long 0x38 15. "OC6CE,Output compare 6 clear" "0,1"
|
|
bitfld.long 0x38 12.--14. "OC6M,Output compare 6 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 11. "OC6PE,Output compare 6 preload" "0,1"
|
|
bitfld.long 0x38 10. "OC6FE,Output compare 6 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x38 7. "OC5CE,Output compare 5 clear" "0,1"
|
|
bitfld.long 0x38 4.--6. "OC5M,Output compare 5 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 3. "OC5PE,Output compare 5 preload" "0,1"
|
|
bitfld.long 0x38 2. "OC5FE,Output compare 5 fast" "0,1"
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|
line.long 0x3C "TIM1_CCR5,capture/compare register 4"
|
|
bitfld.long 0x3C 31. "GC5C3,Group Channel 5 and Channel 3" "0: No effect of OC5REF on OC3REFC,1: OC3REFC is the logical AND of OC3REFC and OC5REF"
|
|
bitfld.long 0x3C 30. "GC5C2,Group Channel 5 and Channel 2" "0: No effect of OC5REF on OC2REFC,1: OC2REFC is the logical AND of OC2REFC and OC5REF"
|
|
newline
|
|
bitfld.long 0x3C 29. "GC5C1,Group Channel 5 and Channel 1" "0: No effect of OC5REF on OC1REFC5,1: OC1REFC is the logical AND of OC1REFC and OC5REF"
|
|
hexmask.long.word 0x3C 0.--15. 1. "CCR5,Capture/Compare 5 value"
|
|
line.long 0x40 "TIM1_CCR6,capture/compare register 4"
|
|
hexmask.long.word 0x40 0.--15. 1. "CCR6,Capture/Compare value"
|
|
line.long 0x44 "TIM1_AF1,DMA address for full transfer"
|
|
hexmask.long.byte 0x44 14.--17. 1. "ETRSEL,ETR source selection"
|
|
bitfld.long 0x44 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
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|
newline
|
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bitfld.long 0x44 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
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|
bitfld.long 0x44 9. "BKINP,BRK BKIN input polarity" "0: BKIN input polarity is not inverted (active low..,1: BKIN input polarity is inverted (active high if.."
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|
newline
|
|
bitfld.long 0x44 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
bitfld.long 0x44 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
newline
|
|
bitfld.long 0x44 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
line.long 0x48 "TIM1_AF2,DMA address for full transfer"
|
|
bitfld.long 0x48 11. "BK2CMP2P,BRK2 COMP2 input polarity" "0: COMP2 input polarity is not inverted (active low..,1: COMP2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 10. "BK2CMP1P,BRK2 COMP1 input polarity" "0: COMP1 input polarity is not inverted (active low..,1: COMP1 input polarity is inverted (active high if.."
|
|
newline
|
|
bitfld.long 0x48 9. "BK2INP,BRK2 BKIN2 input polarity" "0: BKIN2 input polarity is not inverted (active low..,1: BKIN2 input polarity is inverted (active high if.."
|
|
bitfld.long 0x48 2. "BK2CMP2E,BRK2 COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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|
newline
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|
bitfld.long 0x48 1. "BK2CMP1E,BRK2 COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x48 0. "BK2INE,BRK2 BKIN input enable" "0: BKIN2 input disabled,1: BKIN2 input enabled"
|
|
line.long 0x4C "TIM1_TISEL,TIM1 timer input selection"
|
|
hexmask.long.byte 0x4C 24.--27. 1. "TI4SEL,selects TI4[0] to TI4[15] input"
|
|
hexmask.long.byte 0x4C 16.--19. 1. "TI3SEL,selects TI3[0] to TI3[15] input"
|
|
newline
|
|
hexmask.long.byte 0x4C 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
|
|
hexmask.long.byte 0x4C 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "TIM2 (General-purpose-timers)"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM3 (General Purpose Timer)"
|
|
base ad:0x40000400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
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|
newline
|
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bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
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|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
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bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
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|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
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|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
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|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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|
newline
|
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bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
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|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
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|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
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|
newline
|
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bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
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|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
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|
newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
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|
newline
|
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bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
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|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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|
newline
|
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bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
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|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
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bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
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|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
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|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
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|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
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|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
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|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
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line.long 0x4 "CCER,capture/compare enable"
|
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bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
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|
newline
|
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bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
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|
newline
|
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bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM4 (General Purpose Timer)"
|
|
base ad:0x40000800
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 5.--6. "CMS,Center-aligned mode selection" "0: Edge-aligned mode. The counter counts up or down..,1: Center-aligned mode 1. The counter counts up and..,2: Center-aligned mode 2. The counter counts up and..,3: Center-aligned mode 3. The counter counts up and.."
|
|
newline
|
|
bitfld.long 0x0 4. "DIR,Direction" "0: Counter used as upcounter,1: Counter used as downcounter"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 and CH3 pins are connected to.."
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,6: Compare - OC3REFC signal is used as trigger..,7: Compare - OC4REFC signal is used as trigger.."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
line.long 0x8 "SMCR,slave mode control register"
|
|
bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
|
|
bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on.."
|
|
newline
|
|
bitfld.long 0x8 15. "ETP,External trigger polarity" "0: ETR is non-inverted active at high level or..,1: ETR is inverted active at low level or falling.."
|
|
bitfld.long 0x8 14. "ECE,External clock enable" "0: External clock mode 2 disabled,1: External clock mode 2 enabled. The counter is.."
|
|
newline
|
|
bitfld.long 0x8 12.--13. "ETPS,External trigger prescaler" "0: Prescaler OFF,1: ETRP frequency divided by 2,2: ETRP frequency divided by 4,3: ETRP frequency divided by 8"
|
|
hexmask.long.byte 0x8 8.--11. 1. "ETF,External trigger filter"
|
|
newline
|
|
bitfld.long 0x8 7. "MSM,Master/Slave mode" "0: No action,1: The effect of an event on the trigger input.."
|
|
bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),7: External Trigger input (ETRF)"
|
|
newline
|
|
bitfld.long 0x8 3. "OCCS,OCREF clear selection" "0: OCREF_CLR_INT is connected to COMP1 or COMP2..,1: OCREF_CLR_INT is connected to ETRF"
|
|
bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1 then the..,1: Encoder mode 1 - Counter counts up/down on..,2: Encoder mode 2 - Counter counts up/down on..,3: Encoder mode 3 - Counter counts up/down on both..,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
|
|
line.long 0xC "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled.,1: Trigger DMA request enabled."
|
|
bitfld.long 0xC 12. "CC4DE,Capture/Compare 4 DMA request enable" "0: CC4 DMA request disabled.,1: CC4 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 11. "CC3DE,Capture/Compare 3 DMA request enable" "0: CC3 DMA request disabled.,1: CC3 DMA request enabled."
|
|
bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled.,1: CC2 DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled.,1: CC1 DMA request enabled."
|
|
bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
newline
|
|
bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled.,1: Trigger interrupt enabled."
|
|
bitfld.long 0xC 4. "CC4IE,Capture/Compare 4 interrupt enable" "0: CC4 interrupt disabled.,1: CC4 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 3. "CC3IE,Capture/Compare 3 interrupt enable" "0: CC3 interrupt disabled.,1: CC3 interrupt enabled."
|
|
bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled.,1: CC2 interrupt enabled."
|
|
newline
|
|
bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled.,1: CC1 interrupt enabled."
|
|
bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x10 "SR,status register"
|
|
bitfld.long 0x10 12. "CC4OF,Capture/Compare 4 overcapture flag" "0,1"
|
|
bitfld.long 0x10 11. "CC3OF,Capture/Compare 3 overcapture flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 10. "CC2OF,Capture/compare 2 overcapture flag" "0,1"
|
|
bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
newline
|
|
bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred.,1: Trigger interrupt pending."
|
|
bitfld.long 0x10 4. "CC4IF,Capture/Compare 4 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "CC3IF,Capture/Compare 3 interrupt flag" "0,1"
|
|
bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
|
|
bitfld.long 0x0 4. "CC4G,Capture/compare 4 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CC3G,Capture/compare 3 generation" "0,1"
|
|
bitfld.long 0x0 2. "CC2G,Capture/compare 2 generation" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 24. "OC2M_3,Output Compare 2 mode - bit" "0,1"
|
|
bitfld.long 0x0 16. "OC1M_3,Output Compare 1 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OC2CE,Output compare 2 clear" "0,1"
|
|
bitfld.long 0x0 12.--14. "OC2M,Output compare 2 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 11. "OC2PE,Output compare 2 preload" "0,1"
|
|
bitfld.long 0x0 10. "OC2FE,Output compare 2 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
|
|
bitfld.long 0x0 7. "OC1CE,Output compare 1 clear enable" "0: OC1Ref is not affected by the ETRF input,1: OC1Ref is cleared as soon as a High level is.."
|
|
newline
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - In upcounting channel 1 is active..,7: PWM mode 2 - In upcounting channel 1 is inactive.."
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
newline
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast" "0,1"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
|
|
bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC2S,Capture/compare 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1" "0,1,2,3"
|
|
line.long 0x4 "CCMR2_Output,capture/compare mode register 2 (output"
|
|
bitfld.long 0x4 24. "OC4M_3,Output Compare 4 mode - bit" "0,1"
|
|
bitfld.long 0x4 16. "OC3M_3,Output Compare 3 mode - bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "OC4CE,Output compare 4 clear" "0,1"
|
|
bitfld.long 0x4 12.--14. "OC4M,Output compare 4 mode" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 11. "OC4PE,Output compare 4 preload" "0,1"
|
|
bitfld.long 0x4 10. "OC4FE,Output compare 4 fast" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "CC4S,Capture/Compare 4" "0,1,2,3"
|
|
bitfld.long 0x4 7. "OC3CE,Output compare 3 clear" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--6. "OC3M,Output compare 3 mode" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 3. "OC3PE,Output compare 3 preload" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "OC3FE,Output compare 3 fast" "0,1"
|
|
bitfld.long 0x4 0.--1. "CC3S,Capture/Compare 3" "0,1,2,3"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "CCMR2_Input,capture/compare mode register 2 (input"
|
|
hexmask.long.byte 0x0 12.--15. 1. "IC4F,Input capture 4 filter"
|
|
bitfld.long 0x0 10.--11. "IC4PSC,Input capture 4 prescaler" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "CC4S,Capture/Compare 4 selection" "0: CC4 channel is configured as output,1: CC4 channel is configured as input IC4 is mapped..,2: CC4 channel is configured as input IC4 is mapped..,3: CC4 channel is configured as input IC4 is mapped.."
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC3F,Input capture 3 filter"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IC3PSC,Input capture 3 prescaler" "0,1,2,3"
|
|
bitfld.long 0x0 0.--1. "CC3S,Capture/Compare 3 selection" "0: CC3 channel is configured as output,1: CC3 channel is configured as input IC3 is mapped..,2: CC3 channel is configured as input IC3 is mapped..,3: CC3 channel is configured as input IC3 is mapped.."
|
|
line.long 0x4 "CCER,capture/compare enable"
|
|
bitfld.long 0x4 15. "CC4NP,Capture/Compare 4 output Polarity." "0,1"
|
|
bitfld.long 0x4 13. "CC4P,Capture/Compare 4 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CC4E,Capture/Compare 4 output enable." "0,1"
|
|
bitfld.long 0x4 11. "CC3NP,Capture/Compare 3 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CC3P,Capture/Compare 3 output Polarity." "0,1"
|
|
bitfld.long 0x4 8. "CC3E,Capture/Compare 3 output enable." "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CC2NP,Capture/Compare 2 output Polarity." "0,1"
|
|
bitfld.long 0x4 5. "CC2P,Capture/Compare 2 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CC2E,Capture/Compare 2 output enable." "0,1"
|
|
bitfld.long 0x4 3. "CC1NP,Capture/Compare 1 output Polarity." "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges"
|
|
bitfld.long 0x4 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x8 "CNT,counter"
|
|
hexmask.long.word 0x8 16.--31. 1. "CNT_H,High counter value (TIM2"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT_L,Low counter value"
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT_ALTERNATE5,counter"
|
|
bitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long 0x0 0.--30. 1. "CNT,Most significant part counter value (TIM2)"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long 0x8 0.--31. 1. "ARR,High auto-reload value (TIM2)"
|
|
group.long 0x34++0xF
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long 0x0 0.--31. 1. "CCR1,High Capture/Compare 1 value (TIM2)"
|
|
line.long 0x4 "CCR2,capture/compare register 2"
|
|
hexmask.long 0x4 0.--31. 1. "CCR2,High Capture/Compare 2 value (TIM2)"
|
|
line.long 0x8 "CCR3,capture/compare register 3"
|
|
hexmask.long 0x8 0.--31. 1. "CCR3,High Capture/Compare 3 value (TIM2)"
|
|
line.long 0xC "CCR4,capture/compare register 4"
|
|
hexmask.long 0xC 0.--31. 1. "CCR4,High Capture/Compare 4 value (TIM2)"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "DCR,DMA control register"
|
|
hexmask.long.byte 0x0 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x4 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x4 0.--15. 1. "DMAB,DMA register for burst"
|
|
line.long 0x8 "OR1,TIM option register"
|
|
bitfld.long 0x8 0. "OCREF_CLR,Ocref_clr source selection" "0: COMP1 output is connected to the OCREF_CLR input,1: COMP2 output is connected to the OCREF_CLR input"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 14.--17. 1. "ETRSEL,ETR source selection"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM alternate function option register"
|
|
hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,TI2[0] to TI2[15] input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,TI1[0] to TI1[15] input selection"
|
|
tree.end
|
|
tree "TIM6 (Basic Timer)"
|
|
base ad:0x40001000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM7 (Basic Timer)"
|
|
base ad:0x40001400
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered.,1: TIMx_ARR register is buffered."
|
|
newline
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generates an update..,1: Only counter overflow/underflow generates an.."
|
|
newline
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter enable signal CNT_EN is..,2: Update - The update event is selected as a..,?,?,?,?,?"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled.,1: Update DMA request enabled."
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled.,1: Update interrupt enabled."
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Re-initializes the timer counter and generates.."
|
|
group.long 0x24++0xB
|
|
line.long 0x0 "CNT,counter"
|
|
rbitfld.long 0x0 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CNT,Counter value"
|
|
line.long 0x4 "PSC,prescaler"
|
|
hexmask.long.word 0x4 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0x8 "ARR,auto-reload register"
|
|
hexmask.long.word 0x8 0.--15. 1. "ARR,Prescaler value"
|
|
tree.end
|
|
tree "TIM14 (General Purpose Timer)"
|
|
base ad:0x40002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2 * tCK_INT,2: tDTS = 4 * tCK_INT,?"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped on the update event,1: Counter stops counting on the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an UEV if..,1: Only counter overflow generates an UEV if enabled."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. An UEV is generated by one of the..,1: UEV disabled. No UEV is generated shadow.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected.,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 1. "CC1IF,Capture/compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred."
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 1. "CC1G,Capture/compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Re-initialize the counter and generates an.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register 1 (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output compare 1 mode (refer to bit 16 for OC1M[3])" "0: Frozen. The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT =..,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0xF
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output Polarity." "0,1"
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output Polarity." "0: This configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
newline
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable." "0: Capture mode disabled / OC1 is not active,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
bitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,low counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Low Auto-reload value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCR1,Low Capture/Compare 1"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,TIM timer input selection"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM15 (General Purpose Timer)"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS = tCK_INT,1: tDTS = 2*tCK_INT,2: tDTS = 4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One-pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 10. "OIS2,Output idle state 2 (OC2 output)" "0: OC2=0 when MOE=0,1: OC2=1 when MOE=0"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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bitfld.long 0x4 7. "TI1S,TI1 selection" "0: The TIMx_CH1 pin is connected to TI1 input,1: The TIMx_CH1 CH2 pins are connected to the TI1.."
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bitfld.long 0x4 4.--6. "MMS,Master mode selection" "0: Reset - the UG bit from the TIMx_EGR register is..,1: Enable - the Counter Enable signal CNT_EN is..,2: Update - The update event is selected as trigger..,3: Compare Pulse - The trigger output send a..,4: Compare - OC1REFC signal is used as trigger..,5: Compare - OC2REFC signal is used as trigger..,?,?"
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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line.long 0x8 "SMCR,slave mode control register"
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bitfld.long 0x8 20.--21. "TS2,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3)"
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bitfld.long 0x8 16. "SMS2,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?"
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bitfld.long 0x8 7. "MSM,Master/slave mode" "0: No action,1: The effect of an event on the trigger input.."
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bitfld.long 0x8 4.--6. "TS1,Trigger selection" "0: Internal Trigger 0 (ITR0),1: Internal Trigger 1 (ITR1),2: Internal Trigger 2 (ITR2),3: Internal Trigger 3 (ITR3),4: TI1 Edge Detector (TI1F_ED),5: Filtered Timer Input 1 (TI1FP1),6: Filtered Timer Input 2 (TI2FP2),?"
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bitfld.long 0x8 0.--2. "SMS1,Slave mode selection" "0: Slave mode disabled - if CEN = '1' then the..,?,?,?,4: Reset Mode - Rising edge of the selected trigger..,5: Gated Mode - The counter clock is enabled when..,6: Trigger Mode - The counter starts at a rising..,7: External Clock Mode 1 - Rising edges of the.."
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line.long 0xC "DIER,DMA/Interrupt enable register"
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bitfld.long 0xC 14. "TDE,Trigger DMA request enable" "0: Trigger DMA request disabled,1: Trigger DMA request enabled"
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bitfld.long 0xC 13. "COMDE,COM DMA request enable" "0: COM DMA request disabled,1: COM DMA request enabled"
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bitfld.long 0xC 10. "CC2DE,Capture/Compare 2 DMA request enable" "0: CC2 DMA request disabled,1: CC2 DMA request enabled"
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bitfld.long 0xC 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0xC 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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bitfld.long 0xC 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0xC 6. "TIE,Trigger interrupt enable" "0: Trigger interrupt disabled,1: Trigger interrupt enabled"
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bitfld.long 0xC 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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bitfld.long 0xC 2. "CC2IE,Capture/Compare 2 interrupt enable" "0: CC2 interrupt disabled,1: CC2 interrupt enabled"
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bitfld.long 0xC 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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bitfld.long 0xC 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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line.long 0x10 "SR,status register"
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bitfld.long 0x10 10. "CC2OF,Capture/Compare 2 overcapture flag" "0,1"
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bitfld.long 0x10 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x10 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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bitfld.long 0x10 6. "TIF,Trigger interrupt flag" "0: No trigger event occurred,1: Trigger interrupt pending"
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bitfld.long 0x10 5. "COMIF,COM interrupt flag." "0: No COM event occurred,1: COM interrupt pending"
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bitfld.long 0x10 2. "CC2IF,Capture/Compare 2 interrupt flag" "0,1"
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bitfld.long 0x10 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0x10 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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bitfld.long 0x0 7. "BG,Break generation" "0: No action,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 6. "TG,Trigger generation" "0: No action,1: The TIF flag is set in TIMx_SR register. Related.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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bitfld.long 0x0 2. "CC2G,Capture/Compare 2 generation" "0,1"
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action,1: A capture/compare event is generated on channel 1:"
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bitfld.long 0x0 0. "UG,Update generation" "0: No action,1: Reinitialize the counter and generates an update.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 24. "OC2M2,Output Compare 2 mode" "0,1"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 12.--14. "OC2M1,Output Compare 2 mode" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 11. "OC2PE,Output Compare 2 preload enable" "0,1"
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bitfld.long 0x0 10. "OC2FE,Output Compare 2 fast enable" "0,1"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output.,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output.,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x18++0x3
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line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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hexmask.long.byte 0x0 12.--15. 1. "IC2F,Input capture 2 filter"
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bitfld.long 0x0 10.--11. "IC2PSC,Input capture 2 prescaler" "0,1,2,3"
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bitfld.long 0x0 8.--9. "CC2S,Capture/Compare 2 selection" "0: CC2 channel is configured as output,1: CC2 channel is configured as input IC2 is mapped..,2: CC2 channel is configured as input IC2 is mapped..,3: CC2 channel is configured as input IC2 is mapped.."
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hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
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bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,2: CC1 channel is configured as input IC1 is mapped..,3: CC1 channel is configured as input IC1 is mapped.."
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group.long 0x20++0x1B
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line.long 0x0 "CCER,capture/compare enable"
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bitfld.long 0x0 7. "CC2NP,Capture/Compare 2 complementary output polarity" "0,1"
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bitfld.long 0x0 5. "CC2P,Capture/Compare 2 output polarity" "0,1"
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bitfld.long 0x0 4. "CC2E,Capture/Compare 2 output enable" "0,1"
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bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
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bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
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bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
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bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
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line.long 0x4 "CNT,counter"
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rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
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hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
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line.long 0x8 "PSC,prescaler"
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hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
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line.long 0xC "ARR,auto-reload register"
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hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
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line.long 0x10 "RCR,repetition counter register"
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hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
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line.long 0x14 "CCR1,capture/compare register 1"
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hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
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line.long 0x18 "CCR2,capture/compare register 2"
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hexmask.long.word 0x18 0.--15. 1. "CCR2,Capture/Compare 2 value"
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group.long 0x44++0xB
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line.long 0x0 "BDTR,break and dead-time register"
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bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
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bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
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hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
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bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
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bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
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bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
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bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
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bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
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bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
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bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
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hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
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line.long 0x4 "DCR,DMA control register"
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hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
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hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
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line.long 0x8 "DMAR,DMA address for full transfer"
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hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
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group.long 0x60++0x3
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line.long 0x0 "AF1,TIM15 alternate register 1"
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bitfld.long 0x0 12. "BKCMP3P,BRK COMP3 input polarity" "0: COMP3 input is active low,1: COMP3 input is active high"
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bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
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bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
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bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
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bitfld.long 0x0 3. "BKCMP3E,BRK COMP3 enable" "0: COMP3 input disabled,1: COMP3 input enabled"
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bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
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bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
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bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
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group.long 0x68++0x3
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line.long 0x0 "TISEL,input selection register"
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hexmask.long.byte 0x0 8.--11. 1. "TI2SEL,selects TI2[0] to TI2[15] input"
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hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
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tree.end
|
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tree "TIM16 (General Purpose Timer)"
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base ad:0x40014400
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group.long 0x0++0x7
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line.long 0x0 "CR1,control register 1"
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bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
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bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
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bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
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bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
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newline
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bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
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bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
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bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
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line.long 0x4 "CR2,control register 2"
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bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
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bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
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bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
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bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
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newline
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bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
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group.long 0xC++0x7
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line.long 0x0 "DIER,DMA/Interrupt enable register"
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|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
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bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
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newline
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bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
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bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
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newline
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bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
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|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
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|
line.long 0x4 "SR,status register"
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|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
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bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
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bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
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|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
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bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
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wgroup.long 0x14++0x3
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line.long 0x0 "EGR,event generation register"
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|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
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bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
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bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
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|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
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|
group.long 0x18++0x3
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line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
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bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
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bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
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newline
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bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
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|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
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newline
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bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
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|
group.long 0x18++0x3
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|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
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|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
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|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
tree "TIM17 (General Purpose Timer)"
|
|
base ad:0x40014800
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CR1,control register 1"
|
|
bitfld.long 0x0 11. "UIFREMAP,UIF status bit remapping" "0: No remapping. UIF status bit is not copied to..,1: Remapping enabled. UIF status bit is copied to.."
|
|
bitfld.long 0x0 8.--9. "CKD,Clock division" "0: tDTS=tCK_INT,1: tDTS=2*tCK_INT,2: tDTS=4*tCK_INT,3: Reserved do not program this value"
|
|
newline
|
|
bitfld.long 0x0 7. "ARPE,Auto-reload preload enable" "0: TIMx_ARR register is not buffered,1: TIMx_ARR register is buffered"
|
|
bitfld.long 0x0 3. "OPM,One pulse mode" "0: Counter is not stopped at update event,1: Counter stops counting at the next update event.."
|
|
newline
|
|
bitfld.long 0x0 2. "URS,Update request source" "0: Any of the following events generate an update..,1: Only counter overflow/underflow generates an.."
|
|
bitfld.long 0x0 1. "UDIS,Update disable" "0: UEV enabled. The Update (UEV) event is generated..,1: UEV disabled. The Update event is not generated.."
|
|
newline
|
|
bitfld.long 0x0 0. "CEN,Counter enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "CR2,control register 2"
|
|
bitfld.long 0x4 9. "OIS1N,Output Idle state 1 (OC1N output)" "0: OC1N=0 after a dead-time when MOE=0,1: OC1N=1 after a dead-time when MOE=0"
|
|
bitfld.long 0x4 8. "OIS1,Output Idle state 1 (OC1 output)" "0: OC1=0 (after a dead-time if OC1N is implemented)..,1: OC1=1 (after a dead-time if OC1N is implemented).."
|
|
newline
|
|
bitfld.long 0x4 3. "CCDS,Capture/compare DMA selection" "0: CCx DMA request sent when CCx event occurs,1: CCx DMA requests sent when update event occurs"
|
|
bitfld.long 0x4 2. "CCUS,Capture/compare control update selection" "0: When capture/compare control bits are preloaded..,1: When capture/compare control bits are preloaded.."
|
|
newline
|
|
bitfld.long 0x4 0. "CCPC,Capture/compare preloaded control" "0: CCxE CCxNE and OCxM bits are not preloaded,1: CCxE CCxNE and OCxM bits are preloaded after.."
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "DIER,DMA/Interrupt enable register"
|
|
bitfld.long 0x0 9. "CC1DE,Capture/Compare 1 DMA request enable" "0: CC1 DMA request disabled,1: CC1 DMA request enabled"
|
|
bitfld.long 0x0 8. "UDE,Update DMA request enable" "0: Update DMA request disabled,1: Update DMA request enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "BIE,Break interrupt enable" "0: Break interrupt disabled,1: Break interrupt enabled"
|
|
bitfld.long 0x0 5. "COMIE,COM interrupt enable" "0: COM interrupt disabled,1: COM interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CC1IE,Capture/Compare 1 interrupt enable" "0: CC1 interrupt disabled,1: CC1 interrupt enabled"
|
|
bitfld.long 0x0 0. "UIE,Update interrupt enable" "0: Update interrupt disabled,1: Update interrupt enabled"
|
|
line.long 0x4 "SR,status register"
|
|
bitfld.long 0x4 9. "CC1OF,Capture/Compare 1 overcapture flag" "0: No overcapture has been detected,1: The counter value has been captured in TIMx_CCR1.."
|
|
bitfld.long 0x4 7. "BIF,Break interrupt flag" "0: No break event occurred,1: An active level has been detected on the break.."
|
|
newline
|
|
bitfld.long 0x4 5. "COMIF,COM interrupt flag" "0: No COM event occurred,1: COM interrupt pending"
|
|
bitfld.long 0x4 1. "CC1IF,Capture/Compare 1 interrupt flag" "0: No compare match / No input capture occurred,1: A compare match or an input capture occurred"
|
|
newline
|
|
bitfld.long 0x4 0. "UIF,Update interrupt flag" "0: No update occurred.,1: Update interrupt pending. This bit is set by.."
|
|
wgroup.long 0x14++0x3
|
|
line.long 0x0 "EGR,event generation register"
|
|
bitfld.long 0x0 7. "BG,Break generation" "0: No action.,1: A break event is generated. MOE bit is cleared.."
|
|
bitfld.long 0x0 5. "COMG,Capture/Compare control update generation" "0: No action,1: When the CCPC bit is set it is possible to.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1G,Capture/Compare 1 generation" "0: No action.,1: A capture/compare event is generated on channel 1:"
|
|
bitfld.long 0x0 0. "UG,Update generation" "0: No action.,1: Reinitialize the counter and generates an update.."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Output,capture/compare mode register (output"
|
|
bitfld.long 0x0 16. "OC1M2,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF.."
|
|
bitfld.long 0x0 4.--6. "OC1M1,Output Compare 1 mode" "0: Frozen - The comparison between the output..,1: Set channel 1 to active level on match. OC1REF..,2: Set channel 1 to inactive level on match. OC1REF..,3: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1.,4: Force inactive level - OC1REF is forced low.,5: Force active level - OC1REF is forced high.,6: PWM mode 1 - Channel 1 is active as long as..,7: PWM mode 2 - Channel 1 is inactive as long as.."
|
|
newline
|
|
bitfld.long 0x0 3. "OC1PE,Output Compare 1 preload enable" "0: Preload register on TIMx_CCR1 disabled.,1: Preload register on TIMx_CCR1 enabled."
|
|
bitfld.long 0x0 2. "OC1FE,Output Compare 1 fast enable" "0: CC1 behaves normally depending on counter and..,1: An active edge on the trigger input acts like a.."
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CCMR1_Input,capture/compare mode register 1 (input"
|
|
hexmask.long.byte 0x0 4.--7. 1. "IC1F,Input capture 1 filter"
|
|
bitfld.long 0x0 2.--3. "IC1PSC,Input capture 1 prescaler" "0: no prescaler capture is done each time an edge..,1: capture is done once every 2 events,2: capture is done once every 4 events,3: capture is done once every 8 events"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "CC1S,Capture/Compare 1 Selection" "0: CC1 channel is configured as output,1: CC1 channel is configured as input IC1 is mapped..,?,?"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "CCER,capture/compare enable"
|
|
bitfld.long 0x0 3. "CC1NP,Capture/Compare 1 complementary output polarity" "0: OC1N active high,1: OC1N active low"
|
|
bitfld.long 0x0 2. "CC1NE,Capture/Compare 1 complementary output enable" "0: Off - OC1N is not active. OC1N level is then..,1: On - OC1N signal is output on the corresponding.."
|
|
newline
|
|
bitfld.long 0x0 1. "CC1P,Capture/Compare 1 output polarity" "0: this configuration is reserved,1: non-inverted/both edges/ The circuit is.."
|
|
bitfld.long 0x0 0. "CC1E,Capture/Compare 1 output enable" "0: Capture mode disabled / OC1 is not active (see..,1: Capture mode enabled / OC1 signal is output on.."
|
|
line.long 0x4 "CNT,counter"
|
|
rbitfld.long 0x4 31. "UIFCPY,UIF Copy" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "CNT,counter value"
|
|
line.long 0x8 "PSC,prescaler"
|
|
hexmask.long.word 0x8 0.--15. 1. "PSC,Prescaler value"
|
|
line.long 0xC "ARR,auto-reload register"
|
|
hexmask.long.word 0xC 0.--15. 1. "ARR,Auto-reload value"
|
|
line.long 0x10 "RCR,repetition counter register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "REP,Repetition counter value"
|
|
line.long 0x14 "CCR1,capture/compare register 1"
|
|
hexmask.long.word 0x14 0.--15. 1. "CCR1,Capture/Compare 1 value"
|
|
group.long 0x44++0xB
|
|
line.long 0x0 "BDTR,break and dead-time register"
|
|
bitfld.long 0x0 28. "BKBID,Break Bidirectional" "0: Break input BRK in input mode,1: Break input BRK in bidirectional mode"
|
|
bitfld.long 0x0 26. "BKDSRM,Break Disarm" "0: Break input BRK is armed,1: Break input BRK is disarmed"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BKF,Break filter"
|
|
bitfld.long 0x0 15. "MOE,Main output enable" "0: OC and OCN outputs are disabled or forced to..,1: OC and OCN outputs are enabled if their.."
|
|
newline
|
|
bitfld.long 0x0 14. "AOE,Automatic output enable" "0: MOE can be set only by software,1: MOE can be set by software or automatically at.."
|
|
bitfld.long 0x0 13. "BKP,Break polarity" "0: Break input BRK is active low,1: Break input BRK is active high"
|
|
newline
|
|
bitfld.long 0x0 12. "BKE,Break enable" "0: Break inputs (BRK and CCS clock failure event)..,?"
|
|
bitfld.long 0x0 11. "OSSR,Off-state selection for Run mode" "0: When inactive OC/OCN outputs are disabled (the..,1: When inactive OC/OCN outputs are enabled with.."
|
|
newline
|
|
bitfld.long 0x0 10. "OSSI,Off-state selection for Idle mode" "0: When inactive OC/OCN outputs are disabled..,1: When inactive OC/OCN outputs are forced first.."
|
|
bitfld.long 0x0 8.--9. "LOCK,Lock configuration" "0: LOCK OFF - No bit is write protected,1: LOCK Level 1 = DTG bits in TIMx_BDTR register..,2: LOCK Level 2 = LOCK Level 1 + CC Polarity bits..,3: LOCK Level 3 = LOCK Level 2 + CC Control bits.."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DTG,Dead-time generator setup"
|
|
line.long 0x4 "DCR,DMA control register"
|
|
hexmask.long.byte 0x4 8.--12. 1. "DBL,DMA burst length"
|
|
hexmask.long.byte 0x4 0.--4. 1. "DBA,DMA base address"
|
|
line.long 0x8 "DMAR,DMA address for full transfer"
|
|
hexmask.long.word 0x8 0.--15. 1. "DMAB,DMA register for burst"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "AF1,TIM17 option register 1"
|
|
bitfld.long 0x0 11. "BKCMP2P,BRK COMP2 input polarity" "0: COMP2 input is active low,1: COMP2 input is active high"
|
|
bitfld.long 0x0 10. "BKCMP1P,BRK COMP1 input polarity" "0: COMP1 input is active low,1: COMP1 input is active high"
|
|
newline
|
|
bitfld.long 0x0 9. "BKINP,BRK BKIN input polarity" "0: BKIN input is active low,1: BKIN input is active high"
|
|
bitfld.long 0x0 2. "BKCMP2E,BRK COMP2 enable" "0: COMP2 input disabled,1: COMP2 input enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "BKCMP1E,BRK COMP1 enable" "0: COMP1 input disabled,1: COMP1 input enabled"
|
|
bitfld.long 0x0 0. "BKINE,BRK BKIN input enable" "0: BKIN input disabled,1: BKIN input enabled"
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "TISEL,input selection register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TI1SEL,selects TI1[0] to TI1[15] input"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "UCPD (USB Type-C / USB Power Delivery Interface)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*"))
|
|
tree "UCPD1"
|
|
base ad:0x4000A000
|
|
sif (cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CFG1,UCPD configuration register"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1"
|
|
bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV"
|
|
line.long 0x4 "CFG2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1"
|
|
bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1"
|
|
bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1"
|
|
line.long 0x8 "CFG3,UCPD configuration register 3"
|
|
hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0"
|
|
hexmask.long.byte 0x8 20.--24. 1. "TRIM2_NG_CC1A5,TRIM2_NG_CC1A5"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD"
|
|
hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "TRIM1_NG_CC1A5,TRIM1_NG_CC1A5"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD"
|
|
line.long 0xC "CR,UCPD control register"
|
|
bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1"
|
|
bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "RDCH,RDCH" "0,1"
|
|
bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1"
|
|
bitfld.long 0xC 15. "DBATTEN,DBATTEN" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3"
|
|
bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3"
|
|
bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1"
|
|
bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1"
|
|
bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3"
|
|
line.long 0x10 "IMR,UCPD Interrupt Mask Register"
|
|
bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1"
|
|
bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1"
|
|
bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1"
|
|
bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1"
|
|
bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1"
|
|
bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1"
|
|
bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1"
|
|
bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SR,UCPD Status Register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3"
|
|
bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1"
|
|
bitfld.long 0x0 13. "RXERR,RXERR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1"
|
|
bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1"
|
|
bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 6. "TXUND,TXUND" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1"
|
|
bitfld.long 0x0 0. "TXIS,TXIS" "0,1"
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "ICR,UCPD Interrupt Clear Register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1"
|
|
line.long 0x4 "TX_ORDSET,UCPD Tx Ordered Set Type"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "TXORDSET,TXORDSET"
|
|
line.long 0x8 "TX_PAYSZ,UCPD Tx Paysize Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "TXPAYSZ,TXPAYSZ"
|
|
line.long 0xC "TXDR,UCPD Tx Data Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TXDATA,TXDATA"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "RX_PAYSZ,UCPD Rx Paysize Register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RXPAYSZ,RXPAYSZ"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RXDR,UCPD Receive Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA,RXDATA"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1"
|
|
line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "IPVER,UCPD IP ID register"
|
|
hexmask.long 0x0 0.--31. 1. "IPVER,IPVER"
|
|
line.long 0x4 "IPID,UCPD IP ID register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IPID"
|
|
line.long 0x8 "MID,UCPD IP ID register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IPID"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock"
|
|
line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request"
|
|
newline
|
|
bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples"
|
|
bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable"
|
|
line.long 0x8 "UCPD_CFGR3,UCPD configuration register 3"
|
|
hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,SW trim value for RP3A0 resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 20.--24. 1. "TRIM2_NG_CC1A5,SW trim value for RP1A5 resistors on the CC2 line"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,SW trim value for RPD resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,SW trim value for RP3A0 resistors on the CC1 line"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "TRIM1_NG_CC1A5,SW trim value for RP1A5 resistors on the CC1 line"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,SW trim value for RPD resistors on the CC1 line"
|
|
line.long 0xC "UCPD_CR,UCPD control register"
|
|
bitfld.long 0xC 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable"
|
|
bitfld.long 0xC 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0xC 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive"
|
|
bitfld.long 0xC 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 15. "DBATTEN,Dead battery function enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 14. "CC2VCONNEN,VCONN switch enable for CC2" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 13. "CC1VCONNEN,VCONN switch enable for CC1" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY"
|
|
bitfld.long 0xC 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink"
|
|
newline
|
|
bitfld.long 0xC 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3"
|
|
bitfld.long 0xC 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication"
|
|
newline
|
|
bitfld.long 0xC 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)"
|
|
newline
|
|
bitfld.long 0xC 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message"
|
|
bitfld.long 0xC 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?"
|
|
line.long 0x10 "UCPD_IMR,UCPD interrupt mask register"
|
|
rbitfld.long 0x10 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1"
|
|
bitfld.long 0x10 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "UCPD_SR,UCPD status register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest"
|
|
bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event"
|
|
bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received"
|
|
bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received"
|
|
bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty"
|
|
bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent"
|
|
bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort"
|
|
bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded"
|
|
bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "UCPD_ICR,UCPD interrupt clear register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit"
|
|
line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit"
|
|
line.long 0x8 "UCPD_TXDR,UCPD Tx data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No code corrupted,1: First code corrupted,2: Second code corrupted,3: Third code corrupted,4: Fourth code corrupted,?,?,?"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct. For debug purposes only." "0: 4 correct codes out of 4,1: 3 correct codes out of 4"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver"
|
|
line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received"
|
|
line.long 0x8 "UCPD_RXDR,UCPD receive data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received"
|
|
line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B1*"))
|
|
tree "UCPD2"
|
|
base ad:0x4000A400
|
|
sif (cpuis("STM32G070*")||cpuis("STM32G071*")||cpuis("STM32G081*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CFG1,UCPD configuration register"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPDEN" "0,1"
|
|
bitfld.long 0x0 30. "RXDMAEN,RXDMAEN:" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,TXDMAEN" "0,1"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,RXORDSETEN"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,PSC_USBPDCLK" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,TRANSWIN"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,IFRGAP"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,HBITCLKDIV"
|
|
line.long 0x4 "CFG2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,WUPEN" "0,1"
|
|
bitfld.long 0x4 2. "FORCECLK,FORCECLK" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXFILT2N3,RXFILT2N3" "0,1"
|
|
bitfld.long 0x4 0. "RXFILTDIS,RXFILTDIS" "0,1"
|
|
line.long 0x8 "CFG3,UCPD configuration register 3"
|
|
hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,TRIM2_NG_CC3A0"
|
|
hexmask.long.byte 0x8 20.--24. 1. "TRIM2_NG_CC1A5,TRIM2_NG_CC1A5"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,TRIM2_NG_CCRPD"
|
|
hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,TRIM1_NG_CC3A0"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "TRIM1_NG_CC1A5,TRIM1_NG_CC1A5"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,TRIM1_NG_CCRPD"
|
|
line.long 0xC "CR,UCPD control register"
|
|
bitfld.long 0xC 21. "CC2TCDIS,CC2TCDIS" "0,1"
|
|
bitfld.long 0xC 20. "CC1TCDIS,CC1TCDIS" "0,1"
|
|
newline
|
|
bitfld.long 0xC 18. "RDCH,RDCH" "0,1"
|
|
bitfld.long 0xC 17. "FRSTX,FRSTX" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "FRSRXEN,FRSRXEN" "0,1"
|
|
bitfld.long 0xC 15. "DBATTEN,DBATTEN" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CCENABLE,CCENABLE" "0,1,2,3"
|
|
bitfld.long 0xC 9. "ANAMODE,ANAMODE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7.--8. "ANASUBMODE,ANASUBMODE" "0,1,2,3"
|
|
bitfld.long 0xC 6. "PHYCCSEL,PHYCCSEL" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "PHYRXEN,PHYRXEN" "0,1"
|
|
bitfld.long 0xC 4. "RXMODE,RXMODE" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "TXHRST,TXHRST" "0,1"
|
|
bitfld.long 0xC 2. "TXSEND,TXSEND" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "TXMODE,TXMODE" "0,1,2,3"
|
|
line.long 0x10 "IMR,UCPD Interrupt Mask Register"
|
|
bitfld.long 0x10 20. "FRSEVTIE,FRSEVTIE" "0,1"
|
|
bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2IE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1IE" "0,1"
|
|
bitfld.long 0x10 12. "RXMSGENDIE,RXMSGENDIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "RXOVRIE,RXOVRIE" "0,1"
|
|
bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDETIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "RXORDDETIE,RXORDDETIE" "0,1"
|
|
bitfld.long 0x10 8. "RXNEIE,RXNEIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "TXUNDIE,TXUNDIE" "0,1"
|
|
bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISCIE" "0,1"
|
|
bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABTIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENTIE" "0,1"
|
|
bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISCIE" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "TXISIE,TXISIE" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SR,UCPD Status Register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRSEVT" "0,1"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,TYPEC_VSTATE_CC2" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,TYPEC_VSTATE_CC1" "0,1,2,3"
|
|
bitfld.long 0x0 15. "TYPECEVT2,TYPECEVT2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,TYPECEVT1" "0,1"
|
|
bitfld.long 0x0 13. "RXERR,RXERR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,RXMSGEND" "0,1"
|
|
bitfld.long 0x0 11. "RXOVR,RXOVR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,RXHRSTDET" "0,1"
|
|
bitfld.long 0x0 9. "RXORDDET,RXORDDET" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 6. "TXUND,TXUND" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,HRSTSENT" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISC,HRSTDISC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,TXMSGABT" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENT,TXMSGSENT" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,TXMSGDISC" "0,1"
|
|
bitfld.long 0x0 0. "TXIS,TXIS" "0,1"
|
|
group.long 0x18++0xF
|
|
line.long 0x0 "ICR,UCPD Interrupt Clear Register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRSEVTCF" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,TYPECEVT2CF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,TYPECEVT1CF" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,RXMSGENDCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,RXOVRCF" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,RXHRSTDETCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,RXORDDETCF" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,TXUNDCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,HRSTSENTCF" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,HRSTDISCCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,TXMSGABTCF" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,TXMSGSENTCF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,TXMSGDISCCF" "0,1"
|
|
line.long 0x4 "TX_ORDSET,UCPD Tx Ordered Set Type"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "TXORDSET,TXORDSET"
|
|
line.long 0x8 "TX_PAYSZ,UCPD Tx Paysize Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "TXPAYSZ,TXPAYSZ"
|
|
line.long 0xC "TXDR,UCPD Tx Data Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "TXDATA,TXDATA"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "RX_ORDSET,UCPD Rx Ordered Set Register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,RXSOPKINVALID" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,RXSOP3OF4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,RXORDSET" "0,1,2,3,4,5,6,7"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "RX_PAYSZ,UCPD Rx Paysize Register"
|
|
hexmask.long.word 0x0 0.--9. 1. "RXPAYSZ,RXPAYSZ"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x0 "RXDR,UCPD Receive Data Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA,RXDATA"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "RX_ORDEXT1,UCPD Rx Ordered Set Extension"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,RXSOPX1"
|
|
line.long 0x4 "RX_ORDEXT2,UCPD Rx Ordered Set Extension"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,RXSOPX2"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "IPVER,UCPD IP ID register"
|
|
hexmask.long 0x0 0.--31. 1. "IPVER,IPVER"
|
|
line.long 0x4 "IPID,UCPD IP ID register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IPID"
|
|
line.long 0x8 "MID,UCPD IP ID register"
|
|
hexmask.long 0x8 0.--31. 1. "IPID,IPID"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock"
|
|
line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request"
|
|
newline
|
|
bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples"
|
|
bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable"
|
|
line.long 0x8 "UCPD_CFGR3,UCPD configuration register 3"
|
|
hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,SW trim value for RP3A0 resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 20.--24. 1. "TRIM2_NG_CC1A5,SW trim value for RP1A5 resistors on the CC2 line"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,SW trim value for RPD resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,SW trim value for RP3A0 resistors on the CC1 line"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "TRIM1_NG_CC1A5,SW trim value for RP1A5 resistors on the CC1 line"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,SW trim value for RPD resistors on the CC1 line"
|
|
line.long 0xC "UCPD_CR,UCPD control register"
|
|
bitfld.long 0xC 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable"
|
|
bitfld.long 0xC 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0xC 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive"
|
|
bitfld.long 0xC 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 15. "DBATTEN,Dead battery function enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 14. "CC2VCONNEN,VCONN switch enable for CC2" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 13. "CC1VCONNEN,VCONN switch enable for CC1" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY"
|
|
bitfld.long 0xC 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink"
|
|
newline
|
|
bitfld.long 0xC 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3"
|
|
bitfld.long 0xC 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication"
|
|
newline
|
|
bitfld.long 0xC 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)"
|
|
newline
|
|
bitfld.long 0xC 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message"
|
|
bitfld.long 0xC 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?"
|
|
line.long 0x10 "UCPD_IMR,UCPD interrupt mask register"
|
|
rbitfld.long 0x10 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1"
|
|
bitfld.long 0x10 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "UCPD_SR,UCPD status register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest"
|
|
bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event"
|
|
bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received"
|
|
bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received"
|
|
bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty"
|
|
bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent"
|
|
bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort"
|
|
bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded"
|
|
bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "UCPD_ICR,UCPD interrupt clear register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit"
|
|
line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit"
|
|
line.long 0x8 "UCPD_TXDR,UCPD Tx data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No code corrupted,1: First code corrupted,2: Second code corrupted,3: Third code corrupted,4: Fourth code corrupted,?,?,?"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct. For debug purposes only." "0: 4 correct codes out of 4,1: 3 correct codes out of 4"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver"
|
|
line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received"
|
|
line.long 0x8 "UCPD_RXDR,UCPD receive data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received"
|
|
line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "UCPD1"
|
|
base ad:0x4000A000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock"
|
|
line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request"
|
|
newline
|
|
bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples"
|
|
bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable"
|
|
line.long 0x8 "UCPD_CFGR3,UCPD configuration register 3"
|
|
hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,SW trim value for RP3A0 resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 20.--24. 1. "TRIM2_NG_CC1A5,SW trim value for RP1A5 resistors on the CC2 line"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,SW trim value for RPD resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,SW trim value for RP3A0 resistors on the CC1 line"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "TRIM1_NG_CC1A5,SW trim value for RP1A5 resistors on the CC1 line"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,SW trim value for RPD resistors on the CC1 line"
|
|
line.long 0xC "UCPD_CR,UCPD control register"
|
|
bitfld.long 0xC 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable"
|
|
bitfld.long 0xC 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0xC 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive"
|
|
bitfld.long 0xC 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 15. "DBATTEN,Dead battery function enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 14. "CC2VCONNEN,VCONN switch enable for CC2" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 13. "CC1VCONNEN,VCONN switch enable for CC1" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY"
|
|
bitfld.long 0xC 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink"
|
|
newline
|
|
bitfld.long 0xC 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3"
|
|
bitfld.long 0xC 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication"
|
|
newline
|
|
bitfld.long 0xC 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)"
|
|
newline
|
|
bitfld.long 0xC 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message"
|
|
bitfld.long 0xC 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?"
|
|
line.long 0x10 "UCPD_IMR,UCPD interrupt mask register"
|
|
rbitfld.long 0x10 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1"
|
|
bitfld.long 0x10 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "UCPD_SR,UCPD status register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest"
|
|
bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event"
|
|
bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received"
|
|
bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received"
|
|
bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty"
|
|
bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent"
|
|
bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort"
|
|
bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded"
|
|
bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "UCPD_ICR,UCPD interrupt clear register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit"
|
|
line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit"
|
|
line.long 0x8 "UCPD_TXDR,UCPD Tx data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No code corrupted,1: First code corrupted,2: Second code corrupted,3: Third code corrupted,4: Fourth code corrupted,?,?,?"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct For debug purposes only." "0: 4 correct out of 4,1: 3 correct out of 4"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver"
|
|
line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received"
|
|
line.long 0x8 "UCPD_RXDR,UCPD receive data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received."
|
|
line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received"
|
|
tree.end
|
|
tree "UCPD2"
|
|
base ad:0x4000A400
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "UCPD_CFGR1,UCPD configuration register 1"
|
|
bitfld.long 0x0 31. "UCPDEN,UCPD peripheral enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 30. "RXDMAEN,Reception DMA mode enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 29. "TXDMAEN,Transmission DMA mode enable" "0: Disable,1: Enable"
|
|
hexmask.long.word 0x0 20.--28. 1. "RXORDSETEN,Receiver ordered set enable"
|
|
newline
|
|
bitfld.long 0x0 17.--19. "PSC_USBPDCLK,Pre-scaler division ratio for generating ucpd_clk" "0: 1 (bypass),1: 2,2: 4,3: 8,4: 16,?,?,?"
|
|
hexmask.long.byte 0x0 11.--15. 1. "TRANSWIN,Transition window duration"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--10. 1. "IFRGAP,Division ratio for producing inter-frame gap timer clock"
|
|
hexmask.long.byte 0x0 0.--5. 1. "HBITCLKDIV,Division ratio for producing half-bit clock"
|
|
line.long 0x4 "UCPD_CFGR2,UCPD configuration register 2"
|
|
bitfld.long 0x4 3. "WUPEN,Wakeup from Stop mode enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x4 2. "FORCECLK,Force ClkReq clock request" "0: Do not force clock request,1: Force clock request"
|
|
newline
|
|
bitfld.long 0x4 1. "RXFILT2N3,BMC decoder Rx pre-filter sampling method" "0: 3 samples,1: 2 samples"
|
|
bitfld.long 0x4 0. "RXFILTDIS,BMC decoder Rx pre-filter enable" "0: Enable,1: Disable"
|
|
line.long 0x8 "UCPD_CFGR3,UCPD configuration register 3"
|
|
hexmask.long.byte 0x8 25.--28. 1. "TRIM2_NG_CC3A0,SW trim value for RP3A0 resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 20.--24. 1. "TRIM2_NG_CC1A5,SW trim value for RP1A5 resistors on the CC2 line"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "TRIM2_NG_CCRPD,SW trim value for RPD resistors on the CC2 line"
|
|
hexmask.long.byte 0x8 9.--12. 1. "TRIM1_NG_CC3A0,SW trim value for RP3A0 resistors on the CC1 line"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--8. 1. "TRIM1_NG_CC1A5,SW trim value for RP1A5 resistors on the CC1 line"
|
|
hexmask.long.byte 0x8 0.--3. 1. "TRIM1_NG_CCRPD,SW trim value for RPD resistors on the CC1 line"
|
|
line.long 0xC "UCPD_CR,UCPD control register"
|
|
bitfld.long 0xC 21. "CC2TCDIS,CC2 Type-C detector disable" "0: Enable,1: Disable"
|
|
bitfld.long 0xC 20. "CC1TCDIS,CC1 Type-C detector disable" "0: Enable,1: Disable"
|
|
newline
|
|
bitfld.long 0xC 18. "RDCH,Rdch condition drive" "0: No effect,1: Rdch condition drive"
|
|
bitfld.long 0xC 17. "FRSTX,FRS Tx signaling enable." "0: No effect,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 16. "FRSRXEN,FRS event detection enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 15. "DBATTEN,Dead battery function enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 14. "CC2VCONNEN,VCONN switch enable for CC2" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 13. "CC1VCONNEN,VCONN switch enable for CC1" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0xC 10.--11. "CCENABLE,CC line enable" "0: Disable both PHYs,1: Enable CC1 PHY,2: Enable CC2 PHY,3: Enable CC1 and CC2 PHY"
|
|
bitfld.long 0xC 9. "ANAMODE,Analog PHY operating mode" "0: Source,1: Sink"
|
|
newline
|
|
bitfld.long 0xC 7.--8. "ANASUBMODE,Analog PHY sub-mode" "0,1,2,3"
|
|
bitfld.long 0xC 6. "PHYCCSEL,CC1/CC2 line selector for USB Power Delivery signaling" "0: Use CC1 IO for Power Delivery communication,1: Use CC2 IO for Power Delivery communication"
|
|
newline
|
|
bitfld.long 0xC 5. "PHYRXEN,USB Power Delivery receiver enable" "0: Disable,1: Enable"
|
|
bitfld.long 0xC 4. "RXMODE,Receiver mode" "0: Normal receive mode,1: BIST receive mode (BIST test data mode)"
|
|
newline
|
|
bitfld.long 0xC 3. "TXHRST,Command to send a Tx Hard Reset" "0: No effect,1: Start Tx Hard Reset message"
|
|
bitfld.long 0xC 2. "TXSEND,Command to send a Tx packet" "0: No effect,1: Start Tx packet transmission"
|
|
newline
|
|
bitfld.long 0xC 0.--1. "TXMODE,Type of Tx packet" "0: Transmission of Tx packet previously defined in..,1: Cable Reset sequence,2: BIST test sequence (BIST Carrier Mode 2),?"
|
|
line.long 0x10 "UCPD_IMR,UCPD interrupt mask register"
|
|
rbitfld.long 0x10 20. "FRSEVTIE,FRSEVT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 15. "TYPECEVT2IE,TYPECEVT2 interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 14. "TYPECEVT1IE,TYPECEVT1 interrupt enable" "0,1"
|
|
bitfld.long 0x10 12. "RXMSGENDIE,RXMSGEND interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 11. "RXOVRIE,RXOVR interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 10. "RXHRSTDETIE,RXHRSTDET interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 9. "RXORDDETIE,RXORDDET interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 8. "RXNEIE,RXNE interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 6. "TXUNDIE,TXUND interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 5. "HRSTSENTIE,HRSTSENT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 4. "HRSTDISCIE,HRSTDISC interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 3. "TXMSGABTIE,TXMSGABT interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 2. "TXMSGSENTIE,TXMSGSENT interrupt enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x10 1. "TXMSGDISCIE,TXMSGDISC interrupt enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x10 0. "TXISIE,TXIS interrupt enable" "0: Disable,1: Enable"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "UCPD_SR,UCPD status register"
|
|
bitfld.long 0x0 20. "FRSEVT,FRS detection event" "0: No new event,1: New FRS receive event occurred"
|
|
bitfld.long 0x0 18.--19. "TYPEC_VSTATE_CC2,CC2 line voltage level" "0: Lowest,1: Low,2: High,3: Highest"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TYPEC_VSTATE_CC1,The status bitfield indicates the voltage level on the CC1 line in its steady state." "0: Lowest,1: Low,2: High,3: Highest"
|
|
bitfld.long 0x0 15. "TYPECEVT2,Type-C voltage level event on CC2 line" "0: No new event,1: A new Type-C event"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1,Type-C voltage level event on CC1 line" "0: No new event,1: A new Type-C event"
|
|
bitfld.long 0x0 13. "RXERR,Receive message error" "0: No error detected,1: Error(s) detected"
|
|
newline
|
|
bitfld.long 0x0 12. "RXMSGEND,Rx message received" "0: No new Rx message received,1: A new Rx message received"
|
|
bitfld.long 0x0 11. "RXOVR,Rx data overflow detection" "0: No overflow,1: Overflow"
|
|
newline
|
|
bitfld.long 0x0 10. "RXHRSTDET,Rx Hard Reset receipt detection" "0: Hard Reset not received,1: Hard Reset received"
|
|
bitfld.long 0x0 9. "RXORDDET,Rx ordered set (4 K-codes) detection" "0: No ordered set detected,1: A new ordered set detected"
|
|
newline
|
|
bitfld.long 0x0 8. "RXNE,Receive data register not empty detection" "0: Rx data register empty,1: Rx data register not empty"
|
|
bitfld.long 0x0 6. "TXUND,Tx data underrun detection" "0: No Tx data underrun detected,1: Tx data underrun detected"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENT,Hard Reset message sent" "0: No Hard Reset message sent,1: Hard Reset message sent"
|
|
bitfld.long 0x0 4. "HRSTDISC,Hard Reset discarded" "0: No Hard Reset discarded,1: Hard Reset discarded"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABT,Transmit message abort" "0: No transmit message abort,1: Transmit message abort"
|
|
bitfld.long 0x0 2. "TXMSGSENT,Message transmission completed" "0: No Tx message completed,1: Tx message completed"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISC,Message transmission discarded" "0: No Tx message discarded,1: Tx message discarded"
|
|
bitfld.long 0x0 0. "TXIS,Transmit interrupt status" "0: New Tx data write not required,1: New Tx data write required"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "UCPD_ICR,UCPD interrupt clear register"
|
|
bitfld.long 0x0 20. "FRSEVTCF,FRS event flag (FRSEVT) clear" "0,1"
|
|
bitfld.long 0x0 15. "TYPECEVT2CF,Type-C CC2 line event flag (TYPECEVT2) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "TYPECEVT1CF,Type-C CC1 event flag (TYPECEVT1) clear" "0,1"
|
|
bitfld.long 0x0 12. "RXMSGENDCF,Rx message received flag (RXMSGEND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RXOVRCF,Rx overflow flag (RXOVR) clear" "0,1"
|
|
bitfld.long 0x0 10. "RXHRSTDETCF,Rx Hard Reset detect flag (RXHRSTDET) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXORDDETCF,Rx ordered set detect flag (RXORDDET) clear" "0,1"
|
|
bitfld.long 0x0 6. "TXUNDCF,Tx underflow flag (TXUND) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "HRSTSENTCF,Hard reset send flag (HRSTSENT) clear" "0,1"
|
|
bitfld.long 0x0 4. "HRSTDISCCF,Hard reset discard flag (HRSTDISC) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXMSGABTCF,Tx message abort flag (TXMSGABT) clear" "0,1"
|
|
bitfld.long 0x0 2. "TXMSGSENTCF,Tx message send flag (TXMSGSENT) clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXMSGDISCCF,Tx message discard flag (TXMSGDISC) clear" "0,1"
|
|
group.long 0x1C++0xB
|
|
line.long 0x0 "UCPD_TX_ORDSETR,UCPD Tx ordered set type register"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "TXORDSET,Ordered set to transmit"
|
|
line.long 0x4 "UCPD_TX_PAYSZR,UCPD Tx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "TXPAYSZ,Payload size yet to transmit"
|
|
line.long 0x8 "UCPD_TXDR,UCPD Tx data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TXDATA,Data byte to transmit"
|
|
rgroup.long 0x28++0xB
|
|
line.long 0x0 "UCPD_RX_ORDSETR,UCPD Rx ordered set register"
|
|
bitfld.long 0x0 4.--6. "RXSOPKINVALID,The bitfield is for debug purposes only." "0: No code corrupted,1: First code corrupted,2: Second code corrupted,3: Third code corrupted,4: Fourth code corrupted,?,?,?"
|
|
bitfld.long 0x0 3. "RXSOP3OF4,The bit indicates the number of correct For debug purposes only." "0: 4 correct out of 4,1: 3 correct out of 4"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "RXORDSET,Rx ordered set code detected" "0: SOP code detected in receiver,1: SOP' code detected in receiver,2: SOP'' code detected in receiver,3: SOP'_Debug detected in receiver,4: SOP''_Debug detected in receiver,5: Cable Reset detected in receiver,6: SOP extension#1 detected in receiver,7: SOP extension#2 detected in receiver"
|
|
line.long 0x4 "UCPD_RX_PAYSZR,UCPD Rx payload size register"
|
|
hexmask.long.word 0x4 0.--9. 1. "RXPAYSZ,Rx payload size received"
|
|
line.long 0x8 "UCPD_RXDR,UCPD receive data register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXDATA,Data byte received"
|
|
group.long 0x34++0x7
|
|
line.long 0x0 "UCPD_RX_ORDEXTR1,UCPD Rx ordered set extension register 1"
|
|
hexmask.long.tbyte 0x0 0.--19. 1. "RXSOPX1,Ordered set 1 received."
|
|
line.long 0x4 "UCPD_RX_ORDEXTR2,UCPD Rx ordered set extension register 2"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "RXSOPX2,Ordered set 2 received"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "USART (Universal Synchronous Asynchronous Receiver Transmitter)"
|
|
base ad:0x0
|
|
sif (cpuis("STM32G031*"))
|
|
tree "LPUART"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT0"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT0,DEDT0"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G041*"))
|
|
tree "LPUART"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT0"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT0,DEDT0"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR2,Control register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
newline
|
|
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x0 17. "TXINV,TX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the USART node"
|
|
newline
|
|
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
newline
|
|
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
newline
|
|
bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
newline
|
|
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
bitfld.long 0x0 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
newline
|
|
bitfld.long 0x0 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
bitfld.long 0x0 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
newline
|
|
bitfld.long 0x0 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
newline
|
|
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
bitfld.long 0x0 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
endif
|
|
line.long 0x4 "CR3,Control register 3"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x4 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x4 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x4 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x4 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x4 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x4 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x4 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x4 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
endif
|
|
line.long 0x8 "BRR,Baud rate register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.word 0x8 0.--15. 1. "BRR,USART baud rate"
|
|
endif
|
|
line.long 0xC "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value"
|
|
endif
|
|
line.long 0x10 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
endif
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G050*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
endif
|
|
group.long 0x4++0x13
|
|
line.long 0x0 "CR2,Control register 2"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x0 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x0 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
newline
|
|
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x0 17. "TXINV,TX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x0 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x0 10. "CPOL,Clock polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x0 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.byte 0x0 24.--31. 1. "ADD,Address of the USART node"
|
|
newline
|
|
bitfld.long 0x0 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
bitfld.long 0x0 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
newline
|
|
bitfld.long 0x0 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
bitfld.long 0x0 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
newline
|
|
bitfld.long 0x0 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
bitfld.long 0x0 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x0 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x0 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
newline
|
|
bitfld.long 0x0 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
bitfld.long 0x0 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
newline
|
|
bitfld.long 0x0 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
bitfld.long 0x0 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
newline
|
|
bitfld.long 0x0 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
bitfld.long 0x0 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
bitfld.long 0x0 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
newline
|
|
bitfld.long 0x0 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
bitfld.long 0x0 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
endif
|
|
line.long 0x4 "CR3,Control register 3"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x4 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x4 14. "DEM,Driver enable mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x4 8. "RTSE,RTS enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x4 2. "IRLP,Ir low-power" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x4 0. "EIE,Error interrupt enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x4 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x4 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x4 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x4 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x4 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x4 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x4 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x4 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x4 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x4 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x4 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x4 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x4 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x4 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x4 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x4 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x4 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x4 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x4 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x4 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
endif
|
|
line.long 0x8 "BRR,Baud rate register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.word 0x8 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0x8 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
hexmask.long.word 0x8 0.--15. 1. "BRR,USART baud rate"
|
|
endif
|
|
line.long 0xC "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0xC 8.--15. 1. "GT,Guard time value"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0xC 0.--7. 1. "PSC,Prescaler value"
|
|
endif
|
|
line.long 0x10 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x10 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
endif
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
endif
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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|
line.long 0xC "BRR,Baud rate register"
|
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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|
line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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|
rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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|
newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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|
newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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|
newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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|
newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
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newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
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newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
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wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
|
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
|
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
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newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
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newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
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newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
|
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
|
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "LPUART"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT0"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT0,DEDT0"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
group.long 0x3EC++0x7
|
|
line.long 0x0 "HWCFGR2,LPUART Hardware Configuration register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,LUART hardware configuration"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,LUART hardware configuration"
|
|
line.long 0x4 "HWCFGR1,LPUART Hardware Configuration register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "CFG8,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "CFG7,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CFG6,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 16.--19. 1. "CFG5,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CFG4,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 8.--11. 1. "CFG3,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 4.--7. 1. "CFG2,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CFG1,LUART hardware configuration"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "LPUART"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT0"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT0,DEDT0"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
group.long 0x3EC++0x7
|
|
line.long 0x0 "HWCFGR2,LPUART Hardware Configuration register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,LUART hardware configuration"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,LUART hardware configuration"
|
|
line.long 0x4 "HWCFGR1,LPUART Hardware Configuration register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "CFG8,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "CFG7,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CFG6,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 16.--19. 1. "CFG5,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CFG4,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 8.--11. 1. "CFG3,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 4.--7. 1. "CFG2,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CFG1,LUART hardware configuration"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "USART3"
|
|
base ad:0x40004800
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "USART4"
|
|
base ad:0x40004C00
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt" "0,1"
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,DEDT"
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0,1"
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0,1,2,3"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0,1"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0,1"
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0,1"
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0,1"
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0,1"
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt" "0,1"
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DSI_NSS bit is set the NSS pin" "0,1"
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 24. "TCBGTIE,Tr Complete before guard time interrupt" "0,1"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0,1"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 2. "IRLP,Ir low-power" "0,1"
|
|
bitfld.long 0x8 1. "IREN,Ir mode enable" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 4.--15. 1. "BRR_4_15,BRR_4_15"
|
|
hexmask.long.byte 0xC 0.--3. 1. "BRR_0_3,BRR_0_3"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 15. "ABRF,ABRF" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,ABRE" "0,1"
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error" "0,1"
|
|
bitfld.long 0x0 12. "EOBF,EOBF" "0,1"
|
|
bitfld.long 0x0 11. "RTOF,RTOF" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 8. "LBDF,LBDF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
tree "LPUART"
|
|
base ad:0x40008000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CR1,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt" "0,1"
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt" "0,1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0,1"
|
|
bitfld.long 0x0 28. "M1,Word length" "0,1"
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,DEAT0"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT0,DEDT0"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt" "0,1"
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0,1"
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0,1"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0,1"
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0,1"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0,1"
|
|
bitfld.long 0x0 7. "TXEIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt" "0,1"
|
|
bitfld.long 0x0 5. "RXNEIE,RXNE interrupt enable" "0,1"
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0,1"
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0,1"
|
|
bitfld.long 0x0 1. "UESM,USART enable in Stop mode" "0,1"
|
|
bitfld.long 0x0 0. "UE,USART enable" "0,1"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 28.--31. 1. "ADD4_7,Address of the USART node"
|
|
hexmask.long.byte 0x4 24.--27. 1. "ADD0_3,Address of the USART node"
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0,1"
|
|
bitfld.long 0x4 18. "TAINV,Binary data inversion" "0,1"
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level" "0,1"
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level" "0,1"
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0,1"
|
|
bitfld.long 0x4 12.--13. "STOP,STOP bits" "0,1,2,3"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address" "0,1"
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt" "0,1"
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 23. "TXFTIE,threshold interrupt enable" "0,1"
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from Stop mode interrupt" "0,1"
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from Stop mode interrupt flag" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity" "0,1"
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0,1"
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0,1"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0,1"
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0,1"
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0,1"
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0,1"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0,1"
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0,1"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0,1"
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.tbyte 0xC 0.--19. 1. "BRR,BRR"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0,1"
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO Full" "0,1"
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO Empty" "0,1"
|
|
bitfld.long 0x0 22. "REACK,REACK" "0,1"
|
|
bitfld.long 0x0 21. "TEACK,TEACK" "0,1"
|
|
bitfld.long 0x0 20. "WUF,WUF" "0,1"
|
|
bitfld.long 0x0 19. "RWU,RWU" "0,1"
|
|
bitfld.long 0x0 18. "SBKF,SBKF" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,CMF" "0,1"
|
|
bitfld.long 0x0 16. "BUSY,BUSY" "0,1"
|
|
bitfld.long 0x0 10. "CTS,CTS" "0,1"
|
|
bitfld.long 0x0 9. "CTSIF,CTSIF" "0,1"
|
|
bitfld.long 0x0 7. "TXE,TXE" "0,1"
|
|
bitfld.long 0x0 6. "TC,TC" "0,1"
|
|
bitfld.long 0x0 5. "RXNE,RXNE" "0,1"
|
|
bitfld.long 0x0 4. "IDLE,IDLE" "0,1"
|
|
bitfld.long 0x0 3. "ORE,ORE" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NF,NF" "0,1"
|
|
bitfld.long 0x0 1. "FE,FE" "0,1"
|
|
bitfld.long 0x0 0. "PE,PE" "0,1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from Stop mode clear" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear" "0,1"
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
bitfld.long 0x0 2. "NCF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
group.long 0x3EC++0x7
|
|
line.long 0x0 "HWCFGR2,LPUART Hardware Configuration register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CFG2,LUART hardware configuration"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CFG1,LUART hardware configuration"
|
|
line.long 0x4 "HWCFGR1,LPUART Hardware Configuration register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "CFG8,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "CFG7,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CFG6,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 16.--19. 1. "CFG5,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 12.--15. 1. "CFG4,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 8.--11. 1. "CFG3,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 4.--7. 1. "CFG2,LUART hardware configuration"
|
|
hexmask.long.byte 0x4 0.--3. 1. "CFG1,LUART hardware configuration"
|
|
rgroup.long 0x3F4++0xB
|
|
line.long 0x0 "VERR,EXTI IP Version register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "MAJREV,Major Revision number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MINREV,Minor Revision number"
|
|
line.long 0x4 "IPIDR,EXTI Identification register"
|
|
hexmask.long 0x4 0.--31. 1. "IPID,IP Identification"
|
|
line.long 0x8 "SIDR,EXTI Size ID register"
|
|
hexmask.long 0x8 0.--31. 1. "SID,Size Identification"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
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|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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|
newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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|
newline
|
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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|
newline
|
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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|
newline
|
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART3"
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base ad:0x40004800
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
|
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART4"
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base ad:0x40004C00
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
|
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
|
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
|
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
|
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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|
newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
|
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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|
newline
|
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
|
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
|
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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|
newline
|
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
|
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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|
newline
|
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
|
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
|
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART5"
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base ad:0x40005000
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
|
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
|
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART6"
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base ad:0x40013C00
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
|
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
|
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
|
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
|
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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|
line.long 0x4 "CR2,Control register 2"
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|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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|
newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
|
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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|
newline
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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|
line.long 0x8 "CR3,Control register 3"
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|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
|
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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|
line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
|
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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|
rgroup.long 0x1C++0x3
|
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
|
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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|
newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART3"
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base ad:0x40004800
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
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wgroup.long 0x20++0x3
|
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line.long 0x0 "ICR,Interrupt flag clear register"
|
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
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line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART4"
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base ad:0x40004C00
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART5"
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base ad:0x40005000
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
|
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
|
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
|
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
|
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
|
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
|
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
|
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
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newline
|
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
|
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
|
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
|
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line.long 0x0 "RQR,Request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
|
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
|
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
|
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
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newline
|
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART6"
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base ad:0x40013C00
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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newline
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
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bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
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newline
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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newline
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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newline
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
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bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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newline
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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newline
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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newline
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
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|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "USART1"
|
|
base ad:0x40013800
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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|
newline
|
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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|
newline
|
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
|
|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
|
|
newline
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
|
|
newline
|
|
bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
tree "USART2"
|
|
base ad:0x40004400
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
|
|
bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
|
|
bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
|
bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
|
|
bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
|
newline
|
|
bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
|
bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
|
bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
|
bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
|
|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
|
bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
|
bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
|
|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
|
|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
|
|
bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
|
|
newline
|
|
bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
|
|
newline
|
|
bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
|
|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
|
|
newline
|
|
bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
|
|
newline
|
|
bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
|
|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
|
|
newline
|
|
bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
|
|
newline
|
|
bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
|
|
line.long 0xC "BRR,Baud rate register"
|
|
hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
|
|
line.long 0x10 "GTPR,Guard time and prescaler"
|
|
hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
|
|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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|
line.long 0x0 "RQR,Request register"
|
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
|
bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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|
newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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|
newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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|
newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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|
newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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|
rgroup.long 0x1C++0x3
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|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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|
newline
|
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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|
newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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|
newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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|
newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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|
newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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|
newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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|
line.long 0x0 "ICR,Interrupt flag clear register"
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|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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|
newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART3"
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base ad:0x40004800
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
|
newline
|
|
hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
|
newline
|
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
|
bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
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line.long 0x4 "CR2,Control register 2"
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|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
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bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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|
newline
|
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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|
newline
|
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
|
|
bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
|
|
newline
|
|
bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
|
|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
|
|
newline
|
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
|
|
bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
|
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
|
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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newline
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART4"
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base ad:0x40004C00
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
|
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
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group.long 0x0++0x17
|
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
|
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
|
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newline
|
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
|
|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
|
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newline
|
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
|
|
newline
|
|
bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
|
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newline
|
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
|
|
bitfld.long 0x0 12. "M0,Word length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
|
|
newline
|
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
|
|
newline
|
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
|
|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
|
|
newline
|
|
bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
|
|
newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
|
bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
|
|
newline
|
|
bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
|
|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
|
|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
|
|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
|
|
newline
|
|
bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
|
|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
|
|
newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
|
bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
|
|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
|
|
newline
|
|
bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
|
|
newline
|
|
bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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|
newline
|
|
bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
|
|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
|
|
newline
|
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
|
|
newline
|
|
bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
|
|
newline
|
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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|
newline
|
|
bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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newline
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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newline
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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newline
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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newline
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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newline
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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newline
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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newline
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART5"
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base ad:0x40005000
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
|
|
hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
|
|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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|
bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
|
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
|
|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
|
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
|
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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|
bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
|
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
|
|
bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
|
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
|
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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|
bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
|
|
line.long 0x4 "CR2,Control register 2"
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|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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|
newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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|
newline
|
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
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|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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|
newline
|
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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newline
|
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
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bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
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bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
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bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
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line.long 0x8 "CR3,Control register 3"
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bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
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bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
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bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
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bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
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bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
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bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
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bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
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bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
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line.long 0x14 "RTOR,Receiver timeout register"
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hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
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hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
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wgroup.long 0x18++0x3
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line.long 0x0 "RQR,Request register"
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bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
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bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
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bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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rgroup.long 0x1C++0x3
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line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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newline
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bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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newline
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
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bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
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bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
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newline
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bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
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bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
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bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
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bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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newline
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
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bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
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newline
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
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bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
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wgroup.long 0x20++0x3
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line.long 0x0 "ICR,Interrupt flag clear register"
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bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
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bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
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newline
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bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
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bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
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newline
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bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
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bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
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newline
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bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
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bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
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newline
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bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
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bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
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newline
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bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
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bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
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newline
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bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
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bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
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newline
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bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
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rgroup.long 0x24++0x3
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line.long 0x0 "RDR,Receive data register"
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hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
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group.long 0x28++0x7
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line.long 0x0 "TDR,Transmit data register"
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hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
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line.long 0x4 "PRESC,Prescaler register"
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hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
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tree.end
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tree "USART6"
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base ad:0x40013C00
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group.long 0x0++0x3
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line.long 0x0 "CR1_FIFO_ENABLED,Control register 1"
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bitfld.long 0x0 31. "RXFFIE,RXFIFO Full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when RXFF = 1 in the.."
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bitfld.long 0x0 30. "TXFEIE,TXFIFO empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFE = 1 in the.."
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newline
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXFNFIE,TXFIFO not full interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TXFNF =1 in.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXFNEIE,RXFIFO not empty interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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group.long 0x0++0x17
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line.long 0x0 "CR1_FIFO_DISABLED,Control register 1"
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bitfld.long 0x0 29. "FIFOEN,FIFO mode enable" "0: FIFO mode is disabled.,1: FIFO mode is enabled."
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bitfld.long 0x0 28. "M1,Word length" "0: 1 start bit,1: 1 start bit"
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newline
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bitfld.long 0x0 27. "EOBIE,End of Block interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the EOBF flag is.."
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|
bitfld.long 0x0 26. "RTOIE,Receiver timeout interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the RTOF bit is.."
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newline
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hexmask.long.byte 0x0 21.--25. 1. "DEAT,Driver Enable assertion time"
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hexmask.long.byte 0x0 16.--20. 1. "DEDT,Driver Enable deassertion time"
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newline
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bitfld.long 0x0 15. "OVER8,Oversampling mode" "0: Oversampling by 16,1: Oversampling by 8"
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|
bitfld.long 0x0 14. "CMIE,Character match interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when the CMF bit is.."
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newline
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bitfld.long 0x0 13. "MME,Mute mode enable" "0: Receiver in active mode permanently,1: Receiver can switch between Mute mode and active.."
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bitfld.long 0x0 12. "M0,Word length" "0,1"
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newline
|
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bitfld.long 0x0 11. "WAKE,Receiver wakeup method" "0: Idle line,1: Address mark"
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|
bitfld.long 0x0 10. "PCE,Parity control enable" "0: Parity control disabled,1: Parity control enabled"
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newline
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bitfld.long 0x0 9. "PS,Parity selection" "0: Even parity,1: Odd parity"
|
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bitfld.long 0x0 8. "PEIE,PE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever PE = 1 in the.."
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newline
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bitfld.long 0x0 7. "TXEIE,Transmit data register empty" "0: Interrupt inhibited,1: USART interrupt generated whenever TXE =1 in the.."
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bitfld.long 0x0 6. "TCIE,Transmission complete interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TC = 1 in the.."
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newline
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bitfld.long 0x0 5. "RXNEIE,Receive data register not empty" "0: Interrupt inhibited,1: USART interrupt generated whenever ORE = 1 or.."
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bitfld.long 0x0 4. "IDLEIE,IDLE interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever IDLE = 1 in.."
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newline
|
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bitfld.long 0x0 3. "TE,Transmitter enable" "0: Transmitter is disabled,1: Transmitter is enabled"
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bitfld.long 0x0 2. "RE,Receiver enable" "0: Receiver is disabled,1: Receiver is enabled and begins searching for a.."
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newline
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bitfld.long 0x0 1. "UESM,USART enable in low-power mode" "0: USART not able to wake up the MCU from low-power..,1: USART able to wake up the MCU from low-power.."
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bitfld.long 0x0 0. "UE,USART enable" "0: USART prescaler and outputs disabled low-power..,1: USART enabled"
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line.long 0x4 "CR2,Control register 2"
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|
hexmask.long.byte 0x4 24.--31. 1. "ADD,Address of the USART node"
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|
bitfld.long 0x4 23. "RTOEN,Receiver timeout enable" "0: Receiver timeout feature disabled.,1: Receiver timeout feature enabled."
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|
newline
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bitfld.long 0x4 21.--22. "ABRMOD,Auto baud rate mode" "0: Measurement of the start bit is used to detect..,1: Falling edge to falling edge measurement (the..,2: 0x7F frame detection.,3: 0x55 frame detection"
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|
bitfld.long 0x4 20. "ABREN,Auto baud rate enable" "0: Auto baud rate detection is disabled.,1: Auto baud rate detection is enabled."
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|
newline
|
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bitfld.long 0x4 19. "MSBFIRST,Most significant bit first" "0: data is transmitted/received with data bit 0..,1: data is transmitted/received with the MSB (bit.."
|
|
bitfld.long 0x4 18. "DATAINV,Binary data inversion" "0: Logical data from the data register are..,1: Logical data from the data register are.."
|
|
newline
|
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bitfld.long 0x4 17. "TXINV,TX pin active level inversion" "0: TX pin signal works using the standard logic..,1: TX pin signal values are inverted (VDD =0/mark.."
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|
bitfld.long 0x4 16. "RXINV,RX pin active level inversion" "0: RX pin signal works using the standard logic..,1: RX pin signal values are inverted (VDD =0/mark.."
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|
newline
|
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bitfld.long 0x4 15. "SWAP,Swap TX/RX pins" "0: TX/RX pins are used as defined in standard pinout,1: The TX and RX pins functions are swapped. This.."
|
|
bitfld.long 0x4 14. "LINEN,LIN mode enable" "0: LIN mode disabled,1: LIN mode enabled"
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|
newline
|
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bitfld.long 0x4 12.--13. "STOP,stop bits" "0: 1 stop bit,1: 0.5 stop bit.,2: 2 stop bits,3: 1.5 stop bits"
|
|
bitfld.long 0x4 11. "CLKEN,Clock enable" "0: SCLK pin disabled,1: SCLK pin enabled"
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|
newline
|
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bitfld.long 0x4 10. "CPOL,Clock polarity" "0: Steady low value on SCLK pin outside..,1: Steady high value on SCLK pin outside.."
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|
bitfld.long 0x4 9. "CPHA,Clock phase" "0: The first clock transition is the first data..,1: The second clock transition is the first data.."
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newline
|
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bitfld.long 0x4 8. "LBCL,Last bit clock pulse" "0: The clock pulse of the last data bit is not..,1: The clock pulse of the last data bit is output.."
|
|
bitfld.long 0x4 6. "LBDIE,LIN break detection interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever LBDF = 1 in.."
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|
newline
|
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bitfld.long 0x4 5. "LBDL,LIN break detection length" "0: 10-bit break detection,1: 11-bit break detection"
|
|
bitfld.long 0x4 4. "ADDM7,7-bit Address Detection/4-bit Address Detection" "0: 4-bit address detection,1: 7-bit address detection (in 8-bit data mode)"
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|
newline
|
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bitfld.long 0x4 3. "DIS_NSS,When the DIS_NSS bit is set the NSS pin input is ignored." "0: SPI slave selection depends on NSS input pin.,1: SPI slave is always selected and NSS input pin.."
|
|
bitfld.long 0x4 0. "SLVEN,Synchronous Slave mode enable" "0: Slave mode disabled.,1: Slave mode enabled."
|
|
line.long 0x8 "CR3,Control register 3"
|
|
bitfld.long 0x8 29.--31. "TXFTCFG,TXFIFO threshold configuration" "0: TXFIFO reaches 1/8 of its depth,1: TXFIFO reaches 1/4 of its depth,2: TXFIFO reaches 1/2 of its depth,3: TXFIFO reaches 3/4 of its depth,4: TXFIFO reaches 7/8 of its depth,5: TXFIFO becomes empty,?,?"
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|
bitfld.long 0x8 28. "RXFTIE,RXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when Receive FIFO.."
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|
newline
|
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bitfld.long 0x8 25.--27. "RXFTCFG,Receive FIFO threshold configuration" "0: Receive FIFO reaches 1/8 of its depth,1: Receive FIFO reaches 1/4 of its depth,2: Receive FIFO reaches 1/2 of its depth,3: Receive FIFO reaches 3/4 of its depth,4: Receive FIFO reaches 7/8 of its depth,5: Receive FIFO becomes full,?,?"
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bitfld.long 0x8 24. "TCBGTIE,Transmission Complete before guard time interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever TCBGT=1 in.."
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|
newline
|
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bitfld.long 0x8 23. "TXFTIE,TXFIFO threshold interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated when TXFIFO reaches.."
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|
bitfld.long 0x8 22. "WUFIE,Wakeup from low-power mode interrupt enable" "0: Interrupt inhibited,1: USART interrupt generated whenever WUF = 1 in.."
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|
newline
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bitfld.long 0x8 20.--21. "WUS,Wakeup from low-power mode interrupt flag selection" "0: WUF active on address match (as defined by..,?,2: WUF active on start bit detection,3: WUF active on RXNE/RXFNE."
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bitfld.long 0x8 17.--19. "SCARCNT,Smartcard auto-retry count" "0: retransmission disabled - No automatic..,1: number of automatic retransmission attempts..,2: number of automatic retransmission attempts..,3: number of automatic retransmission attempts..,4: number of automatic retransmission attempts..,5: number of automatic retransmission attempts..,6: number of automatic retransmission attempts..,7: number of automatic retransmission attempts.."
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newline
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bitfld.long 0x8 15. "DEP,Driver enable polarity selection" "0: DE signal is active high.,1: DE signal is active low."
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bitfld.long 0x8 14. "DEM,Driver enable mode" "0: DE function is disabled.,1: DE function is enabled. The DE signal is output.."
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newline
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bitfld.long 0x8 13. "DDRE,DMA Disable on Reception Error" "0: DMA is not disabled in case of reception error.,1: DMA is disabled following a reception error. The.."
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|
bitfld.long 0x8 12. "OVRDIS,Overrun Disable" "0: Overrun Error Flag ORE is set when received data..,1: Overrun functionality is disabled. If new data.."
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|
newline
|
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bitfld.long 0x8 11. "ONEBIT,One sample bit method enable" "0: Three sample bit method,1: One sample bit method"
|
|
bitfld.long 0x8 10. "CTSIE,CTS interrupt enable" "0: Interrupt is inhibited,1: An interrupt is generated whenever CTSIF = 1 in.."
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|
newline
|
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bitfld.long 0x8 9. "CTSE,CTS enable" "0: CTS hardware flow control disabled,1: CTS mode enabled data is only transmitted when.."
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|
bitfld.long 0x8 8. "RTSE,RTS enable" "0: RTS hardware flow control disabled,1: RTS output enabled data is only requested when.."
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|
newline
|
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bitfld.long 0x8 7. "DMAT,DMA enable transmitter" "0: DMA mode is disabled for transmission,1: DMA mode is enabled for transmission"
|
|
bitfld.long 0x8 6. "DMAR,DMA enable receiver" "0: DMA mode is disabled for reception,1: DMA mode is enabled for reception"
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|
newline
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bitfld.long 0x8 5. "SCEN,Smartcard mode enable" "0: Smartcard Mode disabled,1: Smartcard Mode enabled"
|
|
bitfld.long 0x8 4. "NACK,Smartcard NACK enable" "0: NACK transmission in case of parity error is..,1: NACK transmission during parity error is enabled"
|
|
newline
|
|
bitfld.long 0x8 3. "HDSEL,Half-duplex selection" "0: Half duplex mode is not selected,1: Half duplex mode is selected"
|
|
bitfld.long 0x8 2. "IRLP,IrDA low-power" "0: Normal mode,1: Low-power mode"
|
|
newline
|
|
bitfld.long 0x8 1. "IREN,IrDA mode enable" "0: IrDA disabled,1: IrDA enabled"
|
|
bitfld.long 0x8 0. "EIE,Error interrupt enable" "0: Interrupt inhibited,1: interrupt generated when FE = 1 or ORE = 1 or NE.."
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|
line.long 0xC "BRR,Baud rate register"
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hexmask.long.word 0xC 0.--15. 1. "BRR,USART baud rate"
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|
line.long 0x10 "GTPR,Guard time and prescaler"
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hexmask.long.byte 0x10 8.--15. 1. "GT,Guard time value"
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|
hexmask.long.byte 0x10 0.--7. 1. "PSC,Prescaler value"
|
|
line.long 0x14 "RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "BLEN,Block Length"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "RTO,Receiver timeout value"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x0 "RQR,Request register"
|
|
bitfld.long 0x0 4. "TXFRQ,Transmit data flush request" "0,1"
|
|
bitfld.long 0x0 3. "RXFRQ,Receive data flush request" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "MMRQ,Mute mode request" "0,1"
|
|
bitfld.long 0x0 1. "SBKRQ,Send break request" "0,1"
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newline
|
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bitfld.long 0x0 0. "ABRRQ,Auto baud rate request" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_ENABLED,Interrupt & status"
|
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bitfld.long 0x0 27. "TXFT,TXFIFO threshold flag" "0: TXFIFO does not reach the programmed threshold.,1: TXFIFO reached the programmed threshold."
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|
bitfld.long 0x0 26. "RXFT,RXFIFO threshold flag" "0: Receive FIFO does not reach the programmed..,1: Receive FIFO reached the programmed threshold."
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newline
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bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
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|
bitfld.long 0x0 24. "RXFF,RXFIFO full" "0: RXFIFO not full.,1: RXFIFO Full."
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|
newline
|
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bitfld.long 0x0 23. "TXFE,TXFIFO empty" "0: TXFIFO not empty.,1: TXFIFO empty."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
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newline
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bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
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|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
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newline
|
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bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
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|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
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newline
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bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
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|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
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newline
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bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
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bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
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|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
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|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
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|
newline
|
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bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
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newline
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bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
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bitfld.long 0x0 7. "TXFNF,TXFIFO not full" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
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|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
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newline
|
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bitfld.long 0x0 5. "RXFNE,RXFIFO not empty" "0: Data is not received,1: Received data is ready to be read."
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|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
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|
newline
|
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bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
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bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "ISR_FIFO_DISABLED,Interrupt & status"
|
|
bitfld.long 0x0 25. "TCBGT,Transmission complete before guard time flag" "0: Transmission is not complete or transmission is..,1: Transmission is complete successfully (before.."
|
|
bitfld.long 0x0 22. "REACK,Receive enable acknowledge flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TEACK,Transmit enable acknowledge flag" "0,1"
|
|
bitfld.long 0x0 20. "WUF,Wakeup from low-power mode flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RWU,Receiver wakeup from Mute mode" "0: Receiver in active mode,1: Receiver in Mute mode"
|
|
bitfld.long 0x0 18. "SBKF,Send break flag" "0: Break character transmitted,1: Break character requested by setting SBKRQ bit.."
|
|
newline
|
|
bitfld.long 0x0 17. "CMF,Character match flag" "0: No Character match detected,1: Character Match detected"
|
|
bitfld.long 0x0 16. "BUSY,Busy flag" "0: USART is idle (no reception),1: Reception on going"
|
|
newline
|
|
bitfld.long 0x0 15. "ABRF,Auto baud rate flag" "0,1"
|
|
bitfld.long 0x0 14. "ABRE,Auto baud rate error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDR,SPI slave underrun error flag" "0: No underrun error,1: underrun error"
|
|
bitfld.long 0x0 12. "EOBF,End of block flag" "0: End of Block not reached,1: End of Block (number of characters) reached"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOF,Receiver timeout" "0: Timeout value not reached,1: Timeout value reached without any data reception"
|
|
bitfld.long 0x0 10. "CTS,CTS flag" "0: nCTS line set,1: nCTS line reset"
|
|
newline
|
|
bitfld.long 0x0 9. "CTSIF,CTS interrupt flag" "0: No change occurred on the nCTS status line,1: A change occurred on the nCTS status line"
|
|
bitfld.long 0x0 8. "LBDF,LIN break detection flag" "0: LIN Break not detected,1: LIN break detected"
|
|
newline
|
|
bitfld.long 0x0 7. "TXE,Transmit data register empty" "0: Data register full,1: Data register not full"
|
|
bitfld.long 0x0 6. "TC,Transmission complete" "0: Transmission is not complete,1: Transmission is complete"
|
|
newline
|
|
bitfld.long 0x0 5. "RXNE,Read data register not empty" "0: Data is not received,1: Received data is ready to be read."
|
|
bitfld.long 0x0 4. "IDLE,Idle line detected" "0: No Idle line is detected,1: Idle line is detected"
|
|
newline
|
|
bitfld.long 0x0 3. "ORE,Overrun error" "0: No overrun error,1: Overrun error is detected"
|
|
bitfld.long 0x0 2. "NE,Noise detection flag" "0: No noise is detected,1: Noise is detected"
|
|
newline
|
|
bitfld.long 0x0 1. "FE,Framing error" "0: No Framing error is detected,1: Framing error or break character is detected"
|
|
bitfld.long 0x0 0. "PE,Parity error" "0: No parity error,1: Parity error"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x0 "ICR,Interrupt flag clear register"
|
|
bitfld.long 0x0 20. "WUCF,Wakeup from low-power mode clear flag" "0,1"
|
|
bitfld.long 0x0 17. "CMCF,Character match clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "UDRCF,SPI slave underrun clear flag" "0,1"
|
|
bitfld.long 0x0 12. "EOBCF,End of block clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RTOCF,Receiver timeout clear flag" "0,1"
|
|
bitfld.long 0x0 9. "CTSCF,CTS clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LBDCF,LIN break detection clear flag" "0,1"
|
|
bitfld.long 0x0 7. "TCBGTCF,Transmission complete before Guard time clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TCCF,Transmission complete clear flag" "0,1"
|
|
bitfld.long 0x0 5. "TXFECF,TXFIFO empty clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "IDLECF,Idle line detected clear flag" "0,1"
|
|
bitfld.long 0x0 3. "ORECF,Overrun error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "NECF,Noise detected clear flag" "0,1"
|
|
bitfld.long 0x0 1. "FECF,Framing error clear flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PECF,Parity error clear flag" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "RDR,Receive data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "RDR,Receive data value"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TDR,Transmit data register"
|
|
hexmask.long.word 0x0 0.--8. 1. "TDR,Transmit data value"
|
|
line.long 0x4 "PRESC,Prescaler register"
|
|
hexmask.long.byte 0x4 0.--3. 1. "PRESCALER,Clock prescaler"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32G0B0*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "USB (Universal Serial Bus Full-Speed Host/Device Interface)"
|
|
base ad:0x40005C00
|
|
group.long 0x0++0x1F
|
|
line.long 0x0 "USB_CHEP0R,USB endpoint/channel 0 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x0 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x0 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x0 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x0 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x0 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x0 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x0 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x0 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x4 "USB_CHEP1R,USB endpoint/channel 1 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x4 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x4 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x4 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x4 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x4 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x4 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x4 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x4 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x4 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x4 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x4 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x8 "USB_CHEP2R,USB endpoint/channel 2 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x8 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x8 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x8 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x8 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x8 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x8 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x8 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x8 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x8 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x8 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x8 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0xC "USB_CHEP3R,USB endpoint/channel 3 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0xC 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0xC 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0xC 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0xC 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0xC 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0xC 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0xC 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0xC 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0xC 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0xC 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0xC 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0xC 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0xC 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x10 "USB_CHEP4R,USB endpoint/channel 4 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x10 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x10 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x10 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x10 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x10 24. "LS_EP,Low speed endpoint" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x10 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x10 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x10 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x10 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x10 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x10 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x10 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x10 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x14 "USB_CHEP5R,USB endpoint/channel 5 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x14 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x14 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x14 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x14 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24. "LS_EP,Low speed endpoint host with HUB only" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x14 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x14 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x14 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x14 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x14 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x14 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x14 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x14 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x14 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x18 "USB_CHEP6R,USB endpoint/channel 6 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x18 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x18 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x18 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x18 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24. "LS_EP,Low speed endpoint host with HUB only" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x18 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x18 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x18 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x18 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x18 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x18 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x18 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x18 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x18 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x18 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x18 0.--3. 1. "EA,endpoint/channel address"
|
|
line.long 0x1C "USB_CHEP7R,USB endpoint/channel 7 register"
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x1C 29.--30. "THREE_ERR_RX,Three errors for an IN transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
bitfld.long 0x1C 27.--28. "THREE_ERR_TX,Three errors for an OUT or SETUP transaction" "0: Less than 3 errors received.,1: More than 3 errors received last error is..,2: More than 3 errors received last error is data..,3: More than 3 errors received last error is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x1C 26. "ERR_RX,Received error for an IN transaction" "0,1"
|
|
bitfld.long 0x1C 25. "ERR_TX,Received error for an OUT/SETUP transaction" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 24. "LS_EP,Low speed endpoint host with HUB only" "0: Full speed endpoint,1: Low speed endpoint"
|
|
bitfld.long 0x1C 23. "NAK,Host mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x1C 16.--22. 1. "DEVADDR,Host mode"
|
|
bitfld.long 0x1C 15. "VTRX,USB valid transaction received" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 14. "DTOGRX,Data Toggle for reception transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x1C 12.--13. "STATRX,Status bits for reception transfers" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x1C 11. "SETUP,Setup transaction completed" "0,1"
|
|
bitfld.long 0x1C 9.--10. "UTYPE,USB type of transaction" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x1C 8. "EPKIND,endpoint/channel kind" "0,1"
|
|
bitfld.long 0x1C 7. "VTTX,Valid USB transaction transmitted" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 6. "DTOGTX,Data toggle for transmission transfers" "0: DATA0,1: DATA1"
|
|
bitfld.long 0x1C 4.--5. "STATTX,Status bits for transmission transfers" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "EA,endpoint/channel address"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "USB_CNTR,"
|
|
bitfld.long 0x0 31. "HOST,HOST mode" "0: USB Device function,1: USB host function"
|
|
bitfld.long 0x0 16. "THR512M,512 byte threshold interrupt mask" "0: 512 byte threshold interrupt disabled,1: 512 byte threshold interrupt enabled"
|
|
newline
|
|
bitfld.long 0x0 15. "CTRM,Correct transfer interrupt mask" "0: Correct transfer (CTR) interrupt disabled.,1: CTR interrupt enabled an interrupt request is.."
|
|
bitfld.long 0x0 14. "PMAOVRM,Packet memory area over / underrun interrupt mask" "0: PMAOVR interrupt disabled.,1: PMAOVR interrupt enabled an interrupt request is.."
|
|
newline
|
|
bitfld.long 0x0 13. "ERRM,Error interrupt mask" "0: ERR interrupt disabled.,1: ERR interrupt enabled an interrupt request is.."
|
|
bitfld.long 0x0 12. "WKUPM,Wakeup interrupt mask" "0: WKUP interrupt disabled.,1: WKUP interrupt enabled an interrupt request is.."
|
|
newline
|
|
bitfld.long 0x0 11. "SUSPM,Suspend mode interrupt mask" "0: Suspend mode request (SUSP) interrupt disabled.,1: SUSP interrupt enabled an interrupt request is.."
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 10. "RST_DCONM,USB reset request (Device mode) or device connect/disconnect (Host mode) interrupt mask" "0: RESET interrupt disabled.,1: RESET interrupt enabled an interrupt request is.."
|
|
newline
|
|
bitfld.long 0x0 5. "L1RES,L1 remote wakeup / resume driver Device mode" "0: No effect,1: Send 50 remote-wakeup signaling to host"
|
|
bitfld.long 0x0 4. "L2RES,L2 remote wakeup / resume driver" "0: No effect,1: Send L2 resume signaling to device"
|
|
newline
|
|
bitfld.long 0x0 3. "SUSPEN,Suspend state enable" "0: No effect.,1: Enter L1/L2 suspend"
|
|
bitfld.long 0x0 0. "USBRST,USB Reset" "0: No effect,1: USB core is under reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 10. "RESETM,USB reset interrupt mask" "0: RESET Interrupt disabled.,1: RESET Interrupt enabled an interrupt request is.."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 10. "RESETM,USB reset interrupt mask" "0: RESET Interrupt disabled.,1: RESET Interrupt enabled an interrupt request is.."
|
|
newline
|
|
endif
|
|
bitfld.long 0x0 9. "SOFM,Start of frame interrupt mask" "0: SOF interrupt disabled.,1: SOF interrupt enabled an interrupt request is.."
|
|
bitfld.long 0x0 8. "ESOFM,Expected start of frame interrupt mask" "0: Expected start of frame (ESOF) interrupt disabled.,1: ESOF interrupt enabled an interrupt request is.."
|
|
newline
|
|
bitfld.long 0x0 7. "L1REQM,LPM L1 state request interrupt mask" "0: LPM L1 state request (L1REQ) interrupt disabled.,1: L1REQ interrupt enabled an interrupt request is.."
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 5. "L1RESUME,L1 Remote Wakeup / Resume driver" "0: No effect,1: Send 50us remote-wakeup signaling to host"
|
|
newline
|
|
bitfld.long 0x0 4. "L2RESUME,L2 Remote Wakeup / Resume driver" "0: No effect,1: Send L2 resume signaling to device"
|
|
bitfld.long 0x0 3. "SUSPEN,Suspend state enable" "0: No effect.,1: Enter L1/L2 suspend"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 5. "L1RESUME,L1 Remote Wakeup / Resume driver" "0: No effect,1: Send L1 resume signaling to device"
|
|
newline
|
|
bitfld.long 0x0 4. "L2RESUME,L2 Remote Wakeup / Resume driver" "0: No effect,1: Send L2 resume signaling to device"
|
|
bitfld.long 0x0 3. "SUSPEN,Suspend state enable" "0: No effect.,1: Enter L1/L2 suspend"
|
|
newline
|
|
endif
|
|
rbitfld.long 0x0 2. "SUSPRDY,Suspend state effective" "0: Normal operation,1: Suspend state"
|
|
newline
|
|
bitfld.long 0x0 1. "PDWN,Power down" "0: Exit power down.,1: Enter power down mode."
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 0. "USBRST,USB Reset" "0: No effect,1: USB core is under reset"
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 0. "USBRST,USB Reset" "0: No effect,1: USB core is under reset"
|
|
endif
|
|
line.long 0x4 "USB_ISTR,USB interrupt status register"
|
|
rbitfld.long 0x4 30. "LS_DCON,Low speed device connected" "0,1"
|
|
rbitfld.long 0x4 29. "DCON_STAT,Device connection status" "0: No device connected,1: FS or LS device connected to the host"
|
|
newline
|
|
bitfld.long 0x4 16. "THR512,512 byte threshold interrupt" "0,1"
|
|
rbitfld.long 0x4 15. "CTR,Completed transfer in host mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "PMAOVR,Packet memory area over / underrun" "0,1"
|
|
bitfld.long 0x4 13. "ERR,Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "WKUP,Wakeup" "0,1"
|
|
bitfld.long 0x4 11. "SUSP,Suspend mode request" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "RST_DCON,USB reset request (Device mode) or device connect/disconnect (Host mode)" "0,1"
|
|
bitfld.long 0x4 9. "SOF,Start of frame" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "ESOF,Expected start of frame" "0,1"
|
|
bitfld.long 0x4 7. "L1REQ,LPM L1 state request" "0,1"
|
|
newline
|
|
rbitfld.long 0x4 4. "DIR,Direction of transaction" "0,1"
|
|
hexmask.long.byte 0x4 0.--3. 1. "IDN,Device Endpoint / host channel identification number"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "USB_FNR,USB frame number register"
|
|
bitfld.long 0x0 15. "RXDP,Receive data + line status" "0,1"
|
|
bitfld.long 0x0 14. "RXDM,Receive data - line status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LCK,Locked" "0,1"
|
|
bitfld.long 0x0 11.--12. "LSOF,Lost SOF" "0,1,2,3"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "FN,Frame number"
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "USB_DADDR,"
|
|
bitfld.long 0x0 7. "EF,Enable function" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "ADD,Device address"
|
|
group.long 0x54++0x7
|
|
line.long 0x0 "USB_LPMCSR,"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BESL,BESL value"
|
|
rbitfld.long 0x0 3. "REMWAKE,bRemoteWake value" "0,1"
|
|
newline
|
|
sif (cpuis("STM32G0B0*"))
|
|
bitfld.long 0x0 1. "LPMACK,LPM token acknowledge enable" "0: the valid LPM token is NYET.,1: the valid LPM token is ACK."
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
bitfld.long 0x0 1. "LPMACK,LPM Token acknowledge enable" "0: the valid LPM Token will be NYET.,1: the valid LPM Token will be ACK."
|
|
newline
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
bitfld.long 0x0 1. "LPMACK,LPM Token acknowledge enable" "0: the valid LPM Token will be NYET.,1: the valid LPM Token will be ACK."
|
|
endif
|
|
bitfld.long 0x0 0. "LPMEN,LPM support enable" "0,1"
|
|
line.long 0x4 "USB_BCDR,"
|
|
bitfld.long 0x4 15. "DPPU_DPD,DP pull-up / DPDM pull-down" "0,1"
|
|
rbitfld.long 0x4 7. "PS2DET,DM pull-up detection status" "0: Normal port detected (connected to SDP ACA CDP..,1: PS2 port or proprietary charger detected."
|
|
newline
|
|
rbitfld.long 0x4 6. "SDET,Secondary detection (SD) status" "0: CDP detected.,1: DCP detected."
|
|
rbitfld.long 0x4 5. "PDET,Primary detection (PD) status" "0: no BCD support detected (connected to SDP or..,1: BCD support detected (connected to ACA CDP or.."
|
|
newline
|
|
rbitfld.long 0x4 4. "DCDET,Data contact detection (DCD) status" "0: data lines contact not detected.,1: data lines contact detected."
|
|
bitfld.long 0x4 3. "SDEN,Secondary detection (SD) mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "PDEN,Primary detection (PD) mode enable" "0,1"
|
|
bitfld.long 0x4 1. "DCDEN,Data contact detection (DCD) mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "BCDEN,Battery charging detector (BCD) enable" "0,1"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*")||cpuis("STM32G051*")||cpuis("STM32G061*")||cpuis("STM32G071*")||cpuis("STM32G081*")||cpuis("STM32G0B0*")||cpuis("STM32G0B1*")||cpuis("STM32G0C1*"))
|
|
tree "VREFBUF (Voltage Reference Buffer)"
|
|
base ad:0x40010030
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CSR,VREFBUF control and status"
|
|
bitfld.long 0x0 4.--6. "VRS,Voltage reference scale These bits" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode This bit controls" "0,1"
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0,1"
|
|
line.long 0x4 "CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code These bits are"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "VREFBUF_CSR,VREFBUF control and status"
|
|
rbitfld.long 0x0 3. "VRR,Voltage reference buffer ready" "0: the voltage reference buffer output is not ready.,1: the voltage reference buffer output reached the.."
|
|
bitfld.long 0x0 2. "VRS,Voltage reference scale" "0: Voltage reference set to VREF_OUT1 (around 2.048..,1: Voltage reference set to VREF_OUT2 (around 2.5.."
|
|
newline
|
|
bitfld.long 0x0 1. "HIZ,High impedance mode" "0: VREF+ pin is internally connected to the voltage..,1: VREF+ pin is high impedance."
|
|
bitfld.long 0x0 0. "ENVR,Voltage reference buffer mode enable" "0: Internal voltage reference mode disable..,1: Internal voltage reference mode (reference.."
|
|
line.long 0x4 "VREFBUF_CCR,VREFBUF calibration control"
|
|
hexmask.long.byte 0x4 0.--5. 1. "TRIM,Trimming code"
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "WWDG (System Window Watchdog)"
|
|
base ad:0x40002C00
|
|
sif (cpuis("STM32G030*")||cpuis("STM32G031*")||cpuis("STM32G041*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G050*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "WWDG_CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "WWDG_CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK Counter Clock (PCLK div 4096) div 1,1: CK Counter Clock (PCLK div 4096) div 2,2: CK Counter Clock (PCLK div 4096) div 4,3: CK Counter Clock (PCLK div 4096) div 8,4: CK Counter Clock (PCLK div 4096) div 16,5: CK Counter Clock (PCLK div 4096) div 32,6: CK Counter Clock (PCLK div 4096) div 64,7: CK Counter Clock (PCLK div 4096) div 128"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "WWDG_SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G051*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "WWDG_CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "WWDG_CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK Counter Clock (PCLK div 4096) div 1,1: CK Counter Clock (PCLK div 4096) div 2,2: CK Counter Clock (PCLK div 4096) div 4,3: CK Counter Clock (PCLK div 4096) div 8,4: CK Counter Clock (PCLK div 4096) div 16,5: CK Counter Clock (PCLK div 4096) div 32,6: CK Counter Clock (PCLK div 4096) div 64,7: CK Counter Clock (PCLK div 4096) div 128"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "WWDG_SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G061*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "WWDG_CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "WWDG_CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK Counter Clock (PCLK div 4096) div 1,1: CK Counter Clock (PCLK div 4096) div 2,2: CK Counter Clock (PCLK div 4096) div 4,3: CK Counter Clock (PCLK div 4096) div 8,4: CK Counter Clock (PCLK div 4096) div 16,5: CK Counter Clock (PCLK div 4096) div 32,6: CK Counter Clock (PCLK div 4096) div 64,7: CK Counter Clock (PCLK div 4096) div 128"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "WWDG_SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G070*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G071*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G081*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B0*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "WWDG_CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "WWDG_CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK Counter Clock (PCLK div 4096) div 1,1: CK Counter Clock (PCLK div 4096) div 2,2: CK Counter Clock (PCLK div 4096) div 4,3: CK Counter Clock (PCLK div 4096) div 8,4: CK Counter Clock (PCLK div 4096) div 16,5: CK Counter Clock (PCLK div 4096) div 32,6: CK Counter Clock (PCLK div 4096) div 64,7: CK Counter Clock (PCLK div 4096) div 128"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "WWDG_SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0B1*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "WWDG_CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "WWDG_CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK Counter Clock (PCLK div 4096) div 1,1: CK Counter Clock (PCLK div 4096) div 2,2: CK Counter Clock (PCLK div 4096) div 4,3: CK Counter Clock (PCLK div 4096) div 8,4: CK Counter Clock (PCLK div 4096) div 16,5: CK Counter Clock (PCLK div 4096) div 32,6: CK Counter Clock (PCLK div 4096) div 64,7: CK Counter Clock (PCLK div 4096) div 128"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "WWDG_SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("STM32G0C1*"))
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "WWDG_CR,Control register"
|
|
bitfld.long 0x0 7. "WDGA,Activation bit" "0: Watchdog disabled,1: Watchdog enabled"
|
|
hexmask.long.byte 0x0 0.--6. 1. "T,7-bit counter (MSB to LSB)"
|
|
line.long 0x4 "WWDG_CFR,Configuration register"
|
|
bitfld.long 0x4 11.--13. "WDGTB,Timer base" "0: CK Counter Clock (PCLK div 4096) div 1,1: CK Counter Clock (PCLK div 4096) div 2,2: CK Counter Clock (PCLK div 4096) div 4,3: CK Counter Clock (PCLK div 4096) div 8,4: CK Counter Clock (PCLK div 4096) div 16,5: CK Counter Clock (PCLK div 4096) div 32,6: CK Counter Clock (PCLK div 4096) div 64,7: CK Counter Clock (PCLK div 4096) div 128"
|
|
bitfld.long 0x4 9. "EWI,Early wakeup interrupt" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "W,7-bit window value"
|
|
line.long 0x8 "WWDG_SR,Status register"
|
|
bitfld.long 0x8 0. "EWIF,Early wakeup interrupt" "0,1"
|
|
endif
|
|
tree.end
|
|
AUTOINDENT.OFF
|