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Gen4_R-Car_Trace32/2_Trunk/perpsoc4000t.per
woody d411edd9b4 add Trace32 File
2025-10-14 09:52:32 +09:00

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; --------------------------------------------------------------------------------
; @Title: PSoC4000T On-Chip Peripherals
; @Props: Released
; @Author: NEJ
; @Changelog: 2024-01-15 NEJ
; @Manufacturer: INFINEON - Infineon Technologies AG
; @Doc: Generated (TRACE32, build: 165992.), based on:
; psoc4000t.svd (Ver. 1.0)
; @Core: Cortex-M0+
; @Chip: CY8C4025LQI-T412, CY8C4025LQI-T411, CY8C4025FNI-T412T, CY8C4045LQI-T412,
; CY8C4045LQI-T411, CY8C4045FNI-T412T, CY8C4026LQI-T412, CY8C4026LQI-T411,
; CY8C4026FNI-T412T, CY8C4046LQI-T412, CY8C4046LQI-T411, CY8C4046FNI-T412T,
; CY8C4046LQI-T452, CY8C4046LQI-T451, CY8C4046FNI-T452T
; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: perpsoc4000t.per 17354 2024-01-19 12:59:06Z kwisniewski $
AUTOINDENT.ON CENTER TREE
ENUMDELIMITER ","
base ad:0x0
tree.close "Core Registers (Cortex-M0+)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0x8
if (CORENAME()=="CORTEXM1")
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
else
group.long 0x10++0x0b
line.long 0x00 "STCSR,SysTick Control and Status Register"
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
textline " "
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
line.long 0x04 "STRVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
line.long 0x08 "STCVR,SysTick Current Value Register"
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
endif
if (CORENAME()=="CORTEXM1")
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
else
rgroup.long 0x1c++0x03
line.long 0x00 "STCR,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
textline " "
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
endif
rgroup.long 0xd00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
textline " "
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
group.long 0xd04++0x03
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
textline " "
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
textline " "
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
textline " "
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
textline " "
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
if (CORENAME()=="CORTEXM0+")
group.long 0xd08++0x03
line.long 0x00 "VTOR,Vector Table Offset Register"
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
else
textline " "
endif
group.long 0xd0c++0x03
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
textline " "
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
group.long 0xd10++0x03
line.long 0x00 "SCR,System Control Register"
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
textline " "
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
rgroup.long 0xd14++0x03
line.long 0x00 "CCR,Configuration and Control Register"
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
group.long 0xd1c++0x0b
line.long 0x00 "SHPR2,System Handler Priority Register 2"
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
line.long 0x04 "SHPR3,System Handler Priority Register 3"
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
line.long 0x08 "SHCSR,System Handler Control and State Register"
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
if (CORENAME()=="CORTEXM0+")
hgroup.long 0x08++0x03
hide.long 0x00 "ACTLR,Auxiliary Control Register"
else
textline " "
endif
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit (MPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline " "
textline " "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline " "
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
textline " "
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline " "
textline " "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller (NVIC)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
tree "Interrupt Enable Registers"
group.long 0x100++0x03
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
tree.end
tree "Interrupt Pending Registers"
group.long 0x200++0x03
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline " "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
tree.end
width 6.
tree "Interrupt Priority Registers"
group.long 0x400++0x1F
line.long 0x00 "INT0,Interrupt Priority Register"
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
line.long 0x04 "INT1,Interrupt Priority Register"
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
line.long 0x08 "INT2,Interrupt Priority Register"
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
line.long 0x0C "INT3,Interrupt Priority Register"
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
line.long 0x10 "INT4,Interrupt Priority Register"
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
line.long 0x14 "INT5,Interrupt Priority Register"
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
line.long 0x18 "INT6,Interrupt Priority Register"
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
line.long 0x1C "INT7,Interrupt Priority Register"
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 0xA
group.long 0xD30++0x03
line.long 0x00 "DFSR,Data Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
textline " "
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
textline " "
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
if (CORENAME()=="CORTEXM1")
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
else
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
textline " "
textfld " "
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
else
group.long 0xDF0++0x03
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
textline " "
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
textline " "
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
textline " "
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
textline " "
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
textline " "
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
endif
endif
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Selector Register"
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
group.long 0xDF8++0x07
line.long 0x00 "DCRDR,Debug Core Register Data Register"
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
textline " "
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Breakpoint Unit (BPU)"
sif COMPonent.AVAILABLE("BPU")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
width 8.
group.long 0x00++0x03
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
group.long 0x8++0x03
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
group.long 0xC++0x03
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
group.long 0x10++0x03
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
group.long 0x14++0x03
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
else
newline
textline "BPU component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 14.
rgroup.long 0x00++0x03
line.long 0x00 "DW_CTRL,DW Control Register "
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x1c++0x03
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
group.long 0x20++0x0b
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
line.long 0x04 "DW_MASK0,DW Mask Register 0"
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
group.long 0x30++0x0b
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
tree "CPUSS (CPU Sub System)"
base ad:0x40100000
group.long 0x0++0x2B
line.long 0x0 "CONFIG,Configuration register"
bitfld.long 0x0 0. "VECT_IN_RAM,0': Vector Table is located at 0x0000:0000 in flash" "0: 0000 in flash,1: Vector Table is located at"
line.long 0x4 "SYSREQ,SYSCALL control register"
bitfld.long 0x4 31. "SYSCALL_REQ,CPU/DAP writes a '1' to this field to request a SystemCall. The HMASTER_0 field indicates the source of the write access. Setting this field to '1' immediate results in a NMI. The SystemCall NMI interrupt handler sets this field to '0' after.." "0,1"
rbitfld.long 0x4 30. "HMASTER_0,Indicates the source of the write access to the SYSREQ register." "0: the current source of write access is captured,1: the previous value"
newline
rbitfld.long 0x4 29. "ROM_ACCESS_EN,Indicates that executing from Boot ROM is enabled. HW sets this field to '1' on reset or when the SystemCall NMI vector is fetched from Boot ROM. HW sets this field to '0' when the CPU is NOT executing from either Boot or System ROM. This.." "0,1"
bitfld.long 0x4 28. "PRIVILEGED,Indicates whether the system is in privileged ('1') or user mode ('0'). Only CPU SW executing from ROM can set this field to '1' when ROM_ACCESS_EN is '1' (the CPU is executing a SystemCall NMI interrupt handler). Any other write to this field.." "0,1"
newline
bitfld.long 0x4 27. "DIS_RESET_VECT_REL,Disable Reset Vector fetch relocation:" "0: 0007 are made to flash,1: CPU accesses to locations"
hexmask.long.word 0x4 0.--15. 1. "SYSCALL_COMMAND,Opcode of the system call being requested."
line.long 0x8 "SYSARG,SYSARG control register"
hexmask.long 0x8 0.--31. 1. "SYSCALL_ARG,Argument to System Call specified in SYSREQ. Semantics of argument depends on system call made. Typically a pointer to a parameter block."
line.long 0xC "PROTECTION,Protection control register"
bitfld.long 0xC 31. "PROTECTION_LOCK,Setting this field will block (ignore) any further writes to the PROTECTION_MODE field in this register. Once '1' this field cannot be cleared." "0,1"
bitfld.long 0xC 30. "FLASH_LOCK,Setting this bit will force SPCIF.ADDRESS.AXA to be ignored which prevents SM Flash from being erased or overwritten. It is used to indicate the DEAD protection mode. Writes to this field are ignored when PROTECTION_LOCK is '1'" "0,1"
newline
hexmask.long.byte 0xC 0.--3. 1. "PROTECTION_MODE,Current protection mode; this field is available as a global signal everywhere in the system. Writes to this field are ignored when PROTECTION_LOCK is '1':"
line.long 0x10 "PRIV_ROM,ROM privilege register"
hexmask.long.word 0x10 16.--25. 1. "SROM_PROT_LIMIT,Indicates the limit where the privileged area of System ROM partition starts in increments of 256 Bytes. The limit is wrt. the start of the ROM memory (start of the Boot ROM partition)."
hexmask.long.byte 0x10 0.--7. 1. "BROM_PROT_LIMIT,Indicates the limit where the privileged area of the Boot ROM partition starts in increments of 256 Bytes."
line.long 0x14 "PRIV_RAM,RAM privilege register"
hexmask.long.word 0x14 0.--8. 1. "RAM_PROT_LIMIT,Indicates the limit where the privileged area of SRAM starts in increments of 256 Bytes."
line.long 0x18 "PRIV_FLASH,Flash privilege register"
hexmask.long.word 0x18 0.--11. 1. "FLASH_PROT_LIMIT,Indicates the limit where the privileged area of flash starts in increments of 256 Bytes."
line.long 0x1C "WOUNDING,Wounding register"
bitfld.long 0x1C 24.--26. "RAM1_WOUND,Wounding of RAM 1 (see description of RAM_WOUND)." "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 20.--22. "FLASH_WOUND,Indicates the amount of accessible flash in this part. The value in this field is effectively write-once (it is only possible to set bits not clear them). The remainder portion of flash is not accessible and will return an AHB-Lite bus error." "0: entire memory accessible,1: first 1/2 of the memory accessible,2: first 1/4 of the memory accessible,3: first 1/8 of the memory accessible,4: first 1/16 of the memory accessible,5: first 1/32 of the memory accessible,6: first 1/64 of the memory accessible,7: first 1/128 of the memory accessible"
newline
bitfld.long 0x1C 16.--18. "RAM_WOUND,Indicates the amount of accessible RAM 0 memory capacity in this part. The value in this field is effectively write-once (it is only possible to set bits not clear them). The remainder portion of SRAM is not accessible and will return an.." "0: entire memory accessible,1: first 1/2 of the memory accessible,2: first 1/4 of the memory accessible,3: first 1/8 of the memory accessible,4: first 1/16 of the memory accessible,5: first 1/32 of the memory accessible,6: first 1/64 of the memory accessible,7: first 1/128 of the memory accessible"
line.long 0x20 "INT_SEL,Interrupt multiplexer select register"
hexmask.long 0x20 0.--31. 1. "DSI,Specifies interrupt source:"
line.long 0x24 "INT_MODE,DSI interrupt pulse mode register"
hexmask.long 0x24 0.--31. 1. "DSI_INT_PULSE,Specifies DSI interrupt format:"
line.long 0x28 "NMI_MODE,DSI NMI pulse mode register"
bitfld.long 0x28 0. "DSI_NMI_PULSE,Specifies DSI NMI format:" "0: level sensitive,1: pulse generator on rising edge"
group.long 0x30++0xF
line.long 0x0 "FLASH_CTL,FLASH control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
bitfld.long 0x0 8. "FLASH_INVALIDATE,1': Invalidates the content of the flash controller's buffers." "?,1: Invalidates the content of the flash.."
newline
bitfld.long 0x0 4. "PREF_EN,Prefetch enable:" "0: disabled,1: enabled"
bitfld.long 0x0 0.--1. "FLASH_WS,Amount of ROM wait states:" "0: 0 wait states,1: 1 wait state,2: 2 wait states,3: 3 wait states"
line.long 0x4 "ROM_CTL,ROM control register"
bitfld.long 0x4 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
bitfld.long 0x4 0. "ROM_WS,Amount of ROM wait states:" "0: 0 wait states,1: 1 wait state"
line.long 0x8 "RAM_CTL,RAM control register"
bitfld.long 0x8 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
line.long 0xC "DMAC_CTL,DMA controller register"
bitfld.long 0xC 16.--17. "ARB,Arbitration policy:" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
group.long 0xA0++0x7
line.long 0x0 "PRIV_RAM1,RAM 1 privilege register"
hexmask.long.word 0x0 0.--8. 1. "RAM_PROT_LIMIT,See description of PRIV_RAM.RAM_PROT_LIMIT. Note that the reset value is 0x1ff indicating that the complete RAM 1 memory capacity is User accessible."
line.long 0x4 "RAM1_CTL,RAM 1 control register"
bitfld.long 0x4 16.--17. "ARB,Arbitration policy (for RAM controller 1):" "0: CPU has priority,1: DW/DMA has priority,2: Roundrobin,3: Roundrobin"
group.long 0xB0++0x3
line.long 0x0 "MTB_CTL,MTB control register"
bitfld.long 0x0 0. "CPU_HALT_TSTOP_EN,1': Enable CPU Halt to stop MTB trace. ('HALTED' output of CM0+ can stop the trace when high/'1')" "0: 'HALTED' output of CM0+ can not strop trace,1: Enable CPU Halt to stop MTB trace"
repeat 24. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "SL_CTL[$1],Slave control register"
bitfld.long 0x0 16.--17. "ARB,Arbitration policy:" "0: CPU priority,1: DMA priority,2: Roundrobin,3: Roundrobin"
repeat.end
tree.end
tree "GPIO (General Purpose IO)"
base ad:0x40040000
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x40040000 ad:0x40040100 ad:0x40040200 ad:0x40040300 ad:0x40040400)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "DR,Port output data register"
bitfld.long 0x0 7. "DATA7,IO pad 7 output data." "0,1"
newline
bitfld.long 0x0 6. "DATA6,IO pad 6 output data." "0,1"
newline
bitfld.long 0x0 5. "DATA5,IO pad 5 output data." "0,1"
newline
bitfld.long 0x0 4. "DATA4,IO pad 4 output data." "0,1"
newline
bitfld.long 0x0 3. "DATA3,IO pad 3 output data." "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 output data." "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 output data." "0,1"
newline
bitfld.long 0x0 0. "DATA0,IO pad 0 output data." "0,1"
rgroup.long ($2+0x4)++0x3
line.long 0x0 "PS,Port IO pad state register"
bitfld.long 0x0 8. "FLT_DATA,Reads of this register return the logical state of the filtered pin." "0,1"
newline
bitfld.long 0x0 7. "DATA7,IO pad 7 state." "0,1"
newline
bitfld.long 0x0 6. "DATA6,IO pad 6 state." "0,1"
newline
bitfld.long 0x0 5. "DATA5,IO pad 5 state." "0,1"
newline
bitfld.long 0x0 4. "DATA4,IO pad 4 state." "0,1"
newline
bitfld.long 0x0 3. "DATA3,IO pad 3 state." "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 state." "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 state." "0,1"
newline
bitfld.long 0x0 0. "DATA0,IO pad 0 state:" "0: Logic low,1: Logic high"
group.long ($2+0x8)++0x13
line.long 0x0 "PC,Port configuration register"
bitfld.long 0x0 30.--31. "PORT_IB_MODE_SEL,This field selects the input buffer reference. The size (1 or 2 bits) and functionality is dependent on the IO cell." "0: CMOS input buffer,1: vcchib,2: OVT,3: Reference"
newline
bitfld.long 0x0 28.--29. "PORT_SLEW_CTL,Slew control. Only used in the O_Z drive mode (mode 4: strong pull down open drain): This field is intended for I2C functionality. See BROS 001-70428 for more details." "0: HS mode (100pf < Cb < 400pF 1.71<VDDD<5.5..,1: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext>2.8..,2: HS mode (100pf<Cb<400pf 1.71<VDDD<5.5 Vext<3.3)..,3: HS mode (Cb<100pf 1.71<VDDD<5.5 Vext<=2.8.."
newline
bitfld.long 0x0 27. "PORT_HYST_TRIM,This field is used to improve the hysteresis (to 10 percent of vddio) of the selectable trip point input buffer. The voltage reference comes from the VREFGEN block and is only available when using the VREFGEN block:" "0: <= 2,1: > 2"
newline
bitfld.long 0x0 25. "PORT_SLOW,This field controls the output edge rate of all pins on the port:" "0: fast,1: slow"
newline
bitfld.long 0x0 24. "PORT_VTRIP_SEL,The GPIO cells include a VTRIP_SEL signal to alter the input buffer voltage. Note: this bit is ignored for SIO ports the VTRIP_SEL settings in the SIO register are used instead (a separate VTRIP_SEL is provided for each pin pair)." "0: input buffer functions as a CMOS input buffer,1: input buffer functions as a LVTTL input buffer"
newline
bitfld.long 0x0 21.--23. "DM7,The GPIO drive mode for IO pad 7." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 18.--20. "DM6,The GPIO drive mode for IO pad 6." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 15.--17. "DM5,The GPIO drive mode for IO pad 5." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 12.--14. "DM4,The GPIO drive mode for IO pad 4." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 9.--11. "DM3,The GPIO drive mode for IO pad 3." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 6.--8. "DM2,The GPIO drive mode for IO pad 2." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 3.--5. "DM1,The GPIO drive mode for IO pad 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0 0.--2. "DM0,The GPIO drive mode for IO pad 0." "0: Mode 0 (analog mode): Output buffer off (high..,1: Mode 1: Output buffer off (high Z). Input buffer..,2: Mode 2: Strong pull down ('0') weak/resistive..,3: Mode 3: Weak/resistive pull down (PD) strong..,4: Mode 4: Strong pull down ('0') open drain (pull..,5: Mode 5: Open drain (pull down off) strong pull..,6: Mode 6: Strong pull down ('0') strong pull up..,7: Mode 7: Weak/resistive pull down (PD).."
line.long 0x4 "INTR_CFG,Port interrupt configuration register"
bitfld.long 0x4 18.--20. "FLT_SEL,Selects which pin is routed through the 50ns glitch filter to provide a glitch-safe interrupt." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x4 16.--17. "FLT_EDGE_SEL,Same for the glitch filtered pin (selected by FLT_SEL)." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
newline
bitfld.long 0x4 14.--15. "EDGE7_SEL,Sets which edge will trigger an IRQ for IO pad 7." "0,1,2,3"
newline
bitfld.long 0x4 12.--13. "EDGE6_SEL,Sets which edge will trigger an IRQ for IO pad 6." "0,1,2,3"
newline
bitfld.long 0x4 10.--11. "EDGE5_SEL,Sets which edge will trigger an IRQ for IO pad 5." "0,1,2,3"
newline
bitfld.long 0x4 8.--9. "EDGE4_SEL,Sets which edge will trigger an IRQ for IO pad 4." "0,1,2,3"
newline
bitfld.long 0x4 6.--7. "EDGE3_SEL,Sets which edge will trigger an IRQ for IO pad 3." "0,1,2,3"
newline
bitfld.long 0x4 4.--5. "EDGE2_SEL,Sets which edge will trigger an IRQ for IO pad 2." "0,1,2,3"
newline
bitfld.long 0x4 2.--3. "EDGE1_SEL,Sets which edge will trigger an IRQ for IO pad 1." "0,1,2,3"
newline
bitfld.long 0x4 0.--1. "EDGE0_SEL,Sets which edge will trigger an IRQ for IO pad 0." "0: Disabled,1: Rising edge,2: Falling edge,3: Both rising and falling edges"
line.long 0x8 "INTR,Port interrupt status register"
rbitfld.long 0x8 24. "PS_FLT_DATA,This is a duplicate of the contents of the PS register provided here to allow reading of both pin state and interrupt state of the port in a single read operation." "0,1"
newline
rbitfld.long 0x8 23. "PS_DATA7,N/A" "0,1"
newline
rbitfld.long 0x8 22. "PS_DATA6,N/A" "0,1"
newline
rbitfld.long 0x8 21. "PS_DATA5,N/A" "0,1"
newline
rbitfld.long 0x8 20. "PS_DATA4,N/A" "0,1"
newline
rbitfld.long 0x8 19. "PS_DATA3,N/A" "0,1"
newline
rbitfld.long 0x8 18. "PS_DATA2,N/A" "0,1"
newline
rbitfld.long 0x8 17. "PS_DATA1,N/A" "0,1"
newline
rbitfld.long 0x8 16. "PS_DATA0,`" "0,1"
newline
bitfld.long 0x8 8. "FLT_DATA,Deglitched interrupt pending (selected by FLT_SEL)." "0,1"
newline
bitfld.long 0x8 7. "DATA7,Interrupt pending on IO pad 7. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 6. "DATA6,Interrupt pending on IO pad 6. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 5. "DATA5,Interrupt pending on IO pad 5. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 4. "DATA4,Interrupt pending on IO pad 4. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 3. "DATA3,Interrupt pending on IO pad 3. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 2. "DATA2,Interrupt pending on IO pad 2. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 1. "DATA1,Interrupt pending on IO pad 1. Firmware writes 1 to clear the interrupt." "0,1"
newline
bitfld.long 0x8 0. "DATA0,Interrupt pending on IO pad 0. Firmware writes 1 to clear the interrupt." "0,1"
line.long 0xC "SIO,Port SIO configuration register"
bitfld.long 0xC 29.--31. "PAIR_VOH67_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3,4,5,6,7"
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bitfld.long 0xC 27.--28. "PAIR_VREF67_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3"
newline
bitfld.long 0xC 26. "PAIR_VTRIP67_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 25. "PAIR_IBUF67_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 24. "PAIR_VREG67_EN,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 21.--23. "PAIR_VOH45_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 19.--20. "PAIR_VREF45_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3"
newline
bitfld.long 0xC 18. "PAIR_VTRIP45_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 17. "PAIR_IBUF45_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 16. "PAIR_VREG45_EN,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 13.--15. "PAIR_VOH23_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC 11.--12. "PAIR_VREF23_SEL,See corresponding definition for IO pads 0 and 1." "0,1,2,3"
newline
bitfld.long 0xC 10. "PAIR_VTRIP23_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 9. "PAIR_IBUF23_SEL,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 8. "PAIR_VREG23_EN,See corresponding definition for IO pads 0 and 1." "0,1"
newline
bitfld.long 0xC 5.--7. "PAIR_VOH01_SEL,Selects regulated Voh output level and trip point of input buffer for a specific SIO pin pair. Voh depends on the selected reference voltage (VREF_SEL)." "0: Voh = 1*reference,1: Voh = 1,2: Voh = 1,3: Voh = 1,4: Voh = 2,5: Voh = 2,6: Voh = 2,7: Voh = 4"
newline
bitfld.long 0xC 3.--4. "PAIR_VREF01_SEL,Selects reference voltage Vref for trip-point of input buffer:" "0: trip-point reference of SRSS internal reference..,1: trip-point reference of SRSS internal reference..,2: trip-point reference of AMUXBUS_A,3: trip-point reference of AMUXBUS_B"
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bitfld.long 0xC 2. "PAIR_VTRIP01_SEL,Selects trip-point of input buffer. In single ended input buffer mode (IBUF01_SEL = '0'):" "0: trip-point is 0,1: trip-point is 0"
newline
bitfld.long 0xC 1. "PAIR_IBUF01_SEL,Selects input buffer mode:" "0: singled ended input buffer,1: differential input buffer"
newline
bitfld.long 0xC 0. "PAIR_VREG01_EN,Selects output buffer mode:" "0: unregulated output buffer,1: regulated output buffer"
line.long 0x10 "PC2,Port configuration register 2"
bitfld.long 0x10 7. "INP_DIS7,Disables the input buffer for IO pad 7." "0,1"
newline
bitfld.long 0x10 6. "INP_DIS6,Disables the input buffer for IO pad 6." "0,1"
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bitfld.long 0x10 5. "INP_DIS5,Disables the input buffer for IO pad 5." "0,1"
newline
bitfld.long 0x10 4. "INP_DIS4,Disables the input buffer for IO pad 4." "0,1"
newline
bitfld.long 0x10 3. "INP_DIS3,Disables the input buffer for IO pad 3." "0,1"
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bitfld.long 0x10 2. "INP_DIS2,Disables the input buffer for IO pad 2." "0,1"
newline
bitfld.long 0x10 1. "INP_DIS1,Disables the input buffer for IO pad 1." "0,1"
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bitfld.long 0x10 0. "INP_DIS0,Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM). This bit should be set when analog signals are present on the pin and PC.DM != 0 is required to use the output driver." "0,1"
group.long ($2+0x24)++0x3
line.long 0x0 "MSC_ANA,Port MSCLP AMUX enable"
bitfld.long 0x0 7. "DATA7,IO pad 7 MSC_ANA_EN" "0,1"
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bitfld.long 0x0 6. "DATA6,IO pad 6 MSC_ANA_EN." "0,1"
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bitfld.long 0x0 5. "DATA5,IO pad 5 MSC_ANA_EN" "0,1"
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bitfld.long 0x0 4. "DATA4,IO pad 4 MSC_ANA_EN" "0,1"
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bitfld.long 0x0 3. "DATA3,IO pad 3 MSC_ANA_EN" "0,1"
newline
bitfld.long 0x0 2. "DATA2,IO pad 2 MSC_ANA_EN" "0,1"
newline
bitfld.long 0x0 1. "DATA1,IO pad 1 MSC_ANA_EN." "0,1"
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bitfld.long 0x0 0. "DATA0,IO pad 0 MSC_ANA_EN" "0,1"
group.long ($2+0x40)++0x13
line.long 0x0 "DR_SET,Port output data set register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,IO pad i:"
line.long 0x4 "DR_CLR,Port output data clear register"
hexmask.long.byte 0x4 0.--7. 1. "DATA,IO pad i:"
line.long 0x8 "DR_INV,Port output data invert register"
hexmask.long.byte 0x8 0.--7. 1. "DATA,IO pad i:"
line.long 0xC "DS,Port drive strength register"
bitfld.long 0xC 17. "PORT_V1P2_IB_MODE_SEL,For GPIOV1P2 cell " "0: vtrip_sel register controls the vtrip_sel of the..,1: vddio detect cell output controls the vtrip_sel.."
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bitfld.long 0xC 16. "PORT_V1P2_VTRIP_SEL,For GPIOV1P2:" "0: 1,1: 1"
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bitfld.long 0xC 14.--15. "DS7,The GPIO drive strength for IO pad 7." "0,1,2,3"
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bitfld.long 0xC 12.--13. "DS6,The GPIO drive strength for IO pad 6." "0,1,2,3"
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bitfld.long 0xC 10.--11. "DS5,The GPIO drive strength for IO pad 5." "0,1,2,3"
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bitfld.long 0xC 8.--9. "DS4,The GPIO drive strength for IO pad 4." "0,1,2,3"
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bitfld.long 0xC 6.--7. "DS3,The GPIO drive strength for IO pad 3." "0,1,2,3"
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bitfld.long 0xC 4.--5. "DS2,The GPIO drive strength for IO pad 2." "0,1,2,3"
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bitfld.long 0xC 2.--3. "DS1,The GPIO drive strength for IO pad 1." "0,1,2,3"
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bitfld.long 0xC 0.--1. "DS0,The GPIO drive strength for IO pad 0." "0: 1 ma drive nominal - changes with external R/C..,1: 2 ma drive nominal - changes with external R/C..,2: 4 ma drive nominal - changes with external R/C..,3: 8 ma drive nominal - changes with external R/C.."
line.long 0x10 "FILT_CONFIG,IO filter config register"
bitfld.long 0x10 23. "FILT7_EN,Filter selection for IO pad 7" "0,1"
newline
bitfld.long 0x10 22. "FILT6_EN,Filter selection for IO pad 6" "0,1"
newline
bitfld.long 0x10 21. "FILT5_EN,Filter selection for IO pad 5" "0,1"
newline
bitfld.long 0x10 20. "FILT4_EN,Filter selection for IO pad 4" "0,1"
newline
bitfld.long 0x10 19. "FILT3_EN,Filter selection for IO pad 3" "0,1"
newline
bitfld.long 0x10 18. "FILT2_EN,Filter selection for IO pad 2" "0,1"
newline
bitfld.long 0x10 17. "FILT1_EN,Filter selection for IO pad 1" "0,1"
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bitfld.long 0x10 16. "FILT0_EN,Filter selection for IO pad 0" "0,1"
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bitfld.long 0x10 14.--15. "TRIM7,trim bits for 50ns filter on IO pad 7" "0,1,2,3"
newline
bitfld.long 0x10 12.--13. "TRIM6,trim bits for 50ns filter on IO pad 6" "0,1,2,3"
newline
bitfld.long 0x10 10.--11. "TRIM5,trim bits for 50ns filter on IO pad 5" "0,1,2,3"
newline
bitfld.long 0x10 8.--9. "TRIM4,trim bits for 50ns filter on IO pad 4" "0,1,2,3"
newline
bitfld.long 0x10 6.--7. "TRIM3,trim bits for 50ns filter on IO pad 3" "0,1,2,3"
newline
bitfld.long 0x10 4.--5. "TRIM2,trim bits for 50ns filter on IO pad 2" "0,1,2,3"
newline
bitfld.long 0x10 2.--3. "TRIM1,trim bits for 50ns filter on IO pad 1" "0,1,2,3"
newline
bitfld.long 0x10 0.--1. "TRIM0,trim bits for 50ns filter on IO pad 0" "0,1,2,3"
group.long ($2+0x80)++0x3
line.long 0x0 "VREFGEN,Reference generator configuration register"
bitfld.long 0x0 8. "VREFGEN_EN,Reference generator enable:" "0: Disabled,1: Enabled"
newline
hexmask.long.byte 0x0 0.--4. 1. "REF_SEL,Reference selection. A reference Voltage vinref is created using a Voltage vddio:"
tree.end
repeat.end
base ad:0x40040000
rgroup.long 0x1000++0x3
line.long 0x0 "INTR_CAUSE,Interrupt port cause register"
hexmask.long 0x0 0.--31. 1. "PORT_INT,Each IO port has an associated bit field in this register. The bit field reflects the IO port's interrupt line (bit field i reflects 'interrupts_gpio[i]' for IO port i). The register is used when the system uses a shared/combined interrupt line.."
group.long 0x1010++0x3
line.long 0x0 "DFT_IO_TEST,IO SELF TEST control register for DfT purposes only"
bitfld.long 0x0 28. "DFT_ANA_POL_2,'analog_pol' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 27. "DFT_ANA_SEL_2,'analog_sel' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 26. "DFT_ANALOG_EN_2,'analog_en' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 25. "DFT_OE_N_2,'oe_n' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
newline
bitfld.long 0x0 24. "DFT_HLD_OVR_2,'hld_ovr' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 20. "DFT_ANA_POL_1,'analog_pol' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 19. "DFT_ANA_SEL_1,'analog_sel' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 18. "DFT_ANALOG_EN_1,'analog_en' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
newline
bitfld.long 0x0 17. "DFT_OE_N_1,'oe_n' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 16. "DFT_HLD_OVR_1,'hld_ovr' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 12. "DFT_ANA_POL_0,'analog_pol' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 11. "DFT_ANA_SEL_0,'analog_sel' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
newline
bitfld.long 0x0 10. "DFT_ANALOG_EN_0,'analog_en' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 9. "DFT_OE_N_0,'oe_n' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 8. "DFT_HLD_OVR_0,'hld_ovr' DfT control for IO cells depending on DFT_IO_TEST_MODE as given below." "0,1"
bitfld.long 0x0 0.--1. "DFT_IO_TEST_MODE,DfT IO SELF TEST mode:" "0: Functional mode: disables the DfT IO SELF TEST;..,1: select this mode during ADFT testing to control..,2: select this mode for testing analog switches to..,3: select this mode for generic testing to control.."
rgroup.long 0x1020++0x3
line.long 0x0 "GPIOV1P2_DET,GPIOV1P2 Detect output"
bitfld.long 0x0 0. "DET,Indicates HI when VDDIO is in 1.8V range and LOW when VDDIO is in 1.2V range." "0,1"
tree.end
tree "HSIOM (High Speed IO Matrix)"
base ad:0x40020000
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x40020000 ad:0x40020100 ad:0x40020200 ad:0x40020300 ad:0x40020400)
tree "PRT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "PORT_SEL,Port selection register"
hexmask.long.byte 0x0 28.--31. 1. "IO7_SEL,Selects connection for IO pad 7 route."
hexmask.long.byte 0x0 24.--27. 1. "IO6_SEL,Selects connection for IO pad 6 route."
hexmask.long.byte 0x0 20.--23. 1. "IO5_SEL,Selects connection for IO pad 5 route."
hexmask.long.byte 0x0 16.--19. 1. "IO4_SEL,Selects connection for IO pad 4 route."
hexmask.long.byte 0x0 12.--15. 1. "IO3_SEL,Selects connection for IO pad 3 route."
hexmask.long.byte 0x0 8.--11. 1. "IO2_SEL,Selects connection for IO pad 2 route."
hexmask.long.byte 0x0 4.--7. 1. "IO1_SEL,Selects connection for IO pad 1 route."
hexmask.long.byte 0x0 0.--3. 1. "IO0_SEL,Selects connection for IO pad 0 route."
tree.end
repeat.end
base ad:0x40020000
group.long 0x2000++0x3
line.long 0x0 "PUMP_CTL,Pump control"
bitfld.long 0x0 31. "ENABLED,Pump enabled:" "0: Disabled,1: Enabled"
bitfld.long 0x0 0. "CLOCK_SEL,Clock select:" "0: External clock,1: Internal clock"
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x2100)++0x3
line.long 0x0 "AMUX_SPLIT_CTL[$1],AMUX splitter cell control"
bitfld.long 0x0 6. "SWITCH_BB_S0,T-switch control for AMUXBUSB vssa/ground switch." "0,1"
bitfld.long 0x0 5. "SWITCH_BB_SR,T-switch control for Right AMUXBUSB switch." "0,1"
bitfld.long 0x0 4. "SWITCH_BB_SL,T-switch control for Left AMUXBUSB switch." "0,1"
bitfld.long 0x0 2. "SWITCH_AA_S0,T-switch control for AMUXBUSA vssa/ground switch:" "0: switch open,1: switch closed"
newline
bitfld.long 0x0 1. "SWITCH_AA_SR,T-switch control for Right AMUXBUSA switch:" "0: switch open,1: switch closed"
bitfld.long 0x0 0. "SWITCH_AA_SL,T-switch control for Left AMUXBUSA switch:" "0: switch open,1: switch closed"
repeat.end
tree.end
tree "MSCLP (Multi-Sense Converter)"
base ad:0x40290000
group.long 0x0++0x2B
line.long 0x0 "CTL,Configuration and Control"
bitfld.long 0x0 31. "ENABLED,Master enable of the MSCv3LP IP. Must be set to '1' for any operation to function." "0: N/A,1: N/A"
newline
bitfld.long 0x0 26. "DEBUG_EN,Master debug control for debug features." "0: Gate the logic for the following features:,1: Enable all debug features"
newline
bitfld.long 0x0 24. "CLK_MSC_RATIO,Control bit for logic that creates clk_msc from clk_hf (applicable if LP_AOS_PRESENT = 0)." "0: Divided,1: 1"
newline
bitfld.long 0x0 20. "BUF_MODE,Shield buffer operating mode select." "0: High bandwidth mode,1: Shield mode"
newline
bitfld.long 0x0 16.--17. "OPERATING_MODE,Sequencer FSM Operating Mode" "0: CPU Mode,1: Chained-Scan DMA Mode,2: Autonomous Scan Multi Sensor Mode,3: Low Power Always-On-Sense Mode"
newline
hexmask.long.byte 0x0 12.--15. 1. "CFG_OFFSET,Starting 32-bit word address offset index from SNS_LP_AOS_SNS_CTL0 register for each sensor configuration structure in local IP storage SENSOR_DATA. The difference between this CFG_OFFSET index and the index of SNS_CTL (index of 0xd addresses.."
newline
bitfld.long 0x0 10.--11. "EXT_FRAME_START_MODE,Control to enable external frame start of Sequencer FSM or LP-AoS Sequencer via GPIO." "0: External frame start capability off,1: External frame start capability on for Sequencer..,2: External frame start capability on for LP-AoS..,?"
newline
bitfld.long 0x0 8. "CLK_SYNC_EN,Control bit to create external channel sync clock. Used for multi-chip operation." "0: msc_ext_sync_clk_out,1: Generate msc_ext_sync_clk_out using.."
newline
bitfld.long 0x0 4. "MSCCMP_EN,MSC Comparator Enable." "0: N/A,1: N/A"
newline
bitfld.long 0x0 0. "SENSE_EN,Enables the sense modulator output." "0: All switches,1: Switches can be closed/open as per register.."
line.long 0x4 "SPARE,Spare MMIO"
hexmask.long.byte 0x4 0.--5. 1. "SPARE,Spare MMIO (Hard IP)."
line.long 0x8 "SCAN_CTL1,Scan Control 1"
bitfld.long 0x8 30. "RC_STORE_MODE,Controls the behaviour of the result FIFO when it is full." "0: When full,1: When full"
newline
bitfld.long 0x8 28. "RC_STORE_EN,Control whether raw counts are stored into result FIFO while scanning. Typically enabled but may be disabled in a signal detection scenario where absolute raw counts are not required and are not stored to save power." "0: N/A,1: N/A"
newline
hexmask.long.word 0x8 16.--25. 1. "FRAME_RES_START_ADDR,Base address (in terms of 32-bit SRAM entries) in SENSOR_DATA where the result FIFO exists. The size of the FIFO is from this location to the final location in SENSOR_DATA. Access to the result FIFO is done via RESULT_FIFO_RD but may.."
newline
bitfld.long 0x8 12. "DEBUG_CONV_PH_SEL,Debug counter conversion chop phase select for DEBUG_CONV_COUNT." "0,1"
newline
bitfld.long 0x8 8. "RAW_COUNT_MODE,Control bit to handle behaviour when RAW_COUNT and/or CIC2 subsample accumulator exceed the programmed arithmetic range." "0: N/A,1: N/A"
newline
bitfld.long 0x8 4.--5. "NUM_SAMPLES,Number of samples (minus 1) to be scanned. NUM_SAMPLES > 1 results in autonomous scan same sensor (AS-SS) behaviour. This implies for a frame of e.g. 3 sensors (s0 s1 s2) with NUM_SAMPLES = 1 (2 samples per sensor) the result fifo will have.." "0,1,2,3"
newline
bitfld.long 0x8 3. "RESCAN_DEBUG_MODE,If this bit is set all results (good and bad) generated by NUM_AUTO_RESAMPLE are stored. Debug feature." "0: N/A,1: N/A"
newline
bitfld.long 0x8 0.--2. "NUM_AUTO_RESAMPLE,If Sequencer detects a bad conversion and NUM_AUTO_RESAMPLE != 0 it will not store the bad result. Instead it will automatically re-sample using current configuration without firmware intervention. This process repeats until a good.." "0,1,2,3,4,5,6,7"
line.long 0xC "SCAN_CTL2,Scan Control 2"
bitfld.long 0xC 30. "INFINITE_SCAN_MODE,DFT bit that has the effect of keeping the Sequencer FSM in SUB_CONV forever to allow test measurements. With this bit set the FSM remains in SUB_CONV once entered. The sub conversion counter will keep decrementing to zero and.." "0: N/A,1: N/A"
newline
bitfld.long 0xC 28. "EXT_REF_CLK_EN,Control whether the clock used for external Cref clocking is enabled (clk_extfb)." "0: N/A,1: N/A"
newline
hexmask.long.word 0xC 16.--25. 1. "FRAME_CFG_START_ADDR,Pointer (in terms of 32-bit SRAM entries) to first sensor configuration of a frame in SENSOR_DATA. Hardware increments a local pointer from this start point. In LP_AOS mode hardware returns to this pointer after the frame is.."
newline
bitfld.long 0xC 12. "CHOP_POL,Polarity of first chop phase. Hardware updates chop control locally from this point (via inversion)." "0,1"
newline
hexmask.long.byte 0xC 8.--11. 1. "NUM_EPI_KREF_DELAY,The duration of EPILOGUE defined in relation to Kref when (LFSR_MODE != PRS). The value is interpreted as Kref/4 increments."
newline
hexmask.long.byte 0xC 0.--7. 1. "NUM_EPI_KREF_DELAY_PRS,The duration of EPILOGUE defined in relation to Kref when (LFSR_MODE = PRS). The value is interpreted as Kref/4 increments. Kref is defined via SENSE_DIV."
line.long 0x10 "INIT_CTL1,Initialisation Control 1"
bitfld.long 0x10 28. "PER_SAMPLE,Decides if coarse initialisation is done per sample when NUM_SAMPLES > 0 (i.e. more than one sample per scan). Applies to CMOD_SEL selected Cmod." "0: N/A,1: N/A"
newline
hexmask.long.word 0x10 16.--27. 1. "NUM_INIT_CMOD_12_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod1 and Cmod2 in full-wave mode). Programmed in terms of clk_mod cycles."
newline
hexmask.long.word 0x10 0.--11. 1. "NUM_INIT_CMOD_12_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod1 to vdda and Cmod2 to vssa in full-wave mode). Programmed in terms of clk_mod cycles."
line.long 0x14 "INIT_CTL2,Initialisation Control 2"
hexmask.long.word 0x14 16.--27. 1. "NUM_INIT_CMOD_34_SHORT_CYCLES,Duration of the coarse short phase (shorting Cmod3 and Cmod4 in full-wave mode). Programmed in terms of clk_mod cycles."
newline
hexmask.long.word 0x14 0.--11. 1. "NUM_INIT_CMOD_34_RAIL_CYCLES,Duration of the coarse initialisation phase (e.g. connecting Cmod3 to vdda and Cmod4 to vssa in full-wave mode). Programmed in terms of clk_mod cycles."
line.long 0x18 "INIT_CTL3,Initialisation Control 3"
bitfld.long 0x18 15. "INIT_MODE,Determines autonomous initialisation behaviour during INIT_CMOD." "0: Decode CMOD_SEL,1: Decode CMOD_SEL"
newline
bitfld.long 0x18 10.--11. "CMOD_SEL,Select which Cmod are used and the cycle thresholds to be used for coarse initialisation. Note this field affects which Cmod switches are autonomously initialised by hardware as well as influencing the cycle counters as per INIT_MODE." "0: Used for full-wave,1: Used for full-wave,2: Used for half-wave,3: Used for half-wave"
newline
bitfld.long 0x18 8.--9. "NUM_PRO_OFFSET_TRIPS,Number of comparator trips required to be observed in PRO_OFFSET before proceeding to dummy cycles." "0,1,2,3"
newline
hexmask.long.byte 0x18 0.--7. 1. "NUM_PRO_OFFSET_CYCLES,Maximum number of clk_mod cycles to be assigned for the PRO_OFFSET state. If NUM_PRO_OFFSET_TRIPS are observed before this timeout exit at that point."
line.long 0x1C "INIT_CTL4,Initialisation Control 4"
bitfld.long 0x1C 24. "PRO_BYPASS,Decides whether to skip prologue (PRO_OFFSET/DUMMY/WAIT) for every conversion after the first chop phase (if any as defined by NUM_CONV)." "0: N/A,1: N/A"
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hexmask.long.byte 0x1C 16.--19. 1. "NUM_PRO_WAIT_KREF_DELAY,The duration of PRO_WAIT defined in relation to Kref when (LFSR_MODE != PRS). The value is interpreted as Kref/4 increments."
newline
hexmask.long.byte 0x1C 8.--12. 1. "NUM_PRO_WAIT_KREF_DELAY_PRS,The duration of PRO_WAIT defined in relation to Kref when (LFSR_MODE = PRS). The value is interpreted as Kref/4 increments."
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hexmask.long.byte 0x1C 0.--7. 1. "NUM_PRO_DUMMY_SUB_CONVS,Number of sub-conversions (dummy cycles) to be run during PRO_DUMMY."
line.long 0x20 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x20 27. "PHASE_WIDTH_SEL,Select which phases the PHASE_WIDTH applies to:" "0: PHASE_WIDTH corresponds to width of ph0 and ph2,1: PHASE_WIDTH corresponds to width of ph1 and ph3"
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hexmask.long.word 0x20 16.--25. 1. "PHASE_SHIFT_CYCLES,Phase shift cycle control for ph0X and ph1X."
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hexmask.long.word 0x20 0.--11. 1. "PHASE_WIDTH,Control width (clk_mod cycles) of ph0 and ph2 OR ph1 and ph3. If set to zero Fs is divided equally between all phases. This field is only applicable when LFSR_MODE = DIRECT_CLOCK."
line.long 0x24 "SENSE_PERIOD_CTL,Sense Clock Period Control"
hexmask.long.byte 0x24 16.--19. 1. "LFSR_SCALE,Shift the LFSR output left by LSFR_SCALE bits before adding to SENSE_DIV. This scaling is only applicable in spread spectrum mode."
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hexmask.long.word 0x24 0.--11. 1. "LFSR_POLY,Programmable polynomial to be used for the sense LFSR. For example (default):"
line.long 0x28 "FILTER_CTL,Filter Control"
bitfld.long 0x28 24. "FILTER_MODE,N/A" "0: Use the standard first order counter low pass..,1: Use CIC2 Filter. Advantage of CIC2 over CIC1 is.."
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bitfld.long 0x28 16. "BIT_FORMAT,Determines how the synchronised comparator output is interpreted by the filter pipeline." "0: Input values [0 +1],1: Input values [-1 +1]. In this scenario a value.."
group.long 0x30++0xB
line.long 0x0 "CCOMP_CDAC_CTL,Compensation CAPDAC Control"
bitfld.long 0x0 31. "EPILOGUE_EN,Control on whether Ccomp is active during EPILOGUE for final balancing in a conversion." "0: N/A,1: N/A"
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bitfld.long 0x0 24. "COMP_BLANKING_MODE,Control on type of compensation blanking applied when compensation blanking is enabled (COMP_BLANKING_EN = 1)." "0: Compensation is enabled for 25 percent of the..,1: Compensation is enabled for 50 percent of the.."
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hexmask.long.byte 0x0 8.--15. 1. "SEL_CO_PRO_OFFSET,Select value for Compensation CAPDAC size during PRO_OFFSET until the first comparator trip is observed. After the first trip in PRO_OFFSET the following overriding applies:"
line.long 0x4 "DITHER_CDAC_CTL,Flatspot/Dither CAPDAC Switch Control"
hexmask.long.byte 0x4 16.--23. 1. "LFSR_POLY_FL,Dither/Flatspot CAPDAC LFSR polynomial. Uses same encoding as the spread spectrum polynomial LFSR_POLY. For example (default):"
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hexmask.long.byte 0x4 0.--7. 1. "SEL_FL,Select value for Dither/Flatspot CAPDAC size."
line.long 0x8 "MSCCMP_CTL,MSC Comparator Control"
bitfld.long 0x8 8.--9. "FILT,MSC comparator filter frequency select (corner frequencies - 90 percent settling)." "0: N/A,1: N/A,2: N/A,3: N/A"
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bitfld.long 0x8 0.--1. "PWR,Power control setting on MSC comparator to allow noise reduction at the cost of current consumption (less noise more power)." "0: N/A,1: N/A,2: N/A,3: N/A"
group.long 0x50++0x3
line.long 0x0 "OBS_CTL,Observability Control"
hexmask.long.byte 0x0 24.--27. 1. "OBSERVE3,Selects the source for observe output signal 3:"
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hexmask.long.byte 0x0 16.--19. 1. "OBSERVE2,Selects the source for observe output signal 2:"
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hexmask.long.byte 0x0 8.--11. 1. "OBSERVE1,Selects the source for observe output signal 1:"
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hexmask.long.byte 0x0 0.--3. 1. "OBSERVE0,Selects the source for observe output signal 0:"
group.long 0x70++0x7
line.long 0x0 "AOS_CTL,Always On Scanning Control"
bitfld.long 0x0 31. "MRSS_PWR_CYCLE_EN,Control bit to enable/disable hardware controlled power cycling of MRSS resources (reference IMO pump). This power cycling occurs at the end of frames initiated via FRAME_START_AOS that do not result in an interrupt. By default this.." "0: N/A,1: N/A"
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bitfld.long 0x0 30. "STOP_ON_SD,Stop on signal detection control bit. If set and a signal is detected mid frame the frame will terminate immediately and assert the SIG_DET interrupt. Otherwise only SIG_DET asserts the frame continues to the end of the frame (at which point.." "0: N/A,1: N/A"
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hexmask.long.word 0x0 16.--29. 1. "FR_TIMEOUT_INTERVAL,Threshold for the number of consecutive frames initiated by the LP-AoS FSM before asserting FR_TIMEOUT interrupt. Once this threshold is met the LP-AoS FSM asserts the FR_TIMEOUT interrupt. Setting this register to 0 disables this.."
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hexmask.long.word 0x0 0.--15. 1. "WAKEUP_TIMER,Timer interval in terms of ILO clk_lf cycles (minus 1) between AoS frames when using LP-AoS FSM. The ILO operates at a nominal frequency f_ILO. Desired interval range is typically 1->2000ms. Intended usage is in DEEP_SLEEP where only the ILO.."
line.long 0x4 "CE_CTL,Channel Engine Control"
bitfld.long 0x4 31. "ENABLED,Channel Engine enable. If set = 1 then the Channel Engine processes the raw counts produced by the CIC1/CIC2 filter according to RCF_EN and BLSD_EN." "0: N/A,1: N/A"
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bitfld.long 0x4 24. "CE_TEST_MODE,Channel Engine test mode control" "0: N/A,1: N/A"
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bitfld.long 0x4 8. "BLSD_EN,If set (and CE_CTL.ENABLED == 1) then the Channel Engine executes hardware baselining and signal detection." "0: N/A,1: N/A"
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bitfld.long 0x4 0. "RCF_EN,If set (and CE_CTL.ENABLED == 1) then the Channel Engine executes the raw count filter IIR on the raw counts produced by the CIC1/CIC2 filter." "0: N/A,1: N/A"
group.long 0x80++0x7
line.long 0x0 "PUMP_CTL,Local MRSS Pump Control"
bitfld.long 0x0 0. "PUMP_MODE,Local pump mode control. The programming of this register is acted on by the LP-AoS FSM when controlling the pump settings prior to periodic scanning." "0: Bypass the local pump (used when vdda > 4V).,1: Use the local pump (used when vdda < 4V)."
line.long 0x4 "IMO_CTL,Local MRSS IMO Control"
hexmask.long.word 0x4 16.--25. 1. "CLOCK_MSC_DIV,Clock division ratio for clk_imo_msc to clk_msc. This specifies the frequency at which the main MSCv3LP digital is running at (clk_msc) and is equivalent to the modulator clock (clk_mod which runs at Fmod frequency). Note that.."
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bitfld.long 0x4 8.--10. "CLOCK_SYNC_DIV,Clock division for clk_imo_msc to clk_sync. This clock (clk_sync) is enabled via CLK_SYNC_EN for the master channel in a multi-chip topology." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,7: N/A"
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bitfld.long 0x4 0.--2. "FREQ,Select operating frequency of MRSS clk_imo_msc" "0: IMO runs at 25 MHz,1: IMO runs at 28 MHz,2: IMO runs at 32 MHz,3: IMO runs at 38 MHz,4: IMO runs at 40 MHz,5: IMO runs at 44 MHz,6: IMO runs at 46 MHz,?"
group.long 0x100++0xB
line.long 0x0 "INTR,MSCv3 Interrupt Cause Register"
bitfld.long 0x0 31. "FIFO_OVERFLOW,Result FIFO overflow condition." "0,1"
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bitfld.long 0x0 30. "FIFO_UNDERFLOW,Result FIFO underflow condition." "0,1"
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bitfld.long 0x0 24. "CONFIG_REQ,Request for scan configuration and scan start. The Sequencer FSM is entering WAIT_SCAN_START when this interrupt is raised. This interrupt can be used in CPU mode in a multi-channel scenario with external frame start to indicate to firmware.." "0,1"
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bitfld.long 0x0 16. "FRAME,A single frame is complete." "0,1"
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bitfld.long 0x0 12. "INIT,Coarse initialisation complete. For debug purposes." "0,1"
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bitfld.long 0x0 8. "SCAN,A single scan is complete." "0,1"
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bitfld.long 0x0 4. "SAMPLE,A single sample is complete. For debug purposes." "0,1"
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bitfld.long 0x0 0. "SUB_SAMPLE,A valid CIC2 sub-sample is complete. To facilitate firmware averaging of sub-samples. For debug purposes." "0,1"
line.long 0x4 "INTR_SET,MSCv3 Interrupt Set Register"
bitfld.long 0x4 31. "FIFO_OVERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 30. "FIFO_UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 24. "CONFIG_REQ,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 16. "FRAME,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 12. "INIT,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 8. "SCAN,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 4. "SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 0. "SUB_SAMPLE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_MASK,MSCv3 Interrupt Mask Register"
bitfld.long 0x8 31. "FIFO_OVERFLOW,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 30. "FIFO_UNDERFLOW,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 24. "CONFIG_REQ,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 16. "FRAME,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 12. "INIT,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 8. "SCAN,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 4. "SAMPLE,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 0. "SUB_SAMPLE,Mask bit for corresponding bit in interrupt cause register." "0,1"
rgroup.long 0x10C++0x3
line.long 0x0 "INTR_MASKED,MSCv3 Interrupt Masked Register"
bitfld.long 0x0 31. "FIFO_OVERFLOW,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 30. "FIFO_UNDERFLOW,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 24. "CONFIG_REQ,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 16. "FRAME,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 12. "INIT,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 8. "SCAN,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 4. "SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
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bitfld.long 0x0 0. "SUB_SAMPLE,Logical AND of corresponding INTR and INTR_MASK bits." "0,1"
group.long 0x120++0xB
line.long 0x0 "INTR_LP,Low Power Interrupt Cause Register"
bitfld.long 0x0 24. "IMO_UP,MSCv3LP logic has turned on the MRSS IMO." "0,1"
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bitfld.long 0x0 20. "CE_DONE,Channel Engine done signal. Asserted '1' at the end of the Channel Engine processing pipeline. For use in debug firmware in CE_TEST_MODE after initiating CE_START. Not intended to be used as a DEEP_SLEEP wakeup source." "0,1"
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bitfld.long 0x0 16. "FRAME,A single frame is complete. Identical to INTR.FRAME except a DEEP_SLEEP wakeup variant." "0,1"
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bitfld.long 0x0 4. "FR_TIMEOUT,LP-AoS has detected a frame timeout." "0,1"
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bitfld.long 0x0 0. "SIG_DET,LP-AoS has detected a signal wakeup." "0,1"
line.long 0x4 "INTR_LP_SET,Low Power Interrupt Set Register"
bitfld.long 0x4 24. "IMO_UP,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 20. "CE_DONE,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 16. "FRAME,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 4. "FR_TIMEOUT,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
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bitfld.long 0x4 0. "SIG_DET,Write with '1' to set corresponding bit in interrupt request register (a write of '0' has no effect)." "0,1"
line.long 0x8 "INTR_LP_MASK,Low Power Interrupt Mask Register"
bitfld.long 0x8 24. "IMO_UP,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 20. "CE_DONE,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 16. "FRAME,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 4. "FR_TIMEOUT,Mask bit for corresponding bit in interrupt cause register." "0,1"
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bitfld.long 0x8 0. "SIG_DET,Mask bit for corresponding bit in interrupt cause register." "0,1"
rgroup.long 0x12C++0x3
line.long 0x0 "INTR_LP_MASKED,Low Power Interrupt Masked Register"
bitfld.long 0x0 24. "IMO_UP,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
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bitfld.long 0x0 20. "CE_DONE,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
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bitfld.long 0x0 16. "FRAME,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
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bitfld.long 0x0 4. "FR_TIMEOUT,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
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bitfld.long 0x0 0. "SIG_DET,Logical AND of corresponding INTR_LP and INTR_LP_MASK bits." "0,1"
group.long 0x140++0x7
line.long 0x0 "WAKEUP_CMD,Wakeup Command Register"
bitfld.long 0x0 0. "START_FRAME_AOS,Set by firmware to initiate frame scanning by the LP-AoS FSM (required for DEEP_SLEEP scanning). When detected hardware clears the bit down and the LP-AoS FSM periodically scans all valid sensor configurations programmed in the sensor.." "0,1"
line.long 0x4 "MRSS_CMD,MRSS Command Register"
bitfld.long 0x4 16. "MRSS_PUMP_STOP,Stop the MRSS pump resource. The ability to shut off the MRSS pump allows for power saving when MSCv3LP is in a standby state (CTL.ENABLED = 0) not scanning and hence no pump is needed. In this case the MRSS reference and IMO remain on so.." "0,1"
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bitfld.long 0x4 8. "MRSS_STOP,Stop the MRSS resources (shut down the reference IMO and pump)." "0,1"
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bitfld.long 0x4 0. "MRSS_START,Start the MRSS local resources. Activates logic on the clk_lf domain to boot up the MRSS resources. The boot up happens in sequence according to required timing specifications with reference IMO (at frequencey IMO_CTL.FREQ) and pump (based on.." "0,1"
rgroup.long 0x180++0x7
line.long 0x0 "MRSS_STATUS,MRSS Status"
bitfld.long 0x0 24. "IMO_UP,Status bit to indicate whether the MRSS IMO is up or not. If this bit is 1 the MRSS references are also up." "0,1"
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bitfld.long 0x0 0. "MRSS_UP,Status bit to indicate whether all of the MRSS resources are booted or not (references IMO pump). This booting may occur as the result of firmware intervention via MRSS_START/STOP/PUMP_STOP or hardware based control via the LP-AoS FSM." "0,1"
line.long 0x4 "AOS_STATUS,AoS Status"
bitfld.long 0x4 16. "FRAME_EXE_STATE,LP-AoS Frame Execute FSM state. FSM runs on clk_imo_msc and no CDC implemented to AOS_STATUS (clk_sys)." "0: N/A,1: N/A"
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bitfld.long 0x4 8.--9. "MRSS_BOOT_STATE,LP-AoS MRSS Boot FSM state. FSM runs on clk_lf and no CDC implemented to AOS_STATUS (clk_sys)." "0: N/A,1: N/A,2: N/A,3: N/A"
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bitfld.long 0x4 0.--2. "FRAME_TIMER_STATE,LP-AoS Frame Timer FSM state. FSM runs on clk_lf and no CDC implemented to AOS_STATUS (clk_sys)." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,?,?,?"
group.long 0x200++0xF
line.long 0x0 "SW_SEL_GPIO,GPIO Switch Control"
bitfld.long 0x0 24.--26. "SW_DSI_CSH_TANK,MUX select for dsi_csh_tank waveform." "0: N/A,1: N/A,2: chop == 1 ? ph0 : ph1,3: chop == 1 ? ph1 : ph3,4: N/A,?,?,?"
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bitfld.long 0x0 20.--22. "SW_DSI_CMOD,MUX select for dsi_cmod waveform." "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph0,3: chop == 1 ? ph3 : ph1,4: N/A,?,?,?"
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bitfld.long 0x0 16. "SW_CSD_CHARGE,MUX select for csd_charge waveform." "0: N/A,1: N/A"
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bitfld.long 0x0 12.--13. "SW_CSD_POLARITY,MUX select for csd_polarity waveform." "0: N/A,1: N/A,2: N/A,?"
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bitfld.long 0x0 8. "SW_CSD_MUTUAL,MUX select for csd_mutual waveform." "0: N/A,1: N/A"
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bitfld.long 0x0 4.--6. "SW_CSD_SHIELD,MUX select for csd_shield waveform." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: ph0 || [Fs2_ph1 && (ph1 || ph3)],6: N/A,?"
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bitfld.long 0x0 0.--2. "SW_CSD_SENSE,MUX select for csd_sense waveform." "0: N/A,1: N/A,2: N/A,3: N/A,4: N/A,5: N/A,6: N/A,?"
line.long 0x4 "SW_SEL_CDAC_RE,Reference CAPDAC Switch Control"
bitfld.long 0x4 20.--22. "SW_REBG,Reference CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode (ph1X ? sel = 01 : sel = 00),?,?,?"
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bitfld.long 0x4 16.--18. "SW_REBV,Reference CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode (ph0X ? sel = 01 : sel = 00),?,?,?"
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bitfld.long 0x4 12.--14. "SW_RETG,Reference CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x4 8.--10. "SW_RETV,Reference CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x4 4.--6. "SW_RECD,Reference CAPDAC to CSD Bus D Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb) : sel = 11..,3: chop == 1 ? sel = 10 (clk_reffb) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x4 0.--2. "SW_RETCC,Reference CAPDAC top plate to CSD Bus C Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_reffb) : sel = 11..,3: chop == 1 ? sel = 10 (clk_reffb) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),6: DFT mode (ph0 ? sel = 01 : sel = 00),?"
line.long 0x8 "SW_SEL_CDAC_CO,Compensation CAPDAC Switch Control"
bitfld.long 0x8 20.--22. "SW_COBG,Compensation CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp),4: DFT mode (ph1X ? sel = 01 : sel = 00),?,?,?"
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bitfld.long 0x8 16.--18. "SW_COBV,Compensation CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_comp),3: sel = 11 (!clk_comp),4: DFT mode (ph0X ? sel = 01 : sel = 00),?,?,?"
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bitfld.long 0x8 12.--14. "SW_COTG,Compensation CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x8 8.--10. "SW_COTV,Compensation CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 (clk_reffb),3: sel = 11 (!clk_reffb),4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x8 4.--6. "SW_COCB,Compensation CAPDAC to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp) : sel = 11..,3: chop == 1 ? sel = 10 (clk_comp) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0x8 0.--2. "SW_COTCA,Compensation CAPDAC top plate to CSD Bus A Switch." "0: sel = 00,1: sel = 01,2: chop == 0 ? sel = 10 (clk_comp) : sel = 11..,3: chop == 1 ? sel = 10 (clk_comp) : sel = 11..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),6: DFT mode (ph0 ? sel = 01 : sel = 00),?"
line.long 0xC "SW_SEL_CDAC_CF,Fine CAPDAC Switch Control"
bitfld.long 0xC 20.--22. "SW_CFBG,Fine CAPDAC bottom plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb) :..,3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb) :..,4: DFT mode (ph1X ? sel = 01 : sel = 00),?,?,?"
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bitfld.long 0xC 16.--18. "SW_CFBV,Fine CAPDAC bottom plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: FINE_MODE == REFERENCE ? sel = 10 (clk_reffb) :..,3: FINE_MODE == REFERENCE ? sel = 11 (!clk_reffb) :..,4: DFT mode (ph0X ? sel = 01 : sel = 00),?,?,?"
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bitfld.long 0xC 12.--14. "SW_CFTG,Fine CAPDAC top plate to vssa_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ? clk_reffb :..,3: sel = 11 [(FINE_MODE == REFERENCE) ? !clk_reffb..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0xC 8.--10. "SW_CFTV,Fine CAPDAC top plate to vdda_q Switch." "0: sel = 00,1: sel = 01,2: sel = 10 [(FINE_MODE == REFERENCE) ? clk_reffb :..,3: sel = 11 [(FINE_MODE == REFERENCE) ? !clk_reffb..,4: DFT mode (ph0 ? sel = 01 : sel = 00),5: DFT mode (ph2 ? sel = 01 : sel = 00),?,?"
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bitfld.long 0xC 4.--6. "SW_CFTCB,Fine CAPDAC top plate to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE} : sel = 11..,3: case({chop FINE_MODE}) {1 REFERENCE} : sel = 10..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),6: DFT mode (ph0 ? sel = 01 : sel = 00),?"
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bitfld.long 0xC 0.--2. "SW_CFTCA,Fine CAPDAC top plate to CSD Bus A Switch." "0: sel = 00,1: sel = 01,2: case({chop FINE_MODE}) {1 REFERENCE} : sel = 11..,3: case({chop FINE_MODE}) {1 REFERENCE} : sel = 10..,4: DFT mode (ph1 ? sel = 01 : sel = 00),5: DFT mode (ph3 ? sel = 01 : sel = 00),6: DFT mode (ph0 ? sel = 01 : sel = 00),?"
group.long 0x220++0x3
line.long 0x0 "SW_SEL_BGR,Bandgap Reference Switch Control"
bitfld.long 0x0 8. "SW_BGRMA,Connect buffered 1.2V reference to ADFT pin via AMUXBUSA. For DFT purposes." "0: N/A,1: N/A"
newline
bitfld.long 0x0 4. "SW_IGMA,Connect 48uA ganged IREF to ADFT pin via AMUXBUSA. For DFT purposes." "0: N/A,1: N/A"
newline
bitfld.long 0x0 0. "SW_BGRCM,BandGap reference to Comparator minus terminal switch." "0: N/A,1: N/A"
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "SW_SEL_CSW[$1],CapSense Sensor Switch Control"
bitfld.long 0x0 31. "DDRV_EN,MultiSense GPIO Sensor N digital driver enable in MSC specific GPIO." "0: N/A,1: N/A"
newline
bitfld.long 0x0 30. "REF_MODE,MultiSense GPIO Sensor N is used as a reference." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_PD,MultiSense GPIO Sensor N pull down to vssa_q Switch. Switch exists in MSC specific GPIO."
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_PU,MultiSense GPIO Sensor N pull up to vdda_q Switch. Switch exists in MSC specific GPIO. Also drives the MSC specific GPIO digital driver (enable controlled by DDRV_EN)."
newline
hexmask.long.byte 0x0 8.--11. 1. "SW_AMUXB,MultiSense GPIO Sensor N to AMUXBUSB Switch. Switch exists in MSC specific GPIO."
newline
hexmask.long.byte 0x0 0.--3. 1. "SW_AMUXA,MultiSense GPIO Sensor N to AMUXBUSA Switch. Switch exists in MSC specific GPIO."
repeat.end
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "SW_SEL_CSW_FUNC[$1],CapSense Sensor Switch Control Global Functions"
bitfld.long 0x0 31. "DDRV_EN,MultiSense GPIO Sensor N digital driver enable in MSC specific GPIO." "0: N/A,1: N/A"
newline
bitfld.long 0x0 30. "REF_MODE,MultiSense GPIO Sensor is used as a reference." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_PD,MultiSense GPIO Sensor pull down to vssa_q Switch. Switch exists in MSC specific GPIO."
newline
hexmask.long.byte 0x0 16.--19. 1. "SW_PU,MultiSense GPIO Sensor pull up to vdda_q Switch. Switch exists in MSC specific GPIO. Also drives the MSC specific GPIO digital driver (enable controlled by DDRV_EN)."
newline
hexmask.long.byte 0x0 8.--11. 1. "SW_AMUXB,MultiSense GPIO Sensor N to AMUXBUSB Switch. Switch exists in MSC specific GPIO."
newline
hexmask.long.byte 0x0 0.--3. 1. "SW_AMUXA,MultiSense GPIO Sensor to AMUXBUSA Switch. Switch exists in MSC specific GPIO."
repeat.end
group.long 0x500++0x7
line.long 0x0 "CSW_CTL_LO,CapSense Sensor Switch Control Low"
hexmask.long 0x0 0.--31. 1. "CSW_FUNC_MODE,Select between SW_SEL_CSW[x] and SW_SEL_CSW_FUNC."
line.long 0x4 "CSW_CTL_HI,CapSense Sensor Switch Control High"
hexmask.long 0x4 0.--31. 1. "CSW_FUNC_MODE,Select between SW_SEL_CSW[x] and SW_SEL_CSW_FUNC."
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40290600 ad:0x40290640 ad:0x40290680)
tree "MODE[$1]"
base $2
group.long ($2)++0x1B
line.long 0x0 "SENSE_DUTY_CTL,Sense Clock Duty Cycle Control"
bitfld.long 0x0 28. "PHASE_MODE_SEL,Select 4-phase or 2-phase mode." "0: Four phase,1: Two phase"
bitfld.long 0x0 24. "PHASE_SHIFT_EN,Enable phase shift logic that generates the Ph0X and Ph1X waveforms. Used for inductive and impedance sensing." "0: N/A,1: N/A"
newline
bitfld.long 0x0 10. "PHX_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0X/ph1X if the corresponding PHASE_GAP_*_EN is set." "0: N/A,1: N/A"
bitfld.long 0x0 9. "PHASE_GAP_PH1X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1x." "0: 1x cycle gap,1: 2x cycle gap"
newline
bitfld.long 0x0 8. "PHASE_GAP_PH0X_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0x." "0: 1x cycle gap,1: 2x cycle gap"
bitfld.long 0x0 6. "PH_GAP_2CYCLE_EN,If set applies a two cycle gap on ph0/ph1/ph2/ph3/Fs2_ph0/Fs2_ph1 if the corresponding PHASE_GAP_*_EN is set." "0: N/A,1: N/A"
newline
bitfld.long 0x0 5. "PHASE_GAP_FS2_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0." "0: 1x cycle gap,1: 2x cycle gap"
bitfld.long 0x0 4. "PHASE_GAP_FS2_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of Fs2_ph0." "0: 1x cycle gap,1: 2x cycle gap"
newline
bitfld.long 0x0 3. "PHASE_GAP_PH3_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph3." "0: 1x cycle gap,1: 2x cycle gap"
bitfld.long 0x0 2. "PHASE_GAP_PH2_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph2." "0: 1x cycle gap,1: 2x cycle gap"
newline
bitfld.long 0x0 1. "PHASE_GAP_PH1_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph1." "0: 1x cycle gap,1: 2x cycle gap"
bitfld.long 0x0 0. "PHASE_GAP_PH0_EN,Decide whether clk_mod cycle non-overlap gap is applied at the end of ph0." "0: 1x cycle gap,1: 2x cycle gap"
line.long 0x4 "SW_SEL_CDAC_FL,Flatspot/Dither CAPDAC Switch Control"
bitfld.long 0x4 31. "ACTIVATION_MODE,Activation event for Dither/Flatspot LFSR." "0: Clock LFSR on ph0,1: Clock LFSR on ph0 or ph2"
bitfld.long 0x4 20.--22. "SW_FLBG,Flatspot/Dither CAPDAC bottom plate to vssa_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
newline
bitfld.long 0x4 16.--18. "SW_FLBV,Flatspot/Dither CAPDAC bottom plate to vdda_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: [(msb^ph1)^(ph0||ph1)] & [ph0||ph1],5: (![(msb^ph1)^(ph0||ph1)]) & [ph0||ph1],6: [(msb^(ph2||ph3))^(ph0||ph2)] &..,7: (![(msb^(ph2||ph3))^(ph0||ph2)]) &.."
bitfld.long 0x4 12.--14. "SW_FLTG,Flatspot/Dither CAPDAC top plate to vssa_q Switch." "0: N/A,1: N/A,2: N/A,3: N/A,4: DFT mode,5: DFT mode,?,?"
newline
bitfld.long 0x4 8.--9. "SW_FLTV,Flatspot/Dither CAPDAC top plate to vdda_q Switch." "0: N/A,1: N/A,2: DFT mode,3: DFT mode"
bitfld.long 0x4 4.--6. "SW_FLCB,Flatspot/Dither CAPDAC to CSD Bus B Switch." "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph3,3: chop == 1 ? ph3 : ph1,4: chop == 1 ? ph0 : ph1,5: chop == 1 ? ph1 : ph0,?,?"
newline
bitfld.long 0x4 0.--2. "SW_FLTCA,Flatspot/Dither CAPDAC top plate to CSD Bus A Switch." "0: N/A,1: N/A,2: chop == 1 ? ph1 : ph3,3: chop == 1 ? ph3 : ph1,4: chop == 1 ? ph0 : ph1,5: chop == 1 ? ph1 : ph0,?,?"
line.long 0x8 "SW_SEL_TOP,Top Level Switch Control"
bitfld.long 0x8 31. "MBF,AMUXBUSB to Filter Switch" "0: N/A,1: N/A"
bitfld.long 0x8 24.--25. "RMF,Ratiometric Reference to Filter Switch. Connect a tap off from the resistor divider to the input of the RC filter. This tap off point is programmable." "0: Resistor divider off.,1: vdda/2,2: vdda*0.3 (Used to detect when vdda=4V then..,3: vdda*0.8"
newline
bitfld.long 0x8 20. "BGRF,Bandgap Reference to Filter Switch" "0: N/A,1: N/A"
bitfld.long 0x8 16.--17. "BYB,AMUXBUS B to CSD Bus B Switch." "0: sel = 00,1: sel = 01,2: sel = 10,3: sel = 11"
newline
bitfld.long 0x8 15. "AYB_EN,AMUXBUS A to CSD Bus B Switch. Controls first part of AYB switch (AYB_EN<0> on the hardIP)." "0: Opens first part of AYB switch. Enables..,1: Closes first part of AYB switch and disables.."
bitfld.long 0x8 12.--14. "AYB_CTL,AMUXBUS A to CSD Bus B Switch. Controls second part of AYB switch (AYB_EN<1> on hardIP)." "0: Opens second part of AYB switch. Enables..,1: N/A,2: chop == 0 ? ph1 : ph0,3: chop == 0 ? ph3 : ph1,4: chop == 0 ? ph1 : ph3,5: chop == 0 ? ph0 : ph1,6: N/A,7: N/A"
newline
bitfld.long 0x8 11. "AYA_EN,AMUXBUS A to CSD Bus A Switch. Controls the first part of AYA switch (AYA_EN<0> on the hardIP)." "0: Opens first part of AYA switch. Enables..,1: Closes first part of AYA switch and disables.."
bitfld.long 0x8 8.--10. "AYA_CTL,AMUXBUS A to CSD Bus A Switch. Controls second part of AYA switch (AYA_EN<1> on hardIP)." "0: Opens second part of AYA switch. Enables..,1: N/A,2: chop == 0 ? ph0 : ph1,3: chop == 0 ? ph1 : ph3,4: chop == 0 ? ph3 : ph1,5: chop == 0 ? ph1 : ph0,6: N/A,7: N/A"
newline
bitfld.long 0x8 4. "CBCD,CSD Bus B to CSD Bus D Switch." "0: N/A,1: N/A"
bitfld.long 0x8 2. "CACC,CSD Bus A to CSD Bus C Switch." "0: N/A,1: N/A"
newline
bitfld.long 0x8 0. "CACB,CSD Bus A to CSD Bus B Switch." "0: N/A,1: N/A"
line.long 0xC "SW_SEL_COMP,MSC Comparator Switch Control"
bitfld.long 0xC 31. "HALF_WAVE_EN,Enables halfwave mode in the comparator where reference is vdda_q." "0: N/A,1: N/A"
bitfld.long 0xC 22. "CMF,Comparator Minus Terminal to Reference Filter Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 20. "CMG,Comparator Minus Terminal to vssa_q Switch." "0: N/A,1: N/A"
bitfld.long 0xC 18. "CMV,Comparator Minus Terminal to vdda_q Switch." "0: N/A,1: N/A"
newline
bitfld.long 0xC 16. "CMCS4,Comparator Minus Terminal to CMOD4 Sense Switch" "0: N/A,1: N/A"
bitfld.long 0xC 14. "CMCS2,Comparator Minus Terminal to CMOD2 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 12. "CPF,Comparator Plus Terminal to Reference Filter Switch" "0: N/A,1: N/A"
bitfld.long 0xC 10. "CMCB,Comparator Minus Terminal to CSD Bus B Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 8. "CPCB,Comparator Plus Terminal to CSD Bus B Switch" "0: N/A,1: N/A"
bitfld.long 0xC 6. "CPCA,Comparator Plus Terminal to CSD Bus A Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 4. "CPMA,Comparator Plus Terminal to AMUXBUSA Switch" "0: N/A,1: N/A"
bitfld.long 0xC 2. "CPCS3,Comparator Plus Terminal to CMOD3 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0xC 0. "CPCS1,Comparator Plus Terminal to CMOD1 Sense Switch" "0: N/A,1: N/A"
line.long 0x10 "SW_SEL_SH,Shielding Switch Control"
bitfld.long 0x10 31. "BUF_EN,Enable the shield buffer." "0: Off,1: On"
hexmask.long.byte 0x10 24.--27. 1. "BUF_SEL,Selects value of compensation capacitance in shield buffer."
newline
bitfld.long 0x10 16. "FSP,Reference Filter to Shield Positive Terminal Switch" "0: N/A,1: N/A"
bitfld.long 0x10 14. "SPCS3,Shield Positive Terminal to CMOD3 Sense Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 12. "SPCS1,Shield Positive Terminal to CMOD1 Sense Switch" "0: N/A,1: N/A"
bitfld.long 0x10 10. "CBSO,CSD Bus B to Shield OpAmp Switch" "0: N/A,1: N/A"
newline
bitfld.long 0x10 8. "SOMB,Shield OpAmp to AMUXBUSB Switch." "0: N/A,1: N/A"
line.long 0x14 "SW_SEL_CMOD1,CMOD Switch Control 1"
bitfld.long 0x14 31. "DDRV_EN,CMOD1 digital driver enable in MSC specific GPIO." "0: N/A,1: N/A"
bitfld.long 0x14 30. "REF_MODE,CMOD1 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x14 24.--27. 1. "SW_PD,CMOD1 to vssa_q Switch. Switch exists in MSC specific GPIO."
hexmask.long.byte 0x14 16.--19. 1. "SW_PU,CMOD1 to vdda_q Switch. Switch exists in MSC specific GPIO. Also drives the MSC specific GPIO digital driver (enable controlled by DDRV_EN)."
newline
hexmask.long.byte 0x14 8.--11. 1. "SW_AMUXB,CMOD1 to AMUXBUSB Switch. Switch exists in MSC specific GPIO."
bitfld.long 0x14 6. "SW_C1CC,CMOD1 to CSD Bus C Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
newline
bitfld.long 0x14 4. "SW_C1CA,CMOD1 to CSD Bus A Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
hexmask.long.byte 0x14 0.--3. 1. "SW_AMUXA,CMOD1 to AMUXBUSA Switch. Switch exists in MSC specific GPIO."
line.long 0x18 "SW_SEL_CMOD2,CMOD Switch Control 2"
bitfld.long 0x18 31. "DDRV_EN,CMOD2 digital driver enable in MSC specific GPIO." "0: N/A,1: N/A"
bitfld.long 0x18 30. "REF_MODE,CMOD2 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x18 24.--27. 1. "SW_PD,CMOD2 to vssa_q Switch. Switch exists in MSC specific GPIO."
hexmask.long.byte 0x18 16.--19. 1. "SW_PU,CMOD2 to vdda_q Switch. Switch exists in MSC specific GPIO. Also drives the MSC specific GPIO digital driver (enable controlled by DDRV_EN)."
newline
bitfld.long 0x18 14. "SW_C2CD,CMOD2 to CSD Bus D Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
bitfld.long 0x18 12. "SW_C2CB,CMOD2 to CSD Bus B Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x18 8.--11. 1. "SW_AMUXB,CMOD2 to AMUXBUSB Switch. Switch exists in MSC specific GPIO."
hexmask.long.byte 0x18 0.--3. 1. "SW_AMUXA,CMOD2 to AMUXBUSA Switch. Switch exists in MSC specific GPIO."
group.long ($2+0x20)++0x7
line.long 0x0 "SW_SEL_CMOD3,CMOD Switch Control 3"
bitfld.long 0x0 31. "DDRV_EN,CMOD3 digital driver enable in MSC specific GPIO." "0: N/A,1: N/A"
bitfld.long 0x0 30. "REF_MODE,CMOD3 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x0 24.--27. 1. "SW_PD,CMOD3 to vssa_q Switch. Switch exists in MSC specific GPIO."
hexmask.long.byte 0x0 16.--19. 1. "SW_PU,CMOD3 to vdda_q Switch. Switch exists in MSC specific GPIO. Also drives the MSC specific GPIO digital driver (enable controlled by DDRV_EN)."
newline
hexmask.long.byte 0x0 8.--11. 1. "SW_AMUXB,CMOD3 to AMUXBUSB Switch. Switch exists in MSC specific GPIO."
bitfld.long 0x0 6. "SW_C3CC,CMOD3 to CSD Bus C Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
newline
bitfld.long 0x0 4. "SW_C3CA,CMOD3 to CSD Bus A Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
hexmask.long.byte 0x0 0.--3. 1. "SW_AMUXA,CMOD3 to AMUXBUSA Switch. Switch exists in MSC specific GPIO."
line.long 0x4 "SW_SEL_CMOD4,CMOD Switch Control 4"
bitfld.long 0x4 31. "DDRV_EN,CMOD4 digital driver enable in MSC specific GPIO." "0: N/A,1: N/A"
bitfld.long 0x4 30. "REF_MODE,CMOD4 is used as a reference in scenario where CMOD can be re-purposed when not used as a CMOD." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x4 24.--27. 1. "SW_PD,CMOD4 to vssa_q Switch. Switch exists in MSC specific GPIO."
hexmask.long.byte 0x4 16.--19. 1. "SW_PU,CMOD4 to vdda_q Switch. Switch exists in MSC specific GPIO. Also drives the MSC specific GPIO digital driver (enable controlled by DDRV_EN)."
newline
bitfld.long 0x4 14. "SW_C4CD,CMOD4 to CSD Bus D Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
bitfld.long 0x4 12. "SW_C4CB,CMOD4 to CSD Bus B Switch. Switch exists in MSCv3LP hard IP." "0: N/A,1: N/A"
newline
hexmask.long.byte 0x4 8.--11. 1. "SW_AMUXB,CMOD4 to AMUXBUSB Switch. Switch exists in MSC specific GPIO."
hexmask.long.byte 0x4 0.--3. 1. "SW_AMUXA,CMOD4 to AMUXBUSA Switch. Switch exists in MSC specific GPIO."
tree.end
repeat.end
base ad:0x40290000
tree "SNS (Sensor Configuration Structure)"
base ad:0x40292000
repeat 1024. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "SENSOR_DATA[$1],Sensor Configuration Storage"
hexmask.long 0x0 0.--31. 1. "DATA,Local IP storage to support per-sensor configuration and results for AS-MS/LP-AoS mode. The per sensor registers all have the prefix SNS_* in the SNS_STRUCTLP register tab."
repeat.end
group.long 0x1000++0x37
line.long 0x0 "SNS_LP_AOS_SNS_CTL0,LP-AoS Sensor Control 0"
hexmask.long.byte 0x0 24.--31. 1. "BL_UPDATE_DELAY,Specifies the value from which BL_UPDATE_TMR is decremented from on consecutive scans where the baseline update IIR produces a zero. Used to enable a bucket filter at a programmable tuning rate."
newline
hexmask.long.byte 0x0 16.--21. 1. "LOW_BL_RESET,Specifies the value from which BL_RESET_TMR is decremented from on consecutive scans where diff as per SIGNAL_TYPE is below NOISE_THR and -diff is above NOISE_THR_NEG."
newline
hexmask.long.byte 0x0 8.--11. 1. "BL_COEFF_FAST,Baseline update IIR coefficient when baseline update state is fast."
newline
hexmask.long.byte 0x0 4.--7. 1. "BL_COEFF_SLOW,Baseline update IIR coefficient when baseline update state is slow."
newline
hexmask.long.byte 0x0 0.--3. 1. "RC_COEFF,Raw count filter coefficient."
line.long 0x4 "SNS_LP_AOS_SNS_CTL1,LP-AoS Sensor Control 1"
hexmask.long.word 0x4 16.--31. 1. "NOISE_THR_NEG,Sensor baseline negative noise threshold."
newline
hexmask.long.word 0x4 0.--15. 1. "NOISE_THR,Sensor baseline noise threshold."
line.long 0x8 "SNS_LP_AOS_SNS_CTL2,LP-AoS Sensor Control 2"
bitfld.long 0x8 24. "SIGNAL_TYPE,Setting that specifies whether the raw counts increase or decrease when the sensor is excited by an event (e.g. when a finger approaches a sensor - if self-cap sensing is used the raw counts increase but if mutual-cap sensing is used the.." "0: Positive,1: Negative"
newline
bitfld.long 0x8 16.--18. "DEBOUNCE_THRESHOLD,Global threshold for successive SIGNAL_THR exceeds to warrant a full system wakeup." "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x8 0.--15. 1. "SIGNAL_THR,Per sensor threshold for |baseline - rawCount| to warrant a signal detect."
line.long 0xC "SNS_LP_AOS_SNS_CTL3,LP-AoS Sensor Control 3"
hexmask.long.byte 0xC 24.--31. 1. "BL_UPDATE_TMR,Sensor baseline update timer. Decremented from BL_UPDATE_DELAY on consecutive scans where the baseline update IIR produces a zero. Used to enable a bucket filter."
newline
hexmask.long.tbyte 0xC 0.--23. 1. "SNS_FRC_SCALED,Sensor raw count filter IIR state (filtered raw count scaled)."
line.long 0x10 "SNS_LP_AOS_SNS_CTL4,LP-AoS Sensor Control 4"
bitfld.long 0x10 24.--26. "SIG_DEBOUNCE_TMR,Sensor signal detect debounce timer. Decremented from DEBOUNCE_THRESHOLD on consecutive scans with a signal detection." "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x10 16.--21. 1. "BL_RESET_TMR,Sensor low baseline reset timer. Decremented from LOW_BL_RESET tuning parameter on consecutive scans where diff as per SIGNAL_TYPE is below NOISE_THR and -diff is above NOISE_THR_NEG."
newline
hexmask.long.word 0x10 0.--15. 1. "SNS_BL,Sensor baseline value."
line.long 0x14 "SNS_SW_SEL_CSW_HI_MASK2,CapSense Sensor Switch Function Select High Mask 2"
hexmask.long 0x14 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_HI_MASK2.FUNC_MASK[x] "
line.long 0x18 "SNS_SW_SEL_CSW_HI_MASK1,CapSense Sensor Switch Function Select High Mask 1"
hexmask.long 0x18 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_HI_MASK2.FUNC_MASK[x] "
line.long 0x1C "SNS_SW_SEL_CSW_HI_MASK0,CapSense Sensor Switch Function Select High Mask 0"
hexmask.long 0x1C 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_HI_MASK2.FUNC_MASK[x] "
line.long 0x20 "SNS_SW_SEL_CSW_LO_MASK2,CapSense Sensor Switch Function Select Low Mask 2"
hexmask.long 0x20 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_LO_MASK2.FUNC_MASK[x] "
line.long 0x24 "SNS_SW_SEL_CSW_LO_MASK1,CapSense Sensor Switch Function Select Low Mask 1"
hexmask.long 0x24 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_LO_MASK2.FUNC_MASK[x] "
line.long 0x28 "SNS_SW_SEL_CSW_LO_MASK0,CapSense Sensor Switch Function Select Low Mask 0"
hexmask.long 0x28 0.--31. 1. "FUNC_MASK,{SNS_SW_SEL_CSW_LO_MASK2.FUNC_MASK[x] "
line.long 0x2C "SNS_SCAN_CTL,Sensor Scan Control"
hexmask.long.byte 0x2C 28.--31. 1. "CIC2_SHIFT,Programmable shift to allow averaging of the CIC2 subsample accumulator (25-bits) to produce the reported raw count result in the result FIFO."
newline
hexmask.long.word 0x2C 16.--27. 1. "COMP_DIV,The ratio (minus 1) of clk_comp::clk_mod."
newline
bitfld.long 0x2C 15. "INIT_BYPASS,Coarse initialisation bypass control. Applies to CMOD_SEL selected Cmod." "0: N/A,1: N/A"
newline
bitfld.long 0x2C 14. "NUM_CONV,Number of conversions (minus 1) per scanned sample. This is required for chopping (chop polarity is updated per conversion)." "0: N/A,1: N/A"
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hexmask.long.word 0x2C 0.--13. 1. "NUM_SUB_CONVS,Number of sub-conversions (minus 1) in a conversion."
line.long 0x30 "SNS_CDAC_CTL,Sensor CAPDAC Control"
bitfld.long 0x30 31. "LFSR_SCALE_TYPE_FL,Flatspot/Dither CAPDAC shift direction." "0: N/A,1: N/A"
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bitfld.long 0x30 28.--30. "LFSR_SCALE_FL,Shift the magnitude portion of the Flatspot/Dither CAPDAC LFSR output code left or right by LSFR_SCALE_FL bits. Direction of shift controlled by LFSR_SCALE_TYPE_FL." "?,?,?,?,?,?,6: N/A,?"
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bitfld.long 0x30 26. "COMP_BLANKING_EN,Compensation blanking control. Type of blanking controlled by COMP_BLANKING_MODE." "0: N/A,1: N/A"
newline
bitfld.long 0x30 23.--24. "FL_MODE,Dither/Flatspot LFSR enable control." "0: Dither/Flatspot LFSR is disabled,1: The Dither/Flatspot LFSR is enabled,2: Dither/Flatspot LFSR is used as an offset,?"
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bitfld.long 0x30 22. "CLOCK_REF_RATE,Used to select clk_mod or clk_mod/2 to as clk_ref. This clock is gated depending on the synchronised comparator to generate the gated feedback clock (clk_reffb) to the Reference CAPDAC." "0: Use clk_mod,1: Use clk_mod/2"
newline
bitfld.long 0x30 21. "FINE_MODE,Operational mode for Fine CAPDAC" "0: N/A,1: N/A"
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hexmask.long.byte 0x30 16.--20. 1. "SEL_CF,Select value for Fine CAPDAC size."
newline
hexmask.long.byte 0x30 8.--15. 1. "SEL_CO,Select value for Compensation CAPDAC size."
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hexmask.long.byte 0x30 0.--7. 1. "SEL_RE,Select value for Reference CAPDAC size."
line.long 0x34 "SNS_CTL,Sense Control and Command Register"
bitfld.long 0x34 30.--31. "LFSR_BITS,Selects the number of LSB bits to use from the LSFR to provide the clock dithering variation on the base period (spread spectrum mode)." "0: Use 2 bits: range = [-2 1],1: Use 3 bits: range = [-4 3],2: Use 4 bits: range = [-8 7],3: Use 5 bits: range = [-16 15] (default)"
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bitfld.long 0x34 28.--29. "LFSR_MODE,Mode for generating the sense clock." "0: Direct Clocking,1: Spread Spectrum,2: PRS,?"
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hexmask.long.word 0x34 16.--27. 1. "SENSE_DIV,The length (minus 1) of the sense modulation 'clock' period in clk_mod cycles (frequency = Fs). SENSE_DIV + 1 = sense_ratio = Kref."
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hexmask.long.byte 0x34 8.--15. 1. "DECIM_RATE,Sets the decimation rate for the sinc^2 filter (CIC2). Typically referred to as N. Note N = DECIM_RATE + 1. Only applies when FILTER_CTL.FILTER_MODE = CIC2 and irrelevant for CIC1 mode (no effect in this mode)."
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bitfld.long 0x34 6.--7. "SENSE_MODE_SEL,Sense mode register structure selection. This field allows quick change between registers that influence sense mode. This register selects which structure is currently 'live' and used by the IP." "0: Use MODE_STRUCT[0].,1: Use MODE_STRUCT[1].,2: Use MODE_STRUCT[2].,3: Use MODE_STRUCT[3]."
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bitfld.long 0x34 4.--5. "MULTI_CH_MODE,Multi channel mode configuration. Determines whether consensus mechanism is engaged to ensure channels scan in lockstep." "0: Single channel,1: Wait for internal sync,2: Wait for external sync,?"
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bitfld.long 0x34 2. "LAST,Indicator that current sensor configuration is the last sensor in the frame." "0,1"
newline
bitfld.long 0x34 1. "VALID,Indicator of sensor configuration validity." "0,1"
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bitfld.long 0x34 0. "START_SCAN,Start the MSCv3 sequencer scan process. The sequencer will clear this bit when it is done. Depending on the mode the sequencer is done when all NUM_SAMPLES for this scan have been accumulated or if the sequencer is reset." "0,1"
rgroup.long 0x1200++0x3
line.long 0x0 "RESULT_FIFO_RD,Result FIFO Pointer"
bitfld.long 0x0 24.--25. "BAD_CONV_COUNT,Counter to indicate whether conversion of a sample is bad at the end of each chop phase. This is true if the comparator has not tripped by the end of EPILOGUE in a chop phase." "0,1,2,3"
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bitfld.long 0x0 20.--22. "RESAMPLE_COUNT,Counter indicating number of attempted re-samples (via NUM_AUTO_RESAMPLE) for this raw count." "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18. "CIC2_SUBSAMPLE_COUNT_OVERFLOW,CIC2 subsample counter overflow for NUM_CIC2_SUB_SAMPLES." "0,1"
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bitfld.long 0x0 17. "CIC2_ACC_OVERFLOW,CIC2 subsample accumulator overflow as defined by RAW_COUNT_MODE." "0,1"
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bitfld.long 0x0 16. "OVERFLOW,RAW_COUNT overflow." "0,1"
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hexmask.long.word 0x0 0.--15. 1. "RAW_COUNT,FILTER_MODE = CIC1: Accumulated raw count for a sample (post raw count filtering if RCF_EN = 1 and CE_CTL.ENABLED = 1)."
rgroup.long 0x1400++0x1F
line.long 0x0 "STATUS1,General Status Register 1"
hexmask.long.word 0x0 16.--31. 1. "RAW_COUNT_POS,Useful for determining component counts for positive and negative charge by subtracting from RAW_COUNT."
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hexmask.long.word 0x0 0.--15. 1. "RAW_COUNT,Live current raw counter (pre any Channel Engine raw count filtering). For debug/test purposes. In normal operation Firmware/DMA will typically read results from RESULT_FIFO_RD. The result FIFO value has accounted for Channel Engine raw count.."
line.long 0x4 "STATUS2,General Status Register 2"
hexmask.long.word 0x4 0.--15. 1. "DEBUG_CONV_COUNT,Debug raw count for a particular conversion. Enabled only during a specified conversion of a sample (a specific chop phase)."
line.long 0x8 "STATUS3,General Status Register 3"
bitfld.long 0x8 28. "MSC_CMP_OUT,Output of main sensing comparator (synchronized). For debug/test purposes." "0,1"
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bitfld.long 0x8 24. "FS_CLOCK,Sense clock Fs control waveform. For debug/test purposes." "0,1"
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hexmask.long.byte 0x8 16.--20. 1. "SEQ_STATE,MSC Sequencer FSM state."
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hexmask.long.word 0x8 0.--13. 1. "NUM_SUB_CONVS,Number of sub-conversions remaining while in PRO_DUMMY and SUB_CONV."
line.long 0xC "STATUS4,General Status Register 4"
hexmask.long.word 0xC 0.--8. 1. "NUM_CIC2_SUB_SAMPLES,Number of valid sub-samples produced by the CIC2 filter (saturates at 0x1FF and overflow flagged via CIC2_SUBSAMPLE_COUNT_OVERFLOW). This register is useful for firmware in the case of spread spectrum or PRS clocking where the number.."
line.long 0x10 "RESULT_FIFO_STATUS,Result FIFO Status"
hexmask.long.word 0x10 16.--25. 1. "SCAN_IDX,Scan index counter within a frame."
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hexmask.long.word 0x10 0.--10. 1. "USED,Number of used/occupied entries in the result FIFO. When '0' the FIFO is empty."
line.long 0x14 "RESULT_FIFO_STATUS2,Result FIFO Status 2"
bitfld.long 0x14 31. "FIFO_OVERFLOW,Set if hardware attempts to write a RAW_COUNT (and associated metrics) to an already full result FIFO." "0,1"
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bitfld.long 0x14 30. "FIFO_UNDERFLOW,Hardware sets this field to '1' when reading from an empty FIFO (RESULT_FIFO_STATUS.USED is '0')." "0,1"
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hexmask.long.word 0x14 16.--25. 1. "RD_PTR,Result FIFO read pointer: FIFO location from which data is read via AHB."
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hexmask.long.word 0x14 0.--9. 1. "WR_PTR,Result FIFO write pointer: FIFO location at which a new data is written by the hardware."
line.long 0x18 "CE_STATUS,Channel Engine Status"
bitfld.long 0x18 24. "SIG_STATE,Current sensor signal state." "0,1"
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bitfld.long 0x18 20.--21. "BL_STATE,Channel Engine baseline update state." "0: Initialise baseline to raw count.,1: Slow baseline update when raw count minus..,2: Fast baseline update when baseline minus raw..,?"
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hexmask.long.tbyte 0x18 0.--16. 1. "BL_DELTA,Current value of Channel Engine baseline update delta (int17 format)."
line.long 0x1C "BRIDGE_STATUS,AHB2AHB Bridge Status"
bitfld.long 0x1C 0. "READY,Status bit to indicate that the logic behind the AHB2AHB bridge has fully completed the side effect of all buffered write transactions. The bridge itself enforces buffered writes regardless of AHB hprot[3:0]." "0,1"
group.long 0x1800++0xB
line.long 0x0 "FRAME_CMD,Frame Command Register"
bitfld.long 0x0 0. "START_FRAME,Start the MSCv3 sequencer frame process. Note that a rising edge on this bit also creates a 4x cycle clk_msc pulse on the msc_ext_frm_start_out signal (when EXT_FRAME_START_MODE = DISABLED). The corresponding msc_ext_frm_start_out_en is.." "0,1"
line.long 0x4 "CE_CMD,Channel Engine Command"
bitfld.long 0x4 16. "CE_START,Initiates Channel Engine processing if CE_TEST_MODE = 1." "0,1"
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hexmask.long.word 0x4 0.--15. 1. "TEST_RAW_COUNT,Firmware settable raw count for Channel Engine when CE_TEST_MODE = 1."
line.long 0x8 "FIFO_CMD,FIFO Command"
bitfld.long 0x8 0. "FIFO_RESET,Initiate a reset of the result FIFO." "0,1"
group.long 0x1C00++0x3
line.long 0x0 "CE_INIT_CTL,Channel Engine Initialisation Control"
bitfld.long 0x0 0. "SENSOR_INIT,Set by firmware when hardware initialisation of the raw count filter and baselines is required for the first frame after FRAME_START_AOS FRAME_START or an external frame start detected. Hardware clears this bit down at the end of this frame." "0: N/A,1: N/A"
tree.end
base ad:0x40290000
group.long 0xFF00++0x1B
newline
line.long 0x0 "TRIM_CTL,Trim Control"
bitfld.long 0x0 5. "TRIM_POLARITY,Controls polarity of comparator offset trim." "0,1"
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bitfld.long 0x0 4. "TRIM_EN,Enables comparator offset trim." "0: N/A,1: N/A"
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hexmask.long.byte 0x0 0.--3. 1. "TRIM_IN,Controls magnitude of comparator offset trim."
line.long 0x4 "CLK_IMO_TRIM1,Local IMO Trim Register 1"
hexmask.long.byte 0x4 0.--7. 1. "OFFSET,Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting (CLK_IMO_TRIM2) and stored in SFLASH. This field is mapped to the most significant bits of the IMO trim imo_clk_trim[10:3]. The step size of 1 LSB on this.."
line.long 0x8 "CLK_IMO_TRIM2,Local IMO Trim Register 2"
bitfld.long 0x8 0.--2. "FSOFFSET,Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is mapped to the least significant bits of the IMO trim imo_clk_trim[2:0]. The step size of 1 LSB on this field is.." "0,1,2,3,4,5,6,7"
line.long 0xC "CLK_IMO_TRIM3,Local IMO Trim Register 3"
bitfld.long 0xC 0.--1. "TCTRIM,IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence. This bits are dependent on frequency and need to be changed using the provided frequency change algorithm." "0,1,2,3"
line.long 0x10 "PWR_BG_TRIM1,Bandgap Trim Register 1"
hexmask.long.byte 0x10 0.--5. 1. "REF_VTRIM,Trims the bandgap reference voltage output. Used to trim the VBG to the voltage where its temperature curvature is minimal. Bit [5] is unused within the bandgap block."
line.long 0x14 "PWR_BG_TRIM2,Bandgap Trim Register 2"
hexmask.long.byte 0x14 0.--5. 1. "REF_ITRIM,Trims the bandgap reference current output. Used to trim the IBG to the voltage where its temperature curvature is minimal."
line.long 0x18 "PWR_BG_TRIM3,Bandgap Trim Register 3"
hexmask.long.byte 0x18 0.--3. 1. "REF_TCTRIM,Active-Reference temperature compensation trim (repurposed from spare bits)."
tree.end
tree "PERI (Peripheral Interconnect)"
base ad:0x40010000
group.long 0x0++0x3
line.long 0x0 "DIV_CMD,Divider command register"
bitfld.long 0x0 31. "ENABLE,Clock divider enable command (mutually exclusive with DISABLE). Typically SW sets this field to '1' to enable a divider and HW sets this field to '0' to indicate that divider enabling has completed. When a divider is enabled its integer and.." "0: Disable the divider using the DIV_CMD,1: Configure the divider's DIV_XXX_CTL register"
bitfld.long 0x0 30. "DISABLE,Clock divider disable command (mutually exclusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'." "0,1"
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bitfld.long 0x0 14.--15. "PA_SEL_TYPE,Specifies the divider type of the divider to which phase alignment is performed for the clock enable command:" "0: 8,1: 16,2: 16,3: 24"
hexmask.long.byte 0x0 8.--13. 1. "PA_SEL_DIV,(PA_SEL_TYPE PA_SEL_DIV) specifies the divider to which phase alignment is performed for the clock enable command. Any enabled divider can be used as reference. This allows all dividers to be aligned with each other even when they are.."
newline
bitfld.long 0x0 6.--7. "SEL_TYPE,Specifies the divider type of the divider on which the command is performed:" "0: 8,1: 16,2: 16,3: 24"
hexmask.long.byte 0x0 0.--5. 1. "SEL_DIV,(SEL_TYPE SEL_DIV) specifies the divider on which the command (DISABLE/ENABLE) is performed."
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x100)++0x3
line.long 0x0 "PCLK_CTL[$1],Programmable clock control register"
bitfld.long 0x0 6.--7. "SEL_TYPE,Specifies divider type:" "0: 8,1: 16,2: 16,3: 24"
hexmask.long.byte 0x0 0.--5. 1. "SEL_DIV,Specifies one of the dividers of the divider type specified by SEL_TYPE."
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x200)++0x3
line.long 0x0 "DIV_8_CTL[$1],Divider control register (for 8.0 divider)"
hexmask.long.byte 0x0 8.--15. 1. "INT8_DIV,Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1 256]. Note: this type of divider does NOT allow for a fractional division."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x300)++0x3
line.long 0x0 "DIV_16_CTL[$1],Divider control register (for 16.0 divider)"
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: this type of divider does NOT allow for a fractional division."
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 64. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x400)++0x3
line.long 0x0 "DIV_16_5_CTL[$1],Divider control register (for 16.5 divider)"
hexmask.long.word 0x0 8.--23. 1. "INT16_DIV,Integer division by (1+INT16_DIV). Allows for integer divisions in the range [1 65 536]. Note: combined with fractional division this divider type allows for a division in the range [1 65 536 31/32] in 1/32 increments."
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods."
newline
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
repeat 63. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2+0x500)++0x3
line.long 0x0 "DIV_24_5_CTL[$1],Divider control register (for 24.5 divider)"
hexmask.long.tbyte 0x0 8.--31. 1. "INT24_DIV,Integer division by (1+INT24_DIV). Allows for integer divisions in the range [1 16 777 216]. Note: combined with fractional division this divider type allows for a division in the range [1 16 777 216 31/32] in 1/32 increments."
hexmask.long.byte 0x0 3.--7. 1. "FRAC5_DIV,Fractional division by (FRAC5_DIV/32). Allows for fractional divisions in the range [0 31/32]. Note that fractional division results in clock jitter as some clock periods may be 1 'clk_hf' cycle longer than other clock periods."
newline
rbitfld.long 0x0 0. "EN,Divider enabled. HW sets this field to '1' as a result of an ENABLE command. HW sets this field to '0' as a result on a DISABLE command." "0,1"
repeat.end
group.long 0x600++0x3
line.long 0x0 "TR_CTL,Trigger control register"
bitfld.long 0x0 31. "TR_ACT,SW sets this field to '1' to activate (set to '1') a trigger as identified by TR_SEL and TR_OUT for TR_COUNT cycles. HW sets this field to '0' when the cycle counter is decremented to '0'. Note: a TR_COUNT value of 255 is a special case and.." "0,1"
bitfld.long 0x0 30. "TR_OUT,Specifies whether trigger activation is for a specific input or output trigger of the trigger multiplexer. Activation of a specific input trigger will result in activation of all output triggers that have the specific input trigger selected.." "0: TR_SEL selection and trigger activation is for..,1: TR_SEL selection and trigger activation is for.."
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hexmask.long.byte 0x0 16.--23. 1. "TR_COUNT,Amount of cycles a specific trigger is activated. During activation (TR_ACT is '1') HW decrements this field to '0' using a cycle counter. During activation SW should not modify this register field. A value of 255 is a special case: HW does.."
hexmask.long.byte 0x0 8.--11. 1. "TR_GROUP,Specifies the trigger group."
newline
hexmask.long.byte 0x0 0.--6. 1. "TR_SEL,Specifies the activated trigger when TR_ACT is '1'. TR_OUT specifies whether the activated trigger is an input trigger or output trigger to the trigger multiplexer. During activation (TR_ACT is '1') SW should not modify this register field. If.."
tree "TR_GROUP"
base ad:0x40012000
repeat 128. (increment 0x0 0x1)(increment 0x0 0x4)
group.long ($2)++0x3
line.long 0x0 "TR_OUT_CTL[$1],Trigger control register"
hexmask.long.byte 0x0 0.--6. 1. "SEL,Specifies input trigger. This field is typically set during the setup of a chip use case scenario. Changing this field while activated triggers are present on the input triggers may result in unpredictable behavior. Note that input trigger 0 (default.."
repeat.end
tree.end
tree.end
tree "SCB (Serial Communication Block (SPI/UART/I2C))"
base ad:0x0
tree "SCB0"
base ad:0x40240000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "?,?"
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
newline
bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
newline
hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
newline
bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
newline
hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
newline
bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: the SPI master MISO line 'spi_miso_in' is..,1: the SPI master MISO line 'spi_miso_in' is.."
newline
bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0: 1,1: 2"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0: 0,1: 1"
newline
bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0: 0,1: 1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
newline
bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0: high/'1' active precede/coincide pulse,1: low/'0' active precede/coincide pulse"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0: SCLK is generated,1: SCLK is generated"
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bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0: SCLK is '0' when not transmitting data,1: SCLK is '1' when not transmitting data"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0: MOSI is driven on a rising edge of SCLK,1: MOSI is driven on a falling edge of SCLK"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0: Disabled,1: Enabled"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0: CTS is low/'0' active,1: CTS is high/'1' active"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0: RTS is low/'0' active,1: RTS is high/'1' active"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0: 0 ns,1: 50 ns"
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bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
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bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0: 0 ns,1: 50 ns"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
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bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0: I2C Hs-mode is disabled,1: I2C Hs-mode is enabled"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
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bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
newline
bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0: # entries != FF_DATA_NR,1: # entries != FF_DATA_NR/2"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
newline
bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0: # entries == FF_DATA_NR,1: # entries == FF_DATA_NR/2"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree "SCB1"
base ad:0x40250000
group.long 0x0++0x3
line.long 0x0 "CTRL,Generic control"
bitfld.long 0x0 31. "ENABLED,IP enabled ('1') or not ('0'). The proper order in which to initialize the IP is as follows:" "0,1"
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bitfld.long 0x0 28. "EC_ACCESS,used to enable I2CS_EC or SPIS_EC access to internal SRAM memory." "0: enable clock_scb_en,1: disable clock_scb_en"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: Inter-Integrated Circuits (I2C) mode.,1: Serial Peripheral Interface (SPI) mode.,2: Universal Asynchronous Receiver/Transmitter..,?"
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bitfld.long 0x0 17. "BLOCK,Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0')." "?,?"
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bitfld.long 0x0 16. "ADDR_ACCEPT,Determines whether a received matching address is accepted in the RX FIFO ('1') or not ('0')." "0,1"
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bitfld.long 0x0 14.--15. "MEM_WIDTH,Determines the number of bits per FIFO data element depending on physical SRAM cell data width." "0: 8-bit FIFO data elements. This mode provides the..,1: 16-bit FIFO data elements. TX_CTRL.DATA_WIDTH..,2: 32-bit FIFO data elements. This mode provides..,3: N/A"
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bitfld.long 0x0 12. "CMD_RESP_MODE,Determines CMD_RESP mode of operation:" "0: CMD_RESP mode disabled,1: CMD_RESP mode enabled"
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bitfld.long 0x0 10. "EZ_MODE,Non EZ mode ('0') or EZ mode ('1'). In EZ mode a meta protocol is applied to the serial interface protocol. This meta protocol adds meaning to the data frames transferred by the serial interface protocol: a data frame can represent a memory.." "0,1"
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bitfld.long 0x0 9. "EC_OP_MODE,Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface protocols run off the clock as.." "0,1"
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bitfld.long 0x0 8. "EC_AM_MODE,Internally clocked mode ('0') or externally clocked mode ('1') address matching (I2C) or selection (SPI). In internally clocked mode the serial interface protocols run off the peripheral clock. In externally clocked mode the serial interface.." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "OVS,N/A"
rgroup.long 0x4++0x3
line.long 0x0 "STATUS,Generic status"
bitfld.long 0x0 0. "EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory (this is only possible in EZ mode). This bit can be used by SW to determine whether it is safe to issue a SW access to the EZ memory (without bus wait states (a.." "0,1"
group.long 0x8++0x3
line.long 0x0 "CMD_RESP_CTRL,Command/response control"
hexmask.long.word 0x0 16.--24. 1. "BASE_WR_ADDR,I2C/SPI write base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode write transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode write transfer (CTRL.MODE is SPI): at the start of a write transfer BASE_WE_ADDR is copied to.."
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hexmask.long.word 0x0 0.--8. 1. "BASE_RD_ADDR,I2C/SPI read base address for CMD_RESP mode. Address is used by a I2C CMD_RESP mode read transfer (CTRL.MODE is I2C) or a SPI CMD_RESP mode read transfer (CTRL.MODE is SPI): at the start of a read transfer BASE_RD_ADDR is copied to.."
rgroup.long 0xC++0x3
line.long 0x0 "CMD_RESP_STATUS,Command/response status"
bitfld.long 0x0 31. "CMD_RESP_EC_BUSY,Indicates whether the CURR_RD_ADDR and CURR_WR_ADDR fields in this register are reliable (when CMD_RESP_EC_BUSY is '0') or not reliable (when CMD_RESP_EC_BUSY is '1'). Note:" "0,1"
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bitfld.long 0x0 30. "CMD_RESP_EC_BUS_BUSY,Indicates whether there is an ongoing bus transfer to the IP." "0: no ongoing bus transfer,1: ongoing bus transfer"
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hexmask.long.word 0x0 16.--24. 1. "CURR_WR_ADDR,I2C/SPI write current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
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hexmask.long.word 0x0 0.--8. 1. "CURR_RD_ADDR,I2C/SPI read current address for CMD_RESP mode. HW increments the field after a read access to the memory buffer. However when the last memory buffer address is reached the address is NOT incremented (but remains at the maximum memory.."
group.long 0x20++0x3
line.long 0x0 "SPI_CTRL,SPI control"
bitfld.long 0x0 31. "MASTER_MODE,Master ('1') or slave ('0') mode. In master mode transmission will commence on availability of data frames in the TX FIFO. In slave mode when selected and there is no data frame in the TX FIFO the slave will transmit all '1's. In both.." "0,1"
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bitfld.long 0x0 26.--27. "SSEL,Selects one of the four incoming/outgoing SPI slave select signals:" "0: Slave 0,1: Slave 1,2: Slave 2,3: Slave 3"
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bitfld.long 0x0 24.--25. "MODE,N/A" "0: SPI Motorola submode. In master mode when not..,1: SPI Texas Instruments submode. In master mode..,2: SPI National Semiconductors submode. In master..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only used in master mode. Not used in National Semiconductors submode." "0: the SPI master MISO line 'spi_miso_in' is..,1: the SPI master MISO line 'spi_miso_in' is.."
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bitfld.long 0x0 14. "SSEL_INTER_FRAME_DEL,Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation)." "0: 1,1: 2"
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bitfld.long 0x0 13. "SSEL_HOLD_DEL,Indicates the SPI SELECT hold delay (between SPI clock edge to sample the last MOSI bit and SELECT deactivation)." "0: 0,1: 1"
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bitfld.long 0x0 12. "SSEL_SETUP_DEL,Indicates the SPI SELECT setup delay (between SELECT activation and SCLK clock edge to sample the first MOSI bit)." "0: 0,1: 1"
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bitfld.long 0x0 11. "SSEL_POLARITY3,Slave select polarity." "0,1"
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bitfld.long 0x0 10. "SSEL_POLARITY2,Slave select polarity." "0,1"
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bitfld.long 0x0 9. "SSEL_POLARITY1,Slave select polarity." "0,1"
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bitfld.long 0x0 8. "SSEL_POLARITY0,Slave select polarity. SSEL_POLARITY0 applies to the outgoing SPI slave select signal 0 (master mode) and to the incoming SPI slave select signal (slave mode). For Motorola and National Semiconductors submodes:" "0: high/'1' active precede/coincide pulse,1: low/'0' active precede/coincide pulse"
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bitfld.long 0x0 5. "SCLK_CONTINUOUS,Only applicable in master mode." "0: SCLK is generated,1: SCLK is generated"
newline
bitfld.long 0x0 4. "LATE_MISO_SAMPLE,Changes the SCLK edge on which MISO is captured. Only used in master mode." "0,1"
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bitfld.long 0x0 3. "CPOL,Indicates the clock polarity. This field together with the CPHA field indicates when MOSI data is driven and MISO data is captured:" "0: SCLK is '0' when not transmitting data,1: SCLK is '1' when not transmitting data"
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bitfld.long 0x0 2. "CPHA,Indicates the clock phase. This field together with the CPOL field indicates when MOSI data is driven and MISO data is captured:" "0: MOSI is driven on a rising edge of SCLK,1: MOSI is driven on a falling edge of SCLK"
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bitfld.long 0x0 1. "SELECT_PRECEDE,Only used in SPI Texas Instruments' submode." "0,1"
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bitfld.long 0x0 0. "SSEL_CONTINUOUS,Continuous SPI data transfers enabled ('1') or not ('0'). This field is used in master mode. In slave mode both continuous and non-continuous SPI data transfers are supported independent of this field." "0,1"
rgroup.long 0x24++0x3
line.long 0x0 "SPI_STATUS,SPI status"
hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,SPI base EZ address. Address as provided by a SPI write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the design."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,SPI current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when SPI_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 1. "SPI_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,SPI bus is busy. The bus is considered busy ('1') during an ongoing transaction. For Motorola and National submodes the busy bit is '1' when the slave selection is activated. For TI submode the busy bit is '1' from the time the.." "0,1"
group.long 0x28++0x7
line.long 0x0 "SPI_TX_CTRL,SPI transmitter control"
bitfld.long 0x0 16. "MOSI_IDLE_HIGH,SPI master MOSI output level when SELECT output inactive " "0: retain the level of last data bit,1: change to high"
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bitfld.long 0x0 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity." "0,1"
line.long 0x4 "SPI_RX_CTRL,SPI receiver control"
bitfld.long 0x4 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0')." "0,1"
newline
bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity." "0,1"
group.long 0x40++0xB
line.long 0x0 "UART_CTRL,UART control"
bitfld.long 0x0 24.--25. "MODE,N/A" "0: Standard UART submode.,1: SmartCard (ISO7816) submode. Support for..,2: Infrared Data Association (IrDA) submode. Return..,?"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). When '0' the transmitter TX line 'uart_tx_out' is connected to the TX pin and the receiver RX line 'uart_rx_in' is connected to the RX pin. When '1' the transmitter TX line.." "0,1"
line.long 0x4 "UART_TX_CTRL,UART transmitter control"
bitfld.long 0x4 8. "RETRY_ON_NACK,When '1' a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode." "0,1"
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bitfld.long 0x4 5. "PARITY_ENABLED,Parity generation enabled ('1') or not ('0'). Only applicable in standard UART submodes. In SmartCard submode parity generation is always enabled through hardware. In IrDA submode parity generation is always disabled through hardware" "0,1"
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bitfld.long 0x4 4. "PARITY,Parity bit. When '0' the transmitter generates an even parity. When '1' the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x4 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
line.long 0x8 "UART_RX_CTRL,UART receiver control"
bitfld.long 0x8 24. "BREAK_LEVEL,0: low level pulse detection like Break field in LIN protocol" "0: low level pulse detection,1: high level pulse detection"
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hexmask.long.byte 0x8 16.--19. 1. "BREAK_WIDTH,Break width. BREAK_WIDTH + 1 is the minimum width in bit periods of a break. During a break the transmitted/received line value is '0'. This feature is useful for standard UART submode and LIN submode ('break field' detection). Once the.."
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bitfld.long 0x8 13. "SKIP_START,Only applicable in standard UART submode. When '1' the receiver skips start bit detection for the first received data frame. Instead it synchronizes on the first received data frame bit which should be a '1'. This functionality is intended.." "0,1"
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bitfld.long 0x8 12. "LIN_MODE,Only applicable in standard UART submode. When '1' the receiver performs break detection and baud rate detection on the incoming data. First break detection counts the amount of bit periods that have a line value of '0'. BREAK_WIDTH specifies.." "0,1"
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bitfld.long 0x8 10. "MP_MODE,Multi-processor mode. When '1' multi-processor mode is enabled. In this mode RX_CTRL.DATA_WIDTH should indicate a 9-bit data frame. In multi-processor mode the 9th received bit of a data frame separates addresses (bit is '1') from data (bit is.." "0,1"
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bitfld.long 0x8 9. "DROP_ON_FRAME_ERROR,Behavior when an error is detected in a start or stop period. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost." "0,1"
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bitfld.long 0x8 8. "DROP_ON_PARITY_ERROR,Behavior when a parity check fails. When '0' received data is send to the RX FIFO. When '1' received data is dropped and lost. Only applicable in standard UART and SmartCard submodes (negatively acknowledged SmartCard data frames.." "0,1"
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bitfld.long 0x8 6. "POLARITY,Inverts incoming RX line signal 'uart_rx_in'. Inversion is after local loopback. This functionality is intended for IrDA receiver functionality." "0,1"
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bitfld.long 0x8 5. "PARITY_ENABLED,Parity checking enabled ('1') or not ('0'). Only applicable in standard UART submode. In SmartCard submode parity checking is always enabled through hardware. In IrDA submode parity checking is always disabled through hardware." "0,1"
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bitfld.long 0x8 4. "PARITY,Parity bit. When '0' the receiver expects an even parity. When '1' the receiver expects an odd parity. Only applicable in standard UART and SmartCard submodes." "0,1"
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bitfld.long 0x8 0.--2. "STOP_BITS,Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1 7]; i.e. a stop period should last at least one bit period." "0,1,2,3,4,5,6,7"
rgroup.long 0x4C++0x3
line.long 0x0 "UART_RX_STATUS,UART receiver status"
hexmask.long.word 0x0 0.--11. 1. "BR_COUNTER,Amount of peripheral clock periods that constitute the transmission of a 0x55 data frame (sent least significant bit first) as determined by the receiver. BR_COUNTER / 8 is the amount of peripheral clock periods that constitute a bit period."
group.long 0x50++0x3
line.long 0x0 "UART_FLOW_CTRL,UART flow control"
bitfld.long 0x0 25. "CTS_ENABLED,Enable use of CTS input signal 'uart_cts_in' by the UART transmitter:" "0: Disabled,1: Enabled"
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bitfld.long 0x0 24. "CTS_POLARITY,Polarity of the CTS input signal 'uart_cts_in':" "0: CTS is low/'0' active,1: CTS is high/'1' active"
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bitfld.long 0x0 16. "RTS_POLARITY,Polarity of the RTS output signal 'uart_rts_out':" "0: RTS is low/'0' active,1: RTS is high/'1' active"
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hexmask.long.byte 0x0 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has less entries than the amount of this field a Ready To Send (RTS) output signal 'uart_rts_out' is activated. By setting this field to '0' flow control is effectively SW disabled (may be useful for.."
group.long 0x60++0x3
line.long 0x0 "I2C_CTRL,I2C control"
bitfld.long 0x0 31. "MASTER_MODE,Master mode enabled ('1') or not ('0'). Note that both master and slave modes can be enabled at the same time. This allows the IP to address itself." "0,1"
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bitfld.long 0x0 30. "SLAVE_MODE,Slave mode enabled ('1') or not ('0')." "0,1"
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bitfld.long 0x0 16. "LOOPBACK,Local loopback control (does NOT affect the information on the pins). Only applicable in master/slave mode. When '0' the I2C SCL and SDA lines are connected to the I2C SCL and SDA pins. When '1' I2C SCL and SDA lines are routed internally in.." "0,1"
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bitfld.long 0x0 15. "S_NOT_READY_DATA_NACK,For internally clocked logic only. Only used when:" "0: clock stretching is performed,1: a received data element byte the slave is.."
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bitfld.long 0x0 14. "S_NOT_READY_ADDR_NACK,For internally clocked logic (EC_AM is '0' and EC_OP is '0') on an address match or general call address (and S_GENERAL_IGNORE is '0'). Only used when:" "0: clock stretching is performed,1: a received"
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bitfld.long 0x0 13. "S_READY_DATA_ACK,When '1' a received data element by the slave is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 12. "S_READY_ADDR_ACK,When '1' a received (matching) slave address is immediately ACK'd when the receiver FIFO is not full. In EZ mode this field should be set to '1'." "0,1"
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bitfld.long 0x0 11. "S_GENERAL_IGNORE,When '1' a received general call slave address is immediately NACK'd (no ACK or clock stretching) and treated as a non matching slave address. This is useful for slaves that do not need any data supplied within the general call structure." "0,1"
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bitfld.long 0x0 9. "M_NOT_READY_DATA_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 8. "M_READY_DATA_ACK,When '1' a received data element by the master is immediately ACK'd when the receiver FIFO is not full." "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LOW_PHASE_OVS,Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock periods constitute the low phase of a bit period. The valid range is [7 15] with input signal median filtering and [6 15] without input signal median.."
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hexmask.long.byte 0x0 0.--3. 1. "HIGH_PHASE_OVS,Serial I2C interface high phase oversampling factor. HIGH_PHASE_OVS + 1 peripheral clock periods constitute the high phase of a bit period. The valid range is [5 15] with input signal median filtering and [4 15] without input signal.."
rgroup.long 0x64++0x3
line.long 0x0 "I2C_STATUS,I2C status"
bitfld.long 0x0 24. "HS_MODE,this is to indicate I2C Hs-mode transfer " "0,1"
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hexmask.long.byte 0x0 16.--23. 1. "BASE_EZ_ADDR,I2C slave base EZ address. Address as provided by an I2C write transfer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable as clock domain synchronization is not performed in the.."
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hexmask.long.byte 0x0 8.--15. 1. "CURR_EZ_ADDR,I2C slave current EZ address. Current address pointer. This field is only reliable in internally clocked mode. In externally clocked mode the field may be unreliable (during an ongoing transfer when I2C_EC_BUSY is '1') as clock domain.."
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bitfld.long 0x0 5. "M_READ,I2C master read transfer ('1') or I2C master write transfer ('0'). When the I2C master is inactive/idle or transmitting START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 4. "S_READ,I2C slave read transfer ('1') or I2C slave write transfer ('0'). When the I2C slave is inactive/idle or receiving START REPEATED START STOP or an address this field is '0''." "0,1"
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bitfld.long 0x0 2. "I2CS_IC_BUSY,Indicates whether the internally clocked slave logic is being accessed by external I2C master." "0,1"
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bitfld.long 0x0 1. "I2C_EC_BUSY,Indicates whether the externally clocked logic is potentially accessing the EZ memory and/or updating BASE_EZ_ADDR or CURR_EZ_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_EZ_ADDR and.." "0,1"
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bitfld.long 0x0 0. "BUS_BUSY,I2C bus is busy. The bus is considered busy ('1') from the time a START is detected or from the time the SCL line is '0'. The bus is considered idle ('0') from the time a STOP is detected. If the IP is disabled BUS_BUSY is '0'. After enabling.." "0,1"
group.long 0x68++0xF
line.long 0x0 "I2C_M_CMD,I2C master command"
bitfld.long 0x0 4. "M_STOP,When '1' attempt to transmit a STOP. When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 3. "M_NACK,for I2C master the NACKed byte should be properly received. it write the data byte before ACK/NACK decision." "0,1"
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bitfld.long 0x0 2. "M_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'." "0,1"
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bitfld.long 0x0 1. "M_START_ON_IDLE,When '1' transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0' note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result bus idle detection is only.." "0,1"
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bitfld.long 0x0 0. "M_START,When '1' transmit a START or REPEATED START. Whether a START or REPEATED START is transmitted depends on the state of the master state machine. A START is only transmitted when the master state machine is in the default state. A REPEATED START.." "0,1"
line.long 0x4 "I2C_S_CMD,I2C slave command"
bitfld.long 0x4 8. "S_STRETCH_HS,When '1' attempt to stretch SCL at time t1 SCL falling edge after 'START Master-code NACK' pattern is detected." "0,1"
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bitfld.long 0x4 2. "S_TX_ONES_ON_EMPTY,When '1' attempt to send ones when TX_FIFO is empty." "0,1"
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bitfld.long 0x4 1. "S_NACK,When '1' attempt to transmit a negative acknowledgement (NACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode). This command has a higher.." "0,1"
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bitfld.long 0x4 0. "S_ACK,When '1' attempt to transmit an acknowledgement (ACK). When this action is performed the hardware sets this field to '0'. In EZ mode this field should be set to '0' (it is only to be used in non EZ mode)." "0,1"
line.long 0x8 "I2C_CFG,I2C configuration"
bitfld.long 0x8 28.--29. "SDA_OUT_FILT_SEL,Selection of cumulative 'i2c_sda_out' filter delay:" "0: 0 ns,1: 50 ns,2: 100 ns,3: 150 ns"
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bitfld.long 0x8 20.--21. "SDA_OUT_FILT2_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 2." "0,1,2,3"
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bitfld.long 0x8 18.--19. "SDA_OUT_FILT1_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 1." "0,1,2,3"
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bitfld.long 0x8 16.--17. "SDA_OUT_FILT0_TRIM,Trim bits for 'i2c_sda_out' 50 ns filter 0." "0,1,2,3"
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bitfld.long 0x8 12. "SCL_IN_FILT_SEL,Selection of 'i2c_scl_in' filter delay:" "0: 0 ns,1: 50 ns"
newline
bitfld.long 0x8 8.--9. "SCL_IN_FILT_TRIM,Trim bits for 'i2c_scl_in' 50 ns filter." "0,1,2,3"
newline
bitfld.long 0x8 4. "SDA_IN_FILT_SEL,Selection of 'i2c_sda_in' filter delay:" "0: 0 ns,1: 50 ns"
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bitfld.long 0x8 0.--1. "SDA_IN_FILT_TRIM,Trim bits for 'i2c_sda_in' 50 ns filter." "0,1,2,3"
line.long 0xC "I2C_STRETCH_CTRL,I2C stretch control"
hexmask.long.byte 0xC 0.--3. 1. "STRETCH_THRESHOLD,stretch threthold."
rgroup.long 0x78++0x3
line.long 0x0 "I2C_STRETCH_STATUS,I2C stretch status"
bitfld.long 0x0 8. "STRETCHING,I2C SCL is stretched by this block (DUT) " "0,1"
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bitfld.long 0x0 5. "SYNC_DETECTED,synchronization detected." "0,1"
newline
bitfld.long 0x0 4. "STRETCH_DETECTED,stretch detected." "0,1"
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hexmask.long.byte 0x0 0.--3. 1. "STRETCH_COUNT,stretch count."
group.long 0x80++0x3
line.long 0x0 "I2C_CTRL_HS,I2C control for High-Speed mode"
bitfld.long 0x0 31. "HS_ENABLED,0': I2C Hs-mode is disabled " "0: I2C Hs-mode is disabled,1: I2C Hs-mode is enabled"
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hexmask.long.byte 0x0 4.--7. 1. "LOVS_HS,Serial I2C interface low phase oversampling factor for I2C Hs-mode. LOVS_HS + 1 peripheral clock periods constitute the low phase of a bit period."
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hexmask.long.byte 0x0 0.--3. 1. "HOVS_HS,Serial I2C interface high phase oversampling factor for I2C Hs-mode. HOVS_HS + 1 peripheral clock periods constitute the high phase of a bit period."
group.long 0x200++0x7
line.long 0x0 "TX_CTRL,Transmitter control"
bitfld.long 0x0 17. "OPEN_DRAIN_SCL,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 16. "OPEN_DRAIN,Each IO cell 'xxx' has two associated IP output signals 'xxx_out_en' and 'xxx_out'." "0: Normal operation mode,1: Open drain operation mode"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "TX_FIFO_CTRL,Transmitter FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware reads from the transmitter FIFO do not remove FIFO entries. Freeze will not advance the TX FIFO read pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the transmitter FIFO and transmitter shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the transmitter FIFO has less entries than the number of this field a transmitter trigger event INTR_TX.TRIGGER is generated."
rgroup.long 0x208++0x3
line.long 0x0 "TX_FIFO_STATUS,Transmitter FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read by the hardware."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the TX shift registers holds a valid data frame ('1') or not ('0'). The shift register can be considered the top of the TX FIFO (the data frame is not included in the USED field of the TX FIFO). The shift register is a working.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the transmitter FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
wgroup.long 0x240++0x3
line.long 0x0 "TX_FIFO_WR,Transmitter FIFO write"
hexmask.long 0x0 0.--31. 1. "DATA,Data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only DATA[15:0] are used."
group.long 0x300++0x7
line.long 0x0 "RX_CTRL,Receiver control"
bitfld.long 0x0 9. "MEDIAN,Median filter. When '1' a digital 3 taps median filter is performed on input interface lines. This filter should reduce the susceptibility to errors. However its requires higher oversampling values. For UART IrDA submode this field should.." "0,1"
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bitfld.long 0x0 8. "MSB_FIRST,Least significant bit first ('0') or most significant bit first ('1'). For I2C this field should be '1'." "0,1"
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hexmask.long.byte 0x0 0.--4. 1. "DATA_WIDTH,Dataframe width depending on CTRL.MEM_WIDTH."
line.long 0x4 "RX_FIFO_CTRL,Receiver FIFO control"
bitfld.long 0x4 17. "FREEZE,When '1' hardware writes to the receiver FIFO have no effect. Freeze will not advance the RX FIFO write pointer." "0,1"
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bitfld.long 0x4 16. "CLEAR,When '1' the receiver FIFO and receiver shift register are cleared/invalidated. Invalidation will last for as long as this field is '1'. If a quick clear/invalidation is required the field should be set to '1' and be followed by a set to '0'. If.." "0,1"
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hexmask.long.byte 0x4 0.--7. 1. "TRIGGER_LEVEL,Trigger level. When the receiver FIFO has more entries than the number of this field a receiver trigger event INTR_RX.TRIGGER is generated."
rgroup.long 0x308++0x3
line.long 0x0 "RX_FIFO_STATUS,Receiver FIFO status"
hexmask.long.byte 0x0 24.--31. 1. "WR_PTR,FIFO write pointer: FIFO location at which a new data frame is written by the hardware."
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hexmask.long.byte 0x0 16.--23. 1. "RD_PTR,FIFO read pointer: FIFO location from which a data frame is read."
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bitfld.long 0x0 15. "SR_VALID,Indicates whether the RX shift registers holds a (partial) valid data frame ('1') or not ('0'). The shift register can be considered the bottom of the RX FIFO (the data frame is not included in the USED field of the RX FIFO). The shift register.." "0,1"
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hexmask.long.word 0x0 0.--8. 1. "USED,Amount of entries in the receiver FIFO. The value of this field ranges from 0 to FF_DATA_NR (EZ_DATA_NR/2)."
group.long 0x310++0x3
line.long 0x0 "RX_MATCH,Slave address and mask"
hexmask.long.byte 0x0 16.--23. 1. "MASK,Slave device address mask. This field is a mask that specifies which of the ADDR field bits in the ADDR field take part in the matching of the slave address: MATCH = ((ADDR & MASK) == ('slave address' & MASK))."
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hexmask.long.byte 0x0 0.--7. 1. "ADDR,Slave device address."
rgroup.long 0x340++0x7
line.long 0x0 "RX_FIFO_RD,Receiver FIFO read"
hexmask.long 0x0 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will remove the data frame from the FIFO; i.e. behavior is similar to that of a POP operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' only.."
line.long 0x4 "RX_FIFO_RD_SILENT,Receiver FIFO read silent"
hexmask.long 0x4 0.--31. 1. "DATA,Data read from the receiver FIFO. Reading a data frame will NOT remove the data frame from the FIFO; i.e. behavior is similar to that of a PEEK operation. Note that when CTRL.MEM_WIDTH is '0' only DATA[7:0] are used and when CTRL.MEM_WIDTH is '1' .."
rgroup.long 0xE00++0x3
line.long 0x0 "INTR_CAUSE,Active clocked interrupt signal"
bitfld.long 0x0 5. "SPI_EC,Externally clocked SPI interrupt active ('interrupt_spi_ec'): INTR_SPI_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 4. "I2C_EC,Externally clock I2C interrupt active ('interrupt_i2c_ec'): INTR_I2C_EC_MASKED != 0." "0,1"
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bitfld.long 0x0 3. "RX,Receiver interrupt active ('interrupt_rx'): INTR_RX_MASKED != 0." "0,1"
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bitfld.long 0x0 2. "TX,Transmitter interrupt active ('interrupt_tx'): INTR_TX_MASKED != 0." "0,1"
newline
bitfld.long 0x0 1. "S,Slave interrupt active ('interrupt_slave'): INTR_S_MASKED != 0." "0,1"
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bitfld.long 0x0 0. "M,Master interrupt active ('interrupt_master'): INTR_M_MASKED != 0." "0,1"
group.long 0xE80++0x3
line.long 0x0 "INTR_I2C_EC,Externally clocked I2C interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (I2C STOP). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (I2C STOP). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base address.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (I2C STOP)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request (with address match)." "0,1"
group.long 0xE88++0x3
line.long 0x0 "INTR_I2C_EC_MASK,Externally clocked I2C interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xE8C++0x3
line.long 0x0 "INTR_I2C_EC_MASKED,Externally clocked I2C interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xEC0++0x3
line.long 0x0 "INTR_SPI_EC,Externally clocked SPI interrupt request"
bitfld.long 0x0 3. "EZ_READ_STOP,STOP detection after a read transfer occurred. Activated on the end of a read transfer (SPI deselection). This event is an indication that a buffer memory location has been read from." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,STOP detection after a write transfer occurred. Activated on the end of a write transfer (SPI deselection). This event is an indication that a buffer memory location has been written to. For EZ mode: a transfer that only writes the base.." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,STOP detection. Activated on the end of a every transfer (SPI deselection)." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Wake up request. Active on incoming slave request when externally clocked selection is '1'." "0,1"
group.long 0xEC8++0x3
line.long 0x0 "INTR_SPI_EC_MASK,Externally clocked SPI interrupt mask"
bitfld.long 0x0 3. "EZ_READ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x0 1. "EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xECC++0x3
line.long 0x0 "INTR_SPI_EC_MASKED,Externally clocked SPI interrupt masked"
bitfld.long 0x0 3. "EZ_READ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "WAKE_UP,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF00++0xB
line.long 0x0 "INTR_M,Master interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,SPI master transfer done event: all data frames in the transmit FIFO are sent the transmit FIFO is empty (both TX FIFO and transmit shifter register are empty) and SPI select output pin is deselected." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C master bus error (unexpected detection of START or STOP condition)." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C master STOP. Set to '1' when the master has transmitted a STOP." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,I2C master acknowledgement. Set to '1' when the master receives a ACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C master negative acknowledgement. Set to '1' when the master receives a NACK (typically after the master transmitted the slave address or TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C master lost arbitration: the value driven by the master on the SDA line is not the same as the value observed on the SDA line." "0,1"
line.long 0x4 "INTR_M_SET,Master interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 9. "SPI_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_M_MASK,Master interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 9. "SPI_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF0C++0x3
line.long 0x0 "INTR_M_MASKED,Master interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 9. "SPI_DONE,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF40++0xB
line.long 0x0 "INTR_S,Slave interrupt request"
bitfld.long 0x0 25. "I2C_HS_EXIT,exited I2C Hs-mode after STOP detection." "0,1"
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bitfld.long 0x0 24. "I2C_HS_ENTER,entered I2C Hs-mode at time t1 SCL falling edge after 'START 8-bit master code (0000_1XXX) NACK' sequence." "0,1"
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bitfld.long 0x0 16. "I2C_RESTART,I2C slave RESTART received." "0,1"
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bitfld.long 0x0 11. "SPI_BUS_ERROR,SPI slave deselected at an unexpected time in the SPI transfer. The Firmware may decide to clear the TX and RX FIFOs in case of this error." "0,1"
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bitfld.long 0x0 10. "SPI_EZ_STOP,SPI slave deselected after any EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,SPI slave deselected after a write EZ SPI transfer occurred." "0,1"
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bitfld.long 0x0 8. "I2C_BUS_ERROR,I2C slave bus error (unexpected detection of START or STOP condition). This should not occur it represents erroneous I2C bus behavior. In case of a bus error the I2C slave state machine abort the ongoing transfer. The Firmware may decide.." "0,1"
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bitfld.long 0x0 7. "I2C_GENERAL,I2C slave general call address received. If CTRL.ADDR_ACCEPT the received address 0x00 (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 6. "I2C_ADDR_MATCH,I2C slave matching address received. If CTRL.ADDR_ACCEPT the received address (including the R/W bit) is available in the RX FIFO. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') and internally clocked.." "0,1"
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bitfld.long 0x0 5. "I2C_START,I2C slave START received. Set to '1' when START or REPEATED START event is detected." "0,1"
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bitfld.long 0x0 4. "I2C_STOP,I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
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bitfld.long 0x0 3. "I2C_WRITE_STOP,I2C STOP event for I2C write transfer intended for this slave (address matching is performed). Set to '1' when STOP or REPEATED START event is detected. The REPEATED START event is included in this interrupt cause such that the I2C.." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,I2C slave acknowledgement received. Set to '1' when the slave receives a ACK (typically after the slave transmitted TX data)." "0,1"
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bitfld.long 0x0 1. "I2C_NACK,I2C slave negative acknowledgement received. Set to '1' when the slave receives a NACK (typically after the slave transmitted TX data)." "0,1"
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bitfld.long 0x0 0. "I2C_ARB_LOST,I2C slave lost arbitration: the value driven on the SDA line is not the same as the value observed on the SDA line (while the SCL line is '1'). This should not occur it represents erroneous I2C bus behavior. In case of lost arbitration the.." "0,1"
line.long 0x4 "INTR_S_SET,Slave interrupt set request"
bitfld.long 0x4 25. "I2C_HS_EXIT,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 24. "I2C_HS_ENTER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 16. "I2C_RESTART,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 11. "SPI_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 10. "SPI_EZ_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 9. "SPI_EZ_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 8. "I2C_BUS_ERROR,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 7. "I2C_GENERAL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 6. "I2C_ADDR_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 5. "I2C_START,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "I2C_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 3. "I2C_WRITE_STOP,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 2. "I2C_ACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "I2C_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 0. "I2C_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_S_MASK,Slave interrupt mask"
bitfld.long 0x8 25. "I2C_HS_EXIT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 24. "I2C_HS_ENTER,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 16. "I2C_RESTART,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 11. "SPI_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "SPI_EZ_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "SPI_EZ_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "I2C_BUS_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "I2C_GENERAL,Mask bit for corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x8 6. "I2C_ADDR_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "I2C_START,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "I2C_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "I2C_WRITE_STOP,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "I2C_ACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "I2C_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "I2C_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF4C++0x3
line.long 0x0 "INTR_S_MASKED,Slave interrupt masked request"
bitfld.long 0x0 25. "I2C_HS_EXIT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 24. "I2C_HS_ENTER,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 16. "I2C_RESTART,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 11. "SPI_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "SPI_EZ_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "SPI_EZ_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "I2C_BUS_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "I2C_GENERAL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "I2C_ADDR_MATCH,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "I2C_START,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "I2C_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "I2C_WRITE_STOP,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "I2C_ACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "I2C_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "I2C_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
group.long 0xF80++0xB
line.long 0x0 "INTR_TX,Transmitter interrupt request"
bitfld.long 0x0 10. "UART_ARB_LOST,UART lost arbitration: the value driven on the TX line is not the same as the value observed on the RX line. This condition event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes. Set to.." "0,1"
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bitfld.long 0x0 9. "UART_DONE,UART transmitter done event. This happens when the IP is done transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty). Set to '1' when event is detected. Write with.." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,UART transmitter received a negative acknowledgement in SmartCard mode. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite write transfer can not get access to the EZ memory (EZ data access) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty TX FIFO. This happens when the IP is ready to transfer data and EMPTY is '1'." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full TX FIFO." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,TX FIFO is empty; i.e. it has 0 entries." "0,1"
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bitfld.long 0x0 1. "NOT_FULL,TX FIFO is not full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0: # entries != FF_DATA_NR,1: # entries != FF_DATA_NR/2"
newline
bitfld.long 0x0 0. "TRIGGER,Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_TX_SET,Transmitter interrupt set request"
bitfld.long 0x4 10. "UART_ARB_LOST,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 9. "UART_DONE,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 8. "UART_NACK,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 4. "EMPTY,Write with '1' to set corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x4 1. "NOT_FULL,Write with '1' to set corresponding bit in interrupt request register." "0,1"
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bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_TX_MASK,Transmitter interrupt mask"
bitfld.long 0x8 10. "UART_ARB_LOST,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "UART_DONE,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "UART_NACK,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 4. "EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 1. "NOT_FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xF8C++0x3
line.long 0x0 "INTR_TX_MASKED,Transmitter interrupt masked request"
bitfld.long 0x0 10. "UART_ARB_LOST,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 9. "UART_DONE,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "UART_NACK,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 4. "EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 1. "NOT_FULL,Logical and of corresponding request and mask bits." "0,1"
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bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
group.long 0xFC0++0xB
line.long 0x0 "INTR_RX,Receiver interrupt request"
bitfld.long 0x0 11. "BREAK_DETECT,Break detection is successful: the line is '0' for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at any time to address unanticipated break fields; i.e. 'break-in-data' is supported. This feature is supported for the UART standard and.." "0,1"
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bitfld.long 0x0 10. "BAUD_DETECT,LIN baudrate detection is completed. The receiver software uses the UART_RX_STATUS.BR_COUNTER value to set the right IP clock (from the programmable clock IP) to guarantee successful receipt of the first LIN data frame (Protected Identifier.." "0,1"
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bitfld.long 0x0 9. "PARITY_ERROR,Parity error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '1' the received frame is dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is '0' the received frame.." "0,1"
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bitfld.long 0x0 8. "FRAME_ERROR,Frame error in received data frame. Set to '1' when event is detected. Write with '1' to clear bit. This can be either a start or stop bit(s) error:" "0,1"
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bitfld.long 0x0 7. "BLOCKED,AHB-Lite read transfer can not get access to the EZ memory (EZ_DATA accesses) due to an externally clocked EZ access. This may happen when STATUS.EC_BUSY is '1'." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Attempt to read from an empty RX FIFO." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Attempt to write to a full RX FIFO. Note: in I2C mode the OVERFLOW is set when a data frame is received and the RX FIFO is full independent of whether it is ACK'd or NACK'd." "0,1"
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bitfld.long 0x0 3. "FULL,RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.MEM_WIDTH: (FF_DATA_NR = EZ_DATA_NR/2)" "0: # entries == FF_DATA_NR,1: # entries == FF_DATA_NR/2"
newline
bitfld.long 0x0 2. "NOT_EMPTY,RX FIFO is not empty." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL." "0,1"
line.long 0x4 "INTR_RX_SET,Receiver interrupt set request"
bitfld.long 0x4 11. "BREAK_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 10. "BAUD_DETECT,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 9. "PARITY_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 8. "FRAME_ERROR,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 7. "BLOCKED,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 6. "UNDERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 5. "OVERFLOW,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 3. "FULL,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 2. "NOT_EMPTY,Write with '1' to set corresponding bit in interrupt status register." "0,1"
newline
bitfld.long 0x4 0. "TRIGGER,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_RX_MASK,Receiver interrupt mask"
bitfld.long 0x8 11. "BREAK_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 10. "BAUD_DETECT,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 9. "PARITY_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 8. "FRAME_ERROR,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 7. "BLOCKED,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 6. "UNDERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 5. "OVERFLOW,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 3. "FULL,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 2. "NOT_EMPTY,Mask bit for corresponding bit in interrupt request register." "0,1"
newline
bitfld.long 0x8 0. "TRIGGER,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long 0xFCC++0x3
line.long 0x0 "INTR_RX_MASKED,Receiver interrupt masked request"
bitfld.long 0x0 11. "BREAK_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 10. "BAUD_DETECT,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 9. "PARITY_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 8. "FRAME_ERROR,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 7. "BLOCKED,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 6. "UNDERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 5. "OVERFLOW,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 3. "FULL,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 2. "NOT_EMPTY,Logical and of corresponding request and mask bits." "0,1"
newline
bitfld.long 0x0 0. "TRIGGER,Logical and of corresponding request and mask bits." "0,1"
tree.end
tree.end
tree "SPCIF (SPC Interface)"
base ad:0x40110000
group.long 0x0++0x3
line.long 0x0 "GEOMETRY,Flash/NVL geometry information"
bitfld.long 0x0 31. "DE_CPD_LP,0': SRAM busy wait loop has not been copied." "0: SRAM busy wait loop has not been copied,1: Busy wait loop has been written into SRAM"
hexmask.long.byte 0x0 24.--30. 1. "NVL,NVLatch size in Byte multiples (chip dependent):"
rbitfld.long 0x0 22.--23. "FLASH_ROW,Page size in 64 Byte multiples (chip dependent):" "0: 64 byte,1: 128 byte,2: 192 byte,3: 256 byte"
rbitfld.long 0x0 20.--21. "NUM_FLASH,Number of flash macros (chip dependent):" "0: 1 flash macro,1: 2 flash macros,2: 3 flash macros,3: 4 flash macros"
newline
hexmask.long.byte 0x0 14.--19. 1. "SFLASH,Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the supervisory flash capacity of all flash macros together:"
hexmask.long.word 0x0 0.--13. 1. "FLASH,Regular flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present this field provides the flash capacity of all flash macros together:"
group.long 0x1C++0x3
line.long 0x0 "NVL_WR_DATA,NVL write data register"
hexmask.long.byte 0x0 0.--7. 1. "DATA,Data to be written to NVLatch array"
group.long 0x7F0++0xB
line.long 0x0 "INTR,SPCIF interrupt request register"
bitfld.long 0x0 0. "TIMER,Timer counter value reaches '0'. Set to '1' when event is detected. Write INTR field with '1' to clear bit. Write INTR_SET field with '1' to set bit." "0,1"
line.long 0x4 "INTR_SET,SPCIF interrupt set request register"
bitfld.long 0x4 0. "TIMER,Write INTR_SET field with '1' to set corresponding INTR field." "0,1"
line.long 0x8 "INTR_MASK,SPCIF interrupt mask register"
bitfld.long 0x8 0. "TIMER,Mask for corresponding field in INTR register." "0,1"
rgroup.long 0x7FC++0x3
line.long 0x0 "INTR_MASKED,SPCIF interrupt masked request register"
bitfld.long 0x0 0. "TIMER,Logical and of corresponding request and mask fields." "0,1"
tree.end
tree "SRSSLT (System Resources Lite Subsystem)"
base ad:0x40030000
group.long 0x0++0x7
line.long 0x0 "PWR_CONTROL,Power Mode Control"
bitfld.long 0x0 23. "EXT_VCCD,Always write 0 except as noted below." "0,1"
rbitfld.long 0x0 18.--19. "SPARE,Spare AHB readback bits that are hooked to PWR_PWRSYS_TRIM1.SPARE_TRIM[1:0] through spare logic equivalent to bitwise inversion. Engineering only." "0,1,2,3"
newline
bitfld.long 0x0 17. "OVER_TEMP_THRESH,Over-temperature threshold." "0: TEMP_HIGH condition occurs between 120C and 125C,1: TEMP_HIGH condition occurs between 60C and 75C"
bitfld.long 0x0 16. "OVER_TEMP_EN,Enables the die over temperature sensor. Must be enabled when using the TEMP_HIGH interrupt." "0,1"
newline
rbitfld.long 0x0 5. "LPM_READY,Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode." "0: If DEEPSLEEP mode is requested,1: Normal operation"
rbitfld.long 0x0 4. "DEBUG_SESSION,Indicates whether a debug session is active (CDBGPWRUPREQ signal is 1)" "0: No debug session active,1: Debug session is active"
newline
hexmask.long.byte 0x0 0.--3. 1. "POWER_MODE,Current power mode of the device. Note that this field cannot be read in all power modes on actual silicon."
line.long 0x4 "PWR_KEY_DELAY,Power System Key&Delay Register"
hexmask.long.word 0x4 0.--9. 1. "WAKEUP_HOLDOFF,Delay to wait for references to settle on wakeup from deepsleep. BOD is ignored and system does not resume until this delay expires. Note that the same delay on POR is hard-coded. The default assumes the output of the predivider is 48MHz.."
group.long 0xC++0x3
line.long 0x0 "PWR_DDFT_SELECT,Power DDFT Mode Selection Register"
hexmask.long.byte 0x0 4.--7. 1. "DDFT1_SEL,Select signal for power DDFT output #1"
hexmask.long.byte 0x0 0.--3. 1. "DDFT0_SEL,Select signal for power DDFT output #0"
group.long 0x14++0x3
line.long 0x0 "TST_MODE,Test Mode Control Register"
bitfld.long 0x0 31. "TEST_MODE,Setting this bit will prevent BootROM from yielding execution to Flash image." "0: Normal operation mode,1: Test mode"
rbitfld.long 0x0 30. "TEST_KEY_DFT_EN,This bit is set when a XRES test mode key is shifted in. It is the value of the test_key_dft_en signal. When this bit is set the BootROM will not yield execution to the FLASH image (same function as setting TEST_MODE bit below)." "0,1"
newline
bitfld.long 0x0 28. "BLOCK_ALT_XRES,Relevant only for parts that have the alternate XRES mechanism of overloading a GPIO pin temporarily as alternate XRES during test. When set this bit blocks the alternate XRES function such that the pin can be used for normal I/O or for.." "0,1"
rbitfld.long 0x0 2. "SWD_CONNECTED,0: SWD not active" "0: SWD not active,1: SWD activated"
group.long 0x28++0x13
line.long 0x0 "CLK_SELECT,Clock Select Register"
bitfld.long 0x0 6.--7. "SYSCLK_DIV,Select clk_sys prescaler value." "0: clk_sys= clk_hf/1,1: clk_sys= clk_hf/2,2: clk_sys= clk_hf/4,3: clk_sys= clk_hf/8"
bitfld.long 0x0 4.--5. "PUMP_SEL,Selects clock source for charge pump clock. This clock is not guaranteed to be glitch free when changing any of its sources or settings." "0: No clock connect to gnd,1: Use main IMO output,2: Use clk_hf (using selected source after..,?"
newline
bitfld.long 0x0 2.--3. "HFCLK_DIV,Selects clk_hf predivider value." "0: Transparent mode feed through selected clock..,1: Divide selected clock source by 2,2: Divide selected clock source by 4,3: Divide selected clock source by 8"
bitfld.long 0x0 0.--1. "HFCLK_SEL,Selects a source for clk_hf and dsi_in[0]. Note that not all products support all clock sources. Selecting a clock source that is not supported will result in undefined behavior." "0: IMO - Internal R/C Oscillator,1: EXTCLK - External Clock Pin,2: ECO - External-Crystal Oscillator or PLL..,?"
line.long 0x4 "CLK_ILO_CONFIG,ILO Configuration"
bitfld.long 0x4 31. "ENABLE,Master enable for ILO oscillator. This bit is hardware set whenever the WDT_DISABLE_KEY is not set to the magic value." "0,1"
line.long 0x8 "CLK_IMO_CONFIG,IMO Configuration"
bitfld.long 0x8 31. "ENABLE,Master enable for IMO oscillator. Clearing this bit will disable the IMO. Don't do this if the system is running off it." "0,1"
line.long 0xC "CLK_DFT_SELECT,Clock DFT Mode Selection Register"
bitfld.long 0xC 14. "DFT_EDGE1,Edge sensitivity for in-line divider on output #1 (only relevant when DIV1>0)." "0: Use posedge for divider,1: Use negedge for divider"
bitfld.long 0xC 12.--13. "DFT_DIV1,DFT Output Divide Down." "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
newline
hexmask.long.byte 0xC 8.--11. 1. "DFT_SEL1,Select signal for DFT output #1"
bitfld.long 0xC 6. "DFT_EDGE0,Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0)." "0: Use posedge for divider,1: Use negedge for divider"
newline
bitfld.long 0xC 4.--5. "DFT_DIV0,DFT Output Divide Down." "0: Direct Output,1: Divide by 2,2: Divide by 4,3: Divide by 8"
hexmask.long.byte 0xC 0.--3. 1. "DFT_SEL0,Select signal for DFT output #0"
line.long 0x10 "WDT_DISABLE_KEY,Watchdog Disable Key Register"
hexmask.long 0x10 0.--31. 1. "KEY,Disables WDT reset when equal to 0xACED8865. The WDT reset functions normally for any other setting."
rgroup.long 0x3C++0x3
line.long 0x0 "WDT_COUNTER,Watchdog Counter Register"
hexmask.long.word 0x0 0.--15. 1. "COUNTER,Current value of WDT Counter"
group.long 0x40++0xF
line.long 0x0 "WDT_MATCH,Watchdog Match Register"
hexmask.long.byte 0x0 16.--19. 1. "IGNORE_BITS,The number of MSB bits of the watchdog timer that are NOT checked against MATCH. This value provides control over the time-to-reset of the watchdog (which happens after 3 successive matches). Note that certain products may enforce a minimum.."
hexmask.long.word 0x0 0.--15. 1. "MATCH,Match value for Watchdog counter. Every time WDT_COUNTER reaches MATCH an interrupt is generated. Two unserviced interrupts will lead to a system reset (i.e. at the third match)."
line.long 0x4 "SRSS_INTR,SRSS Interrupt Register"
bitfld.long 0x4 1. "TEMP_HIGH,Regulator over-temp interrupt. This interrupt can occur when a short circuit exists on the vccd pin or when extreme loads are applied on IO-cells causing the die to overheat. Firmware is encourage to shutdown all IO cells and then go to.." "0,1"
bitfld.long 0x4 0. "WDT_MATCH,WDT Interrupt Request. This bit is set each time WDT_COUNTR==WDT_MATCH. Clearing this bit also feeds the watch dog. Missing 2 interrupts in a row will generate brown-out reset. Due to internal synchronization it takes 2 SYSCLK cycles to.." "0,1"
line.long 0x8 "SRSS_INTR_SET,SRSS Interrupt Set Register"
bitfld.long 0x8 1. "TEMP_HIGH,Writing 1 to this bit internally sets the overtemp interrupt. This can be observed by reading SRSS_INTR.TEMP_HIGH. This bit always reads back as zero." "0,1"
line.long 0xC "SRSS_INTR_MASK,SRSS Interrupt Mask Register"
bitfld.long 0xC 1. "TEMP_HIGH,Masks REG_OVERTEMP interrupt" "0,1"
bitfld.long 0xC 0. "WDT_MATCH,Clearing this bit will not forward the interrupt to the CPU. It will not however disable the WDT reset generation on 2 missed interrupts." "0,1"
group.long 0x54++0x3
line.long 0x0 "RES_CAUSE,Reset Cause Observation Register"
bitfld.long 0x0 4. "RESET_SOFT,Cortex-M0 requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware." "0,1"
bitfld.long 0x0 3. "RESET_PROT_FAULT,A protection violation occurred that requires a RESET. This includes but is not limited to hitting a debug breakpoint while in Privileged Mode." "0,1"
newline
bitfld.long 0x0 0. "RESET_WDT,A WatchDog Timer reset has occurred since last power cycle." "0,1"
group.long 0xF08++0x13
line.long 0x0 "CLK_IMO_SELECT,IMO Frequency Select Register"
bitfld.long 0x0 0.--2. "FREQ,Select operating frequency" "0: IMO runs at 24 MHz,1: IMO runs at 28 MHz,2: IMO runs at 32 MHz,3: IMO runs at 36 MHz,4: IMO runs at 40 MHz,5: IMO runs at 44 MHz,6: IMO runs at 48 MHz,?"
line.long 0x4 "CLK_IMO_TRIM1,IMO Trim Register"
hexmask.long.byte 0x4 0.--7. 1. "OFFSET,Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting in CLK_IMO_SELECT and stored in SFLASH. This field is hardware updated during USB osclock mode or when a WCO uses this mechanism for PLL locking the WCO."
line.long 0x8 "CLK_IMO_TRIM2,IMO Trim Register"
bitfld.long 0x8 0.--2. "FSOFFSET,Frequency trim bits. These bits are not trimmed during manufacturing and kept at 0 under normal operation. This field is hardware updated during USB osclock mode or when a WCO uses this mechanism for PLL locking the WCO. This is only.." "0,1,2,3,4,5,6,7"
line.long 0xC "PWR_PWRSYS_TRIM1,Power System Trim Register"
hexmask.long.byte 0xC 4.--7. 1. "SPARE_TRIM,Active-Reference temperature compensation trim (repurposed from spare bits)."
hexmask.long.byte 0xC 0.--3. 1. "DPSLP_REF_TRIM,Trims the DeepSleep reference that is used by the DeepSleep regulator and DeepSleep power comparator."
line.long 0x10 "CLK_IMO_TRIM3,IMO Trim Register"
bitfld.long 0x10 5.--6. "TCTRIM,IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence. This bits are dependent on frequency and need to be changed using the Cypress provided frequency change algorithm." "0,1,2,3"
hexmask.long.byte 0x10 0.--4. 1. "STEPSIZE,IMO trim stepsize bits. These bits are determined at manufacturing time to adjust for process variation. They are used to tune the stepsize of the FSOFFSET and OFFSET trims."
tree.end
tree "TCPWM (Timer/Counter/PWM)"
base ad:0x40200000
group.long 0x0++0x3
line.long 0x0 "CTRL,TCPWM control register 0."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_ENABLED,Counter enables for counters 0 up to CNT_NR-1."
group.long 0x8++0x3
line.long 0x0 "CMD,TCPWM command register."
hexmask.long.byte 0x0 24.--31. 1. "COUNTER_START,Counters SW start trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 16.--23. 1. "COUNTER_STOP,Counters SW stop trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 8.--15. 1. "COUNTER_RELOAD,Counters SW reload trigger. For HW behavior see COUNTER_CAPTURE field."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_CAPTURE,Counters SW capture trigger. When written with '1' a capture trigger is generated and the HW sets the field to '0' when the SW trigger has taken effect. It should be noted that the HW operates on the counter frequency. If the counter is.."
rgroup.long 0xC++0x3
line.long 0x0 "INTR_CAUSE,TCPWM Counter interrupt cause register."
hexmask.long.byte 0x0 0.--7. 1. "COUNTER_INT,Counters interrupt signal active. If the counter is disabled through CTRL.COUNTER_ENABLED the associated interrupt field is immediately set to '0'."
repeat 2. (list 0x0 0x1)(list ad:0x40200100 ad:0x40200140)
tree "CNT[$1]"
base $2
group.long ($2)++0x3
line.long 0x0 "CTRL,Counter control register"
bitfld.long 0x0 24.--26. "MODE,Counter mode." "0: Timer mode,?,2: Capture mode,3: Quadrature encoding mode,4: Pulse width modulation (PWM) mode,5: PWM with deadtime insertion mode,6: Pseudo random pulse width modulation,?"
bitfld.long 0x0 20.--21. "QUADRATURE_MODE,In QUAD mode selects quadrature encoding mode (X1/X2/X4)." "0: X1 encoding (QUAD mode),1: X2 encoding (QUAD mode),2: X4 encoding (QUAD mode),?"
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bitfld.long 0x0 18. "ONE_SHOT,When '0' counter runs continuous. When '1' counter is turned off by hardware when a terminal count event is generated." "0,1"
bitfld.long 0x0 16.--17. "UP_DOWN_MODE,Determines counter direction." "0: Count up (to PERIOD). An overflow event is..,1: Count down (to '0'). An underflow event is..,2: Count up (to PERIOD) then count down (to '0').,3: Count up (to PERIOD) then count down (to '0')."
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hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit control field. In PWM_DT mode this field is used to determine the dead time: amount of dead time cycles in the counter clock domain. In all other modes the lower 3 bits of this field determine pre-scaling of the selected counter.."
bitfld.long 0x0 3. "PWM_STOP_ON_KILL,Specifies whether the counter stops on a kill events:" "0: kill event does NOT stop counter,1: kill event stops counter"
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bitfld.long 0x0 2. "PWM_SYNC_KILL,Specifies asynchronous/synchronous kill behavior:" "0: asynchronous kill mode: the kill event only..,1: synchronous kill mode: the kill event disables.."
bitfld.long 0x0 1. "AUTO_RELOAD_PERIOD,Specifies switching of the PERIOD and buffered PERIOD values. This field has a function in PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
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bitfld.long 0x0 0. "AUTO_RELOAD_CC,Specifies switching of the CC and buffered CC values. This field has a function in TIMER PWM PWM_DT and PWM_PR modes." "0: never switch,1: switch on a terminal count event with an.."
rgroup.long ($2+0x4)++0x3
line.long 0x0 "STATUS,Counter status register"
bitfld.long 0x0 31. "RUNNING,When '0' the counter is NOT running. When '1' the counter is running." "0,1"
hexmask.long.byte 0x0 8.--15. 1. "GENERIC,Generic 8-bit counter field. In PWM_DT mode this counter is used for dead time insertion. In all other modes this counter is used for pre-scaling the selected counter clock. PWM_DT mode can NOT use prescaled clock functionality."
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bitfld.long 0x0 0. "DOWN,When '0' counter is counting up. When '1' counter is counting down. In QUAD mode this field indicates the direction of the latest counter change: '0' when last incremented and '1' when last decremented." "0,1"
group.long ($2+0x8)++0x13
line.long 0x0 "COUNTER,Counter count register"
hexmask.long.word 0x0 0.--15. 1. "COUNTER,16-bit counter value. It is advised to not write to this field when the counter is running."
line.long 0x4 "CC,Counter compare/capture register"
hexmask.long.word 0x4 0.--15. 1. "CC,In CAPTURE mode captures the counter value. In other modes compared to counter value."
line.long 0x8 "CC_BUFF,Counter buffered compare/capture register"
hexmask.long.word 0x8 0.--15. 1. "CC,Additional buffer for counter CC register."
line.long 0xC "PERIOD,Counter period register"
hexmask.long.word 0xC 0.--15. 1. "PERIOD,Period value: upper value of the counter. When the counter should count for n cycles this field should be set to n-1."
line.long 0x10 "PERIOD_BUFF,Counter buffered period register"
hexmask.long.word 0x10 0.--15. 1. "PERIOD,Additional buffer for counter PERIOD register."
group.long ($2+0x20)++0xB
line.long 0x0 "TR_CTRL0,Counter trigger control register 0"
hexmask.long.byte 0x0 16.--19. 1. "START_SEL,Selects one of the 16 input triggers as a start trigger. In QUAD mode this is the second phase (phi B)."
hexmask.long.byte 0x0 12.--15. 1. "STOP_SEL,Selects one of the 16 input triggers as a stop trigger. In PWM PWM_DT and PWM_PR modes this is the kill trigger. In these modes the kill trigger is used to either temporarily block the PWM outputs (PWM_STOP_ON_KILL is '0') or stop the.."
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hexmask.long.byte 0x0 8.--11. 1. "RELOAD_SEL,Selects one of the 16 input triggers as a reload trigger. In QUAD mode this is the index or revolution pulse. In this mode it will update the counter with the value in the TCPWM_CNTn_PERIOD register."
hexmask.long.byte 0x0 4.--7. 1. "COUNT_SEL,Selects one of the 16 input triggers as a count trigger. In QUAD mode this is the first phase (phi A). Default setting selects input trigger 1 which is always '1'."
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hexmask.long.byte 0x0 0.--3. 1. "CAPTURE_SEL,Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger 1 is always '1'. Input trigger 2 is the first external trigger line (tcpwm.tr_in[0])."
line.long 0x4 "TR_CTRL1,Counter trigger control register 1"
bitfld.long 0x4 8.--9. "START_EDGE,A start event will start the counter; i.e. the counter will become running. Starting does NOT enable the counter. A start event will not initialize the counter whereas the reload event does." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
bitfld.long 0x4 6.--7. "STOP_EDGE,A stop event will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0x4 4.--5. "RELOAD_EDGE,A reload event will initialize the counter. When counting up the counter is initialized to '0'. When counting down the counter is initialized with PERIOD." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
bitfld.long 0x4 2.--3. "COUNT_EDGE,A counter event will increase or decrease the counter by '1'." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
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bitfld.long 0x4 0.--1. "CAPTURE_EDGE,A capture event will copy the counter value into the CC register." "0: Rising edge. Any rising edge generates an event.,1: Falling edge. Any falling edge generates an event.,2: Rising AND falling edge. Any odd amount of edges..,3: No edge detection use trigger as is."
line.long 0x8 "TR_CTRL2,Counter trigger control register 2"
bitfld.long 0x8 4.--5. "UNDERFLOW_MODE,Determines the effect of a counter underflow event (COUNTER reaches '0') on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
bitfld.long 0x8 2.--3. "OVERFLOW_MODE,Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the 'line_out' output signals." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
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bitfld.long 0x8 0.--1. "CC_MATCH_MODE,Determines the effect of a compare match event (COUNTER equals CC register) on the 'line_out' output signals. Note that INVERT is especially useful for center aligned pulse width modulation." "0: Set to '1',1: Set to '0',2: Invert,3: No Change"
group.long ($2+0x30)++0xB
line.long 0x0 "INTR,Interrupt request register."
bitfld.long 0x0 1. "CC_MATCH,Counter matches CC register event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
bitfld.long 0x0 0. "TC,Terminal count event. Set to '1' when event is detected. Write with '1' to clear bit." "0,1"
line.long 0x4 "INTR_SET,Interrupt set request register."
bitfld.long 0x4 1. "CC_MATCH,Write with '1' to set corresponding bit in interrupt request register." "0,1"
bitfld.long 0x4 0. "TC,Write with '1' to set corresponding bit in interrupt request register." "0,1"
line.long 0x8 "INTR_MASK,Interrupt mask register."
bitfld.long 0x8 1. "CC_MATCH,Mask bit for corresponding bit in interrupt request register." "0,1"
bitfld.long 0x8 0. "TC,Mask bit for corresponding bit in interrupt request register." "0,1"
rgroup.long ($2+0x3C)++0x3
line.long 0x0 "INTR_MASKED,Interrupt masked request register"
bitfld.long 0x0 1. "CC_MATCH,Logical and of corresponding request and mask bits." "0,1"
bitfld.long 0x0 0. "TC,Logical and of corresponding request and mask bits." "0,1"
tree.end
repeat.end
tree.end
AUTOINDENT.OFF
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