30408 lines
1.6 MiB
30408 lines
1.6 MiB
; --------------------------------------------------------------------------------
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; @Title: PIC32CXMTG On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-03-08 JDU
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; 2023-10-25 NEJ
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; 2023-11-08 NEJ
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; @Manufacturer: MICROCHIP - Microchip Technology Inc.
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; PIC32CX1025MTG128.svd (Ver. 0), PIC32CX1025MTG64.svd (Ver. 0),
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; PIC32CX2051MTG128.svd (Ver. 0), PIC32CX2051MTG64.svd (Ver. 0),
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; PIC32CX5112MTG128.svd (Ver. 0)
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; @Core: Cortex-M4F
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; @Chip: PIC32CX1025MTG128, PIC32CX1025MTG64, PIC32CX2051MTG128,
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; PIC32CX2051MTG64, PIC32CX5112MTG128
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perpic32cxmtg.per 16960 2023-11-08 16:57:59Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ACC (Analog Comparator Controller)"
|
|
base ad:0x40028000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 14. "FE,Fault Enable" "0: The FAULT output is tied to 0.,1: The FAULT output is driven by the signal defined.."
|
|
bitfld.long 0x0 13. "SELFS,Selection Of Fault Source" "0: The CE flag is used to drive the FAULT output.,1: The output of the analog comparator flag is used.."
|
|
newline
|
|
bitfld.long 0x0 12. "INV,Invert Comparator Output" "0: Analog comparator output is directly processed.,1: Analog comparator output is inverted prior to.."
|
|
bitfld.long 0x0 9.--10. "EDGETYP,Edge Type" "0: Only rising edge of comparator output,1: Falling edge of comparator output,2: Any edge of comparator output,?"
|
|
newline
|
|
bitfld.long 0x0 8. "ACEN,Analog Comparator Enable" "0: Analog comparator disabled.,1: Analog comparator enabled."
|
|
bitfld.long 0x0 4.--6. "SELPLUS,Selection For Plus Comparator Input" "0: Selects AD0,1: Selects AD1,2: Selects AD2,3: Selects VREFP,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "SELMINUS,Selection for Minus Comparator Input" "0: Selects AD3,1: Selects AD4,2: Selects VTEMP,3: Selects VREFTEMP,?,?,?,?"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 0. "CE,Comparison Edge" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 0. "CE,Comparison Edge" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 0. "CE,Comparison Edge" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 31. "MASK,Flag Mask" "0,1"
|
|
bitfld.long 0x4 1. "SCO,Synchronized Comparator Output" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CE,Comparison Edge (cleared on read)" "0,1"
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 0. "MSEL,Masking Period Selection" "0: Masks AC output for 16 peripheral clock periods..,1: Masks AC output for 128 peripheral clock periods.."
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x40024000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 4. "CMPRST,Comparison Restart" "0,1"
|
|
bitfld.long 0x0 3. "SWFIFO,Software FIFO Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "START,Start Conversion" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "USEQ,User Sequence Enable" "0: Normal mode: The controller converts channels in..,1: User Sequence mode: The sequence respects what.."
|
|
bitfld.long 0x0 30. "ALWAYS1," "0,1"
|
|
newline
|
|
bitfld.long 0x0 28.--29. "TRANSFER,Transfer Time" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TRACKTIM,Tracking Time"
|
|
newline
|
|
bitfld.long 0x0 23. "ANACH,Analog Change" "0: No analog change on channel switching: DIFF0 is..,1: Allows different analog settings for each.."
|
|
hexmask.long.byte 0x0 16.--19. 1. "STARTUP,Startup Time"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRESCAL,Prescaler Rate Selection"
|
|
bitfld.long 0x0 6. "FWUP,Fast Wake-up" "0: If SLEEP is 1 then both ADC core and reference..,1: If SLEEP is 1 then Fast Wake-up Sleep mode: The.."
|
|
newline
|
|
bitfld.long 0x0 5. "SLEEP,Sleep Mode" "0: Normal mode: The ADC core and reference voltage..,1: Sleep mode: The wake-up time can be modified by.."
|
|
bitfld.long 0x0 1.--3. "TRGSEL,Trigger Selection" "0: PWM event line 0,1: TIOA0 TC0,2: TIOA1 TC0,3: TIOA2 TC0,4: TIOA0 TC1,5: TIOA1 TC1,6: RTCOUT0,?"
|
|
line.long 0x4 "SEQR1,Channel Sequence Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "USCH8,User Sequence Number 8"
|
|
hexmask.long.byte 0x4 24.--27. 1. "USCH7,User Sequence Number 7"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "USCH6,User Sequence Number 6"
|
|
hexmask.long.byte 0x4 16.--19. 1. "USCH5,User Sequence Number 5"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "USCH4,User Sequence Number 4"
|
|
hexmask.long.byte 0x4 8.--11. 1. "USCH3,User Sequence Number 3"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "USCH2,User Sequence Number 2"
|
|
hexmask.long.byte 0x4 0.--3. 1. "USCH1,User Sequence Number 1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "CHER,Channel Enable Register"
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Enable" "0,1"
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Enable" "0,1"
|
|
line.long 0x4 "CHDR,Channel Disable Register"
|
|
bitfld.long 0x4 7. "CH7,Channel 7 Disable" "0,1"
|
|
bitfld.long 0x4 6. "CH6,Channel 6 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CH5,Channel 5 Disable" "0,1"
|
|
bitfld.long 0x4 4. "CH4,Channel 4 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CH3,Channel 3 Disable" "0,1"
|
|
bitfld.long 0x4 2. "CH2,Channel 2 Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CH1,Channel 1 Disable" "0,1"
|
|
bitfld.long 0x4 0. "CH0,Channel 0 Disable" "0,1"
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "CHSR,Channel Status Register"
|
|
bitfld.long 0x0 7. "CH7,Channel 7 Status" "0,1"
|
|
bitfld.long 0x0 6. "CH6,Channel 6 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CH5,Channel 5 Status" "0,1"
|
|
bitfld.long 0x0 4. "CH4,Channel 4 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,Channel 3 Status" "0,1"
|
|
bitfld.long 0x0 2. "CH2,Channel 2 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CH1,Channel 1 Status" "0,1"
|
|
bitfld.long 0x0 0. "CH0,Channel 0 Status" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "LCDR,Last Converted Data Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "CHNBOSR,Channel Number in Oversampling Mode"
|
|
hexmask.long.word 0x0 0.--15. 1. "LDATA,Last Data Converted"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "LCDR_NO_OSR_MODE,Last Converted Data Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "NO_OSR_CHNB,Channel Number when No Oversampling"
|
|
hexmask.long.word 0x0 0.--11. 1. "NO_OSR_LDATA,Last Data Converted when No Oversampling"
|
|
wgroup.long 0x24++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 28. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 27. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 19. "TEMPCHG,Temperature Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EOS,End Of Sequence Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "SMEV,Supply Monitor Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 28. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 27. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 19. "TEMPCHG,Temperature Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "EOS,End Of Sequence Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "SMEV,Supply Monitor Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "RXUDR,Receive Under Flow Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Receive Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x2C++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 28. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 27. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "COMPE,Comparison Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 25. "GOVRE,General Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 19. "TEMPCHG,Temperature Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EOS,End Of Sequence Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "SMEV,Supply Monitor Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXOVR,Receive Over Flow Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "RXUDR,Receive Under Flow Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXCHUNK,Receive FIFO Chunk Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "RXFULL,Receive FIFO Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXEMPTY,Receive FIFO Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RXRDY,Receive Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 28. "RXBUFF,Receive Buffer Full (cleared by writing ADC_RCR or ADC_RNCR)" "0,1"
|
|
bitfld.long 0x4 27. "ENDRX,End of Receive Transfer (cleared by writing ADC_RCR or ADC_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "COMPE,Comparison Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 25. "GOVRE,General Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "DRDY,Data Ready (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 19. "TEMPCHG,Temperature Change (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "EOS,End Of Sequence (cleared on read)" "0,1"
|
|
bitfld.long 0x4 6. "SMEV,Supply Monitor Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXOVR,Receive Over Flow (cleared on read)" "0,1"
|
|
bitfld.long 0x4 4. "RXUDR,Receive Under Flow (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXCHUNK,Receive FIFO Chunk (cleared on read)" "0,1"
|
|
bitfld.long 0x4 2. "RXFULL,Receive FIFO Full (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXEMPTY,Receive FIFO Empty (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "RXRDY,Receive Ready (cleared on read)" "0,1"
|
|
wgroup.long 0x34++0x7
|
|
line.long 0x0 "EOC_IER,End Of Conversion Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "EOC_IDR,End Of Conversion Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "EOC7,End of Conversion Interrupt Disable 7" "0,1"
|
|
bitfld.long 0x4 6. "EOC6,End of Conversion Interrupt Disable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EOC5,End of Conversion Interrupt Disable 5" "0,1"
|
|
bitfld.long 0x4 4. "EOC4,End of Conversion Interrupt Disable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOC3,End of Conversion Interrupt Disable 3" "0,1"
|
|
bitfld.long 0x4 2. "EOC2,End of Conversion Interrupt Disable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EOC1,End of Conversion Interrupt Disable 1" "0,1"
|
|
bitfld.long 0x4 0. "EOC0,End of Conversion Interrupt Disable 0" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "EOC_IMR,End Of Conversion Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "EOC7,End of Conversion Interrupt Mask 7" "0,1"
|
|
bitfld.long 0x0 6. "EOC6,End of Conversion Interrupt Mask 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "EOC5,End of Conversion Interrupt Mask 5" "0,1"
|
|
bitfld.long 0x0 4. "EOC4,End of Conversion Interrupt Mask 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "EOC3,End of Conversion Interrupt Mask 3" "0,1"
|
|
bitfld.long 0x0 2. "EOC2,End of Conversion Interrupt Mask 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EOC1,End of Conversion Interrupt Mask 1" "0,1"
|
|
bitfld.long 0x0 0. "EOC0,End of Conversion Interrupt Mask 0" "0,1"
|
|
line.long 0x4 "EOC_ISR,End Of Conversion Interrupt Status Register"
|
|
bitfld.long 0x4 7. "EOC7,End of Conversion 7 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 6. "EOC6,End of Conversion 6 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EOC5,End of Conversion 5 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 4. "EOC4,End of Conversion 4 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "EOC3,End of Conversion 3 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 2. "EOC2,End of Conversion 2 (automatically set / cleared)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "EOC1,End of Conversion 1 (automatically set / cleared)" "0,1"
|
|
bitfld.long 0x4 0. "EOC0,End of Conversion 0 (automatically set / cleared)" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "TEMPMR,Temperature Sensor Mode Register"
|
|
bitfld.long 0x0 4.--5. "TEMPCMPMOD,Temperature Comparison Mode" "0: Generates the TEMPCHG flag in ADC_ISR when the..,1: Generates the TEMPCHG flag in ADC_ISR when the..,2: Generates the TEMPCHG flag in ADC_ISR when the..,3: Generates the TEMPCHG flag in ADC_ISR when the.."
|
|
bitfld.long 0x0 0. "TEMPON,Temperature Sensor On" "0,1"
|
|
line.long 0x4 "TEMPCWR,Temperature Compare Window Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "THIGHTHRES,Temperature High Threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "TLOWTHRES,Temperature Low Threshold"
|
|
rgroup.long 0x4C++0x3
|
|
line.long 0x0 "OVER,Overrun Status Register"
|
|
bitfld.long 0x0 7. "OVRE7,Overrun Error 7" "0,1"
|
|
bitfld.long 0x0 6. "OVRE6,Overrun Error 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE5,Overrun Error 5" "0,1"
|
|
bitfld.long 0x0 4. "OVRE4,Overrun Error 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRE3,Overrun Error 3" "0,1"
|
|
bitfld.long 0x0 2. "OVRE2,Overrun Error 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OVRE1,Overrun Error 1" "0,1"
|
|
bitfld.long 0x0 0. "OVRE0,Overrun Error 0" "0,1"
|
|
group.long 0x50++0x7
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 28.--29. "ADCMODE,ADC Running Mode" "0: Normal mode of operation.,1: Offset Error mode to measure the offset error.,2: Gain Error mode to measure the gain error. See..,3: Gain Error mode to measure the gain error. See.."
|
|
bitfld.long 0x0 25.--26. "SIGNMODE,Sign Mode" "0: Single-ended channels: unsigned conversions..,1: Single-ended channels: signed conversions..,2: All channels: unsigned conversions,3: All channels: signed conversions"
|
|
newline
|
|
bitfld.long 0x0 24. "TAG,ADC_LCDR Tag" "0,1"
|
|
bitfld.long 0x0 22.--23. "TRACKX,Tracking Time x4 x8 or x16" "0: ADC_MR.TRACKTIM effect is multiplied by 1.,1: ADC_MR.TRACKTIM effect is multiplied by 4.,2: ADC_MR.TRACKTIM effect is multiplied by 8,3: ADC_MR.TRACKTIM effect is multiplied by 16."
|
|
newline
|
|
bitfld.long 0x0 21. "SRCCLK,External Clock Selection" "0: The peripheral clock is the source for the ADC..,1: GCLK is the source clock for the ADC prescaler.."
|
|
bitfld.long 0x0 20. "ASTE,Averaging on Single Trigger Event" "0: The average requests several trigger events.,1: The average requests only one trigger event."
|
|
newline
|
|
bitfld.long 0x0 16.--18. "OSR,Over Sampling Rate" "0: No averaging. ADC sample rate is maximum.,1: 1-bit enhanced resolution by averaging. ADC..,2: 2-bit enhanced resolution by averaging. ADC..,3: 1-bit enhanced resolution by averaging. ADC..,4: 2-bit enhanced resolution by averaging. ADC..,?,?,?"
|
|
bitfld.long 0x0 12.--13. "CMPFILTER,Compare Event Filtering" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPALL,Compare All Channels" "0,1"
|
|
hexmask.long.byte 0x0 4.--8. 1. "CMPSEL,Comparison Selected Channel"
|
|
newline
|
|
bitfld.long 0x0 2. "CMPTYPE,Comparison Type" "0: Any conversion is performed and comparison..,1: Comparison conditions must be met to start the.."
|
|
bitfld.long 0x0 0.--1. "CMPMODE,Comparison Mode" "0: When the converted data is lower than the low..,1: When the converted data is higher than the high..,2: When the converted data is in the comparison..,3: When the converted data is out of the comparison.."
|
|
line.long 0x4 "CWR,Compare Window Register"
|
|
hexmask.long.word 0x4 16.--31. 1. "HIGHTHRES,High Threshold"
|
|
hexmask.long.word 0x4 0.--15. 1. "LOWTHRES,Low Threshold"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "CCR,Channel Configuration Register"
|
|
bitfld.long 0x0 7. "DIFF7,Differential Inputs for Channel 7" "0,1"
|
|
bitfld.long 0x0 6. "DIFF6,Differential Inputs for Channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DIFF5,Differential Inputs for Channel 5" "0,1"
|
|
bitfld.long 0x0 4. "DIFF4,Differential Inputs for Channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DIFF3,Differential Inputs for Channel 3" "0,1"
|
|
bitfld.long 0x0 2. "DIFF2,Differential Inputs for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DIFF1,Differential Inputs for Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "DIFF0,Differential Inputs for Channel 0" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "CDR[$1],Channel Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,Converted Data"
|
|
repeat.end
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "ACR,Analog Control Register"
|
|
bitfld.long 0x0 22. "SMVT,Supply Monitor Voltage Threshold" "0,1"
|
|
bitfld.long 0x0 21. "SMEN,Supply Monitor Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INTVREFEN,ADC Internal Positive Voltage Reference Enable" "0,1"
|
|
bitfld.long 0x0 2. "ZBAT,VBAT Resistive Load Selection" "0,1"
|
|
line.long 0x4 "FMR,FIFO Mode Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FIFOCNT,FIFO Count (read-only)"
|
|
hexmask.long.byte 0x4 4.--7. 1. "CHUNK,Chunk Size"
|
|
newline
|
|
bitfld.long 0x4 1. "ENLEVEL,Enable Level" "0: Request to DMA is generated as soon as one data..,1: Request to DMA is generated as soon as the.."
|
|
bitfld.long 0x4 0. "ENFIFO,Enable FIFO" "0: FIFO is disabled.,1: FIFO is enabled."
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x4 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
group.long 0x130++0xF
|
|
line.long 0x0 "TRGR,Trigger Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "TRGPER,Trigger Period"
|
|
bitfld.long 0x0 0.--2. "TRGMOD,Trigger Mode" "0: No hardware trigger only software trigger can..,1: Rising edge of the selected trigger event..,2: Falling edge of the selected trigger event,3: Any edge of the selected trigger event,?,5: ADC internal periodic trigger (see TRGPER),6: Continuous mode free run mode,?"
|
|
line.long 0x4 "COSR,Correction Select Register"
|
|
hexmask.long.byte 0x4 0.--4. 1. "CSEL,Channel Correction Select"
|
|
line.long 0x8 "CVR,Correction Values Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "GAINCORR,Gain Correction"
|
|
hexmask.long.word 0x8 0.--15. 1. "OFFSETCORR,Offset Correction"
|
|
line.long 0xC "CECR,Channel Error Correction Register"
|
|
bitfld.long 0xC 7. "ECORR7,Error Correction Enable for Channel 7" "0,1"
|
|
bitfld.long 0xC 6. "ECORR6,Error Correction Enable for Channel 6" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "ECORR5,Error Correction Enable for Channel 5" "0,1"
|
|
bitfld.long 0xC 4. "ECORR4,Error Correction Enable for Channel 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ECORR3,Error Correction Enable for Channel 3" "0,1"
|
|
bitfld.long 0xC 2. "ECORR2,Error Correction Enable for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "ECORR1,Error Correction Enable for Channel 1" "0,1"
|
|
bitfld.long 0xC 0. "ECORR0,Error Correction Enable for Channel 0" "0,1"
|
|
rgroup.long 0x144++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 0. "VADCSM,VDD ADC Supply Monitor Output" "0,1"
|
|
group.long 0x14C++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x150++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "AES (Advanced Encryption Standard)"
|
|
base ad:0x44000000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0,1"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "KSWP,Key Swap" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Key"
|
|
newline
|
|
bitfld.long 0x0 16.--18. "CFBS,Cipher Feedback Data Size" "0: 128-bit,1: 64-bit,2: 32-bit,3: 16-bit,4: 8-bit,?,?,?"
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "OPMOD,Operating Mode" "0: ECB: Electronic Codebook mode,1: CBC: Cipher Block Chaining mode,2: OFB: Output Feedback mode,3: CFB: Cipher Feedback mode,4: CTR: Counter mode (16-bit internal counter),5: GCM: Galois/Counter mode,?,?"
|
|
bitfld.long 0x0 10.--11. "KEYSIZE,Key Size" "0: AES Key Size is 128 bits,1: AES Key Size is 192 bits,2: AES Key Size is 256 bits,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual Mode,1: Auto Mode,2: AES_IDATAR0 access only Auto Mode (PDC),?"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PROCDLY,Processing Delay"
|
|
newline
|
|
bitfld.long 0x0 3. "DUALBUFF,Dual Input Buffer" "0: AES_IDATARx cannot be written during processing..,1: AES_IDATARx can be written during processing of.."
|
|
bitfld.long 0x0 1. "GTAGEN,GCM Automatic Tag Generation Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "PLENERR,Padding Length Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "EOPAD,End of Padding Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "TAGRDY,GCM Tag Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 18. "PLENERR,Padding Length Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "EOPAD,End of Padding" "0,1"
|
|
bitfld.long 0x4 16. "TAGRDY,GCM Tag Ready" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 12.--15. 1. "URAT,Unspecified Register Access (cleared by writing SWRST in AES_CR)"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "TXBUFE,TX Buffer Empty (cleared by writing AES_TCR or AES_TNCR)" "0,1"
|
|
bitfld.long 0x4 3. "RXBUFF,RX Buffer Full (cleared by writing AES_RCR or AES_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ENDTX,End of TX Buffer (cleared by writing AES_TCR or AES_TNCR)" "0,1"
|
|
bitfld.long 0x4 1. "ENDRX,End of RX Buffer (cleared by writing AES_RCR or AES_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx)" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEYWR[$1],Key Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYW,Key Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0x70++0x7
|
|
line.long 0x0 "AADLENR,Additional Authenticated Data Length Register"
|
|
hexmask.long 0x0 0.--31. 1. "AADLEN,Additional Authenticated Data Length"
|
|
line.long 0x4 "CLENR,Plaintext/Ciphertext Length Register"
|
|
hexmask.long 0x4 0.--31. 1. "CLEN,Plaintext/Ciphertext Length"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x78)++0x3
|
|
line.long 0x0 "GHASHR[$1],GCM Intermediate Hash Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "GHASH,Intermediate GCM Hash Word x"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x88)++0x3
|
|
line.long 0x0 "TAGR[$1],GCM Authentication Tag Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "TAG,GCM Authentication Tag x"
|
|
repeat.end
|
|
rgroup.long 0x98++0x3
|
|
line.long 0x0 "CTRR,GCM Encryption Counter Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CTR,GCM Encryption Counter"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x9C)++0x3
|
|
line.long 0x0 "GCMHR[$1],GCM H Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "H,GCM H Word x"
|
|
repeat.end
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 31. "BPE,Block Processing End" "0,1"
|
|
bitfld.long 0x0 24. "ALGO,Encryption Algorithm" "0: The AES algorithm is used for encryption.,1: The ARIA algorithm is used for encryption."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "NHEAD,IPSec Next Header"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PADLEN,Auto Padding Length"
|
|
newline
|
|
bitfld.long 0x0 7. "PKRS,Private Key Internal Register Select" "0,1"
|
|
bitfld.long 0x0 6. "PKWL,Private Key Write Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PLIPD,Protocol Layer Improved Performance Decipher" "0,1"
|
|
bitfld.long 0x0 4. "PLIPEN,Protocol Layer Improved Performance Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "KSEL,Key Selection" "0,1"
|
|
bitfld.long 0x0 1. "APM,Auto Padding Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "APEN,Auto Padding Enable" "0,1"
|
|
line.long 0x4 "BCNT,Byte Counter Register"
|
|
hexmask.long 0x4 0.--31. 1. "BCNT,Auto Padding Byte Counter"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--7. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the..,4: If a processing is in progress when the..,5: If a processing is in progress when the..,6: If a processing is in progress when the..,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 4. "PKRPVS,Private Key Internal Register Protection Violation Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree "AESB (Advanced Encryption Standard Bridge)"
|
|
base ad:0x44004000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0,1"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 31. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CKEY,Key"
|
|
newline
|
|
bitfld.long 0x0 15. "LOD,Last Output Data Mode" "0,1"
|
|
bitfld.long 0x0 12.--14. "OPMOD,Operating Mode" "0: Electronic Code Book mode,1: Cipher Block Chaining mode,?,?,4: Counter mode (16-bit internal counter),?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: AESB_IDATAR0 access only Auto mode,?"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PROCDLY,Processing Delay"
|
|
newline
|
|
bitfld.long 0x0 3. "DUALBUFF,Dual Input Buffer" "0: AESB_IDATARx cannot be written during processing..,1: AESB_IDATARx can be written during processing of.."
|
|
bitfld.long 0x0 2. "AAHB,Automatic Bridge Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CIPHER,Processing Mode" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event" "0,1"
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 19. "SECE,Security and/or Safety Event" "0,1"
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 19. "SECE,Security and/or Safety Event" "0,1"
|
|
hexmask.long.byte 0x4 12.--15. 1. "URAT,Unspecified Register Access"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "KEYWR[$1],Key Word Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEYW,Key Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data Word"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x50)++0x3
|
|
line.long 0x0 "ODATAR[$1],Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x60)++0x3
|
|
line.long 0x0 "IVR[$1],Initialization Vector Register"
|
|
hexmask.long 0x0 0.--31. 1. "IV,Initialization Vector"
|
|
repeat.end
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 7. "PKRS,Private Key Internal Register Select" "0,1"
|
|
bitfld.long 0x0 6. "PKWO,Private Key Write Once" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--7. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the..,4: If a processing is in progress when the..,5: If a processing is in progress when the..,6: If a processing is in progress when the..,?"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 4. "PKRPVS,Private Key Internal Register Protection Violation Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "CHIPID (Chip Identifier)"
|
|
base ad:0x40050200
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CIDR,Chip ID Register"
|
|
bitfld.long 0x0 31. "EXT,Extension Flag" "0,1"
|
|
bitfld.long 0x0 28.--30. "NVPTYP,Nonvolatile Program Memory Type" "0: ROM,1: ROMless or on-chip Flash,2: Embedded Flash Memory,3: ROM and Embedded Flash Memory - NVPSIZ is ROM..,4: SRAM emulating ROM,?,?,?"
|
|
hexmask.long.byte 0x0 20.--27. 1. "ARCH,Architecture Identifier"
|
|
hexmask.long.byte 0x0 16.--19. 1. "SRAMSIZ,Internal SRAM Size"
|
|
hexmask.long.byte 0x0 12.--15. 1. "NVPSIZ2,Second Nonvolatile Program Memory Size"
|
|
hexmask.long.byte 0x0 8.--11. 1. "NVPSIZ,Nonvolatile Program Memory Size"
|
|
newline
|
|
bitfld.long 0x0 5.--7. "EPROC,Embedded Processor" "0: Cortex-M7,1: ARM946ES,2: ARM7TDMI,3: Cortex-M3,4: ARM920T,5: ARM926EJS,6: Cortex-A5,7: Cortex-M4"
|
|
hexmask.long.byte 0x0 0.--4. 1. "VERSION,Version of the Device"
|
|
line.long 0x4 "EXID,Chip ID Extension Register"
|
|
hexmask.long 0x4 0.--31. 1. "EXID,Chip ID Extension"
|
|
tree.end
|
|
tree "CMCC (Cortex-M Cache Controller)"
|
|
base ad:0x0
|
|
tree "CMCC0"
|
|
base ad:0x46008000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TYPE,Cache Controller Type Register"
|
|
bitfld.long 0x0 11.--13. "CLSIZE,Cache LIne Size" "0: Cache line size is 4 bytes,1: Cache line size is 8 bytes,2: Cache line size is 16 bytes,3: Cache line size is 32 bytes,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CSIZE,Data Cache Size" "0: Cache size is 1 Kbyte,1: Cache size is 2 Kbytes,2: Cache size is 4 Kbytes,3: Cache size is 8 Kbytes,4: Cache size is 16 Kbytes,5: Cache size is 32 Kbytes,6: Cache size is 64 Kbytes,?"
|
|
bitfld.long 0x0 7. "LCKDOWN,Lockdown Supported" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "WAYNUM,Number of Ways" "0: Direct Mapped Cache,1: 2-way set associative,2: 4-way set associative,3: 8-way set associative"
|
|
bitfld.long 0x0 4. "RRP,Random Selection Policy Supported" "0,1"
|
|
bitfld.long 0x0 3. "LRUP,Least Recently Used Policy Supported" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RANDP,Random Selection Policy Supported" "0,1"
|
|
bitfld.long 0x0 1. "GCLK,Dynamic Clock Gating Supported" "0,1"
|
|
bitfld.long 0x0 0. "AP,Access Port Access Allowed" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CFG,Configuration Register"
|
|
bitfld.long 0x0 8. "LOCK,Configuration Lock Until Next System Reset (Write-once)" "0,1"
|
|
bitfld.long 0x0 4.--6. "PRGCSIZE,Programmable Cache Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "DCDIS,Data Caching Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ICDIS,Instruction Caching Disable" "0,1"
|
|
bitfld.long 0x0 0. "GCLKDIS,Disable Clock Gating" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CTRL,Control Register"
|
|
bitfld.long 0x0 8. "LOCK,Control Lock Until Next System Reset (Write-once)" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Cache Controller Enable" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 0. "CSTS,Cache Controller Status" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "MAINT0,Maintenance Register 0"
|
|
bitfld.long 0x0 0. "INVALL,Cache Controller Invalidate All" "0,1"
|
|
line.long 0x4 "MAINT1,Maintenance Register 1"
|
|
bitfld.long 0x4 30.--31. "WAY,Invalidate Way" "0: Way 0 is selection for index invalidation.,1: Way 1 is selection for index invalidation.,2: Way 2 is selection for index invalidation.,3: Way 3 is selection for index invalidation."
|
|
hexmask.long.byte 0x4 4.--10. 1. "INDEX,Invalidate Index"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "MCFG,Monitor Configuration Register"
|
|
bitfld.long 0x0 0.--1. "MODE,Cache Controller Monitor Counter Mode" "0: Cycle counter,1: Instruction hit counter only relevant for..,2: Data hit counter only relevant for unified cache..,?"
|
|
line.long 0x4 "MEN,Monitor Enable Register"
|
|
bitfld.long 0x4 0. "MENABLE,Cache Controller Monitor Enable" "0,1"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "MCTRL,Monitor Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Monitor" "0,1"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "MSR,Monitor Status Register"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_CNT,Monitor Event Counter"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCR,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPCFG,Write Protection Configuration Enable" "0,1"
|
|
tree.end
|
|
tree "CMCC1"
|
|
base ad:0x4600C000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TYPE,Cache Controller Type Register"
|
|
bitfld.long 0x0 11.--13. "CLSIZE,Cache LIne Size" "0: Cache line size is 4 bytes,1: Cache line size is 8 bytes,2: Cache line size is 16 bytes,3: Cache line size is 32 bytes,?,?,?,?"
|
|
bitfld.long 0x0 8.--10. "CSIZE,Data Cache Size" "0: Cache size is 1 Kbyte,1: Cache size is 2 Kbytes,2: Cache size is 4 Kbytes,3: Cache size is 8 Kbytes,4: Cache size is 16 Kbytes,5: Cache size is 32 Kbytes,6: Cache size is 64 Kbytes,?"
|
|
bitfld.long 0x0 7. "LCKDOWN,Lockdown Supported" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5.--6. "WAYNUM,Number of Ways" "0: Direct Mapped Cache,1: 2-way set associative,2: 4-way set associative,3: 8-way set associative"
|
|
bitfld.long 0x0 4. "RRP,Random Selection Policy Supported" "0,1"
|
|
bitfld.long 0x0 3. "LRUP,Least Recently Used Policy Supported" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RANDP,Random Selection Policy Supported" "0,1"
|
|
bitfld.long 0x0 1. "GCLK,Dynamic Clock Gating Supported" "0,1"
|
|
bitfld.long 0x0 0. "AP,Access Port Access Allowed" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CFG,Configuration Register"
|
|
bitfld.long 0x0 8. "LOCK,Configuration Lock Until Next System Reset (Write-once)" "0,1"
|
|
bitfld.long 0x0 4.--6. "PRGCSIZE,Programmable Cache Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 2. "DCDIS,Data Caching Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ICDIS,Instruction Caching Disable" "0,1"
|
|
bitfld.long 0x0 0. "GCLKDIS,Disable Clock Gating" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CTRL,Control Register"
|
|
bitfld.long 0x0 8. "LOCK,Control Lock Until Next System Reset (Write-once)" "0,1"
|
|
bitfld.long 0x0 0. "CEN,Cache Controller Enable" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 0. "CSTS,Cache Controller Status" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "MAINT0,Maintenance Register 0"
|
|
bitfld.long 0x0 0. "INVALL,Cache Controller Invalidate All" "0,1"
|
|
line.long 0x4 "MAINT1,Maintenance Register 1"
|
|
bitfld.long 0x4 30.--31. "WAY,Invalidate Way" "0: Way 0 is selection for index invalidation.,1: Way 1 is selection for index invalidation.,2: Way 2 is selection for index invalidation.,3: Way 3 is selection for index invalidation."
|
|
hexmask.long.byte 0x4 4.--10. 1. "INDEX,Invalidate Index"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "MCFG,Monitor Configuration Register"
|
|
bitfld.long 0x0 0.--1. "MODE,Cache Controller Monitor Counter Mode" "0: Cycle counter,1: Instruction hit counter only relevant for..,2: Data hit counter only relevant for unified cache..,?"
|
|
line.long 0x4 "MEN,Monitor Enable Register"
|
|
bitfld.long 0x4 0. "MENABLE,Cache Controller Monitor Enable" "0,1"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "MCTRL,Monitor Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Monitor" "0,1"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "MSR,Monitor Status Register"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_CNT,Monitor Event Counter"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCR,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPCFG,Write Protection Configuration Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "COREDEBUG"
|
|
base ad:0xE000EDF0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DHCSR,Debug Halting Control and Status Register"
|
|
rbitfld.long 0x0 25. "S_RESET_ST," "0,1"
|
|
rbitfld.long 0x0 24. "S_RETIRE_ST," "0,1"
|
|
rbitfld.long 0x0 19. "S_LOCKUP," "0,1"
|
|
rbitfld.long 0x0 18. "S_SLEEP," "0,1"
|
|
rbitfld.long 0x0 17. "S_HALT," "0,1"
|
|
rbitfld.long 0x0 16. "S_REGRDY," "0,1"
|
|
hexmask.long.word 0x0 16.--31. 1. "DBGKEY,"
|
|
bitfld.long 0x0 5. "C_SNAPSTALL," "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "C_MASKINTS," "0,1"
|
|
bitfld.long 0x0 2. "C_STEP," "0,1"
|
|
bitfld.long 0x0 1. "C_HALT," "0,1"
|
|
bitfld.long 0x0 0. "C_DEBUGEN," "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x0 16. "REGWnR," "0,1"
|
|
hexmask.long.byte 0x0 0.--4. 1. "REGSEL,"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DCRDR,Debug Core Register Data Register"
|
|
line.long 0x4 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x4 24. "TRCENA," "0,1"
|
|
bitfld.long 0x4 19. "MON_REQ," "0,1"
|
|
bitfld.long 0x4 18. "MON_STEP," "0,1"
|
|
bitfld.long 0x4 17. "MON_PEND," "0,1"
|
|
bitfld.long 0x4 16. "MON_EN," "0,1"
|
|
bitfld.long 0x4 10. "VC_HARDERR," "0,1"
|
|
bitfld.long 0x4 9. "VC_INTERR," "0,1"
|
|
bitfld.long 0x4 8. "VC_BUSERR," "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "VC_STATERR," "0,1"
|
|
bitfld.long 0x4 6. "VC_CHKERR," "0,1"
|
|
bitfld.long 0x4 5. "VC_NOCPERR," "0,1"
|
|
bitfld.long 0x4 4. "VC_MMERR," "0,1"
|
|
bitfld.long 0x4 0. "VC_CORERESET," "0,1"
|
|
tree.end
|
|
tree "CPKCC (Classical Public Key Cryptography Controller)"
|
|
base ad:0x46000000
|
|
group.long 0x0++0x2B
|
|
line.long 0x0 "R,R Parameter Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_R value"
|
|
line.long 0x4 "X,X Parameter Register"
|
|
hexmask.long 0x4 0.--31. 1. "VALUE,CPKCC_X value"
|
|
line.long 0x8 "Y,Y Parameter Register"
|
|
hexmask.long 0x8 0.--31. 1. "VALUE,CPKCC_Y value"
|
|
line.long 0xC "Z,Z Parameter Register"
|
|
hexmask.long 0xC 0.--31. 1. "VALUE,CPKCC_Z value"
|
|
line.long 0x10 "J,J Parameter Register"
|
|
hexmask.long 0x10 0.--31. 1. "VALUE,CPKCC_J value"
|
|
line.long 0x14 "K,K Parameter Register"
|
|
hexmask.long 0x14 0.--31. 1. "VALUE,CPKCC_K value"
|
|
line.long 0x18 "N,N Parameter Register"
|
|
hexmask.long 0x18 0.--31. 1. "VALUE,CPKCC_N value"
|
|
line.long 0x1C "SMULA,SMULA Register"
|
|
hexmask.long 0x1C 0.--31. 1. "VALUE,CPKCC_SMULA value"
|
|
line.long 0x20 "SMULB,SMULB Register"
|
|
hexmask.long 0x20 0.--31. 1. "VALUE,CPKCC_SMULB value"
|
|
line.long 0x24 "SMULRL,SMULRL Register"
|
|
hexmask.long 0x24 0.--31. 1. "VALUE,CPKCC_SMULRL value"
|
|
line.long 0x28 "SMULRH,SMULRH Register"
|
|
hexmask.long 0x28 0.--31. 1. "VALUE,CPKCC_SMULRH value"
|
|
group.byte 0x2C++0x1
|
|
line.byte 0x0 "IDLE,IDLE Register"
|
|
hexmask.byte 0x0 0.--7. 1. "VALUE,CPKCC_IDLE value"
|
|
line.byte 0x1 "IDLECACHE,IDLECACHE Register"
|
|
hexmask.byte 0x1 0.--7. 1. "VALUE,CPKCC_IDLECACHE value"
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "CR_C,CR_C Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_CR_C value"
|
|
line.long 0x4 "CR_S,CR_S Register"
|
|
hexmask.long 0x4 0.--31. 1. "VALUE,CPKCC_CR_S value"
|
|
line.long 0x8 "CR,CR Register"
|
|
hexmask.long.tbyte 0x8 9.--31. 1. "VALUE,CPKCC_CR value"
|
|
bitfld.long 0x8 8. "CLRRAM,CLRRAM value" "0,1"
|
|
bitfld.long 0x8 7. "ITEN,ITEN value" "0,1"
|
|
bitfld.long 0x8 6. "PKCCIRQ,CPKCC_IRQ value" "0,1"
|
|
bitfld.long 0x8 5. "AWAKE,AWAKE value" "0,1"
|
|
bitfld.long 0x8 4. "SPILLW,Spill Word register bit" "0,1"
|
|
bitfld.long 0x8 3. "ABORT,ABORT value" "0,1"
|
|
bitfld.long 0x8 2. "ONEMUL,ONEMUL value" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CARRYIN,CARRYIN value" "0,1"
|
|
bitfld.long 0x8 0. "GF2N,GF(2n) mode" "0,1"
|
|
line.long 0xC "OR,Operation Register"
|
|
hexmask.long.tbyte 0xC 11.--31. 1. "VALUE,CPKCC_OR value"
|
|
bitfld.long 0xC 10. "CARRYMUL,CARRYMUL value" "0,1"
|
|
bitfld.long 0xC 7. "OPTC1,OPTC1 value" "0,1"
|
|
bitfld.long 0xC 6. "OPTC0,OPTC0 value" "0,1"
|
|
bitfld.long 0xC 5. "OPTM1,OPTM1 value" "0,1"
|
|
bitfld.long 0xC 4. "OPTM0,OPTM0 value" "0,1"
|
|
bitfld.long 0xC 3. "CMD3,CMD3 value" "0,1"
|
|
bitfld.long 0xC 2. "CMD2,CMD2 value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "CMD1,CMD1 value" "0,1"
|
|
bitfld.long 0xC 0. "CMD0,CMD0 value" "0,1"
|
|
line.long 0x10 "SR,SR Register"
|
|
hexmask.long 0x10 7.--31. 1. "VALUE,CPKCC_SR value"
|
|
bitfld.long 0x10 6. "CLRRAM_BUSY,CLRRAM_BUSY value" "0,1"
|
|
bitfld.long 0x10 5. "SHAREV,SHAREV value" "0,1"
|
|
bitfld.long 0x10 4. "RAMV,RAM violation" "0,1"
|
|
bitfld.long 0x10 3. "ZERO,ZERO value" "0,1"
|
|
bitfld.long 0x10 2. "CARRY,CARRY value" "0,1"
|
|
bitfld.long 0x10 1. "CACHE,CACHE value" "0,1"
|
|
bitfld.long 0x10 0. "BUSY,BUSY value" "0,1"
|
|
group.long 0xEC++0x3
|
|
line.long 0x0 "ADDRSIZE,ADDRSIZE Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_ADDRSIZE value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xF0)++0x3
|
|
line.long 0x0 "IPNAME[$1],IPNAME1 Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_IPNAME1 value"
|
|
repeat.end
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "FEATURES,FEATURES Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,CPKCC_FEATURES value"
|
|
tree.end
|
|
tree "DWDT (Dual Watchdog Timer)"
|
|
base ad:0x40052000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "WDT1_CR,Watchdog 1 Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0,1"
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "WDT1_MR,Watchdog 1 Mode Register"
|
|
bitfld.long 0x0 30. "WDDBG1HLT,Watchdog Core 1 Debug Halt" "0,1"
|
|
bitfld.long 0x0 29. "WDDBG0HLT,Watchdog Core 0 Debug Halt" "0,1"
|
|
bitfld.long 0x0 28. "WDIDLEHLT,Watchdog Idle Halt" "0,1"
|
|
bitfld.long 0x0 12. "WDDIS,Watchdog Disable" "0,1"
|
|
bitfld.long 0x0 9. "WDNRSTDIS,Watchdog Reset NRST Pin Disable" "0,1"
|
|
bitfld.long 0x0 5. "RPTHRST,Repeat Threshold Reset Enable" "0,1"
|
|
bitfld.long 0x0 4. "PERIODRST,Watchdog Overflow Period Reset Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "WDT1_VR,Watchdog 1 Value Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "COUNTER,Watchdog Down Counter Value"
|
|
group.long 0xC++0x7
|
|
line.long 0x0 "WDT1_WL,Watchdog 1 Window Level Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "RPTH,Repeat Threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "PERIOD,Watchdog Period"
|
|
line.long 0x4 "WDT1_IL,Watchdog 1 Interrupt Level Register"
|
|
bitfld.long 0x4 16.--18. "PRESC,Prescaler Ratio" "0: The watchdog counter decreased when the..,1: The watchdog counter decreased when the..,2: The watchdog counter decreased when the..,3: The watchdog counter decreased when the..,4: The watchdog counter decreased when the..,5: The watchdog counter decreased when the..,6: The watchdog counter decreased when the..,7: The watchdog counter decreased when the.."
|
|
hexmask.long.word 0x4 0.--11. 1. "LVLTH,Level Threshold"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "WDT1_IER,Watchdog 1 Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "RLDERR,Reload Command Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "RPTHINT,Reload Repeat Period Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "PERINT,Overflow Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "WDT1_IDR,Watchdog 1 Interrupt Disable Register"
|
|
bitfld.long 0x4 5. "RLDERR,Reload Command Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "RPTHINT,Reload Repeat Period Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "PERINT,Overflow Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "WDT1_ISR,Watchdog 1 Interrupt Status Register"
|
|
bitfld.long 0x0 5. "RLDERR,Reload Command Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "RPTHINT,Reload Repeat Period Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "PERINT,Overflow Period Status (cleared on read)" "0,1"
|
|
line.long 0x4 "WDT1_IMR,Watchdog 1 Interrupt Mask Register"
|
|
bitfld.long 0x4 5. "RLDERR,Reload Command Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "RPTHINT,Reload Repeat Period Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 0. "PERINT,Overflow Period Interrupt Mask" "0,1"
|
|
wgroup.long 0x1210++0x3
|
|
line.long 0x0 "WDT0_CR,Watchdog 0 Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 4. "LOCKMR,Lock Mode Register Write Access" "0,1"
|
|
bitfld.long 0x0 0. "WDRSTT,Watchdog Restart" "0,1"
|
|
group.long 0x1214++0x3
|
|
line.long 0x0 "WDT0_MR,Watchdog 0 Mode Register"
|
|
bitfld.long 0x0 30. "WDDBG1HLT,Watchdog Core 1 Debug Halt" "0,1"
|
|
bitfld.long 0x0 29. "WDDBG0HLT,Watchdog Core 0 Debug Halt" "0,1"
|
|
bitfld.long 0x0 28. "WDIDLEHLT,Watchdog Idle Halt" "0,1"
|
|
bitfld.long 0x0 12. "WDDIS,Watchdog Disable" "0,1"
|
|
bitfld.long 0x0 9. "WDNRSTDIS,Watchdog NRST Disable" "0,1"
|
|
bitfld.long 0x0 5. "RPTHRST,Repeat Threshold Reset" "0,1"
|
|
bitfld.long 0x0 4. "PERIODRST,Period Reset" "0,1"
|
|
rgroup.long 0x1218++0x3
|
|
line.long 0x0 "WDT0_VR,Watchdog 0 Value Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "COUNTER,Watchdog Down Counter Value"
|
|
group.long 0x121C++0x7
|
|
line.long 0x0 "WDT0_WL,Watchdog 0 Window Level"
|
|
hexmask.long.word 0x0 16.--27. 1. "RPTH,Repeat Threshold"
|
|
hexmask.long.word 0x0 0.--11. 1. "PERIOD,Watchdog Period"
|
|
line.long 0x4 "WDT0_IL,Watchdog 0 Interrupt Level"
|
|
bitfld.long 0x4 16.--18. "PRESC,Prescaler Ratio" "0: The watchdog counter decreased when the..,1: The watchdog counter decreased when the..,2: The watchdog counter decreased when the..,3: The watchdog counter decreased when the..,4: The watchdog counter decreased when the..,5: The watchdog counter decreased when the..,6: The watchdog counter decreased when the..,7: The watchdog counter decreased when the.."
|
|
hexmask.long.word 0x4 0.--11. 1. "LVLTH,Level Threshold"
|
|
wgroup.long 0x1224++0x7
|
|
line.long 0x0 "WDT0_IER,Watchdog 0 Interrupt Enable Register"
|
|
bitfld.long 0x0 5. "RLDERR,Reload Command Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "W1RPTHINT,Watchdog 1 Repeat Threshold Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "W1PERINT,Watchdog 1 Overflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "RPTHINT,Reload Repeat Period Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "PERINT,Overflow Period Interrupt Enable" "0,1"
|
|
line.long 0x4 "WDT0_IDR,Watchdog 0 Interrupt Disable Register"
|
|
bitfld.long 0x4 5. "RLDERR,Reload Command Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "W1RPTHINT,Watchdog 1 Repeat Threshold Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "W1PERINT,Watchdog 1 Overflow Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "RPTHINT,Reload Repeat Period Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "PERINT,Overflow Period Interrupt Disable" "0,1"
|
|
rgroup.long 0x122C++0x7
|
|
line.long 0x0 "WDT0_ISR,Watchdog 0 Interrupt Status Register"
|
|
bitfld.long 0x0 5. "RLDERR,Reload Command Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "W1RPTHINT,Watchdog 1 Repeat Threshold Interrupt Status" "0,1"
|
|
bitfld.long 0x0 3. "W1PERINT,Watchdog 1 Overflow Interrupt Status" "0,1"
|
|
bitfld.long 0x0 2. "LVLINT,Interrupt Level Threshold Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "RPTHINT,Reload Repeat Period Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "PERINT,Overflow Period Status (cleared on read)" "0,1"
|
|
line.long 0x4 "WDT0_IMR,Watchdog 0 Interrupt Mask Register"
|
|
bitfld.long 0x4 5. "RLDERR,Reload Command Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "W1RPTHINT,Watchdog 1 Repeat Threshold Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 3. "W1PERINT,Watchdog 1 Overflow Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 2. "LVLINT,Interrupt Level Threshold Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 1. "RPTHINT,Reload Repeat Period Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 0. "PERINT,Overflow Period Interrupt Mask" "0,1"
|
|
group.long 0x1234++0xB
|
|
line.long 0x0 "WDT1_LVLLIM,Watchdog 1 Level Limits Register"
|
|
hexmask.long.word 0x0 16.--27. 1. "LVLMAX,Maximum Level"
|
|
hexmask.long.word 0x0 0.--11. 1. "LVLMIN,Minimum Level"
|
|
line.long 0x4 "WDT1_RLIM,Watchdog 1 Repeat Limits Register"
|
|
hexmask.long.word 0x4 16.--27. 1. "RPTHMAX,Maximum Repeat Threshold"
|
|
hexmask.long.word 0x4 0.--11. 1. "RPTHMIN,Minimum Repeat Threshold"
|
|
line.long 0x8 "WDT1_PLIM,Watchdog 1 Period Limits Register"
|
|
hexmask.long.word 0x8 16.--27. 1. "PERMAX,Maximum Period"
|
|
hexmask.long.word 0x8 0.--11. 1. "PERMIN,Minimum Period"
|
|
tree.end
|
|
tree "DWT (Data Watchpoint and Trace)"
|
|
base ad:0xE0001000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "NUMCOMP,"
|
|
bitfld.long 0x0 27. "NOTRCPKT," "0,1"
|
|
bitfld.long 0x0 26. "NOEXTTRIG," "0,1"
|
|
bitfld.long 0x0 25. "NOCYCCNT," "0,1"
|
|
bitfld.long 0x0 24. "NOPRFCNT," "0,1"
|
|
bitfld.long 0x0 22. "CYCEVTENA," "0,1"
|
|
bitfld.long 0x0 21. "FOLDEVTENA," "0,1"
|
|
bitfld.long 0x0 20. "LSUEVTENA," "0,1"
|
|
bitfld.long 0x0 19. "SLEEPEVTENA," "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "EXCEVTENA," "0,1"
|
|
bitfld.long 0x0 17. "CPIEVTENA," "0,1"
|
|
bitfld.long 0x0 16. "EXCTRCENA," "0,1"
|
|
bitfld.long 0x0 12. "PCSAMPLENA," "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCTAP," "0,1,2,3"
|
|
bitfld.long 0x0 9. "CYCTAP," "0,1"
|
|
hexmask.long.byte 0x0 5.--8. 1. "POSTINIT,"
|
|
hexmask.long.byte 0x0 1.--4. 1. "POSTPRESET,"
|
|
bitfld.long 0x0 0. "CYCCNTENA," "0,1"
|
|
line.long 0x4 "CYCCNT,Cycle Count Register"
|
|
line.long 0x8 "CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CPICNT,"
|
|
line.long 0xC "EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXCCNT,"
|
|
line.long 0x10 "SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,"
|
|
line.long 0x14 "LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,"
|
|
line.long 0x18 "FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PCSR,Program Counter Sample Register"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "COMP0,Comparator Register 0"
|
|
line.long 0x4 "MASK0,Mask Register 0"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION0,Function Register 0"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
group.long 0x30++0xB
|
|
line.long 0x0 "COMP1,Comparator Register 1"
|
|
line.long 0x4 "MASK1,Mask Register 1"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION1,Function Register 1"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
group.long 0x40++0xB
|
|
line.long 0x0 "COMP2,Comparator Register 2"
|
|
line.long 0x4 "MASK2,Mask Register 2"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION2,Function Register 2"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "COMP3,Comparator Register 3"
|
|
line.long 0x4 "MASK3,Mask Register 3"
|
|
hexmask.long.byte 0x4 0.--4. 1. "MASK,"
|
|
line.long 0x8 "FUNCTION3,Function Register 3"
|
|
bitfld.long 0x8 24. "MATCHED," "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "DATAVADDR1,"
|
|
hexmask.long.byte 0x8 12.--15. 1. "DATAVADDR0,"
|
|
bitfld.long 0x8 10.--11. "DATAVSIZE," "0,1,2,3"
|
|
bitfld.long 0x8 9. "LNK1ENA," "0,1"
|
|
bitfld.long 0x8 8. "DATAVMATCH," "0,1"
|
|
bitfld.long 0x8 7. "CYCMATCH," "0,1"
|
|
bitfld.long 0x8 5. "EMITRANGE," "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "FUNCTION,"
|
|
tree.end
|
|
tree "FLEXCOM (Flexible Serial Communication Controller)"
|
|
base ad:0x0
|
|
tree "FLEXCOM0"
|
|
base ad:0x40000000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "FLEX_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "FLEX_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
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newline
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bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
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newline
|
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bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
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newline
|
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bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
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newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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newline
|
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bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
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newline
|
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bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
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newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
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newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
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newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
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newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
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newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
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newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
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bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
|
newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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newline
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
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newline
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
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newline
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bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
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newline
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bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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newline
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bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
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newline
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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newline
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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newline
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
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newline
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
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newline
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM1"
|
|
base ad:0x40004000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
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group.long 0x20++0x3
|
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
group.long 0x100++0x1F
|
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line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "FLEX_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "FLEX_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
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line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
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newline
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
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bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
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newline
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
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newline
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
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newline
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
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newline
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bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
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newline
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bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
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newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
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newline
|
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bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
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newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
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wgroup.long 0x414++0x7
|
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
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group.long 0x440++0x3
|
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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group.long 0x448++0x3
|
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x4E4++0x3
|
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
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rgroup.long 0x4E8++0x3
|
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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newline
|
|
bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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|
newline
|
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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|
newline
|
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bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
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newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
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|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
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|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
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newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
|
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
|
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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newline
|
|
bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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|
newline
|
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
|
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
|
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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newline
|
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
|
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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newline
|
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
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newline
|
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
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newline
|
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
|
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM2"
|
|
base ad:0x40008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "FLEX_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "FLEX_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
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newline
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bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
|
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
|
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
|
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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newline
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
|
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
|
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
|
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
|
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
|
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
|
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line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
|
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bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
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newline
|
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bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
|
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
|
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
|
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
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|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
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|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
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|
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bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
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|
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bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
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|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
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|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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|
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bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
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|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
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|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
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|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
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|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
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|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
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|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
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|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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newline
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bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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newline
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
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|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
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|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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|
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bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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newline
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bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
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newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
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newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
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newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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newline
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
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bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
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bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
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newline
|
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
|
|
group.long 0x638++0x1B
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
|
|
line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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|
newline
|
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
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newline
|
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
|
|
line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
|
bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
|
|
newline
|
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
|
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
|
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
|
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newline
|
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
|
|
newline
|
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
|
|
newline
|
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
|
|
line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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rgroup.long 0x660++0x3
|
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
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newline
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x66C++0x3
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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group.long 0x6E4++0x3
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line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x6E8++0x3
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line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
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tree.end
|
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tree "FLEXCOM3"
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base ad:0x4000C000
|
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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group.long 0x100++0x1F
|
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line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
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hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
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line.long 0x4 "FLEX_RCR,Receive Counter Register"
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hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
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line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
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hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
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line.long 0xC "FLEX_TCR,Transmit Counter Register"
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hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
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line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
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hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
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line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
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hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
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line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
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hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
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line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
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hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
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wgroup.long 0x120++0x3
|
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line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
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bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
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newline
|
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bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
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rgroup.long 0x124++0x3
|
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line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
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bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
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newline
|
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bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
|
bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
|
rgroup.long 0x218++0x3
|
|
line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
|
line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
|
bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
|
line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
|
line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
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|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
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|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
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|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
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|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
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|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
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|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
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|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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group.long 0x2E4++0x3
|
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x2E8++0x3
|
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x400++0x3
|
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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|
newline
|
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
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|
newline
|
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
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group.long 0x404++0x3
|
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
|
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bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
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|
newline
|
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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|
newline
|
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
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newline
|
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
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rgroup.long 0x408++0x3
|
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
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newline
|
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
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wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
|
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wgroup.long 0x634++0x3
|
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
|
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group.long 0x638++0x1B
|
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
|
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
|
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
|
|
line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
|
bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
|
|
line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
|
|
newline
|
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
|
|
line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
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tree.end
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tree "FLEXCOM4"
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base ad:0x40010000
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group.long 0x0++0x3
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line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
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bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
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rgroup.long 0x10++0x3
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line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
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group.long 0x20++0x3
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
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group.long 0x100++0x1F
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line.long 0x0 "FLEX_RPR,Receive Pointer Register"
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hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
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line.long 0x4 "FLEX_RCR,Receive Counter Register"
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hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
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line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
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hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
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line.long 0xC "FLEX_TCR,Transmit Counter Register"
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hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
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line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
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hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
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line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
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hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
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line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
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hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
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line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
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hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
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wgroup.long 0x120++0x3
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line.long 0x0 "FLEX_PTCR,Transfer Control Register"
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bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
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newline
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bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
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newline
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bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
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newline
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bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
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newline
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bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
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newline
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bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
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rgroup.long 0x124++0x3
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line.long 0x0 "FLEX_PTSR,Transfer Status Register"
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bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
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newline
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bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
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newline
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bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
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group.long 0x128++0x3
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line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
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newline
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bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
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newline
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bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
|
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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newline
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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newline
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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newline
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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newline
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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newline
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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newline
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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newline
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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newline
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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newline
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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newline
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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newline
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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newline
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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newline
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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newline
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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newline
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
|
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
|
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
|
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
|
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
|
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
|
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
|
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
|
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
|
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line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
|
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bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
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newline
|
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bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
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newline
|
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
|
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
|
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
|
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
|
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
|
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
|
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
|
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
|
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
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newline
|
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
|
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
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wgroup.long 0x20C++0x3
|
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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rgroup.long 0x210++0x7
|
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
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newline
|
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bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
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group.long 0x240++0x3
|
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
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group.long 0x24C++0xF
|
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
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newline
|
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
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newline
|
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
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newline
|
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
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newline
|
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
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newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
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newline
|
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
|
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newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
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newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
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newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
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newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
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newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
|
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x2A4++0x3
|
|
line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
wgroup.long 0x2A8++0x7
|
|
line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
|
line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
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newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
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newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
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bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
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newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
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newline
|
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bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
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newline
|
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bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
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newline
|
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bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
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newline
|
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bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
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group.long 0x604++0xF
|
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line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
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bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
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newline
|
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hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
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newline
|
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bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
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newline
|
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bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
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newline
|
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bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
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line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
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bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
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hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
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hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
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bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
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line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
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hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
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hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
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newline
|
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bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
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bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
|
|
group.long 0x638++0x1B
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
|
|
line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
|
|
line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
|
bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
|
|
line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
|
|
newline
|
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
|
|
line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM5"
|
|
base ad:0x40014000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "FLEX_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "FLEX_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
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newline
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bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
|
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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newline
|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
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newline
|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
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newline
|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
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newline
|
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bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
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newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
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|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
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|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
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|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
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rgroup.long 0x218++0x3
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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newline
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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newline
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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newline
|
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
|
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
|
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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newline
|
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bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
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|
newline
|
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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|
newline
|
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
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|
newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
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newline
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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|
newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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|
newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
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|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
|
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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newline
|
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
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group.long 0x2E4++0x3
|
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
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newline
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hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
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bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
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newline
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
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newline
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bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
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rgroup.long 0x620++0x3
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line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
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bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
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newline
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bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
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newline
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bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
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newline
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bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
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newline
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bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
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wgroup.long 0x624++0x7
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line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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newline
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bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
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newline
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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newline
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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newline
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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newline
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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newline
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
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newline
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
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newline
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
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newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
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bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM6"
|
|
base ad:0x40018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
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group.long 0x20++0x3
|
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line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
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hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
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group.long 0x100++0x1F
|
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line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "FLEX_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
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line.long 0xC "FLEX_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
|
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hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
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line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
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hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
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line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
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hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
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wgroup.long 0x120++0x3
|
|
line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
wgroup.long 0x200++0x3
|
|
line.long 0x0 "FLEX_US_CR,USART Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR,USART Mode Register"
|
|
bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
group.long 0x204++0x3
|
|
line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
|
|
bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
|
|
newline
|
|
bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
|
|
newline
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
|
|
newline
|
|
bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
|
|
newline
|
|
bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
|
|
wgroup.long 0x208++0x3
|
|
line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
wgroup.long 0x208++0x7
|
|
line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
wgroup.long 0x20C++0x3
|
|
line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
|
|
rgroup.long 0x210++0x3
|
|
line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
|
rgroup.long 0x210++0x7
|
|
line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
|
bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
|
newline
|
|
bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
|
rgroup.long 0x214++0x7
|
|
line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
|
bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
|
|
newline
|
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
|
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newline
|
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
|
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
|
|
bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
|
|
wgroup.long 0x21C++0x3
|
|
line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
|
|
newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
|
group.long 0x220++0xB
|
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
|
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
newline
|
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
|
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
|
|
group.long 0x240++0x3
|
|
line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
|
|
rgroup.long 0x244++0x3
|
|
line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
|
|
group.long 0x24C++0xF
|
|
line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
|
|
line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
|
bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
|
|
newline
|
|
bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
|
|
line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
|
|
bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
|
|
newline
|
|
bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
|
|
line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
|
|
rgroup.long 0x25C++0x3
|
|
line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
|
|
bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
|
|
group.long 0x290++0x3
|
|
line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
|
|
hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x2A4++0x3
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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wgroup.long 0x2A8++0x7
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
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rgroup.long 0x2B0++0x7
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
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bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
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bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
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bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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newline
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bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
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group.long 0x2E4++0x3
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line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
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rgroup.long 0x2E8++0x3
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line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
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hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
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newline
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
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wgroup.long 0x400++0x3
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line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
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bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
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bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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newline
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bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
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newline
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bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
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group.long 0x404++0x3
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line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
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newline
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bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
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newline
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bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
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newline
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bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
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newline
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bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
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newline
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bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
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newline
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bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
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newline
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bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
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newline
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bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
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newline
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bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
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hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
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rgroup.long 0x408++0x3
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line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
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hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
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bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
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wgroup.long 0x40C++0x3
|
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line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
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hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
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newline
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hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
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rgroup.long 0x410++0x3
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line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
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bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
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bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
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newline
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bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
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newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
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newline
|
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bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
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newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
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wgroup.long 0x414++0x7
|
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line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
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bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
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newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
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newline
|
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hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
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hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
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bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
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group.long 0x440++0x3
|
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line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
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newline
|
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hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
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rgroup.long 0x444++0x3
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line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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group.long 0x448++0x3
|
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line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
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hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
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group.long 0x4E4++0x3
|
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line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
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hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
|
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
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rgroup.long 0x4E8++0x3
|
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line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
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newline
|
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bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
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wgroup.long 0x600++0x3
|
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line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
|
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newline
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
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bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
|
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bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
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rgroup.long 0x62C++0x7
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line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
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bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
|
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bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
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line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
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bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
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newline
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bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
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newline
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bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
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newline
|
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hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
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rgroup.long 0x630++0x3
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line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
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wgroup.long 0x634++0x3
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line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
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hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
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newline
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hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
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newline
|
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hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
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group.long 0x638++0x1B
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line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
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hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
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newline
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hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
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newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
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line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
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hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
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line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
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bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
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newline
|
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bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
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newline
|
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hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
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newline
|
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bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
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newline
|
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bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
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newline
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hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
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line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
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bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
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newline
|
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bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
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newline
|
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bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
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line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
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bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
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newline
|
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hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
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line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
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hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
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newline
|
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hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
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newline
|
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hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
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newline
|
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hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
|
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line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
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hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
|
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bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
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rgroup.long 0x654++0x3
|
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line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
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rgroup.long 0x660++0x3
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line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
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bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
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|
newline
|
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bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
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wgroup.long 0x664++0x7
|
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line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
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newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
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rgroup.long 0x66C++0x3
|
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line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "FLEXCOM7"
|
|
base ad:0x4001C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FLEX_MR,FLEXCOM Mode Register"
|
|
bitfld.long 0x0 0.--1. "OPMODE,FLEXCOM Operating Mode" "0: No communication,1: All UART related protocols are selected (RS232..,2: SPI operating mode is selected. USART/TWI..,3: All TWI related protocols are selected (TWI.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "FLEX_RHR,FLEXCOM Receive Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RXDATA,Receive Data"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "FLEX_THR,FLEXCOM Transmit Holding Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXDATA,Transmit Data"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "FLEX_RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "FLEX_RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "FLEX_TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "FLEX_TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "FLEX_RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "FLEX_RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "FLEX_TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "FLEX_TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "FLEX_PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "FLEX_PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "FLEX_PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
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newline
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bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
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newline
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bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
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bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
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wgroup.long 0x200++0x3
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line.long 0x0 "FLEX_US_CR,USART Control Register"
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bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
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bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
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bitfld.long 0x0 28. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
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bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
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bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
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bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
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bitfld.long 0x0 21. "LINWKUP,Send LIN Wakeup Signal" "0,1"
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bitfld.long 0x0 20. "LINABT,Abort LIN Transmission" "0,1"
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bitfld.long 0x0 19. "RTSDIS,Request to Send Disable" "0,1"
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bitfld.long 0x0 18. "RTSEN,Request to Send Enable" "0,1"
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bitfld.long 0x0 15. "RETTO,Start Timeout Immediately" "0,1"
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bitfld.long 0x0 14. "RSTNACK,Reset Non Acknowledge" "0,1"
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bitfld.long 0x0 13. "RSTIT,Reset Iterations" "0,1"
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bitfld.long 0x0 12. "SENDA,Send Address" "0,1"
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bitfld.long 0x0 11. "STTTO,Clear TIMEOUT Flag and Start Timeout After Next Character Received" "0,1"
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bitfld.long 0x0 10. "STPBRK,Stop Break" "0,1"
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bitfld.long 0x0 9. "STTBRK,Start Break" "0,1"
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bitfld.long 0x0 8. "RSTSTA,Reset Status Bits" "0,1"
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newline
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bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
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newline
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bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
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newline
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bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
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bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
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bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
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newline
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bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR,USART Mode Register"
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bitfld.long 0x0 31. "ONEBIT,Start Frame Delimiter Selector" "0,1"
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newline
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bitfld.long 0x0 30. "MODSYNC,Manchester Synchronization Mode" "0,1"
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newline
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bitfld.long 0x0 29. "MAN,Manchester Encoder/Decoder Enable" "0,1"
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 24.--26. "MAX_ITERATION,Maximum Number of Automatic Iteration" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 23. "INVDATA,Inverted Data" "0,1"
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newline
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bitfld.long 0x0 22. "VAR_SYNC,Variable Synchronization of Command/Data Sync Start Frame Delimiter" "0,1"
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newline
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bitfld.long 0x0 21. "DSNACK,Disable Successive NACK" "0,1"
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newline
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bitfld.long 0x0 20. "INACK,Inhibit Non Acknowledge" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits,1: Character length is 6 bits,2: Character length is 7 bits,3: Character length is 8 bits"
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected,1: Peripheral clock divided (DIV = 8) is selected,2: PMC generic clock is selected. If the SCK pin is..,3: External pin SCK is selected"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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group.long 0x204++0x3
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line.long 0x0 "FLEX_US_MR_OOK_MODE,USART Mode Register"
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bitfld.long 0x0 28. "FILTER,Receive Line Filter" "0,1"
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newline
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bitfld.long 0x0 21. "OOKEN,OOK Modulation/Demodulation Enabled" "0,1"
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newline
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bitfld.long 0x0 20. "OOKRXD,OOK Demodulation Input Selection" "0,1"
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newline
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bitfld.long 0x0 19. "OVER,Oversampling Mode" "0,1"
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newline
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bitfld.long 0x0 18. "CLKO,Clock Output Select" "0,1"
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newline
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bitfld.long 0x0 17. "MODE9,9-bit Character Length" "0,1"
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newline
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bitfld.long 0x0 16. "MSBF,Bit Order" "0,1"
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newline
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bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic Echo. Receiver input is connected to..,2: Local Loopback. Transmitter output is connected..,3: Remote Loopback. RXD pin is internally connected.."
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newline
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bitfld.long 0x0 12.--13. "NBSTOP,Number of Stop Bits" "0: 1 stop bit,1: 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1),2: 2 stop bits,?"
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newline
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bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even parity,1: Odd parity,2: Parity forced to 0 (Space),3: Parity forced to 1 (Mark),4: No parity,?,6: Multidrop mode,?"
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newline
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bitfld.long 0x0 8. "SYNC,Synchronous Mode Select" "0,1"
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newline
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bitfld.long 0x0 6.--7. "CHRL,Character Length" "0: Character length is 5 bits.,1: Character length is 6 bits.,2: Character length is 7 bits.,3: Character length is 8 bits."
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newline
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bitfld.long 0x0 4.--5. "USCLKS,Clock Selection" "0: Peripheral clock is selected.,1: Peripheral clock divided (DIV=8) is selected.,2: PMC programmable clock (PCK) is selected. If the..,3: Serial clock (SCK) is selected."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "USART_MODE,USART Mode of Operation"
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wgroup.long 0x208++0x3
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line.long 0x0 "FLEX_US_IER,USART Interrupt Enable Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max number of Repetitions Reached Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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wgroup.long 0x208++0x7
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line.long 0x0 "FLEX_US_IER_LIN_MODE_MODE,USART Interrupt Enable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Enable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Enable" "0,1"
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line.long 0x4 "FLEX_US_IDR,USART Interrupt Disable Register"
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bitfld.long 0x4 24. "MANE,Manchester Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 22. "CMP,Comparison Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 12. "RXBUFF,Buffer Full Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 11. "TXBUFE,Buffer Empty Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 4. "ENDTX,End of Transmit Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 3. "ENDRX,End of Receive Transfer Interrupt Disable (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x4 2. "RXBRK,Receiver Break Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x4 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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wgroup.long 0x20C++0x3
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line.long 0x0 "FLEX_US_IDR_LIN_MODE_MODE,USART Interrupt Disable Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Disable" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Disable" "0,1"
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rgroup.long 0x210++0x3
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line.long 0x0 "FLEX_US_IMR,USART Interrupt Mask Register"
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bitfld.long 0x0 24. "MANE,Manchester Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 22. "CMP,Comparison Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 19. "CTSIC,Clear to Send Input Change Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "NACK,Non Acknowledge Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 10. "ITER,Max Number of Repetitions Reached Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask (available in all USART modes of operation)" "0,1"
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newline
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bitfld.long 0x0 2. "RXBRK,Receiver Break Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
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rgroup.long 0x210++0x7
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line.long 0x0 "FLEX_US_IMR_LIN_MODE_MODE,USART Interrupt Mask Register"
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 25. "LINBE,LIN Bus Error Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 12. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,Buffer Empty Interrupt Mask" "0,1"
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newline
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bitfld.long 0x0 9. "TXEMPTY,TXEMPTY Interrupt Mask" "0,1"
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|
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bitfld.long 0x0 8. "TIMEOUT,Timeout Interrupt Mask" "0,1"
|
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|
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bitfld.long 0x0 7. "PARE,Parity Error Interrupt Mask" "0,1"
|
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|
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bitfld.long 0x0 6. "FRAME,Framing Error Interrupt Mask" "0,1"
|
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|
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bitfld.long 0x0 5. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
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|
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bitfld.long 0x0 4. "ENDTX,End of Transmit Interrupt Mask" "0,1"
|
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|
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bitfld.long 0x0 3. "ENDRX,End of Receive Transfer Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXRDY,TXRDY Interrupt Mask" "0,1"
|
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|
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bitfld.long 0x0 0. "RXRDY,RXRDY Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_CSR,USART Channel Status Register"
|
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bitfld.long 0x4 24. "MANE,Manchester Error" "0,1"
|
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|
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bitfld.long 0x4 23. "CTS,Image of CTS Input" "0,1"
|
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|
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bitfld.long 0x4 22. "CMP,Comparison Status" "0,1"
|
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|
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bitfld.long 0x4 19. "CTSIC,Clear to Send Input Change Flag" "0,1"
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newline
|
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bitfld.long 0x4 13. "NACK,Non Acknowledge Interrupt" "0,1"
|
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|
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bitfld.long 0x4 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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|
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bitfld.long 0x4 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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|
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bitfld.long 0x4 10. "ITER,Max Number of Repetitions Reached" "0,1"
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bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
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|
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bitfld.long 0x4 8. "TIMEOUT,Receiver Timeout" "0,1"
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|
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bitfld.long 0x4 7. "PARE,Parity Error" "0,1"
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|
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bitfld.long 0x4 6. "FRAME,Framing Error" "0,1"
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|
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bitfld.long 0x4 5. "OVRE,Overrun Error" "0,1"
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|
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bitfld.long 0x4 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
|
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|
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bitfld.long 0x4 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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bitfld.long 0x4 2. "RXBRK,Break Received/End of Break" "0,1"
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bitfld.long 0x4 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
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bitfld.long 0x4 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
|
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rgroup.long 0x214++0x7
|
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line.long 0x0 "FLEX_US_CSR_LIN_MODE_MODE,USART Channel Status Register"
|
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bitfld.long 0x0 31. "LINHTE,LIN Header Timeout Error" "0,1"
|
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|
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bitfld.long 0x0 30. "LINSTE,LIN Synch Tolerance Error" "0,1"
|
|
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|
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bitfld.long 0x0 29. "LINSNRE,LIN Client Not Responding Error" "0,1"
|
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|
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bitfld.long 0x0 28. "LINCE,LIN Checksum Error" "0,1"
|
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|
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bitfld.long 0x0 27. "LINIPE,LIN Identifier Parity Error" "0,1"
|
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|
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bitfld.long 0x0 26. "LINISFE,LIN Inconsistent Synch Field Error" "0,1"
|
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bitfld.long 0x0 25. "LINBE,LIN Bit Error" "0,1"
|
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|
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bitfld.long 0x0 23. "LINBLS,LIN Bus Line Status" "0,1"
|
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|
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bitfld.long 0x0 15. "LINTC,LIN Transfer Completed" "0,1"
|
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|
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bitfld.long 0x0 14. "LINID,LIN Identifier Sent or LIN Identifier Received" "0,1"
|
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|
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bitfld.long 0x0 13. "LINBK,LIN Break Sent or LIN Break Received" "0,1"
|
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newline
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bitfld.long 0x0 12. "RXBUFF,RX Buffer Full (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
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newline
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bitfld.long 0x0 11. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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|
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bitfld.long 0x0 9. "TXEMPTY,Transmitter Empty (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
|
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bitfld.long 0x0 8. "TIMEOUT,Receiver Timeout" "0,1"
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bitfld.long 0x0 7. "PARE,Parity Error" "0,1"
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|
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bitfld.long 0x0 6. "FRAME,Framing Error" "0,1"
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|
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bitfld.long 0x0 5. "OVRE,Overrun Error" "0,1"
|
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|
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bitfld.long 0x0 4. "ENDTX,End of TX Buffer (cleared by writing FLEX_US_TCR or FLEX_US_TNCR)" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "ENDRX,End of RX Buffer (cleared by writing FLEX_US_RCR or FLEX_US_RNCR)" "0,1"
|
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|
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bitfld.long 0x0 1. "TXRDY,Transmitter Ready (cleared by writing FLEX_US_THR)" "0,1"
|
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newline
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bitfld.long 0x0 0. "RXRDY,Receiver Ready (cleared by reading FLEX_US_RHR)" "0,1"
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line.long 0x4 "FLEX_US_RHR,USART Receive Holding Register"
|
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bitfld.long 0x4 15. "RXSYNH,Received Sync" "0,1"
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newline
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hexmask.long.word 0x4 0.--8. 1. "RXCHR,Received Character"
|
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rgroup.long 0x218++0x3
|
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line.long 0x0 "FLEX_US_RHR_FIFO_MULTI_DATA_MODE,USART Receive Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "RXCHR3,Received Characters"
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hexmask.long.byte 0x0 16.--23. 1. "RXCHR2,Received Characters"
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hexmask.long.byte 0x0 8.--15. 1. "RXCHR1,Received Characters"
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hexmask.long.byte 0x0 0.--7. 1. "RXCHR0,Received Characters"
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wgroup.long 0x21C++0x3
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line.long 0x0 "FLEX_US_THR,USART Transmit Holding Register"
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bitfld.long 0x0 15. "TXSYNH,Sync Field to be Transmitted" "0,1"
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newline
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hexmask.long.word 0x0 0.--8. 1. "TXCHR,Character to be Transmitted"
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wgroup.long 0x21C++0x3
|
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line.long 0x0 "FLEX_US_THR_FIFO_MULTI_DATA_MODE,USART Transmit Holding Register"
|
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hexmask.long.byte 0x0 24.--31. 1. "TXCHR3,Character to be Transmitted"
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hexmask.long.byte 0x0 16.--23. 1. "TXCHR2,Character to be Transmitted"
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hexmask.long.byte 0x0 8.--15. 1. "TXCHR1,Character to be Transmitted"
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hexmask.long.byte 0x0 0.--7. 1. "TXCHR0,Character to be Transmitted"
|
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group.long 0x220++0xB
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line.long 0x0 "FLEX_US_BRGR,USART Baud Rate Generator Register"
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bitfld.long 0x0 16.--18. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
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newline
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hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divider"
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line.long 0x4 "FLEX_US_RTOR,USART Receiver Timeout Register"
|
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hexmask.long.tbyte 0x4 0.--16. 1. "TO,Timeout Value"
|
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line.long 0x8 "FLEX_US_TTGR,USART Transmitter Timeguard Register"
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hexmask.long.byte 0x8 0.--7. 1. "TG,Timeguard Value"
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group.long 0x240++0x3
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line.long 0x0 "FLEX_US_FIDI,USART FI DI Ratio Register"
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hexmask.long.word 0x0 0.--15. 1. "FI_DI_RATIO,FI Over DI Ratio Value"
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rgroup.long 0x244++0x3
|
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line.long 0x0 "FLEX_US_NER,USART Number of Errors Register"
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hexmask.long.byte 0x0 0.--7. 1. "NB_ERRORS,Number of Errors"
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group.long 0x24C++0xF
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line.long 0x0 "FLEX_US_IF,USART IrDA Filter Register"
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hexmask.long.byte 0x0 0.--7. 1. "IRDA_FILTER,IrDA Filter"
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line.long 0x4 "FLEX_US_MAN,USART Manchester Configuration Register"
|
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bitfld.long 0x4 31. "RXIDLEV,Receiver Idle Value" "0,1"
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bitfld.long 0x4 30. "DRIFT,Drift Compensation" "0,1"
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bitfld.long 0x4 29. "ONE,Must Be Set to 1" "0,1"
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newline
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bitfld.long 0x4 28. "RX_MPOL,Receiver Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 24.--25. "RX_PP,Receiver Preamble Pattern detected" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 16.--19. 1. "RX_PL,Receiver Preamble Length"
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newline
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bitfld.long 0x4 12. "TX_MPOL,Transmitter Manchester Polarity" "0,1"
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newline
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bitfld.long 0x4 8.--9. "TX_PP,Transmitter Preamble Pattern" "0: The preamble is composed of '1's,1: The preamble is composed of '0's,2: The preamble is composed of '01's,3: The preamble is composed of '10's"
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newline
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hexmask.long.byte 0x4 0.--3. 1. "TX_PL,Transmitter Preamble Length"
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line.long 0x8 "FLEX_US_LINMR,USART LIN Mode Register"
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bitfld.long 0x8 17. "SYNCDIS,Synchronization Disable" "0,1"
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newline
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bitfld.long 0x8 16. "PDCM,PDC Mode" "0,1"
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newline
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hexmask.long.byte 0x8 8.--15. 1. "DLC,Data Length Control"
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newline
|
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bitfld.long 0x8 7. "WKUPTYP,Wakeup Signal Type" "0,1"
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newline
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bitfld.long 0x8 6. "FSDIS,Frame Slot Mode Disable" "0,1"
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newline
|
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bitfld.long 0x8 5. "DLM,Data Length Mode" "0,1"
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newline
|
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bitfld.long 0x8 4. "CHKTYP,Checksum Type" "0,1"
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newline
|
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bitfld.long 0x8 3. "CHKDIS,Checksum Disable" "0,1"
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newline
|
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bitfld.long 0x8 2. "PARDIS,Parity Disable" "0,1"
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newline
|
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bitfld.long 0x8 0.--1. "NACT,LIN Node Action" "0: The USART transmits the response.,1: The USART receives the response.,2: The USART does not transmit and does not receive..,?"
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line.long 0xC "FLEX_US_LINIR,USART LIN Identifier Register"
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hexmask.long.byte 0xC 0.--7. 1. "IDCHR,Identifier Character"
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rgroup.long 0x25C++0x3
|
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line.long 0x0 "FLEX_US_LINBRR,USART LIN Baud Rate Register"
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bitfld.long 0x0 16.--18. "LINFP,Fractional Part after Synchronization" "0,1,2,3,4,5,6,7"
|
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newline
|
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hexmask.long.word 0x0 0.--15. 1. "LINCD,Clock Divider after Synchronization"
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group.long 0x290++0x3
|
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line.long 0x0 "FLEX_US_CMPR,USART Comparison Register"
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hexmask.long.word 0x0 16.--24. 1. "VAL2,Second Comparison Value for Received Character"
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newline
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bitfld.long 0x0 14. "CMPPAR,Compare Parity" "0,1"
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newline
|
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bitfld.long 0x0 12.--13. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start..,2: Comparison must be met to receive the current..,?"
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newline
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hexmask.long.word 0x0 0.--8. 1. "VAL1,First Comparison Value for Received Character"
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group.long 0x2A0++0x3
|
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line.long 0x0 "FLEX_US_FMR,USART FIFO Mode Register"
|
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hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES2,Receive FIFO Threshold 2"
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newline
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hexmask.long.byte 0x0 16.--21. 1. "RXFTHRES,Receive FIFO Threshold"
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newline
|
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hexmask.long.byte 0x0 8.--13. 1. "TXFTHRES,Transmit FIFO Threshold"
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newline
|
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bitfld.long 0x0 7. "FRTSC,FIFO RTS Pin Control enable (Hardware Handshaking mode only)" "0,1"
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newline
|
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bitfld.long 0x0 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
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newline
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bitfld.long 0x0 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
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rgroup.long 0x2A4++0x3
|
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line.long 0x0 "FLEX_US_FLR,USART FIFO Level Register"
|
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hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
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newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
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wgroup.long 0x2A8++0x7
|
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line.long 0x0 "FLEX_US_FIER,USART FIFO Interrupt Enable Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Enable" "0,1"
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
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line.long 0x4 "FLEX_US_FIDR,USART FIFO Interrupt Disable Register"
|
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bitfld.long 0x4 9. "RXFTHF2,RXFTHF2 Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
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newline
|
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bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x2B0++0x7
|
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line.long 0x0 "FLEX_US_FIMR,USART FIFO Interrupt Mask Register"
|
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bitfld.long 0x0 9. "RXFTHF2,RXFTHF2 Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
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newline
|
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bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
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line.long 0x4 "FLEX_US_FESR,USART FIFO Event Status Register"
|
|
bitfld.long 0x4 9. "RXFTHF2,Receive FIFO Threshold Flag 2 (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 8. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,Receive FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "RXFFF,Receive FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,Receive FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,Transmit FIFO Full Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,Transmit FIFO Empty Flag (cleared by writing the FLEX_US_CR.RSTSTA bit)" "0,1"
|
|
group.long 0x2E4++0x3
|
|
line.long 0x0 "FLEX_US_WPMR,USART Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x2E8++0x3
|
|
line.long 0x0 "FLEX_US_WPSR,USART Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "FLEX_SPI_CR,SPI Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,SPI Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SPIDIS,SPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,SPI Enable" "0,1"
|
|
group.long 0x404++0x3
|
|
line.long 0x0 "FLEX_SPI_MR,SPI Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "PCS,Peripheral Chip Select" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait Data Read Before Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_8_MODE,SPI Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x408++0x3
|
|
line.long 0x0 "FLEX_SPI_RDR_FIFO_MULTI_DATA_16_MODE,SPI Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR,SPI Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0x40C++0x3
|
|
line.long 0x0 "FLEX_SPI_TDR_FIFO_MULTI_DATA_MODE,SPI Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x410++0x3
|
|
line.long 0x0 "FLEX_SPI_SR,SPI Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,SPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing FLEX_SPI_TCR or FLEX_SPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing FLEX_SPI_RCR or FLEX_SPI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing FLEX_SPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading FLEX_SPI_RDR)" "0,1"
|
|
wgroup.long 0x414++0x7
|
|
line.long 0x0 "FLEX_SPI_IER,SPI Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_SPI_IDR,SPI Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "SFERR,Client Mode Frame Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,SPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x41C++0x3
|
|
line.long 0x0 "FLEX_SPI_IMR,SPI Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Mode Frame Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,SPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x430)++0x3
|
|
line.long 0x0 "FLEX_SPI_CSR[$1],SPI Chip Select Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (Ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x440++0x3
|
|
line.long 0x0 "FLEX_SPI_FMR,SPI FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x444++0x3
|
|
line.long 0x0 "FLEX_SPI_FLR,SPI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x448++0x3
|
|
line.long 0x0 "FLEX_SPI_CMPR,SPI Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
group.long 0x4E4++0x3
|
|
line.long 0x0 "FLEX_SPI_WPMR,SPI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4E8++0x3
|
|
line.long 0x0 "FLEX_SPI_WPSR,SPI Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "LOCKCLR,Lock Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "THRCLR,Transmit Holding Register Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
wgroup.long 0x600++0x3
|
|
line.long 0x0 "FLEX_TWI_CR_FIFO_ENABLED_MODE,TWI Control Register"
|
|
bitfld.long 0x0 29. "FIFODIS,FIFO Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "TXFLCLR,Transmit FIFO Lock CLEAR" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ACMDIS,Alternative Command Mode Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "ACMEN,Alternative Command Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLEAR,Bus CLEAR Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "PECRQ,PEC Request" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PECDIS,Packet Error Checking Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PECEN,Packet Error Checking Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "SMBDIS,SMBus Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SMBEN,SMBus Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "HSDIS,TWI High-Speed Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "HSEN,TWI High-Speed Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "QUICK,SMBus Quick Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SVDIS,TWI Client Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVEN,TWI Client Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MSDIS,TWI Host Mode Disabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MSEN,TWI Host Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "STOP,Send a STOP Condition" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "START,Send a START Condition" "0,1"
|
|
group.long 0x604++0xF
|
|
line.long 0x0 "FLEX_TWI_MMR,TWI Host Mode Register"
|
|
bitfld.long 0x0 24. "NOAP,No Auto-Stop On NACK Error" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--22. 1. "DADR,Device Address"
|
|
newline
|
|
bitfld.long 0x0 13.--14. "SCLRBL,SCL Rise Boost Level" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 12. "MREAD,Host Read Direction" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "IADRSZ,Internal Device Address Size" "0: No internal device address,1: One-byte internal device address,2: Two-byte internal device address,3: Three-byte internal device address"
|
|
line.long 0x4 "FLEX_TWI_SMR,TWI Client Mode Register"
|
|
bitfld.long 0x4 31. "DATAMEN,Data Matching Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 30. "SADR3EN,Client Address 3 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "SADR2EN,Client Address 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 28. "SADR1EN,Client Address 1 Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--22. 1. "SADR,Client Address"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "MASK,Client Address Mask"
|
|
newline
|
|
bitfld.long 0x4 7. "SNIFF,Client Sniffer Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SCLWSDIS,Clock Wait State Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "BSEL,TWI Bus Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SADAT,Client Address Treated as Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "SMHH,SMBus Host Header" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SMDA,SMBus Default Address" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "NACKEN,Client Receiver Data Phase NACK Enable" "0,1"
|
|
line.long 0x8 "FLEX_TWI_IADR,TWI Internal Address Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "IADR,Internal Address"
|
|
line.long 0xC "FLEX_TWI_CWGR,TWI Clock Waveform Generator Register"
|
|
hexmask.long.byte 0xC 24.--29. 1. "HOLD,TWD Hold Time Versus TWCK Falling"
|
|
newline
|
|
bitfld.long 0xC 20. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: GCLK is the source clock for the bit rate.."
|
|
newline
|
|
bitfld.long 0xC 16.--18. "CKDIV,Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "CHDIV,Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--7. 1. "CLDIV,Clock Low Divider"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK,TWI Lock Due to Frame Errors" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
rgroup.long 0x620++0x3
|
|
line.long 0x0 "FLEX_TWI_SR_FIFO_ENABLED_MODE,TWI Status Register"
|
|
bitfld.long 0x0 26. "SR,Start Repeated" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SDA,SDA Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "SCL,SCL Line Value" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TXFLOCK,Transmit FIFO Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "SMBAF,SMBus Alert Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,TX Buffer Empty (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,RX Buffer Full (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of TX Buffer (cleared by writing FLEX_TWI_TCR or FLEX_TWI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of RX Buffer (cleared by writing FLEX_TWI_RCR or FLEX_TWI_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCLWS,Clock Wait State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledged (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "SVREAD,Client Read" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready (cleared when reading FLEX_TWI_RHR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed (cleared by writing FLEX_TWI_THR)" "0,1"
|
|
wgroup.long 0x624++0x7
|
|
line.long 0x0 "FLEX_TWI_IER,TWI Interrupt Enable Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_IDR,TWI Interrupt Disable Register"
|
|
bitfld.long 0x4 21. "SMBHHM,SMBus Host Header Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 20. "SMBDAM,SMBus Default Address Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PECERR,PEC Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "TOUT,Timeout Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MCACK,Host Code Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "EOSACC,End Of Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SCL_WS,Clock Wait State Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ARBLST,Arbitration Lost Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NACK,Not Acknowledge Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "UNRE,Underrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "GACC,General Call Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "SVACC,Client Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXRDY,Transmit Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RXRDY,Receive Holding Register Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXCOMP,Transmission Completed Interrupt Disable" "0,1"
|
|
rgroup.long 0x62C++0x7
|
|
line.long 0x0 "FLEX_TWI_IMR,TWI Interrupt Mask Register"
|
|
bitfld.long 0x0 21. "SMBHHM,SMBus Host Header Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "SMBDAM,SMBus Default Address Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "PECERR,PEC Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TOUT,Timeout Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MCACK,Host Code Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "EOSACC,End Of Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "SCL_WS,Clock Wait State Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ARBLST,Arbitration Lost Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NACK,Not Acknowledge Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "UNRE,Underrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "GACC,General Call Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "SVACC,Client Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXRDY,Transmit Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RXRDY,Receive Holding Register Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXCOMP,Transmission Completed Interrupt Mask" "0,1"
|
|
line.long 0x4 "FLEX_TWI_RHR,TWI Receive Holding Register"
|
|
bitfld.long 0x4 11.--12. "ASTATE,Acknowledge State (Client Sniffer Mode only)" "0: No Acknowledge or Nacknowledge detected after..,1: Acknowledge (A) detected after previously logged..,2: Nacknowledge (NA) detected after previously..,3: Not defined"
|
|
newline
|
|
bitfld.long 0x4 10. "PSTATE,Stop State (Client Sniffer Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "SSTATE,Start State (Client Sniffer Mode only)" "0: No START detected with the logged data,1: START (S) detected with the logged data,2: Repeated START (Sr) detected with the logged data,3: Not defined"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "RXDATA,Host or Client Receive Holding Data"
|
|
rgroup.long 0x630++0x3
|
|
line.long 0x0 "FLEX_TWI_RHR_FIFO_ENABLED_MODE,TWI Receive Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RXDATA3,Host or Client Receive Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "RXDATA2,Host or Client Receive Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RXDATA1,Host or Client Receive Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "RXDATA0,Host or Client Receive Holding Data 0"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA,Host or Client Transmit Holding Data"
|
|
wgroup.long 0x634++0x3
|
|
line.long 0x0 "FLEX_TWI_THR_FIFO_ENABLED_MODE,TWI Transmit Holding Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TXDATA3,Host or Client Transmit Holding Data 3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TXDATA2,Host or Client Transmit Holding Data 2"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TXDATA1,Host or Client Transmit Holding Data 1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXDATA0,Host or Client Transmit Holding Data 0"
|
|
group.long 0x638++0x1B
|
|
line.long 0x0 "FLEX_TWI_SMBTR,TWI SMBus Timing Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "THMAX,Clock High Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--23. 1. "TLOWM,Host Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "TLOWS,Client Clock Stretch Maximum Cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRESC,SMBus Clock Prescaler"
|
|
line.long 0x4 "FLEX_TWI_HSR,TWI High Speed Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "MCODE,TWI High Speed Host Code"
|
|
line.long 0x8 "FLEX_TWI_ACR,TWI Alternative Command Register"
|
|
bitfld.long 0x8 25. "NPEC,Next PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "NDIR,Next Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--23. 1. "NDATAL,Next Data Length"
|
|
newline
|
|
bitfld.long 0x8 9. "PEC,PEC Request (SMBus Mode only)" "0,1"
|
|
newline
|
|
bitfld.long 0x8 8. "DIR,Transfer Direction" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--7. 1. "DATAL,Data Length"
|
|
line.long 0xC "FLEX_TWI_FILTR,TWI Filter Register"
|
|
bitfld.long 0xC 8.--10. "THRES,Digital Filter Threshold" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 1. "PADFEN,PAD Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "FILT,RX Digital Filter" "0,1"
|
|
line.long 0x10 "FLEX_TWI_HSCWGR,TWI High Speed Clock Waveform Generator Register"
|
|
bitfld.long 0x10 16.--18. "HSCKDIV,High Speed Clock Divider" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "HSCHDIV,High Speed Clock High Divider"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--7. 1. "HSCLDIV,High Speed Clock Low Divider"
|
|
line.long 0x14 "FLEX_TWI_SWMR,TWI Matching Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. "DATAM,Data Match"
|
|
newline
|
|
hexmask.long.byte 0x14 16.--22. 1. "SADR3,Client Address 3"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--14. 1. "SADR2,Client Address 2"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--6. 1. "SADR1,Client Address 1"
|
|
line.long 0x18 "FLEX_TWI_FMR,TWI FIFO Mode Register"
|
|
hexmask.long.byte 0x18 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
newline
|
|
hexmask.long.byte 0x18 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x18 4.--5. "RXRDYM,Receiver Ready Mode" "0: RXRDY will be at level '1' when at least one..,1: RXRDY will be at level '1' when at least two..,2: RXRDY will be at level '1' when at least four..,?"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "TXRDYM,Transmitter Ready Mode" "0: TXRDY will be at level '1' when at least one..,1: TXRDY will be at level '1' when at least two..,2: TXRDY will be at level '1' when at least four..,?"
|
|
rgroup.long 0x654++0x3
|
|
line.long 0x0 "FLEX_TWI_FLR,TWI FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
rgroup.long 0x660++0x3
|
|
line.long 0x0 "FLEX_TWI_FSR,TWI FIFO Status Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
wgroup.long 0x664++0x7
|
|
line.long 0x0 "FLEX_TWI_FIER,TWI FIFO Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
line.long 0x4 "FLEX_TWI_FIDR,TWI FIFO Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
rgroup.long 0x66C++0x3
|
|
line.long 0x0 "FLEX_TWI_FIMR,TWI FIFO Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
group.long 0x6E4++0x3
|
|
line.long 0x0 "FLEX_TWI_WPMR,TWI Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x6E8++0x3
|
|
line.long 0x0 "FLEX_TWI_WPSR,TWI Write Protection Status Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPVSRC,Write Protection Violation Source"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protect Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "FPU (Floating Point Unit)"
|
|
base ad:0xE000EF30
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x0 31. "ASPEN," "0,1"
|
|
bitfld.long 0x0 30. "LSPEN," "0,1"
|
|
bitfld.long 0x0 8. "MONRDY," "0,1"
|
|
bitfld.long 0x0 6. "BFRDY," "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MMRDY," "0,1"
|
|
bitfld.long 0x0 4. "HFRDY," "0,1"
|
|
bitfld.long 0x0 3. "THREAD," "0,1"
|
|
bitfld.long 0x0 1. "USER," "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LSPACT," "0,1"
|
|
line.long 0x4 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x4 3.--31. 1. "ADDRESS,Address for FP registers in exception stack frame"
|
|
line.long 0x8 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x8 26. "AHP,Default value for FPSCR.AHP" "0,1"
|
|
bitfld.long 0x8 25. "DN,Default value for FPSCR.DN" "0,1"
|
|
bitfld.long 0x8 24. "FZ,Default value for FPSCR.FZ" "0,1"
|
|
bitfld.long 0x8 22.--23. "RMODE,Default value for FPSCR.RMODE" "0: Round to Nearest,1: Round towards Positive Infinity,2: Round towards Negative Infinity,3: Round towards Zero"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "MVFR0,Media and FP Feature Register 0"
|
|
hexmask.long.byte 0x0 28.--31. 1. "FP_rounding_modes,"
|
|
hexmask.long.byte 0x0 24.--27. 1. "Short_vectors,"
|
|
hexmask.long.byte 0x0 20.--23. 1. "Square_root,"
|
|
hexmask.long.byte 0x0 16.--19. 1. "Divide,"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "FP_excep_trapping,"
|
|
hexmask.long.byte 0x0 8.--11. 1. "Double_precision,"
|
|
hexmask.long.byte 0x0 4.--7. 1. "Single_precision,"
|
|
hexmask.long.byte 0x0 0.--3. 1. "A_SIMD_registers,"
|
|
line.long 0x4 "MVFR1,Media and FP Feature Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FP_fused_MAC,"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FP_HPFP,"
|
|
hexmask.long.byte 0x4 4.--7. 1. "D_NaN_mode,"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FtZ_mode,"
|
|
tree.end
|
|
tree "GPBR (General-Purpose Backup Registers)"
|
|
base ad:0x40053060
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,GPBR Mode Register"
|
|
bitfld.long 0x0 31. "GPBRRP15,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 30. "GPBRRP14,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 29. "GPBRRP13,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 28. "GPBRRP12,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 27. "GPBRRP11,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 26. "GPBRRP10,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 25. "GPBRRP9,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 24. "GPBRRP8,GPBRx Read Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPBRRP7,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 22. "GPBRRP6,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 21. "GPBRRP5,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 20. "GPBRRP4,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 19. "GPBRRP3,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 18. "GPBRRP2,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 17. "GPBRRP1,GPBRx Read Protection" "0,1"
|
|
bitfld.long 0x0 16. "GPBRRP0,GPBRx Read Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "GPBRWP15,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 14. "GPBRWP14,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 13. "GPBRWP13,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 12. "GPBRWP12,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 11. "GPBRWP11,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 10. "GPBRWP10,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 9. "GPBRWP9,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 8. "GPBRWP8,GPBRx Write Protection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "GPBRWP7,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 6. "GPBRWP6,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 5. "GPBRWP5,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 4. "GPBRWP4,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 3. "GPBRWP3,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 2. "GPBRWP2,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 1. "GPBRWP1,GPBRx Write Protection" "0,1"
|
|
bitfld.long 0x0 0. "GPBRWP0,GPBRx Write Protection" "0,1"
|
|
repeat 24. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "SYS_GPBR[$1],General Purpose Backup Register"
|
|
hexmask.long 0x0 0.--31. 1. "GPBR_VALUE,Value of SYS_GPBRx"
|
|
repeat.end
|
|
tree.end
|
|
tree "ICM (Integrity Check Monitor)"
|
|
base ad:0x44010000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CFG,Configuration Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "DAPROT,Region Descriptor Area Protection"
|
|
hexmask.long.byte 0x0 16.--21. 1. "HAPROT,Region Hash Area Protection"
|
|
bitfld.long 0x0 13.--15. "UALGO,User SHA Algorithm" "0: SHA1 algorithm processed,1: SHA256 algorithm processed,2: SHA384 algorithm processed,3: SHA512 algorithm processed,4: SHA224 algorithm processed,?,?,?"
|
|
bitfld.long 0x0 12. "UIHASH,User Initial Hash Value" "0,1"
|
|
bitfld.long 0x0 9. "DUALBUFF,Dual Input Buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ASCD,Automatic Switch To Compare Digest" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BBC,Bus Burden Control"
|
|
bitfld.long 0x0 2. "SLBDIS,Secondary List Branching Disable" "0,1"
|
|
bitfld.long 0x0 1. "EOMDIS,End of Monitoring Disable" "0,1"
|
|
bitfld.long 0x0 0. "WBDIS,Write-Back Disable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "CTRL,Control Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMEN,Region Monitoring Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RMDIS,Region Monitoring Disable"
|
|
hexmask.long.byte 0x0 4.--7. 1. "REHASH,Recompute Internal Hash"
|
|
bitfld.long 0x0 2. "SWRST,Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "DISABLE,ICM Disable Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RMDIS,Region Monitoring Disabled Status"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RAWRMDIS,Region Monitoring Disabled Raw Status"
|
|
bitfld.long 0x0 0. "ENABLE,ICM Enable Register" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition detected Interrupt Enable"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Enable"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Enable"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Interrupt Disable" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Interrupt Disable"
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End bit Condition detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Disable"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error Interrupt Disable"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Disable"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed Interrupt Disable"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "URAD,Undefined Register Access Detection Interrupt Mask" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "RSU,Region Status Updated Interrupt Mask"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REC,Region End bit Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 12.--15. 1. "RWC,Region Wrap Condition Detected Interrupt Mask"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RBE,Region Bus Error Interrupt Mask"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RDM,Region Digest Mismatch Interrupt Mask"
|
|
hexmask.long.byte 0x0 0.--3. 1. "RHC,Region Hash Completed Interrupt Mask"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "URAD,Undefined Register Access Detection Status" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "RSU,Region Status Updated Detected"
|
|
hexmask.long.byte 0x4 16.--19. 1. "REC,Region End Bit Condition Detected"
|
|
hexmask.long.byte 0x4 12.--15. 1. "RWC,Region Wrap Condition Detected"
|
|
hexmask.long.byte 0x4 8.--11. 1. "RBE,Region Bus Error"
|
|
newline
|
|
hexmask.long.byte 0x4 4.--7. 1. "RDM,Region Digest Mismatch"
|
|
hexmask.long.byte 0x4 0.--3. 1. "RHC,Region Hash Completed"
|
|
line.long 0x8 "UASR,Undefined Access Status Register"
|
|
bitfld.long 0x8 0.--2. "URAT,Undefined Register Access Trace" "0: Unspecified structure member set to one detected..,1: ICM_CFG modified during active monitoring.,2: ICM_DSCR modified during active monitoring.,3: ICM_HASH modified during active monitoring,4: Write-only register read access,?,?,?"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "DSCR,Region Descriptor Area Start Address Register"
|
|
hexmask.long 0x0 6.--31. 1. "DASA,Descriptor Area Start Address"
|
|
line.long 0x4 "HASH,Region Hash Area Start Address Register"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "HASA,Hash Area Start Address"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "UIHVAL[$1],User Initial Hash Value 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "VAL,Initial Hash Value"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (Cleared on read)" "0,1"
|
|
tree.end
|
|
tree "ITM (Instrumentation Trace Macrocell)"
|
|
base ad:0xE0000000
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "PORT_WORD_MODE[$1],ITM Stimulus Port Registers"
|
|
hexmask.long 0x0 0.--31. 1. "PORT,"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "PORT_BYTE_MODE[$1],ITM Stimulus Port Registers"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PORT,"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "PORT_HWORD_MODE[$1],ITM Stimulus Port Registers"
|
|
hexmask.long.word 0x0 0.--15. 1. "PORT,"
|
|
repeat.end
|
|
group.long 0xE00++0x3
|
|
line.long 0x0 "TER,ITM Trace Enable Register"
|
|
group.long 0xE40++0x3
|
|
line.long 0x0 "TPR,ITM Trace Privilege Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRIVMASK,"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "TCR,ITM Trace Control Register"
|
|
bitfld.long 0x0 23. "BUSY," "0,1"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TraceBusID,"
|
|
bitfld.long 0x0 10.--11. "GTSFREQ," "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "TSPrescale," "0,1,2,3"
|
|
bitfld.long 0x0 5. "STALLENA," "0,1"
|
|
bitfld.long 0x0 4. "SWOENA," "0,1"
|
|
bitfld.long 0x0 3. "DWTENA," "0,1"
|
|
bitfld.long 0x0 2. "SYNCENA," "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TSENA," "0,1"
|
|
bitfld.long 0x0 0. "ITMENA," "0,1"
|
|
wgroup.long 0xEF8++0x3
|
|
line.long 0x0 "IWR,ITM Integration Write Register"
|
|
bitfld.long 0x0 0. "ATVALIDM," "0,1"
|
|
rgroup.long 0xEFC++0x3
|
|
line.long 0x0 "IRR,ITM Integration Read Register"
|
|
bitfld.long 0x0 0. "ATREADYM," "0,1"
|
|
tree.end
|
|
tree "LOCKBIT"
|
|
base ad:0x0
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "WORD0,Lock Bits Word 0"
|
|
bitfld.long 0x0 31. "LOCK_REGION_31,Lock Region 31" "0,1"
|
|
bitfld.long 0x0 30. "LOCK_REGION_30,Lock Region 30" "0,1"
|
|
bitfld.long 0x0 29. "LOCK_REGION_29,Lock Region 29" "0,1"
|
|
bitfld.long 0x0 28. "LOCK_REGION_28,Lock Region 28" "0,1"
|
|
bitfld.long 0x0 27. "LOCK_REGION_27,Lock Region 27" "0,1"
|
|
bitfld.long 0x0 26. "LOCK_REGION_26,Lock Region 26" "0,1"
|
|
bitfld.long 0x0 25. "LOCK_REGION_25,Lock Region 25" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LOCK_REGION_24,Lock Region 24" "0,1"
|
|
bitfld.long 0x0 23. "LOCK_REGION_23,Lock Region 23" "0,1"
|
|
bitfld.long 0x0 22. "LOCK_REGION_22,Lock Region 22" "0,1"
|
|
bitfld.long 0x0 21. "LOCK_REGION_21,Lock Region 21" "0,1"
|
|
bitfld.long 0x0 20. "LOCK_REGION_20,Lock Region 20" "0,1"
|
|
bitfld.long 0x0 19. "LOCK_REGION_19,Lock Region 19" "0,1"
|
|
bitfld.long 0x0 18. "LOCK_REGION_18,Lock Region 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LOCK_REGION_17,Lock Region 17" "0,1"
|
|
bitfld.long 0x0 16. "LOCK_REGION_16,Lock Region 16" "0,1"
|
|
bitfld.long 0x0 15. "LOCK_REGION_15,Lock Region 15" "0,1"
|
|
bitfld.long 0x0 14. "LOCK_REGION_14,Lock Region 14" "0,1"
|
|
bitfld.long 0x0 13. "LOCK_REGION_13,Lock Region 13" "0,1"
|
|
bitfld.long 0x0 12. "LOCK_REGION_12,Lock Region 12" "0,1"
|
|
bitfld.long 0x0 11. "LOCK_REGION_11,Lock Region 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "LOCK_REGION_10,Lock Region 10" "0,1"
|
|
bitfld.long 0x0 9. "LOCK_REGION_9,Lock Region 9" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_REGION_8,Lock Region 8" "0,1"
|
|
bitfld.long 0x0 7. "LOCK_REGION_7,Lock Region 7" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_REGION_6,Lock Region 6" "0,1"
|
|
bitfld.long 0x0 5. "LOCK_REGION_5,Lock Region 5" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_REGION_4,Lock Region 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_REGION_3,Lock Region 3" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_REGION_2,Lock Region 2" "0,1"
|
|
bitfld.long 0x0 1. "LOCK_REGION_1,Lock Region 1" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_REGION_0,Lock Region 0" "0,1"
|
|
line.long 0x4 "WORD1,Lock Bits Word 1"
|
|
bitfld.long 0x4 31. "LOCK_REGION_63,Lock Region 63" "0,1"
|
|
bitfld.long 0x4 30. "LOCK_REGION_62,Lock Region 62" "0,1"
|
|
bitfld.long 0x4 29. "LOCK_REGION_61,Lock Region 61" "0,1"
|
|
bitfld.long 0x4 28. "LOCK_REGION_60,Lock Region 60" "0,1"
|
|
bitfld.long 0x4 27. "LOCK_REGION_59,Lock Region 59" "0,1"
|
|
bitfld.long 0x4 26. "LOCK_REGION_58,Lock Region 58" "0,1"
|
|
bitfld.long 0x4 25. "LOCK_REGION_57,Lock Region 57" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "LOCK_REGION_56,Lock Region 56" "0,1"
|
|
bitfld.long 0x4 23. "LOCK_REGION_55,Lock Region 55" "0,1"
|
|
bitfld.long 0x4 22. "LOCK_REGION_54,Lock Region 54" "0,1"
|
|
bitfld.long 0x4 21. "LOCK_REGION_53,Lock Region 53" "0,1"
|
|
bitfld.long 0x4 20. "LOCK_REGION_52,Lock Region 52" "0,1"
|
|
bitfld.long 0x4 19. "LOCK_REGION_51,Lock Region 51" "0,1"
|
|
bitfld.long 0x4 18. "LOCK_REGION_50,Lock Region 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "LOCK_REGION_49,Lock Region 49" "0,1"
|
|
bitfld.long 0x4 16. "LOCK_REGION_48,Lock Region 48" "0,1"
|
|
bitfld.long 0x4 15. "LOCK_REGION_47,Lock Region 47" "0,1"
|
|
bitfld.long 0x4 14. "LOCK_REGION_46,Lock Region 46" "0,1"
|
|
bitfld.long 0x4 13. "LOCK_REGION_45,Lock Region 45" "0,1"
|
|
bitfld.long 0x4 12. "LOCK_REGION_44,Lock Region 44" "0,1"
|
|
bitfld.long 0x4 11. "LOCK_REGION_43,Lock Region 43" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "LOCK_REGION_42,Lock Region 42" "0,1"
|
|
bitfld.long 0x4 9. "LOCK_REGION_41,Lock Region 41" "0,1"
|
|
bitfld.long 0x4 8. "LOCK_REGION_40,Lock Region 40" "0,1"
|
|
bitfld.long 0x4 7. "LOCK_REGION_39,Lock Region 39" "0,1"
|
|
bitfld.long 0x4 6. "LOCK_REGION_38,Lock Region 38" "0,1"
|
|
bitfld.long 0x4 5. "LOCK_REGION_37,Lock Region 37" "0,1"
|
|
bitfld.long 0x4 4. "LOCK_REGION_36,Lock Region 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK_REGION_35,Lock Region 35" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_REGION_34,Lock Region 34" "0,1"
|
|
bitfld.long 0x4 1. "LOCK_REGION_33,Lock Region 33" "0,1"
|
|
bitfld.long 0x4 0. "LOCK_REGION_32,Lock Region 32" "0,1"
|
|
line.long 0x8 "WORD2,Lock Bits Word 2"
|
|
bitfld.long 0x8 31. "LOCK_REGION_95,Lock Region 95" "0,1"
|
|
bitfld.long 0x8 30. "LOCK_REGION_94,Lock Region 94" "0,1"
|
|
bitfld.long 0x8 29. "LOCK_REGION_93,Lock Region 93" "0,1"
|
|
bitfld.long 0x8 28. "LOCK_REGION_92,Lock Region 92" "0,1"
|
|
bitfld.long 0x8 27. "LOCK_REGION_91,Lock Region 91" "0,1"
|
|
bitfld.long 0x8 26. "LOCK_REGION_90,Lock Region 90" "0,1"
|
|
bitfld.long 0x8 25. "LOCK_REGION_89,Lock Region 89" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24. "LOCK_REGION_88,Lock Region 88" "0,1"
|
|
bitfld.long 0x8 23. "LOCK_REGION_87,Lock Region 87" "0,1"
|
|
bitfld.long 0x8 22. "LOCK_REGION_86,Lock Region 86" "0,1"
|
|
bitfld.long 0x8 21. "LOCK_REGION_85,Lock Region 85" "0,1"
|
|
bitfld.long 0x8 20. "LOCK_REGION_84,Lock Region 84" "0,1"
|
|
bitfld.long 0x8 19. "LOCK_REGION_83,Lock Region 83" "0,1"
|
|
bitfld.long 0x8 18. "LOCK_REGION_82,Lock Region 82" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "LOCK_REGION_81,Lock Region 81" "0,1"
|
|
bitfld.long 0x8 16. "LOCK_REGION_80,Lock Region 80" "0,1"
|
|
bitfld.long 0x8 15. "LOCK_REGION_79,Lock Region 79" "0,1"
|
|
bitfld.long 0x8 14. "LOCK_REGION_78,Lock Region 78" "0,1"
|
|
bitfld.long 0x8 13. "LOCK_REGION_77,Lock Region 77" "0,1"
|
|
bitfld.long 0x8 12. "LOCK_REGION_76,Lock Region 76" "0,1"
|
|
bitfld.long 0x8 11. "LOCK_REGION_75,Lock Region 75" "0,1"
|
|
newline
|
|
bitfld.long 0x8 10. "LOCK_REGION_74,Lock Region 74" "0,1"
|
|
bitfld.long 0x8 9. "LOCK_REGION_73,Lock Region 73" "0,1"
|
|
bitfld.long 0x8 8. "LOCK_REGION_72,Lock Region 72" "0,1"
|
|
bitfld.long 0x8 7. "LOCK_REGION_71,Lock Region 71" "0,1"
|
|
bitfld.long 0x8 6. "LOCK_REGION_70,Lock Region 70" "0,1"
|
|
bitfld.long 0x8 5. "LOCK_REGION_69,Lock Region 69" "0,1"
|
|
bitfld.long 0x8 4. "LOCK_REGION_68,Lock Region 68" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "LOCK_REGION_67,Lock Region 67" "0,1"
|
|
bitfld.long 0x8 2. "LOCK_REGION_66,Lock Region 66" "0,1"
|
|
bitfld.long 0x8 1. "LOCK_REGION_65,Lock Region 65" "0,1"
|
|
bitfld.long 0x8 0. "LOCK_REGION_64,Lock Region 64" "0,1"
|
|
line.long 0xC "WORD3,Lock Bits Word 3"
|
|
bitfld.long 0xC 31. "LOCK_REGION_127,Lock Region 127" "0,1"
|
|
bitfld.long 0xC 30. "LOCK_REGION_126,Lock Region 126" "0,1"
|
|
bitfld.long 0xC 29. "LOCK_REGION_125,Lock Region 125" "0,1"
|
|
bitfld.long 0xC 28. "LOCK_REGION_124,Lock Region 124" "0,1"
|
|
bitfld.long 0xC 27. "LOCK_REGION_123,Lock Region 123" "0,1"
|
|
bitfld.long 0xC 26. "LOCK_REGION_122,Lock Region 122" "0,1"
|
|
bitfld.long 0xC 25. "LOCK_REGION_121,Lock Region 121" "0,1"
|
|
newline
|
|
bitfld.long 0xC 24. "LOCK_REGION_120,Lock Region 120" "0,1"
|
|
bitfld.long 0xC 23. "LOCK_REGION_119,Lock Region 119" "0,1"
|
|
bitfld.long 0xC 22. "LOCK_REGION_118,Lock Region 118" "0,1"
|
|
bitfld.long 0xC 21. "LOCK_REGION_117,Lock Region 117" "0,1"
|
|
bitfld.long 0xC 20. "LOCK_REGION_116,Lock Region 116" "0,1"
|
|
bitfld.long 0xC 19. "LOCK_REGION_115,Lock Region 115" "0,1"
|
|
bitfld.long 0xC 18. "LOCK_REGION_114,Lock Region 114" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "LOCK_REGION_113,Lock Region 113" "0,1"
|
|
bitfld.long 0xC 16. "LOCK_REGION_112,Lock Region 112" "0,1"
|
|
bitfld.long 0xC 15. "LOCK_REGION_111,Lock Region 111" "0,1"
|
|
bitfld.long 0xC 14. "LOCK_REGION_110,Lock Region 110" "0,1"
|
|
bitfld.long 0xC 13. "LOCK_REGION_109,Lock Region 109" "0,1"
|
|
bitfld.long 0xC 12. "LOCK_REGION_108,Lock Region 108" "0,1"
|
|
bitfld.long 0xC 11. "LOCK_REGION_107,Lock Region 107" "0,1"
|
|
newline
|
|
bitfld.long 0xC 10. "LOCK_REGION_106,Lock Region 106" "0,1"
|
|
bitfld.long 0xC 9. "LOCK_REGION_105,Lock Region 105" "0,1"
|
|
bitfld.long 0xC 8. "LOCK_REGION_104,Lock Region 104" "0,1"
|
|
bitfld.long 0xC 7. "LOCK_REGION_103,Lock Region 103" "0,1"
|
|
bitfld.long 0xC 6. "LOCK_REGION_102,Lock Region 102" "0,1"
|
|
bitfld.long 0xC 5. "LOCK_REGION_101,Lock Region 101" "0,1"
|
|
bitfld.long 0xC 4. "LOCK_REGION_100,Lock Region 100" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "LOCK_REGION_99,Lock Region 99" "0,1"
|
|
bitfld.long 0xC 2. "LOCK_REGION_98,Lock Region 98" "0,1"
|
|
bitfld.long 0xC 1. "LOCK_REGION_97,Lock Region 97" "0,1"
|
|
bitfld.long 0xC 0. "LOCK_REGION_96,Lock Region 96" "0,1"
|
|
sif (cpuis("PIC32C?1025MTG128*")||cpuis("PIC32C?1025MTG64*")||cpuis("PIC32C?2051MTG128*")||cpuis("PIC32C?2051MTG64*"))
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "WORD4,Lock Bits Word 4"
|
|
bitfld.long 0x0 31. "LOCK_REGION_159,Lock Region 159" "0,1"
|
|
bitfld.long 0x0 30. "LOCK_REGION_158,Lock Region 158" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LOCK_REGION_157,Lock Region 157" "0,1"
|
|
bitfld.long 0x0 28. "LOCK_REGION_156,Lock Region 156" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LOCK_REGION_155,Lock Region 155" "0,1"
|
|
bitfld.long 0x0 26. "LOCK_REGION_154,Lock Region 154" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LOCK_REGION_153,Lock Region 153" "0,1"
|
|
bitfld.long 0x0 24. "LOCK_REGION_152,Lock Region 152" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK_REGION_151,Lock Region 151" "0,1"
|
|
bitfld.long 0x0 22. "LOCK_REGION_150,Lock Region 150" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LOCK_REGION_149,Lock Region 149" "0,1"
|
|
bitfld.long 0x0 20. "LOCK_REGION_148,Lock Region 148" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LOCK_REGION_147,Lock Region 147" "0,1"
|
|
bitfld.long 0x0 18. "LOCK_REGION_146,Lock Region 146" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LOCK_REGION_145,Lock Region 145" "0,1"
|
|
bitfld.long 0x0 16. "LOCK_REGION_144,Lock Region 144" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LOCK_REGION_143,Lock Region 143" "0,1"
|
|
bitfld.long 0x0 14. "LOCK_REGION_142,Lock Region 142" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LOCK_REGION_141,Lock Region 141" "0,1"
|
|
bitfld.long 0x0 12. "LOCK_REGION_140,Lock Region 140" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LOCK_REGION_139,Lock Region 139" "0,1"
|
|
bitfld.long 0x0 10. "LOCK_REGION_138,Lock Region 138" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LOCK_REGION_137,Lock Region 137" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_REGION_136,Lock Region 136" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LOCK_REGION_135,Lock Region 135" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_REGION_134,Lock Region 134" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LOCK_REGION_133,Lock Region 133" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_REGION_132,Lock Region 132" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_REGION_131,Lock Region 131" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_REGION_130,Lock Region 130" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK_REGION_129,Lock Region 129" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_REGION_128,Lock Region 128" "0,1"
|
|
line.long 0x4 "WORD5,Lock Bits Word 5"
|
|
bitfld.long 0x4 31. "LOCK_REGION_191,Lock Region 191" "0,1"
|
|
bitfld.long 0x4 30. "LOCK_REGION_190,Lock Region 190" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "LOCK_REGION_189,Lock Region 189" "0,1"
|
|
bitfld.long 0x4 28. "LOCK_REGION_188,Lock Region 188" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "LOCK_REGION_187,Lock Region 187" "0,1"
|
|
bitfld.long 0x4 26. "LOCK_REGION_186,Lock Region 186" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "LOCK_REGION_185,Lock Region 185" "0,1"
|
|
bitfld.long 0x4 24. "LOCK_REGION_184,Lock Region 184" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "LOCK_REGION_183,Lock Region 183" "0,1"
|
|
bitfld.long 0x4 22. "LOCK_REGION_182,Lock Region 182" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "LOCK_REGION_181,Lock Region 181" "0,1"
|
|
bitfld.long 0x4 20. "LOCK_REGION_180,Lock Region 180" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "LOCK_REGION_179,Lock Region 179" "0,1"
|
|
bitfld.long 0x4 18. "LOCK_REGION_178,Lock Region 178" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "LOCK_REGION_177,Lock Region 177" "0,1"
|
|
bitfld.long 0x4 16. "LOCK_REGION_176,Lock Region 176" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "LOCK_REGION_175,Lock Region 175" "0,1"
|
|
bitfld.long 0x4 14. "LOCK_REGION_174,Lock Region 174" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "LOCK_REGION_173,Lock Region 173" "0,1"
|
|
bitfld.long 0x4 12. "LOCK_REGION_172,Lock Region 172" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "LOCK_REGION_171,Lock Region 171" "0,1"
|
|
bitfld.long 0x4 10. "LOCK_REGION_170,Lock Region 170" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "LOCK_REGION_169,Lock Region 169" "0,1"
|
|
bitfld.long 0x4 8. "LOCK_REGION_168,Lock Region 168" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "LOCK_REGION_167,Lock Region 167" "0,1"
|
|
bitfld.long 0x4 6. "LOCK_REGION_166,Lock Region 166" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK_REGION_165,Lock Region 165" "0,1"
|
|
bitfld.long 0x4 4. "LOCK_REGION_164,Lock Region 164" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK_REGION_163,Lock Region 163" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_REGION_162,Lock Region 162" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK_REGION_161,Lock Region 161" "0,1"
|
|
bitfld.long 0x4 0. "LOCK_REGION_160,Lock Region 160" "0,1"
|
|
line.long 0x8 "WORD6,Lock Bits Word 6"
|
|
bitfld.long 0x8 31. "LOCK_REGION_223,Lock Region 223" "0,1"
|
|
bitfld.long 0x8 30. "LOCK_REGION_222,Lock Region 222" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "LOCK_REGION_221,Lock Region 221" "0,1"
|
|
bitfld.long 0x8 28. "LOCK_REGION_220,Lock Region 220" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "LOCK_REGION_219,Lock Region 219" "0,1"
|
|
bitfld.long 0x8 26. "LOCK_REGION_218,Lock Region 218" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "LOCK_REGION_217,Lock Region 217" "0,1"
|
|
bitfld.long 0x8 24. "LOCK_REGION_216,Lock Region 216" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "LOCK_REGION_215,Lock Region 215" "0,1"
|
|
bitfld.long 0x8 22. "LOCK_REGION_214,Lock Region 214" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "LOCK_REGION_213,Lock Region 213" "0,1"
|
|
bitfld.long 0x8 20. "LOCK_REGION_212,Lock Region 212" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "LOCK_REGION_211,Lock Region 211" "0,1"
|
|
bitfld.long 0x8 18. "LOCK_REGION_210,Lock Region 210" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "LOCK_REGION_209,Lock Region 209" "0,1"
|
|
bitfld.long 0x8 16. "LOCK_REGION_208,Lock Region 208" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "LOCK_REGION_207,Lock Region 207" "0,1"
|
|
bitfld.long 0x8 14. "LOCK_REGION_206,Lock Region 206" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "LOCK_REGION_205,Lock Region 205" "0,1"
|
|
bitfld.long 0x8 12. "LOCK_REGION_204,Lock Region 204" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "LOCK_REGION_203,Lock Region 203" "0,1"
|
|
bitfld.long 0x8 10. "LOCK_REGION_202,Lock Region 202" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "LOCK_REGION_201,Lock Region 201" "0,1"
|
|
bitfld.long 0x8 8. "LOCK_REGION_200,Lock Region 200" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "LOCK_REGION_199,Lock Region 199" "0,1"
|
|
bitfld.long 0x8 6. "LOCK_REGION_198,Lock Region 198" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "LOCK_REGION_197,Lock Region 197" "0,1"
|
|
bitfld.long 0x8 4. "LOCK_REGION_196,Lock Region 196" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "LOCK_REGION_195,Lock Region 195" "0,1"
|
|
bitfld.long 0x8 2. "LOCK_REGION_194,Lock Region 194" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LOCK_REGION_193,Lock Region 193" "0,1"
|
|
bitfld.long 0x8 0. "LOCK_REGION_192,Lock Region 192" "0,1"
|
|
line.long 0xC "WORD7,Lock Bits Word 7"
|
|
bitfld.long 0xC 31. "LOCK_REGION_255,Lock Region 255" "0,1"
|
|
bitfld.long 0xC 30. "LOCK_REGION_254,Lock Region 254" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "LOCK_REGION_253,Lock Region 253" "0,1"
|
|
bitfld.long 0xC 28. "LOCK_REGION_252,Lock Region 252" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "LOCK_REGION_251,Lock Region 251" "0,1"
|
|
bitfld.long 0xC 26. "LOCK_REGION_250,Lock Region 250" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "LOCK_REGION_249,Lock Region 249" "0,1"
|
|
bitfld.long 0xC 24. "LOCK_REGION_248,Lock Region 248" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "LOCK_REGION_247,Lock Region 247" "0,1"
|
|
bitfld.long 0xC 22. "LOCK_REGION_246,Lock Region 246" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "LOCK_REGION_245,Lock Region 245" "0,1"
|
|
bitfld.long 0xC 20. "LOCK_REGION_244,Lock Region 244" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "LOCK_REGION_243,Lock Region 243" "0,1"
|
|
bitfld.long 0xC 18. "LOCK_REGION_242,Lock Region 242" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "LOCK_REGION_241,Lock Region 241" "0,1"
|
|
bitfld.long 0xC 16. "LOCK_REGION_240,Lock Region 240" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "LOCK_REGION_239,Lock Region 239" "0,1"
|
|
bitfld.long 0xC 14. "LOCK_REGION_238,Lock Region 238" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "LOCK_REGION_237,Lock Region 237" "0,1"
|
|
bitfld.long 0xC 12. "LOCK_REGION_236,Lock Region 236" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "LOCK_REGION_235,Lock Region 235" "0,1"
|
|
bitfld.long 0xC 10. "LOCK_REGION_234,Lock Region 234" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "LOCK_REGION_233,Lock Region 233" "0,1"
|
|
bitfld.long 0xC 8. "LOCK_REGION_232,Lock Region 232" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "LOCK_REGION_231,Lock Region 231" "0,1"
|
|
bitfld.long 0xC 6. "LOCK_REGION_230,Lock Region 230" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "LOCK_REGION_229,Lock Region 229" "0,1"
|
|
bitfld.long 0xC 4. "LOCK_REGION_228,Lock Region 228" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "LOCK_REGION_227,Lock Region 227" "0,1"
|
|
bitfld.long 0xC 2. "LOCK_REGION_226,Lock Region 226" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "LOCK_REGION_225,Lock Region 225" "0,1"
|
|
bitfld.long 0xC 0. "LOCK_REGION_224,Lock Region 224" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32C?2051MTG128*"))
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "WORD8,Lock Bits Word 8"
|
|
bitfld.long 0x0 31. "LOCK_REGION_287,Lock Region 287" "0,1"
|
|
bitfld.long 0x0 30. "LOCK_REGION_286,Lock Region 286" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LOCK_REGION_285,Lock Region 285" "0,1"
|
|
bitfld.long 0x0 28. "LOCK_REGION_284,Lock Region 284" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LOCK_REGION_283,Lock Region 283" "0,1"
|
|
bitfld.long 0x0 26. "LOCK_REGION_282,Lock Region 282" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LOCK_REGION_281,Lock Region 281" "0,1"
|
|
bitfld.long 0x0 24. "LOCK_REGION_280,Lock Region 280" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK_REGION_279,Lock Region 279" "0,1"
|
|
bitfld.long 0x0 22. "LOCK_REGION_278,Lock Region 278" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LOCK_REGION_277,Lock Region 277" "0,1"
|
|
bitfld.long 0x0 20. "LOCK_REGION_276,Lock Region 276" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LOCK_REGION_275,Lock Region 275" "0,1"
|
|
bitfld.long 0x0 18. "LOCK_REGION_274,Lock Region 274" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LOCK_REGION_273,Lock Region 273" "0,1"
|
|
bitfld.long 0x0 16. "LOCK_REGION_272,Lock Region 272" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LOCK_REGION_271,Lock Region 271" "0,1"
|
|
bitfld.long 0x0 14. "LOCK_REGION_270,Lock Region 270" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LOCK_REGION_269,Lock Region 269" "0,1"
|
|
bitfld.long 0x0 12. "LOCK_REGION_268,Lock Region 268" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LOCK_REGION_267,Lock Region 267" "0,1"
|
|
bitfld.long 0x0 10. "LOCK_REGION_266,Lock Region 266" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LOCK_REGION_265,Lock Region 265" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_REGION_264,Lock Region 264" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LOCK_REGION_263,Lock Region 263" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_REGION_262,Lock Region 262" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LOCK_REGION_261,Lock Region 261" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_REGION_260,Lock Region 260" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_REGION_259,Lock Region 259" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_REGION_258,Lock Region 258" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK_REGION_257,Lock Region 257" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_REGION_256,Lock Region 256" "0,1"
|
|
line.long 0x4 "WORD9,Lock Bits Word 9"
|
|
bitfld.long 0x4 31. "LOCK_REGION_319,Lock Region 319" "0,1"
|
|
bitfld.long 0x4 30. "LOCK_REGION_318,Lock Region 318" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "LOCK_REGION_317,Lock Region 317" "0,1"
|
|
bitfld.long 0x4 28. "LOCK_REGION_316,Lock Region 316" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "LOCK_REGION_315,Lock Region 315" "0,1"
|
|
bitfld.long 0x4 26. "LOCK_REGION_314,Lock Region 314" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "LOCK_REGION_313,Lock Region 313" "0,1"
|
|
bitfld.long 0x4 24. "LOCK_REGION_312,Lock Region 312" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "LOCK_REGION_311,Lock Region 311" "0,1"
|
|
bitfld.long 0x4 22. "LOCK_REGION_310,Lock Region 310" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "LOCK_REGION_309,Lock Region 309" "0,1"
|
|
bitfld.long 0x4 20. "LOCK_REGION_308,Lock Region 308" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "LOCK_REGION_307,Lock Region 307" "0,1"
|
|
bitfld.long 0x4 18. "LOCK_REGION_306,Lock Region 306" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "LOCK_REGION_305,Lock Region 305" "0,1"
|
|
bitfld.long 0x4 16. "LOCK_REGION_304,Lock Region 304" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "LOCK_REGION_303,Lock Region 303" "0,1"
|
|
bitfld.long 0x4 14. "LOCK_REGION_302,Lock Region 302" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "LOCK_REGION_301,Lock Region 301" "0,1"
|
|
bitfld.long 0x4 12. "LOCK_REGION_300,Lock Region 300" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "LOCK_REGION_299,Lock Region 299" "0,1"
|
|
bitfld.long 0x4 10. "LOCK_REGION_298,Lock Region 298" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "LOCK_REGION_297,Lock Region 297" "0,1"
|
|
bitfld.long 0x4 8. "LOCK_REGION_296,Lock Region 296" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "LOCK_REGION_295,Lock Region 295" "0,1"
|
|
bitfld.long 0x4 6. "LOCK_REGION_294,Lock Region 294" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK_REGION_293,Lock Region 293" "0,1"
|
|
bitfld.long 0x4 4. "LOCK_REGION_292,Lock Region 292" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK_REGION_291,Lock Region 291" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_REGION_290,Lock Region 290" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK_REGION_289,Lock Region 289" "0,1"
|
|
bitfld.long 0x4 0. "LOCK_REGION_288,Lock Region 288" "0,1"
|
|
line.long 0x8 "WORD10,Lock Bits Word 10"
|
|
bitfld.long 0x8 31. "LOCK_REGION_351,Lock Region 351" "0,1"
|
|
bitfld.long 0x8 30. "LOCK_REGION_350,Lock Region 350" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "LOCK_REGION_349,Lock Region 349" "0,1"
|
|
bitfld.long 0x8 28. "LOCK_REGION_348,Lock Region 348" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "LOCK_REGION_347,Lock Region 347" "0,1"
|
|
bitfld.long 0x8 26. "LOCK_REGION_346,Lock Region 346" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "LOCK_REGION_345,Lock Region 345" "0,1"
|
|
bitfld.long 0x8 24. "LOCK_REGION_344,Lock Region 344" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "LOCK_REGION_343,Lock Region 343" "0,1"
|
|
bitfld.long 0x8 22. "LOCK_REGION_342,Lock Region 342" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "LOCK_REGION_341,Lock Region 341" "0,1"
|
|
bitfld.long 0x8 20. "LOCK_REGION_340,Lock Region 340" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "LOCK_REGION_339,Lock Region 339" "0,1"
|
|
bitfld.long 0x8 18. "LOCK_REGION_338,Lock Region 338" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "LOCK_REGION_337,Lock Region 337" "0,1"
|
|
bitfld.long 0x8 16. "LOCK_REGION_336,Lock Region 336" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "LOCK_REGION_335,Lock Region 335" "0,1"
|
|
bitfld.long 0x8 14. "LOCK_REGION_334,Lock Region 334" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "LOCK_REGION_333,Lock Region 333" "0,1"
|
|
bitfld.long 0x8 12. "LOCK_REGION_332,Lock Region 332" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "LOCK_REGION_331,Lock Region 331" "0,1"
|
|
bitfld.long 0x8 10. "LOCK_REGION_330,Lock Region 330" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "LOCK_REGION_329,Lock Region 329" "0,1"
|
|
bitfld.long 0x8 8. "LOCK_REGION_328,Lock Region 328" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "LOCK_REGION_327,Lock Region 327" "0,1"
|
|
bitfld.long 0x8 6. "LOCK_REGION_326,Lock Region 326" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "LOCK_REGION_325,Lock Region 325" "0,1"
|
|
bitfld.long 0x8 4. "LOCK_REGION_324,Lock Region 324" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "LOCK_REGION_323,Lock Region 323" "0,1"
|
|
bitfld.long 0x8 2. "LOCK_REGION_322,Lock Region 322" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LOCK_REGION_321,Lock Region 321" "0,1"
|
|
bitfld.long 0x8 0. "LOCK_REGION_320,Lock Region 320" "0,1"
|
|
line.long 0xC "WORD11,Lock Bits Word 11"
|
|
bitfld.long 0xC 31. "LOCK_REGION_383,Lock Region 383" "0,1"
|
|
bitfld.long 0xC 30. "LOCK_REGION_382,Lock Region 382" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "LOCK_REGION_381,Lock Region 381" "0,1"
|
|
bitfld.long 0xC 28. "LOCK_REGION_380,Lock Region 380" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "LOCK_REGION_379,Lock Region 379" "0,1"
|
|
bitfld.long 0xC 26. "LOCK_REGION_378,Lock Region 378" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "LOCK_REGION_377,Lock Region 377" "0,1"
|
|
bitfld.long 0xC 24. "LOCK_REGION_376,Lock Region 376" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "LOCK_REGION_375,Lock Region 375" "0,1"
|
|
bitfld.long 0xC 22. "LOCK_REGION_374,Lock Region 374" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "LOCK_REGION_373,Lock Region 373" "0,1"
|
|
bitfld.long 0xC 20. "LOCK_REGION_372,Lock Region 372" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "LOCK_REGION_371,Lock Region 371" "0,1"
|
|
bitfld.long 0xC 18. "LOCK_REGION_370,Lock Region 370" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "LOCK_REGION_369,Lock Region 369" "0,1"
|
|
bitfld.long 0xC 16. "LOCK_REGION_368,Lock Region 368" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "LOCK_REGION_367,Lock Region 367" "0,1"
|
|
bitfld.long 0xC 14. "LOCK_REGION_366,Lock Region 366" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "LOCK_REGION_365,Lock Region 365" "0,1"
|
|
bitfld.long 0xC 12. "LOCK_REGION_364,Lock Region 364" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "LOCK_REGION_363,Lock Region 363" "0,1"
|
|
bitfld.long 0xC 10. "LOCK_REGION_362,Lock Region 362" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "LOCK_REGION_361,Lock Region 361" "0,1"
|
|
bitfld.long 0xC 8. "LOCK_REGION_360,Lock Region 360" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "LOCK_REGION_359,Lock Region 359" "0,1"
|
|
bitfld.long 0xC 6. "LOCK_REGION_358,Lock Region 358" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "LOCK_REGION_357,Lock Region 357" "0,1"
|
|
bitfld.long 0xC 4. "LOCK_REGION_356,Lock Region 356" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "LOCK_REGION_355,Lock Region 355" "0,1"
|
|
bitfld.long 0xC 2. "LOCK_REGION_354,Lock Region 354" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "LOCK_REGION_353,Lock Region 353" "0,1"
|
|
bitfld.long 0xC 0. "LOCK_REGION_352,Lock Region 352" "0,1"
|
|
line.long 0x10 "WORD12,Lock Bits Word 12"
|
|
bitfld.long 0x10 31. "LOCK_REGION_415,Lock Region 415" "0,1"
|
|
bitfld.long 0x10 30. "LOCK_REGION_414,Lock Region 414" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "LOCK_REGION_413,Lock Region 413" "0,1"
|
|
bitfld.long 0x10 28. "LOCK_REGION_412,Lock Region 412" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "LOCK_REGION_411,Lock Region 411" "0,1"
|
|
bitfld.long 0x10 26. "LOCK_REGION_410,Lock Region 410" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "LOCK_REGION_409,Lock Region 409" "0,1"
|
|
bitfld.long 0x10 24. "LOCK_REGION_408,Lock Region 408" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "LOCK_REGION_407,Lock Region 407" "0,1"
|
|
bitfld.long 0x10 22. "LOCK_REGION_406,Lock Region 406" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "LOCK_REGION_405,Lock Region 405" "0,1"
|
|
bitfld.long 0x10 20. "LOCK_REGION_404,Lock Region 404" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "LOCK_REGION_403,Lock Region 403" "0,1"
|
|
bitfld.long 0x10 18. "LOCK_REGION_402,Lock Region 402" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "LOCK_REGION_401,Lock Region 401" "0,1"
|
|
bitfld.long 0x10 16. "LOCK_REGION_400,Lock Region 400" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "LOCK_REGION_399,Lock Region 399" "0,1"
|
|
bitfld.long 0x10 14. "LOCK_REGION_398,Lock Region 398" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "LOCK_REGION_397,Lock Region 397" "0,1"
|
|
bitfld.long 0x10 12. "LOCK_REGION_396,Lock Region 396" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "LOCK_REGION_395,Lock Region 395" "0,1"
|
|
bitfld.long 0x10 10. "LOCK_REGION_394,Lock Region 394" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "LOCK_REGION_393,Lock Region 393" "0,1"
|
|
bitfld.long 0x10 8. "LOCK_REGION_392,Lock Region 392" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LOCK_REGION_391,Lock Region 391" "0,1"
|
|
bitfld.long 0x10 6. "LOCK_REGION_390,Lock Region 390" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "LOCK_REGION_389,Lock Region 389" "0,1"
|
|
bitfld.long 0x10 4. "LOCK_REGION_388,Lock Region 388" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "LOCK_REGION_387,Lock Region 387" "0,1"
|
|
bitfld.long 0x10 2. "LOCK_REGION_386,Lock Region 386" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "LOCK_REGION_385,Lock Region 385" "0,1"
|
|
bitfld.long 0x10 0. "LOCK_REGION_384,Lock Region 384" "0,1"
|
|
line.long 0x14 "WORD13,Lock Bits Word 13"
|
|
bitfld.long 0x14 31. "LOCK_REGION_447,Lock Region 447" "0,1"
|
|
bitfld.long 0x14 30. "LOCK_REGION_446,Lock Region 446" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "LOCK_REGION_445,Lock Region 445" "0,1"
|
|
bitfld.long 0x14 28. "LOCK_REGION_444,Lock Region 444" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "LOCK_REGION_443,Lock Region 443" "0,1"
|
|
bitfld.long 0x14 26. "LOCK_REGION_442,Lock Region 442" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "LOCK_REGION_441,Lock Region 441" "0,1"
|
|
bitfld.long 0x14 24. "LOCK_REGION_440,Lock Region 440" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "LOCK_REGION_439,Lock Region 439" "0,1"
|
|
bitfld.long 0x14 22. "LOCK_REGION_438,Lock Region 438" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "LOCK_REGION_437,Lock Region 437" "0,1"
|
|
bitfld.long 0x14 20. "LOCK_REGION_436,Lock Region 436" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "LOCK_REGION_435,Lock Region 435" "0,1"
|
|
bitfld.long 0x14 18. "LOCK_REGION_434,Lock Region 434" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "LOCK_REGION_433,Lock Region 433" "0,1"
|
|
bitfld.long 0x14 16. "LOCK_REGION_432,Lock Region 432" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "LOCK_REGION_431,Lock Region 431" "0,1"
|
|
bitfld.long 0x14 14. "LOCK_REGION_430,Lock Region 430" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "LOCK_REGION_429,Lock Region 429" "0,1"
|
|
bitfld.long 0x14 12. "LOCK_REGION_428,Lock Region 428" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "LOCK_REGION_427,Lock Region 427" "0,1"
|
|
bitfld.long 0x14 10. "LOCK_REGION_426,Lock Region 426" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "LOCK_REGION_425,Lock Region 425" "0,1"
|
|
bitfld.long 0x14 8. "LOCK_REGION_424,Lock Region 424" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "LOCK_REGION_423,Lock Region 423" "0,1"
|
|
bitfld.long 0x14 6. "LOCK_REGION_422,Lock Region 422" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "LOCK_REGION_421,Lock Region 421" "0,1"
|
|
bitfld.long 0x14 4. "LOCK_REGION_420,Lock Region 420" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LOCK_REGION_419,Lock Region 419" "0,1"
|
|
bitfld.long 0x14 2. "LOCK_REGION_418,Lock Region 418" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LOCK_REGION_417,Lock Region 417" "0,1"
|
|
bitfld.long 0x14 0. "LOCK_REGION_416,Lock Region 416" "0,1"
|
|
line.long 0x18 "WORD14,Lock Bits Word 14"
|
|
bitfld.long 0x18 31. "LOCK_REGION_479,Lock Region 479" "0,1"
|
|
bitfld.long 0x18 30. "LOCK_REGION_478,Lock Region 478" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "LOCK_REGION_477,Lock Region 477" "0,1"
|
|
bitfld.long 0x18 28. "LOCK_REGION_476,Lock Region 476" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "LOCK_REGION_475,Lock Region 475" "0,1"
|
|
bitfld.long 0x18 26. "LOCK_REGION_474,Lock Region 474" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "LOCK_REGION_473,Lock Region 473" "0,1"
|
|
bitfld.long 0x18 24. "LOCK_REGION_472,Lock Region 472" "0,1"
|
|
newline
|
|
bitfld.long 0x18 23. "LOCK_REGION_471,Lock Region 471" "0,1"
|
|
bitfld.long 0x18 22. "LOCK_REGION_470,Lock Region 470" "0,1"
|
|
newline
|
|
bitfld.long 0x18 21. "LOCK_REGION_469,Lock Region 469" "0,1"
|
|
bitfld.long 0x18 20. "LOCK_REGION_468,Lock Region 468" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "LOCK_REGION_467,Lock Region 467" "0,1"
|
|
bitfld.long 0x18 18. "LOCK_REGION_466,Lock Region 466" "0,1"
|
|
newline
|
|
bitfld.long 0x18 17. "LOCK_REGION_465,Lock Region 465" "0,1"
|
|
bitfld.long 0x18 16. "LOCK_REGION_464,Lock Region 464" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "LOCK_REGION_463,Lock Region 463" "0,1"
|
|
bitfld.long 0x18 14. "LOCK_REGION_462,Lock Region 462" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "LOCK_REGION_461,Lock Region 461" "0,1"
|
|
bitfld.long 0x18 12. "LOCK_REGION_460,Lock Region 460" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "LOCK_REGION_459,Lock Region 459" "0,1"
|
|
bitfld.long 0x18 10. "LOCK_REGION_458,Lock Region 458" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "LOCK_REGION_457,Lock Region 457" "0,1"
|
|
bitfld.long 0x18 8. "LOCK_REGION_456,Lock Region 456" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "LOCK_REGION_455,Lock Region 455" "0,1"
|
|
bitfld.long 0x18 6. "LOCK_REGION_454,Lock Region 454" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "LOCK_REGION_453,Lock Region 453" "0,1"
|
|
bitfld.long 0x18 4. "LOCK_REGION_452,Lock Region 452" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "LOCK_REGION_451,Lock Region 451" "0,1"
|
|
bitfld.long 0x18 2. "LOCK_REGION_450,Lock Region 450" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "LOCK_REGION_449,Lock Region 449" "0,1"
|
|
bitfld.long 0x18 0. "LOCK_REGION_448,Lock Region 448" "0,1"
|
|
line.long 0x1C "WORD15,Lock Bits Word 15"
|
|
bitfld.long 0x1C 31. "LOCK_REGION_511,Lock Region 511" "0,1"
|
|
bitfld.long 0x1C 30. "LOCK_REGION_510,Lock Region 510" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 29. "LOCK_REGION_509,Lock Region 509" "0,1"
|
|
bitfld.long 0x1C 28. "LOCK_REGION_508,Lock Region 508" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 27. "LOCK_REGION_507,Lock Region 507" "0,1"
|
|
bitfld.long 0x1C 26. "LOCK_REGION_506,Lock Region 506" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "LOCK_REGION_505,Lock Region 505" "0,1"
|
|
bitfld.long 0x1C 24. "LOCK_REGION_504,Lock Region 504" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 23. "LOCK_REGION_503,Lock Region 503" "0,1"
|
|
bitfld.long 0x1C 22. "LOCK_REGION_502,Lock Region 502" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 21. "LOCK_REGION_501,Lock Region 501" "0,1"
|
|
bitfld.long 0x1C 20. "LOCK_REGION_500,Lock Region 500" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 19. "LOCK_REGION_499,Lock Region 499" "0,1"
|
|
bitfld.long 0x1C 18. "LOCK_REGION_498,Lock Region 498" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 17. "LOCK_REGION_497,Lock Region 497" "0,1"
|
|
bitfld.long 0x1C 16. "LOCK_REGION_496,Lock Region 496" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 15. "LOCK_REGION_495,Lock Region 495" "0,1"
|
|
bitfld.long 0x1C 14. "LOCK_REGION_494,Lock Region 494" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "LOCK_REGION_493,Lock Region 493" "0,1"
|
|
bitfld.long 0x1C 12. "LOCK_REGION_492,Lock Region 492" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "LOCK_REGION_491,Lock Region 491" "0,1"
|
|
bitfld.long 0x1C 10. "LOCK_REGION_490,Lock Region 490" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "LOCK_REGION_489,Lock Region 489" "0,1"
|
|
bitfld.long 0x1C 8. "LOCK_REGION_488,Lock Region 488" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "LOCK_REGION_487,Lock Region 487" "0,1"
|
|
bitfld.long 0x1C 6. "LOCK_REGION_486,Lock Region 486" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "LOCK_REGION_485,Lock Region 485" "0,1"
|
|
bitfld.long 0x1C 4. "LOCK_REGION_484,Lock Region 484" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "LOCK_REGION_483,Lock Region 483" "0,1"
|
|
bitfld.long 0x1C 2. "LOCK_REGION_482,Lock Region 482" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "LOCK_REGION_481,Lock Region 481" "0,1"
|
|
bitfld.long 0x1C 0. "LOCK_REGION_480,Lock Region 480" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32C?2051MTG64*"))
|
|
group.long 0x20++0x1F
|
|
line.long 0x0 "WORD8,Lock Bits Word 8"
|
|
bitfld.long 0x0 31. "LOCK_REGION_287,Lock Region 287" "0,1"
|
|
bitfld.long 0x0 30. "LOCK_REGION_286,Lock Region 286" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LOCK_REGION_285,Lock Region 285" "0,1"
|
|
bitfld.long 0x0 28. "LOCK_REGION_284,Lock Region 284" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LOCK_REGION_283,Lock Region 283" "0,1"
|
|
bitfld.long 0x0 26. "LOCK_REGION_282,Lock Region 282" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LOCK_REGION_281,Lock Region 281" "0,1"
|
|
bitfld.long 0x0 24. "LOCK_REGION_280,Lock Region 280" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LOCK_REGION_279,Lock Region 279" "0,1"
|
|
bitfld.long 0x0 22. "LOCK_REGION_278,Lock Region 278" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LOCK_REGION_277,Lock Region 277" "0,1"
|
|
bitfld.long 0x0 20. "LOCK_REGION_276,Lock Region 276" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LOCK_REGION_275,Lock Region 275" "0,1"
|
|
bitfld.long 0x0 18. "LOCK_REGION_274,Lock Region 274" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LOCK_REGION_273,Lock Region 273" "0,1"
|
|
bitfld.long 0x0 16. "LOCK_REGION_272,Lock Region 272" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LOCK_REGION_271,Lock Region 271" "0,1"
|
|
bitfld.long 0x0 14. "LOCK_REGION_270,Lock Region 270" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LOCK_REGION_269,Lock Region 269" "0,1"
|
|
bitfld.long 0x0 12. "LOCK_REGION_268,Lock Region 268" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LOCK_REGION_267,Lock Region 267" "0,1"
|
|
bitfld.long 0x0 10. "LOCK_REGION_266,Lock Region 266" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LOCK_REGION_265,Lock Region 265" "0,1"
|
|
bitfld.long 0x0 8. "LOCK_REGION_264,Lock Region 264" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LOCK_REGION_263,Lock Region 263" "0,1"
|
|
bitfld.long 0x0 6. "LOCK_REGION_262,Lock Region 262" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LOCK_REGION_261,Lock Region 261" "0,1"
|
|
bitfld.long 0x0 4. "LOCK_REGION_260,Lock Region 260" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LOCK_REGION_259,Lock Region 259" "0,1"
|
|
bitfld.long 0x0 2. "LOCK_REGION_258,Lock Region 258" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK_REGION_257,Lock Region 257" "0,1"
|
|
bitfld.long 0x0 0. "LOCK_REGION_256,Lock Region 256" "0,1"
|
|
line.long 0x4 "WORD9,Lock Bits Word 9"
|
|
bitfld.long 0x4 31. "LOCK_REGION_319,Lock Region 319" "0,1"
|
|
bitfld.long 0x4 30. "LOCK_REGION_318,Lock Region 318" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "LOCK_REGION_317,Lock Region 317" "0,1"
|
|
bitfld.long 0x4 28. "LOCK_REGION_316,Lock Region 316" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "LOCK_REGION_315,Lock Region 315" "0,1"
|
|
bitfld.long 0x4 26. "LOCK_REGION_314,Lock Region 314" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "LOCK_REGION_313,Lock Region 313" "0,1"
|
|
bitfld.long 0x4 24. "LOCK_REGION_312,Lock Region 312" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "LOCK_REGION_311,Lock Region 311" "0,1"
|
|
bitfld.long 0x4 22. "LOCK_REGION_310,Lock Region 310" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "LOCK_REGION_309,Lock Region 309" "0,1"
|
|
bitfld.long 0x4 20. "LOCK_REGION_308,Lock Region 308" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "LOCK_REGION_307,Lock Region 307" "0,1"
|
|
bitfld.long 0x4 18. "LOCK_REGION_306,Lock Region 306" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "LOCK_REGION_305,Lock Region 305" "0,1"
|
|
bitfld.long 0x4 16. "LOCK_REGION_304,Lock Region 304" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "LOCK_REGION_303,Lock Region 303" "0,1"
|
|
bitfld.long 0x4 14. "LOCK_REGION_302,Lock Region 302" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "LOCK_REGION_301,Lock Region 301" "0,1"
|
|
bitfld.long 0x4 12. "LOCK_REGION_300,Lock Region 300" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "LOCK_REGION_299,Lock Region 299" "0,1"
|
|
bitfld.long 0x4 10. "LOCK_REGION_298,Lock Region 298" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "LOCK_REGION_297,Lock Region 297" "0,1"
|
|
bitfld.long 0x4 8. "LOCK_REGION_296,Lock Region 296" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "LOCK_REGION_295,Lock Region 295" "0,1"
|
|
bitfld.long 0x4 6. "LOCK_REGION_294,Lock Region 294" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "LOCK_REGION_293,Lock Region 293" "0,1"
|
|
bitfld.long 0x4 4. "LOCK_REGION_292,Lock Region 292" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "LOCK_REGION_291,Lock Region 291" "0,1"
|
|
bitfld.long 0x4 2. "LOCK_REGION_290,Lock Region 290" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK_REGION_289,Lock Region 289" "0,1"
|
|
bitfld.long 0x4 0. "LOCK_REGION_288,Lock Region 288" "0,1"
|
|
line.long 0x8 "WORD10,Lock Bits Word 10"
|
|
bitfld.long 0x8 31. "LOCK_REGION_351,Lock Region 351" "0,1"
|
|
bitfld.long 0x8 30. "LOCK_REGION_350,Lock Region 350" "0,1"
|
|
newline
|
|
bitfld.long 0x8 29. "LOCK_REGION_349,Lock Region 349" "0,1"
|
|
bitfld.long 0x8 28. "LOCK_REGION_348,Lock Region 348" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "LOCK_REGION_347,Lock Region 347" "0,1"
|
|
bitfld.long 0x8 26. "LOCK_REGION_346,Lock Region 346" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "LOCK_REGION_345,Lock Region 345" "0,1"
|
|
bitfld.long 0x8 24. "LOCK_REGION_344,Lock Region 344" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "LOCK_REGION_343,Lock Region 343" "0,1"
|
|
bitfld.long 0x8 22. "LOCK_REGION_342,Lock Region 342" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "LOCK_REGION_341,Lock Region 341" "0,1"
|
|
bitfld.long 0x8 20. "LOCK_REGION_340,Lock Region 340" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "LOCK_REGION_339,Lock Region 339" "0,1"
|
|
bitfld.long 0x8 18. "LOCK_REGION_338,Lock Region 338" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "LOCK_REGION_337,Lock Region 337" "0,1"
|
|
bitfld.long 0x8 16. "LOCK_REGION_336,Lock Region 336" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "LOCK_REGION_335,Lock Region 335" "0,1"
|
|
bitfld.long 0x8 14. "LOCK_REGION_334,Lock Region 334" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "LOCK_REGION_333,Lock Region 333" "0,1"
|
|
bitfld.long 0x8 12. "LOCK_REGION_332,Lock Region 332" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "LOCK_REGION_331,Lock Region 331" "0,1"
|
|
bitfld.long 0x8 10. "LOCK_REGION_330,Lock Region 330" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "LOCK_REGION_329,Lock Region 329" "0,1"
|
|
bitfld.long 0x8 8. "LOCK_REGION_328,Lock Region 328" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "LOCK_REGION_327,Lock Region 327" "0,1"
|
|
bitfld.long 0x8 6. "LOCK_REGION_326,Lock Region 326" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "LOCK_REGION_325,Lock Region 325" "0,1"
|
|
bitfld.long 0x8 4. "LOCK_REGION_324,Lock Region 324" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "LOCK_REGION_323,Lock Region 323" "0,1"
|
|
bitfld.long 0x8 2. "LOCK_REGION_322,Lock Region 322" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "LOCK_REGION_321,Lock Region 321" "0,1"
|
|
bitfld.long 0x8 0. "LOCK_REGION_320,Lock Region 320" "0,1"
|
|
line.long 0xC "WORD11,Lock Bits Word 11"
|
|
bitfld.long 0xC 31. "LOCK_REGION_383,Lock Region 383" "0,1"
|
|
bitfld.long 0xC 30. "LOCK_REGION_382,Lock Region 382" "0,1"
|
|
newline
|
|
bitfld.long 0xC 29. "LOCK_REGION_381,Lock Region 381" "0,1"
|
|
bitfld.long 0xC 28. "LOCK_REGION_380,Lock Region 380" "0,1"
|
|
newline
|
|
bitfld.long 0xC 27. "LOCK_REGION_379,Lock Region 379" "0,1"
|
|
bitfld.long 0xC 26. "LOCK_REGION_378,Lock Region 378" "0,1"
|
|
newline
|
|
bitfld.long 0xC 25. "LOCK_REGION_377,Lock Region 377" "0,1"
|
|
bitfld.long 0xC 24. "LOCK_REGION_376,Lock Region 376" "0,1"
|
|
newline
|
|
bitfld.long 0xC 23. "LOCK_REGION_375,Lock Region 375" "0,1"
|
|
bitfld.long 0xC 22. "LOCK_REGION_374,Lock Region 374" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "LOCK_REGION_373,Lock Region 373" "0,1"
|
|
bitfld.long 0xC 20. "LOCK_REGION_372,Lock Region 372" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "LOCK_REGION_371,Lock Region 371" "0,1"
|
|
bitfld.long 0xC 18. "LOCK_REGION_370,Lock Region 370" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "LOCK_REGION_369,Lock Region 369" "0,1"
|
|
bitfld.long 0xC 16. "LOCK_REGION_368,Lock Region 368" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "LOCK_REGION_367,Lock Region 367" "0,1"
|
|
bitfld.long 0xC 14. "LOCK_REGION_366,Lock Region 366" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "LOCK_REGION_365,Lock Region 365" "0,1"
|
|
bitfld.long 0xC 12. "LOCK_REGION_364,Lock Region 364" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "LOCK_REGION_363,Lock Region 363" "0,1"
|
|
bitfld.long 0xC 10. "LOCK_REGION_362,Lock Region 362" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "LOCK_REGION_361,Lock Region 361" "0,1"
|
|
bitfld.long 0xC 8. "LOCK_REGION_360,Lock Region 360" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "LOCK_REGION_359,Lock Region 359" "0,1"
|
|
bitfld.long 0xC 6. "LOCK_REGION_358,Lock Region 358" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "LOCK_REGION_357,Lock Region 357" "0,1"
|
|
bitfld.long 0xC 4. "LOCK_REGION_356,Lock Region 356" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "LOCK_REGION_355,Lock Region 355" "0,1"
|
|
bitfld.long 0xC 2. "LOCK_REGION_354,Lock Region 354" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "LOCK_REGION_353,Lock Region 353" "0,1"
|
|
bitfld.long 0xC 0. "LOCK_REGION_352,Lock Region 352" "0,1"
|
|
line.long 0x10 "WORD12,Lock Bits Word 12"
|
|
bitfld.long 0x10 31. "LOCK_REGION_415,Lock Region 415" "0,1"
|
|
bitfld.long 0x10 30. "LOCK_REGION_414,Lock Region 414" "0,1"
|
|
newline
|
|
bitfld.long 0x10 29. "LOCK_REGION_413,Lock Region 413" "0,1"
|
|
bitfld.long 0x10 28. "LOCK_REGION_412,Lock Region 412" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "LOCK_REGION_411,Lock Region 411" "0,1"
|
|
bitfld.long 0x10 26. "LOCK_REGION_410,Lock Region 410" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "LOCK_REGION_409,Lock Region 409" "0,1"
|
|
bitfld.long 0x10 24. "LOCK_REGION_408,Lock Region 408" "0,1"
|
|
newline
|
|
bitfld.long 0x10 23. "LOCK_REGION_407,Lock Region 407" "0,1"
|
|
bitfld.long 0x10 22. "LOCK_REGION_406,Lock Region 406" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "LOCK_REGION_405,Lock Region 405" "0,1"
|
|
bitfld.long 0x10 20. "LOCK_REGION_404,Lock Region 404" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "LOCK_REGION_403,Lock Region 403" "0,1"
|
|
bitfld.long 0x10 18. "LOCK_REGION_402,Lock Region 402" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "LOCK_REGION_401,Lock Region 401" "0,1"
|
|
bitfld.long 0x10 16. "LOCK_REGION_400,Lock Region 400" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "LOCK_REGION_399,Lock Region 399" "0,1"
|
|
bitfld.long 0x10 14. "LOCK_REGION_398,Lock Region 398" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "LOCK_REGION_397,Lock Region 397" "0,1"
|
|
bitfld.long 0x10 12. "LOCK_REGION_396,Lock Region 396" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "LOCK_REGION_395,Lock Region 395" "0,1"
|
|
bitfld.long 0x10 10. "LOCK_REGION_394,Lock Region 394" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "LOCK_REGION_393,Lock Region 393" "0,1"
|
|
bitfld.long 0x10 8. "LOCK_REGION_392,Lock Region 392" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "LOCK_REGION_391,Lock Region 391" "0,1"
|
|
bitfld.long 0x10 6. "LOCK_REGION_390,Lock Region 390" "0,1"
|
|
newline
|
|
bitfld.long 0x10 5. "LOCK_REGION_389,Lock Region 389" "0,1"
|
|
bitfld.long 0x10 4. "LOCK_REGION_388,Lock Region 388" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "LOCK_REGION_387,Lock Region 387" "0,1"
|
|
bitfld.long 0x10 2. "LOCK_REGION_386,Lock Region 386" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "LOCK_REGION_385,Lock Region 385" "0,1"
|
|
bitfld.long 0x10 0. "LOCK_REGION_384,Lock Region 384" "0,1"
|
|
line.long 0x14 "WORD13,Lock Bits Word 13"
|
|
bitfld.long 0x14 31. "LOCK_REGION_447,Lock Region 447" "0,1"
|
|
bitfld.long 0x14 30. "LOCK_REGION_446,Lock Region 446" "0,1"
|
|
newline
|
|
bitfld.long 0x14 29. "LOCK_REGION_445,Lock Region 445" "0,1"
|
|
bitfld.long 0x14 28. "LOCK_REGION_444,Lock Region 444" "0,1"
|
|
newline
|
|
bitfld.long 0x14 27. "LOCK_REGION_443,Lock Region 443" "0,1"
|
|
bitfld.long 0x14 26. "LOCK_REGION_442,Lock Region 442" "0,1"
|
|
newline
|
|
bitfld.long 0x14 25. "LOCK_REGION_441,Lock Region 441" "0,1"
|
|
bitfld.long 0x14 24. "LOCK_REGION_440,Lock Region 440" "0,1"
|
|
newline
|
|
bitfld.long 0x14 23. "LOCK_REGION_439,Lock Region 439" "0,1"
|
|
bitfld.long 0x14 22. "LOCK_REGION_438,Lock Region 438" "0,1"
|
|
newline
|
|
bitfld.long 0x14 21. "LOCK_REGION_437,Lock Region 437" "0,1"
|
|
bitfld.long 0x14 20. "LOCK_REGION_436,Lock Region 436" "0,1"
|
|
newline
|
|
bitfld.long 0x14 19. "LOCK_REGION_435,Lock Region 435" "0,1"
|
|
bitfld.long 0x14 18. "LOCK_REGION_434,Lock Region 434" "0,1"
|
|
newline
|
|
bitfld.long 0x14 17. "LOCK_REGION_433,Lock Region 433" "0,1"
|
|
bitfld.long 0x14 16. "LOCK_REGION_432,Lock Region 432" "0,1"
|
|
newline
|
|
bitfld.long 0x14 15. "LOCK_REGION_431,Lock Region 431" "0,1"
|
|
bitfld.long 0x14 14. "LOCK_REGION_430,Lock Region 430" "0,1"
|
|
newline
|
|
bitfld.long 0x14 13. "LOCK_REGION_429,Lock Region 429" "0,1"
|
|
bitfld.long 0x14 12. "LOCK_REGION_428,Lock Region 428" "0,1"
|
|
newline
|
|
bitfld.long 0x14 11. "LOCK_REGION_427,Lock Region 427" "0,1"
|
|
bitfld.long 0x14 10. "LOCK_REGION_426,Lock Region 426" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "LOCK_REGION_425,Lock Region 425" "0,1"
|
|
bitfld.long 0x14 8. "LOCK_REGION_424,Lock Region 424" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "LOCK_REGION_423,Lock Region 423" "0,1"
|
|
bitfld.long 0x14 6. "LOCK_REGION_422,Lock Region 422" "0,1"
|
|
newline
|
|
bitfld.long 0x14 5. "LOCK_REGION_421,Lock Region 421" "0,1"
|
|
bitfld.long 0x14 4. "LOCK_REGION_420,Lock Region 420" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "LOCK_REGION_419,Lock Region 419" "0,1"
|
|
bitfld.long 0x14 2. "LOCK_REGION_418,Lock Region 418" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "LOCK_REGION_417,Lock Region 417" "0,1"
|
|
bitfld.long 0x14 0. "LOCK_REGION_416,Lock Region 416" "0,1"
|
|
line.long 0x18 "WORD14,Lock Bits Word 14"
|
|
bitfld.long 0x18 31. "LOCK_REGION_479,Lock Region 479" "0,1"
|
|
bitfld.long 0x18 30. "LOCK_REGION_478,Lock Region 478" "0,1"
|
|
newline
|
|
bitfld.long 0x18 29. "LOCK_REGION_477,Lock Region 477" "0,1"
|
|
bitfld.long 0x18 28. "LOCK_REGION_476,Lock Region 476" "0,1"
|
|
newline
|
|
bitfld.long 0x18 27. "LOCK_REGION_475,Lock Region 475" "0,1"
|
|
bitfld.long 0x18 26. "LOCK_REGION_474,Lock Region 474" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "LOCK_REGION_473,Lock Region 473" "0,1"
|
|
bitfld.long 0x18 24. "LOCK_REGION_472,Lock Region 472" "0,1"
|
|
newline
|
|
bitfld.long 0x18 23. "LOCK_REGION_471,Lock Region 471" "0,1"
|
|
bitfld.long 0x18 22. "LOCK_REGION_470,Lock Region 470" "0,1"
|
|
newline
|
|
bitfld.long 0x18 21. "LOCK_REGION_469,Lock Region 469" "0,1"
|
|
bitfld.long 0x18 20. "LOCK_REGION_468,Lock Region 468" "0,1"
|
|
newline
|
|
bitfld.long 0x18 19. "LOCK_REGION_467,Lock Region 467" "0,1"
|
|
bitfld.long 0x18 18. "LOCK_REGION_466,Lock Region 466" "0,1"
|
|
newline
|
|
bitfld.long 0x18 17. "LOCK_REGION_465,Lock Region 465" "0,1"
|
|
bitfld.long 0x18 16. "LOCK_REGION_464,Lock Region 464" "0,1"
|
|
newline
|
|
bitfld.long 0x18 15. "LOCK_REGION_463,Lock Region 463" "0,1"
|
|
bitfld.long 0x18 14. "LOCK_REGION_462,Lock Region 462" "0,1"
|
|
newline
|
|
bitfld.long 0x18 13. "LOCK_REGION_461,Lock Region 461" "0,1"
|
|
bitfld.long 0x18 12. "LOCK_REGION_460,Lock Region 460" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "LOCK_REGION_459,Lock Region 459" "0,1"
|
|
bitfld.long 0x18 10. "LOCK_REGION_458,Lock Region 458" "0,1"
|
|
newline
|
|
bitfld.long 0x18 9. "LOCK_REGION_457,Lock Region 457" "0,1"
|
|
bitfld.long 0x18 8. "LOCK_REGION_456,Lock Region 456" "0,1"
|
|
newline
|
|
bitfld.long 0x18 7. "LOCK_REGION_455,Lock Region 455" "0,1"
|
|
bitfld.long 0x18 6. "LOCK_REGION_454,Lock Region 454" "0,1"
|
|
newline
|
|
bitfld.long 0x18 5. "LOCK_REGION_453,Lock Region 453" "0,1"
|
|
bitfld.long 0x18 4. "LOCK_REGION_452,Lock Region 452" "0,1"
|
|
newline
|
|
bitfld.long 0x18 3. "LOCK_REGION_451,Lock Region 451" "0,1"
|
|
bitfld.long 0x18 2. "LOCK_REGION_450,Lock Region 450" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "LOCK_REGION_449,Lock Region 449" "0,1"
|
|
bitfld.long 0x18 0. "LOCK_REGION_448,Lock Region 448" "0,1"
|
|
line.long 0x1C "WORD15,Lock Bits Word 15"
|
|
bitfld.long 0x1C 31. "LOCK_REGION_511,Lock Region 511" "0,1"
|
|
bitfld.long 0x1C 30. "LOCK_REGION_510,Lock Region 510" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 29. "LOCK_REGION_509,Lock Region 509" "0,1"
|
|
bitfld.long 0x1C 28. "LOCK_REGION_508,Lock Region 508" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 27. "LOCK_REGION_507,Lock Region 507" "0,1"
|
|
bitfld.long 0x1C 26. "LOCK_REGION_506,Lock Region 506" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 25. "LOCK_REGION_505,Lock Region 505" "0,1"
|
|
bitfld.long 0x1C 24. "LOCK_REGION_504,Lock Region 504" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 23. "LOCK_REGION_503,Lock Region 503" "0,1"
|
|
bitfld.long 0x1C 22. "LOCK_REGION_502,Lock Region 502" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 21. "LOCK_REGION_501,Lock Region 501" "0,1"
|
|
bitfld.long 0x1C 20. "LOCK_REGION_500,Lock Region 500" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 19. "LOCK_REGION_499,Lock Region 499" "0,1"
|
|
bitfld.long 0x1C 18. "LOCK_REGION_498,Lock Region 498" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 17. "LOCK_REGION_497,Lock Region 497" "0,1"
|
|
bitfld.long 0x1C 16. "LOCK_REGION_496,Lock Region 496" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 15. "LOCK_REGION_495,Lock Region 495" "0,1"
|
|
bitfld.long 0x1C 14. "LOCK_REGION_494,Lock Region 494" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 13. "LOCK_REGION_493,Lock Region 493" "0,1"
|
|
bitfld.long 0x1C 12. "LOCK_REGION_492,Lock Region 492" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 11. "LOCK_REGION_491,Lock Region 491" "0,1"
|
|
bitfld.long 0x1C 10. "LOCK_REGION_490,Lock Region 490" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 9. "LOCK_REGION_489,Lock Region 489" "0,1"
|
|
bitfld.long 0x1C 8. "LOCK_REGION_488,Lock Region 488" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 7. "LOCK_REGION_487,Lock Region 487" "0,1"
|
|
bitfld.long 0x1C 6. "LOCK_REGION_486,Lock Region 486" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 5. "LOCK_REGION_485,Lock Region 485" "0,1"
|
|
bitfld.long 0x1C 4. "LOCK_REGION_484,Lock Region 484" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 3. "LOCK_REGION_483,Lock Region 483" "0,1"
|
|
bitfld.long 0x1C 2. "LOCK_REGION_482,Lock Region 482" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "LOCK_REGION_481,Lock Region 481" "0,1"
|
|
bitfld.long 0x1C 0. "LOCK_REGION_480,Lock Region 480" "0,1"
|
|
endif
|
|
tree.end
|
|
tree "MATRIX (Bus Matrix)"
|
|
base ad:0x0
|
|
tree "MATRIX0"
|
|
base ad:0x46004000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x46004080 ad:0x46004088 ad:0x46004090 ad:0x46004098 ad:0x460040A0 ad:0x460040A8 ad:0x460040B0 ad:0x460040B8 ad:0x460040C0 ad:0x460040C8 ad:0x460040D0 ad:0x460040D8 ad:0x460040E0 ad:0x460040E8 ad:0x460040F0 ad:0x460040F8)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality of Service Enable for Master 15" "0,1"
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0,1"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x46004000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0,1"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0,1"
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0,1"
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0,1"
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0,1"
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0,1"
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0,1"
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0,1"
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "SFR[$1],Special Function Register"
|
|
hexmask.long 0x0 0.--31. 1. "SFR,Special Function Register Fields"
|
|
repeat.end
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ,Configuration Freeze" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "VERSION,Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Matrix Version"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "PSR[$1],Protection Slave 0 Register"
|
|
bitfld.long 0x0 31. "DPSOA7,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 30. "DPSOA6,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DPSOA5,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 28. "DPSOA4,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DPSOA3,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 26. "DPSOA2,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DPSOA1,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 24. "DPSOA0,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "WRUSERH7,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 22. "WRUSERH6,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRUSERH5,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 20. "WRUSERH4,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRUSERH3,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 18. "WRUSERH2,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRUSERH1,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 16. "WRUSERH0,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDUSERH7,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 14. "RDUSERH6,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDUSERH5,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 12. "RDUSERH4,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDUSERH3,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 10. "RDUSERH2,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDUSERH1,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 8. "RDUSERH0,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LAUSERH7,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 6. "LAUSERH6,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LAUSERH5,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 4. "LAUSERH4,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LAUSERH3,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 2. "LAUSERH2,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LAUSERH1,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 0. "LAUSERH0,Low Area USER in HSELx Protected Region" "0,1"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "PASSR[$1],Protected Areas Split Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PASPLIT7,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PASPLIT6,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PASPLIT5,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PASPLIT4,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PASPLIT3,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PASPLIT2,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PASPLIT1,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PASPLIT0,Protected Areas Split for HSELx Protected Region"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "PRTSR[$1],Protected Region Top Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRTOP7,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRTOP6,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRTOP5,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRTOP4,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRTOP3,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRTOP2,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRTOP1,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRTOP0,HSELx Protected Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "PPSELR[$1],Protected Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "USERP31,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "USERP30,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "USERP29,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "USERP28,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "USERP27,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "USERP26,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "USERP25,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "USERP24,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "USERP23,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "USERP22,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "USERP21,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "USERP20,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "USERP19,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "USERP18,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "USERP17,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "USERP16,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "USERP15,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "USERP14,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "USERP13,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "USERP12,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USERP11,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "USERP10,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "USERP9,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "USERP8,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "USERP7,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "USERP6,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "USERP5,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "USERP4,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "USERP3,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "USERP2,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "USERP1,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "USERP0,User PSELy Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX1"
|
|
base ad:0x40044000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x40044080 ad:0x40044088 ad:0x40044090 ad:0x40044098 ad:0x400440A0 ad:0x400440A8 ad:0x400440B0 ad:0x400440B8 ad:0x400440C0 ad:0x400440C8 ad:0x400440D0 ad:0x400440D8 ad:0x400440E0 ad:0x400440E8 ad:0x400440F0 ad:0x400440F8)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality of Service Enable for Master 15" "0,1"
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0,1"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40044000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0,1"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0,1"
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0,1"
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0,1"
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0,1"
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0,1"
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0,1"
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0,1"
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "SFR[$1],Special Function Register"
|
|
hexmask.long 0x0 0.--31. 1. "SFR,Special Function Register Fields"
|
|
repeat.end
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ,Configuration Freeze" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "VERSION,Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Matrix Version"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "PSR[$1],Protection Slave 0 Register"
|
|
bitfld.long 0x0 31. "DPSOA7,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 30. "DPSOA6,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DPSOA5,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 28. "DPSOA4,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DPSOA3,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 26. "DPSOA2,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DPSOA1,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 24. "DPSOA0,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "WRUSERH7,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 22. "WRUSERH6,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRUSERH5,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 20. "WRUSERH4,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRUSERH3,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 18. "WRUSERH2,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRUSERH1,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 16. "WRUSERH0,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDUSERH7,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 14. "RDUSERH6,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDUSERH5,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 12. "RDUSERH4,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDUSERH3,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 10. "RDUSERH2,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDUSERH1,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 8. "RDUSERH0,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LAUSERH7,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 6. "LAUSERH6,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LAUSERH5,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 4. "LAUSERH4,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LAUSERH3,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 2. "LAUSERH2,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LAUSERH1,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 0. "LAUSERH0,Low Area USER in HSELx Protected Region" "0,1"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "PASSR[$1],Protected Areas Split Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PASPLIT7,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PASPLIT6,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PASPLIT5,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PASPLIT4,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PASPLIT3,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PASPLIT2,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PASPLIT1,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PASPLIT0,Protected Areas Split for HSELx Protected Region"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "PRTSR[$1],Protected Region Top Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRTOP7,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRTOP6,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRTOP5,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRTOP4,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRTOP3,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRTOP2,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRTOP1,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRTOP0,HSELx Protected Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "PPSELR[$1],Protected Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "USERP31,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "USERP30,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "USERP29,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "USERP28,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "USERP27,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "USERP26,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "USERP25,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "USERP24,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "USERP23,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "USERP22,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "USERP21,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "USERP20,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "USERP19,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "USERP18,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "USERP17,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "USERP16,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "USERP15,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "USERP14,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "USERP13,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "USERP12,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USERP11,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "USERP10,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "USERP9,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "USERP8,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "USERP7,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "USERP6,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "USERP5,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "USERP4,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "USERP3,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "USERP2,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "USERP1,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "USERP0,User PSELy Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX2"
|
|
base ad:0x4A000000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x4A000080 ad:0x4A000088 ad:0x4A000090 ad:0x4A000098 ad:0x4A0000A0 ad:0x4A0000A8 ad:0x4A0000B0 ad:0x4A0000B8 ad:0x4A0000C0 ad:0x4A0000C8 ad:0x4A0000D0 ad:0x4A0000D8 ad:0x4A0000E0 ad:0x4A0000E8 ad:0x4A0000F0 ad:0x4A0000F8)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality of Service Enable for Master 15" "0,1"
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0,1"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4A000000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0,1"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0,1"
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0,1"
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0,1"
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0,1"
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0,1"
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0,1"
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0,1"
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "SFR[$1],Special Function Register"
|
|
hexmask.long 0x0 0.--31. 1. "SFR,Special Function Register Fields"
|
|
repeat.end
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ,Configuration Freeze" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "VERSION,Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Matrix Version"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "PSR[$1],Protection Slave 0 Register"
|
|
bitfld.long 0x0 31. "DPSOA7,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 30. "DPSOA6,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DPSOA5,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 28. "DPSOA4,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DPSOA3,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 26. "DPSOA2,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DPSOA1,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 24. "DPSOA0,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "WRUSERH7,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 22. "WRUSERH6,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRUSERH5,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 20. "WRUSERH4,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRUSERH3,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 18. "WRUSERH2,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRUSERH1,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 16. "WRUSERH0,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDUSERH7,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 14. "RDUSERH6,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDUSERH5,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 12. "RDUSERH4,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDUSERH3,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 10. "RDUSERH2,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDUSERH1,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 8. "RDUSERH0,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LAUSERH7,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 6. "LAUSERH6,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LAUSERH5,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 4. "LAUSERH4,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LAUSERH3,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 2. "LAUSERH2,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LAUSERH1,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 0. "LAUSERH0,Low Area USER in HSELx Protected Region" "0,1"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "PASSR[$1],Protected Areas Split Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PASPLIT7,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PASPLIT6,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PASPLIT5,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PASPLIT4,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PASPLIT3,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PASPLIT2,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PASPLIT1,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PASPLIT0,Protected Areas Split for HSELx Protected Region"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "PRTSR[$1],Protected Region Top Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRTOP7,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRTOP6,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRTOP5,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRTOP4,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRTOP3,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRTOP2,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRTOP1,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRTOP0,HSELx Protected Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "PPSELR[$1],Protected Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "USERP31,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "USERP30,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "USERP29,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "USERP28,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "USERP27,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "USERP26,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "USERP25,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "USERP24,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "USERP23,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "USERP22,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "USERP21,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "USERP20,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "USERP19,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "USERP18,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "USERP17,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "USERP16,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "USERP15,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "USERP14,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "USERP13,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "USERP12,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USERP11,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "USERP10,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "USERP9,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "USERP8,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "USERP7,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "USERP6,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "USERP5,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "USERP4,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "USERP3,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "USERP2,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "USERP1,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "USERP0,User PSELy Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree "MATRIX3"
|
|
base ad:0x48020000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration Register"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Unlimited Length Burst-No predicted end of burst..,1: Single Access-The undefined length burst is..,2: 4-beat Burst-The undefined length burst or..,3: 8-beat Burst-The undefined length burst or..,4: 16-beat Burst-The undefined length burst or..,5: 32-beat Burst-The undefined length burst or..,6: 64-beat Burst-The undefined length burst or..,7: 128-beat Burst-The undefined length burst or.."
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration Register"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master-At the end of the current..,1: Last Default Master-At the end of the current..,2: Fixed Default Master-At the end of the current..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Bus Grant Duration for Masters"
|
|
repeat.end
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x48020080 ad:0x48020088 ad:0x48020090 ad:0x48020098 ad:0x480200A0 ad:0x480200A8 ad:0x480200B0 ad:0x480200B8 ad:0x480200C0 ad:0x480200C8 ad:0x480200D0 ad:0x480200D8 ad:0x480200E0 ad:0x480200E8 ad:0x480200F0 ad:0x480200F8)
|
|
tree "MATRIX_PR[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority Register A for Slave 0"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority Register B for Slave 0"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality of Service Enable for Master 15" "0,1"
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality of Service Enable for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality of Service Enable for Master 9" "0,1"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x48020000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control Register"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0,1"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0,1"
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0,1"
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0,1"
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0,1"
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0,1"
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0,1"
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0,1"
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "SFR[$1],Special Function Register"
|
|
hexmask.long 0x0 0.--31. 1. "SFR,Special Function Register Fields"
|
|
repeat.end
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask Register"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status Register"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master 0 Error Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ERRADD,Master Error Address"
|
|
repeat.end
|
|
group.long 0x1E4++0x3
|
|
line.long 0x0 "WPMR,Write Protect Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "CFGFRZ,Configuration Freeze" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x1E8++0x3
|
|
line.long 0x0 "WPSR,Write Protect Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
rgroup.long 0x1FC++0x3
|
|
line.long 0x0 "VERSION,Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Matrix Version"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "PSR[$1],Protection Slave 0 Register"
|
|
bitfld.long 0x0 31. "DPSOA7,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 30. "DPSOA6,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DPSOA5,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 28. "DPSOA4,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DPSOA3,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 26. "DPSOA2,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DPSOA1,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 24. "DPSOA0,Downward Protection Split Address for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "WRUSERH7,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 22. "WRUSERH6,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "WRUSERH5,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 20. "WRUSERH4,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "WRUSERH3,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 18. "WRUSERH2,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "WRUSERH1,Write USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 16. "WRUSERH0,Write USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "RDUSERH7,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 14. "RDUSERH6,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "RDUSERH5,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 12. "RDUSERH4,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "RDUSERH3,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 10. "RDUSERH2,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RDUSERH1,Read USER for HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 8. "RDUSERH0,Read USER for HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LAUSERH7,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 6. "LAUSERH6,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LAUSERH5,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 4. "LAUSERH4,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LAUSERH3,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 2. "LAUSERH2,Low Area USER in HSELx Protected Region" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LAUSERH1,Low Area USER in HSELx Protected Region" "0,1"
|
|
bitfld.long 0x0 0. "LAUSERH0,Low Area USER in HSELx Protected Region" "0,1"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x240)++0x3
|
|
line.long 0x0 "PASSR[$1],Protected Areas Split Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PASPLIT7,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PASPLIT6,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PASPLIT5,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PASPLIT4,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PASPLIT3,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PASPLIT2,Protected Areas Split for HSELx Protected Region"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PASPLIT1,Protected Areas Split for HSELx Protected Region"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PASPLIT0,Protected Areas Split for HSELx Protected Region"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "PRTSR[$1],Protected Region Top Slave 0 Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "PRTOP7,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PRTOP6,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "PRTOP5,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PRTOP4,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "PRTOP3,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 8.--11. 1. "PRTOP2,HSELx Protected Region Top"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "PRTOP1,HSELx Protected Region Top"
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRTOP0,HSELx Protected Region Top"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x2C0)++0x3
|
|
line.long 0x0 "PPSELR[$1],Protected Peripheral Select 1 Register"
|
|
bitfld.long 0x0 31. "USERP31,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 30. "USERP30,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "USERP29,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 28. "USERP28,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "USERP27,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 26. "USERP26,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "USERP25,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 24. "USERP24,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "USERP23,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 22. "USERP22,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "USERP21,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 20. "USERP20,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "USERP19,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 18. "USERP18,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "USERP17,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 16. "USERP16,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "USERP15,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 14. "USERP14,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "USERP13,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 12. "USERP12,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "USERP11,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 10. "USERP10,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "USERP9,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 8. "USERP8,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "USERP7,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 6. "USERP6,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "USERP5,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 4. "USERP4,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "USERP3,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 2. "USERP2,User PSELy Peripheral" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "USERP1,User PSELy Peripheral" "0,1"
|
|
bitfld.long 0x0 0. "USERP0,User PSELy Peripheral" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
sif (cpuis("PIC32C?1025MTG128*")||cpuis("PIC32C?2051MTG128*")||cpuis("PIC32C?5112MTG128*"))
|
|
tree "MCSPI (Multi Channel Serial Peripheral Interface)"
|
|
base ad:0x48018000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 31. "FIFODIS,FIFO Disable" "0,1"
|
|
bitfld.long 0x0 30. "FIFOEN,FIFO Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 17. "RXFCLR,Receive FIFO Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "TXFCLR,Transmit FIFO Clear" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request to Clear the Comparison Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,MCSPI Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "SPIDIS,MCSPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SPIEN,MCSPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCS,Delay Between Chip Selects"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
bitfld.long 0x0 15. "MOSIIE,MOSI Inversion Enable" "0,1"
|
|
bitfld.long 0x0 14. "CSIE,Chip Select Inversion Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TPMEN,Two-Pin Mode Enable" "0,1"
|
|
bitfld.long 0x0 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
newline
|
|
bitfld.long 0x0 9. "TMCSMUX,Two-pin MOSI Chip Select External Multiplexing Mode" "0: External MOSI lines multiplexing is not required..,1: Enables external multiplexing of MOSI lines via.."
|
|
bitfld.long 0x0 8. "LSBHALF,LSB Timing Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LLB,Local Loopback Enable" "0,1"
|
|
bitfld.long 0x0 6. "CRCEN,CRC Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WDRBT,Wait for Data Read Before Transfer" "0,1"
|
|
bitfld.long 0x0 4. "MODFDIS,Mode Fault Detection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "BRSRCCLK,Bit Rate Source Clock" "0: The peripheral clock is the source clock for the..,1: PMC GCLK is the source clock for the bit rate.."
|
|
bitfld.long 0x0 2. "PCSDEC,Chip Select Decode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PS,Peripheral Select" "0,1"
|
|
bitfld.long 0x0 0. "MSTR,Host/Client Mode" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR_FIFO_MULTI_DATA_8_MODE,Receive Data Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "RD3,Receive Data"
|
|
hexmask.long.byte 0x0 16.--23. 1. "RD2,Receive Data"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "RD1,Receive Data"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RD0,Receive Data"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR_FIFO_MULTI_DATA_16_MODE,Receive Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "RD1,Receive Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD0,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "PCS,Peripheral Chip Select"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR_FIFO_MULTI_DATA_MODE,Transmit Data Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "TD1,Transmit Data"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD0,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,Receive FIFO Pointer Error Flag" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,Transmit FIFO Pointer Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,Receive FIFO Threshold Flag" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,Receive FIFO Full Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,Receive FIFO Empty Flag" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,Transmit FIFO Threshold Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,Transmit FIFO Full Flag (cleared on read)" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,Transmit FIFO Empty Flag (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "SPIENS,MCSPI Enable Status" "0,1"
|
|
bitfld.long 0x0 13. "CRCERR,CRC Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "SFERR,Client Frame Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 11. "CMP,Comparison Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Status (Client mode only) (cleared on read)" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty (cleared by writing MCSPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising (cleared on read)" "0,1"
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty (cleared by writing MCSPI_TCR or MCSPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full (cleared by writing MCSPI_RCR or MCSPI_RNCR)" "0,1"
|
|
bitfld.long 0x0 5. "ENDTX,End of TX Buffer (cleared by writing MCSPI_TCR or MCSPI_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of RX Buffer (cleared by writing MCSPI_RCR or MCSPI_RNCR)" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing MCSPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading MCSPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CRCERR,CRC Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,MCSPI Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "RXFPTEF,RXFPTEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "TXFPTEF,TXFPTEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "RXFTHF,RXFTHF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "RXFFF,RXFFF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "RXFEF,RXFEF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "TXFTHF,TXFTHF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "TXFFF,TXFFF Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "TXFEF,TXFEF Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CRCERR,CRC Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "CMP,Comparison Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "UNDES,Underrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "NSSR,NSS Rising Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "MODF,Mode Fault Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "TDRE,MCSPI Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "RXFPTEF,RXFPTEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "TXFPTEF,TXFPTEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "RXFTHF,RXFTHF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "RXFFF,RXFFF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "RXFEF,RXFEF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "TXFTHF,TXFTHF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TXFFF,TXFFF Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "TXFEF,TXFEF Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CRCERR,CRC Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "CMP,Comparison Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "UNDES,Underrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "NSSR,NSS Rising Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "MODF,Mode Fault Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "TDRE,MCSPI Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "CSR[$1],Chip Select Register (CS_number = 0)"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before SPCK"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SCBR,Serial Clock Bit Rate"
|
|
hexmask.long.byte 0x0 4.--7. 1. "BITS,Bits Per Transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "CSAAT,Chip Select Active After Transfer" "0,1"
|
|
bitfld.long 0x0 2. "CSNAAT,Chip Select Not Active After Transfer (ignored if CSAAT = 1)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "NCPHA,Clock Phase" "0,1"
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
repeat.end
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "FMR,FIFO Mode Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "RXFTHRES,Receive FIFO Threshold"
|
|
hexmask.long.byte 0x0 16.--21. 1. "TXFTHRES,Transmit FIFO Threshold"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "RXRDYM,Receive Data Register Full Mode" "0: RDRF will be at level '1' when at least one..,1: RDRF will be at level '1' when at least two..,2: RDRF will be at level '1' when at least four..,?"
|
|
bitfld.long 0x0 0.--1. "TXRDYM,Transmit Data Register Empty Mode" "0: TDRE will be at level '1' when at least one data..,1: TDRE will be at level '1' when at least two data..,?,?"
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x0 "FLR,FIFO Level Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "RXFL,Receive FIFO Level"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TXFL,Transmit FIFO Level"
|
|
group.long 0x48++0xB
|
|
line.long 0x0 "CMPR,Comparison Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "VAL2,Second Comparison Value for Received Character"
|
|
hexmask.long.word 0x0 0.--15. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x4 "CRCR,CRC Register"
|
|
bitfld.long 0x4 27. "DHRX,Disable Header Receiving" "0,1"
|
|
bitfld.long 0x4 26. "DCRX,Disable CRC Receiving" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "FHE,Frame Header Excluded" "0,1"
|
|
bitfld.long 0x4 24. "CRM,Continuous Read Mode" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "FRHL,Frame Header Length"
|
|
bitfld.long 0x4 16. "CRCS,CRC Size" "0: CRC size is 16 bits.,1: CRC size is 32 bits."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "FRL,Frame Length"
|
|
line.long 0x8 "TPMR,Two-Pin Mode Register"
|
|
bitfld.long 0x8 2.--3. "OSR,OverSampling Rate" "0,1,2,3"
|
|
bitfld.long 0x8 1. "MIL,Multiple Input Lines" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "CSM,Chip Select Mode" "0,1"
|
|
rgroup.long 0x54++0x3
|
|
line.long 0x0 "TPHR,Two-Pin Header Register"
|
|
bitfld.long 0x0 5.--6. "OSR,OverSampling Rate" "0,1,2,3"
|
|
bitfld.long 0x0 3.--4. "GAIN,Gain" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 2. "BOOST,Current Boost" "0,1"
|
|
bitfld.long 0x0 0.--1. "CNT,Frame Counter" "0,1,2,3"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "MEM2MEM (Memory to Memory)"
|
|
base ad:0x0
|
|
tree "MEM2MEM0"
|
|
base ad:0x40034000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "THR,Transfer Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THDATA,Transfer Holding Data"
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 0.--1. "TSIZE,Transfer Size" "0: The buffer size is defined in bytes.,1: The buffer size is defined in half-words (16-bit).,2: The buffer size is defined in words (32-bit).,?"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXEND,End of Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RXEND,End of Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RXEND,End of Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "RXBUFF,Buffer Full" "0,1"
|
|
bitfld.long 0x4 0. "RXEND,End of Transfer" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree "MEM2MEM1"
|
|
base ad:0x48004000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "THR,Transfer Holding Register"
|
|
hexmask.long 0x0 0.--31. 1. "THDATA,Transfer Holding Data"
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 0.--1. "TSIZE,Transfer Size" "0: The buffer size is defined in bytes.,1: The buffer size is defined in half-words (16-bit).,2: The buffer size is defined in words (32-bit).,?"
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "RXBUFF,Buffer Full Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXEND,End of Transfer Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "RXBUFF,Buffer Full Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RXEND,End of Transfer Interrupt Disable" "0,1"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "RXBUFF,Buffer Full Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RXEND,End of Transfer Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "RXBUFF,Buffer Full" "0,1"
|
|
bitfld.long 0x4 0. "RXEND,End of Transfer" "0,1"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0xE000ED90
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TYPE,MPU Type Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "IREGION,Number of Instruction Regions"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DREGION,Number of Data Regions"
|
|
bitfld.long 0x0 0. "SEPARATE,Separate instruction and Data Memory MapsRegions" "0,1"
|
|
group.long 0x4++0x27
|
|
line.long 0x0 "CTRL,MPU Control Register"
|
|
bitfld.long 0x0 2. "PRIVDEFENA,Enables privileged software access to default memory map" "0,1"
|
|
bitfld.long 0x0 1. "HFNMIENA,Enable Hard Fault and NMI handlers" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,MPU Enable" "0,1"
|
|
line.long 0x4 "RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REGION,Region referenced by RBAR and RASR"
|
|
line.long 0x8 "RBAR,MPU Region Base Address Register"
|
|
hexmask.long 0x8 5.--31. 1. "ADDR,Region base address"
|
|
bitfld.long 0x8 4. "VALID,Region number valid" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "REGION,Region number"
|
|
line.long 0xC "RASR,MPU Region Attribute and Size Register"
|
|
bitfld.long 0xC 28. "XN,Execute Never Attribute" "0,1"
|
|
bitfld.long 0xC 24.--26. "AP,Access Permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 19.--21. "TEX,TEX bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 18. "S,Shareable bit" "0,1"
|
|
bitfld.long 0xC 17. "C,Cacheable bit" "0,1"
|
|
bitfld.long 0xC 16. "B,Bufferable bit" "0,1"
|
|
hexmask.long.byte 0xC 8.--15. 1. "SRD,Sub-region disable"
|
|
bitfld.long 0xC 1. "SIZE,Region Size" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "ENABLE,Region Enable" "0,1"
|
|
line.long 0x10 "RBAR_A1,MPU Alias 1 Region Base Address Register"
|
|
hexmask.long 0x10 5.--31. 1. "ADDR,Region base address"
|
|
bitfld.long 0x10 4. "VALID,Region number valid" "0,1"
|
|
hexmask.long.byte 0x10 0.--3. 1. "REGION,Region number"
|
|
line.long 0x14 "RASR_A1,MPU Alias 1 Region Attribute and Size Register"
|
|
bitfld.long 0x14 28. "XN,Execute Never Attribute" "0,1"
|
|
bitfld.long 0x14 24.--26. "AP,Access Permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 19.--21. "TEX,TEX bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 18. "S,Shareable bit" "0,1"
|
|
bitfld.long 0x14 17. "C,Cacheable bit" "0,1"
|
|
bitfld.long 0x14 16. "B,Bufferable bit" "0,1"
|
|
hexmask.long.byte 0x14 8.--15. 1. "SRD,Sub-region disable"
|
|
bitfld.long 0x14 1. "SIZE,Region Size" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "ENABLE,Region Enable" "0,1"
|
|
line.long 0x18 "RBAR_A2,MPU Alias 2 Region Base Address Register"
|
|
hexmask.long 0x18 5.--31. 1. "ADDR,Region base address"
|
|
bitfld.long 0x18 4. "VALID,Region number valid" "0,1"
|
|
hexmask.long.byte 0x18 0.--3. 1. "REGION,Region number"
|
|
line.long 0x1C "RASR_A2,MPU Alias 2 Region Attribute and Size Register"
|
|
bitfld.long 0x1C 28. "XN,Execute Never Attribute" "0,1"
|
|
bitfld.long 0x1C 24.--26. "AP,Access Permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 19.--21. "TEX,TEX bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x1C 18. "S,Shareable bit" "0,1"
|
|
bitfld.long 0x1C 17. "C,Cacheable bit" "0,1"
|
|
bitfld.long 0x1C 16. "B,Bufferable bit" "0,1"
|
|
hexmask.long.byte 0x1C 8.--15. 1. "SRD,Sub-region disable"
|
|
bitfld.long 0x1C 1. "SIZE,Region Size" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0. "ENABLE,Region Enable" "0,1"
|
|
line.long 0x20 "RBAR_A3,MPU Alias 3 Region Base Address Register"
|
|
hexmask.long 0x20 5.--31. 1. "ADDR,Region base address"
|
|
bitfld.long 0x20 4. "VALID,Region number valid" "0,1"
|
|
hexmask.long.byte 0x20 0.--3. 1. "REGION,Region number"
|
|
line.long 0x24 "RASR_A3,MPU Alias 3 Region Attribute and Size Register"
|
|
bitfld.long 0x24 28. "XN,Execute Never Attribute" "0,1"
|
|
bitfld.long 0x24 24.--26. "AP,Access Permission" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 19.--21. "TEX,TEX bit" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x24 18. "S,Shareable bit" "0,1"
|
|
bitfld.long 0x24 17. "C,Cacheable bit" "0,1"
|
|
bitfld.long 0x24 16. "B,Bufferable bit" "0,1"
|
|
hexmask.long.byte 0x24 8.--15. 1. "SRD,Sub-region disable"
|
|
bitfld.long 0x24 1. "SIZE,Region Size" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "ENABLE,Region Enable" "0,1"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "ISER[$1],Interrupt Set Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt set enable bits"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "ICER[$1],Interrupt Clear Enable Register"
|
|
hexmask.long 0x0 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "ISPR[$1],Interrupt Set Pending Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt set-pending bits"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x180)++0x3
|
|
line.long 0x0 "ICPR[$1],Interrupt Clear Pending Register"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "IABR[$1],Interrupt Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt active bits"
|
|
repeat.end
|
|
repeat 35. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x300)++0x0
|
|
line.byte 0x0 "IP[$1],Interrupt Priority Register n"
|
|
bitfld.byte 0x0 0.--2. "PRI0,Priority of interrupt n" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
wgroup.long 0xE00++0x3
|
|
line.long 0x0 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID to trigger"
|
|
tree.end
|
|
tree "PIO (Parallel Input/Output Controller)"
|
|
base ad:0x0
|
|
tree "PIO0"
|
|
base ad:0x40048000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40048000 ad:0x40048040 ad:0x40048080)
|
|
tree "PIO_GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "MSKR,PIO Mask Register"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
line.long 0x4 "CFGR,PIO Configuration Register"
|
|
bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
newline
|
|
bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
|
|
bitfld.long 0x4 16.--17. "SLEWRATE,Slew Rate" "0: Fast slew rate,1: Medium-fast slew rate,2: Medium slew rate,3: Slow slew rate"
|
|
newline
|
|
bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
|
|
bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
|
|
newline
|
|
bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0: The glitch filter is able to filter glitches..,1: The debouncing filter is able to filter pulses.."
|
|
bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
|
|
newline
|
|
bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
|
|
bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
|
|
newline
|
|
bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
|
|
bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,?,?,?"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "PDSR,PIO Pin Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
|
|
line.long 0x4 "LOCKSR,PIO Lock Status Register"
|
|
bitfld.long 0x4 31. "P31,Lock Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Lock Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Lock Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Lock Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Lock Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Lock Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Lock Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Lock Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Lock Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Lock Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Lock Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Lock Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Lock Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Lock Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Lock Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Lock Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Lock Status" "0,1"
|
|
wgroup.long ($2+0x10)++0x7
|
|
line.long 0x0 "SODR,PIO Set Output Data Register"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "CODR,PIO Clear Output Data Register"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "ODSR,PIO Output Data Status Register"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "IER,PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,PIO Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "IMR,PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "IOFR,PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40048000
|
|
group.long 0x5E0++0x3
|
|
line.long 0x0 "WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x5E4++0x3
|
|
line.long 0x0 "WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40049000 ad:0x40049040 ad:0x40049080)
|
|
tree "PIO_P[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
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line.long 0x0 "P_MSKR,PIO Privilege Mask Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
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bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
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bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
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bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
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bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
line.long 0x4 "P_CFGR,PIO Privilege Configuration Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
newline
|
|
bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
|
|
bitfld.long 0x4 16.--17. "SLEWRATE,Slew Rate" "0: Slow slew rate,1: Medium-fast slew rate,2: Medium slew rate,3: Slow slew rate"
|
|
newline
|
|
bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
|
|
bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
|
|
newline
|
|
bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0,1"
|
|
bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
|
|
newline
|
|
bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
|
|
bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
|
|
newline
|
|
bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
|
|
bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,?,?,?"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "P_PDSR,PIO Privilege Pin Data Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
|
|
line.long 0x4 "P_LOCKSR,PIO Privilege Lock Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Lock Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Lock Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Lock Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Lock Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Lock Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Lock Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Lock Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Lock Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Lock Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Lock Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Lock Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Lock Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Lock Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Lock Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Lock Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Lock Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Lock Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Lock Status" "0,1"
|
|
wgroup.long ($2+0x10)++0x7
|
|
line.long 0x0 "P_SODR,PIO Privilege Set Output Data Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
|
|
line.long 0x4 "P_CODR,PIO Privilege Clear Output Data Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "P_ODSR,PIO Privilege Output Data Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "P_IER,PIO Privilege Interrupt Enable Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "P_IDR,PIO Privilege Interrupt Disable Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "P_IMR,PIO Privilege Interrupt Mask Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "P_ISR,PIO Privilege Interrupt Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x30)++0x7
|
|
line.long 0x0 "P_SIO_UAR,PIO Privilege Set I/O User Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set I/O in User-Access mode" "0,1"
|
|
line.long 0x4 "P_SIO_PAR,PIO Privilege Set I/O Privilege Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 30. "P30,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 28. "P28,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 26. "P26,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 24. "P24,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 22. "P22,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 20. "P20,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 18. "P18,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 16. "P16,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 14. "P14,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 12. "P12,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 10. "P10,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 8. "P8,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 6. "P6,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 4. "P4,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 2. "P2,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 0. "P0,Set I/O in Privileged-Access mode" "0,1"
|
|
rgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "P_IOSSR,PIO Privilege I/O Security Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 30. "P30,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 29. "P29,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 28. "P28,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 27. "P27,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 26. "P26,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 25. "P25,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 24. "P24,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 23. "P23,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 22. "P22,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 21. "P21,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 20. "P20,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 19. "P19,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 18. "P18,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 17. "P17,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 16. "P16,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 15. "P15,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 14. "P14,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 13. "P13,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 12. "P12,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 11. "P11,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 10. "P10,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 9. "P9,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 8. "P8,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 7. "P7,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 6. "P6,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 5. "P5,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 4. "P4,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 3. "P3,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 2. "P2,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 1. "P1,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 0. "P0,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "P_IOFR,PIO Privilege I/O Freeze Configuration Register (p_iogroup = 0)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40048000
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "P_SCDR,PIO Privilege Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x15E0++0x3
|
|
line.long 0x0 "P_WPMR,PIO Privilege Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x15E4++0x3
|
|
line.long 0x0 "P_WPSR,PIO Privilege Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree "PIO1"
|
|
base ad:0x4800C000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x4800C000 ad:0x4800C040 ad:0x4800C080)
|
|
tree "PIO_GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "MSKR,PIO Mask Register"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
|
|
newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx..,1: Writing the PIO_CFGRx PIO_ODSRx or PIO_IOFRx.."
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line.long 0x4 "CFGR,PIO Configuration Register"
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bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
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bitfld.long 0x4 16.--17. "SLEWRATE,Slew Rate" "0: Fast slew rate,1: Medium-fast slew rate,2: Medium slew rate,3: Slow slew rate"
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bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
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bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
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bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0: The glitch filter is able to filter glitches..,1: The debouncing filter is able to filter pulses.."
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bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
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bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
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bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
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bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
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bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,?,?,?"
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rgroup.long ($2+0x8)++0x7
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line.long 0x0 "PDSR,PIO Pin Data Status Register"
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bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
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bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
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bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
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bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
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bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
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bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
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bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
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bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
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bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
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bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
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bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
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bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
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bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
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bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
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bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
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bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
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bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
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bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
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bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
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bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
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bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
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bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
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bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
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bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
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bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
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bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
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bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
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bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
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bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
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bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
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bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
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bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
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line.long 0x4 "LOCKSR,PIO Lock Status Register"
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bitfld.long 0x4 31. "P31,Lock Status" "0,1"
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bitfld.long 0x4 30. "P30,Lock Status" "0,1"
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bitfld.long 0x4 29. "P29,Lock Status" "0,1"
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bitfld.long 0x4 28. "P28,Lock Status" "0,1"
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bitfld.long 0x4 27. "P27,Lock Status" "0,1"
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bitfld.long 0x4 26. "P26,Lock Status" "0,1"
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bitfld.long 0x4 25. "P25,Lock Status" "0,1"
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bitfld.long 0x4 24. "P24,Lock Status" "0,1"
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bitfld.long 0x4 23. "P23,Lock Status" "0,1"
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bitfld.long 0x4 22. "P22,Lock Status" "0,1"
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bitfld.long 0x4 21. "P21,Lock Status" "0,1"
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bitfld.long 0x4 20. "P20,Lock Status" "0,1"
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bitfld.long 0x4 19. "P19,Lock Status" "0,1"
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bitfld.long 0x4 18. "P18,Lock Status" "0,1"
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bitfld.long 0x4 17. "P17,Lock Status" "0,1"
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bitfld.long 0x4 16. "P16,Lock Status" "0,1"
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bitfld.long 0x4 15. "P15,Lock Status" "0,1"
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bitfld.long 0x4 14. "P14,Lock Status" "0,1"
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bitfld.long 0x4 13. "P13,Lock Status" "0,1"
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bitfld.long 0x4 12. "P12,Lock Status" "0,1"
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bitfld.long 0x4 11. "P11,Lock Status" "0,1"
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bitfld.long 0x4 10. "P10,Lock Status" "0,1"
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bitfld.long 0x4 9. "P9,Lock Status" "0,1"
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bitfld.long 0x4 8. "P8,Lock Status" "0,1"
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bitfld.long 0x4 7. "P7,Lock Status" "0,1"
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bitfld.long 0x4 6. "P6,Lock Status" "0,1"
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bitfld.long 0x4 5. "P5,Lock Status" "0,1"
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bitfld.long 0x4 4. "P4,Lock Status" "0,1"
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bitfld.long 0x4 3. "P3,Lock Status" "0,1"
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bitfld.long 0x4 2. "P2,Lock Status" "0,1"
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bitfld.long 0x4 1. "P1,Lock Status" "0,1"
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bitfld.long 0x4 0. "P0,Lock Status" "0,1"
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wgroup.long ($2+0x10)++0x7
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line.long 0x0 "SODR,PIO Set Output Data Register"
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bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
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bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
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bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
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bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
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bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
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bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
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bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
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bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
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bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
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bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
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bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
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bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
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bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
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bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
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bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
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bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
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bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
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bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
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bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
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bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
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bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
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bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
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bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
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bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
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line.long 0x4 "CODR,PIO Clear Output Data Register"
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bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
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bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
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bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
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bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
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bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
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bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
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bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
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bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
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bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
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bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
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bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
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bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
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bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
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bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
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bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
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bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
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newline
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bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
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bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
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group.long ($2+0x18)++0x3
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line.long 0x0 "ODSR,PIO Output Data Status Register"
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bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
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bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
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newline
|
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bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
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bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
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newline
|
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bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
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bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
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bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
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bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
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newline
|
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bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
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bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
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bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
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bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
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|
newline
|
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bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
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|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
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newline
|
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bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
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bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
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bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
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|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
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|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "IER,PIO Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,PIO Interrupt Disable Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "IMR,PIO Interrupt Mask Register"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,PIO Interrupt Status Register"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "IOFR,PIO I/O Freeze Configuration Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4800C000
|
|
group.long 0x5E0++0x3
|
|
line.long 0x0 "WPMR,PIO Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x5E4++0x3
|
|
line.long 0x0 "WPSR,PIO Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x4800D000 ad:0x4800D040 ad:0x4800D080)
|
|
tree "PIO_P[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "P_MSKR,PIO Privilege Mask Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "MSK31,PIO Line 31 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 30. "MSK30,PIO Line 30 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 29. "MSK29,PIO Line 29 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 28. "MSK28,PIO Line 28 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 27. "MSK27,PIO Line 27 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 26. "MSK26,PIO Line 26 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 25. "MSK25,PIO Line 25 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 24. "MSK24,PIO Line 24 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 23. "MSK23,PIO Line 23 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 22. "MSK22,PIO Line 22 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 21. "MSK21,PIO Line 21 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 20. "MSK20,PIO Line 20 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 19. "MSK19,PIO Line 19 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 18. "MSK18,PIO Line 18 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 17. "MSK17,PIO Line 17 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 16. "MSK16,PIO Line 16 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 15. "MSK15,PIO Line 15 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 14. "MSK14,PIO Line 14 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 13. "MSK13,PIO Line 13 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 12. "MSK12,PIO Line 12 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 11. "MSK11,PIO Line 11 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 10. "MSK10,PIO Line 10 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 9. "MSK9,PIO Line 9 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 8. "MSK8,PIO Line 8 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 7. "MSK7,PIO Line 7 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 6. "MSK6,PIO Line 6 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 5. "MSK5,PIO Line 5 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 4. "MSK4,PIO Line 4 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
newline
|
|
bitfld.long 0x0 3. "MSK3,PIO Line 3 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
bitfld.long 0x0 2. "MSK2,PIO Line 2 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
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newline
|
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bitfld.long 0x0 1. "MSK1,PIO Line 1 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
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|
bitfld.long 0x0 0. "MSK0,PIO Line 0 Mask" "0: Writing the PIO_P_CFGRx PIO_P_ODSRx or..,1: Writing the PIO_P_CFGRx PIO_P_ODSRx or.."
|
|
line.long 0x4 "P_CFGR,PIO Privilege Configuration Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 30. "ICFS,Interrupt Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
|
|
bitfld.long 0x4 29. "PCFS,Physical Configuration Freeze Status (read-only)" "0: The fields are not frozen and can be written for..,1: The fields are frozen and cannot be written for.."
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newline
|
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bitfld.long 0x4 24.--26. "EVTSEL,Event Selection" "0: Event detection on input falling edge,1: Event detection on input rising edge,2: Event detection on input both edge,3: Event detection on low level input,4: Event detection on high level input,?,?,?"
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|
bitfld.long 0x4 16.--17. "SLEWRATE,Slew Rate" "0: Slow slew rate,1: Medium-fast slew rate,2: Medium slew rate,3: Slow slew rate"
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newline
|
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bitfld.long 0x4 15. "SCHMITT,Schmitt Trigger" "0: Schmitt trigger is enabled for the selected I/O..,1: Schmitt trigger is disabled for the selected I/O.."
|
|
bitfld.long 0x4 14. "OPD,Open-Drain" "0: The open-drain is disabled for the selected I/O..,1: The open-drain is enabled for the selected I/O.."
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|
newline
|
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bitfld.long 0x4 13. "IFSCEN,Input Filter Slow Clock Enable" "0,1"
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bitfld.long 0x4 12. "IFEN,Input Filter Enable" "0: The input filter is disabled for the selected..,1: The input filter is enabled for the selected I/O.."
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newline
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bitfld.long 0x4 10. "PDEN,Pull-Down Enable" "0: Pull-Down is disabled for the selected I/O lines.,1: Pull-Down is enabled for the selected I/O lines.."
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bitfld.long 0x4 9. "PUEN,Pull-Up Enable" "0: Pull-Up is disabled for the selected I/O lines.,1: Pull-Up is enabled for the selected I/O lines."
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newline
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bitfld.long 0x4 8. "DIR,Direction" "0: The selected I/O lines are pure inputs.,1: The selected I/O lines are enabled in output."
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bitfld.long 0x4 0.--2. "FUNC,I/O Line Function" "0: Select the PIO mode for the selected I/O lines.,1: Select the peripheral A for the selected I/O..,2: Select the peripheral B for the selected I/O..,3: Select the peripheral C for the selected I/O..,4: Select the peripheral D for the selected I/O..,?,?,?"
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rgroup.long ($2+0x8)++0x7
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line.long 0x0 "P_PDSR,PIO Privilege Pin Data Status Register (p_iogroup = 0)"
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bitfld.long 0x0 31. "P31,Input Data Status" "0,1"
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bitfld.long 0x0 30. "P30,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 29. "P29,Input Data Status" "0,1"
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bitfld.long 0x0 28. "P28,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 27. "P27,Input Data Status" "0,1"
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bitfld.long 0x0 26. "P26,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 25. "P25,Input Data Status" "0,1"
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bitfld.long 0x0 24. "P24,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 23. "P23,Input Data Status" "0,1"
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bitfld.long 0x0 22. "P22,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 21. "P21,Input Data Status" "0,1"
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bitfld.long 0x0 20. "P20,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 19. "P19,Input Data Status" "0,1"
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bitfld.long 0x0 18. "P18,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 17. "P17,Input Data Status" "0,1"
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bitfld.long 0x0 16. "P16,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 15. "P15,Input Data Status" "0,1"
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bitfld.long 0x0 14. "P14,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 13. "P13,Input Data Status" "0,1"
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bitfld.long 0x0 12. "P12,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 11. "P11,Input Data Status" "0,1"
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bitfld.long 0x0 10. "P10,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 9. "P9,Input Data Status" "0,1"
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bitfld.long 0x0 8. "P8,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 7. "P7,Input Data Status" "0,1"
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bitfld.long 0x0 6. "P6,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 5. "P5,Input Data Status" "0,1"
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bitfld.long 0x0 4. "P4,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 3. "P3,Input Data Status" "0,1"
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bitfld.long 0x0 2. "P2,Input Data Status" "0,1"
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newline
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bitfld.long 0x0 1. "P1,Input Data Status" "0,1"
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bitfld.long 0x0 0. "P0,Input Data Status" "0,1"
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line.long 0x4 "P_LOCKSR,PIO Privilege Lock Status Register (p_iogroup = 0)"
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bitfld.long 0x4 31. "P31,Lock Status" "0,1"
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bitfld.long 0x4 30. "P30,Lock Status" "0,1"
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newline
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bitfld.long 0x4 29. "P29,Lock Status" "0,1"
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bitfld.long 0x4 28. "P28,Lock Status" "0,1"
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newline
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bitfld.long 0x4 27. "P27,Lock Status" "0,1"
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bitfld.long 0x4 26. "P26,Lock Status" "0,1"
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newline
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bitfld.long 0x4 25. "P25,Lock Status" "0,1"
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bitfld.long 0x4 24. "P24,Lock Status" "0,1"
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newline
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bitfld.long 0x4 23. "P23,Lock Status" "0,1"
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bitfld.long 0x4 22. "P22,Lock Status" "0,1"
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newline
|
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bitfld.long 0x4 21. "P21,Lock Status" "0,1"
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bitfld.long 0x4 20. "P20,Lock Status" "0,1"
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newline
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bitfld.long 0x4 19. "P19,Lock Status" "0,1"
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bitfld.long 0x4 18. "P18,Lock Status" "0,1"
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newline
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bitfld.long 0x4 17. "P17,Lock Status" "0,1"
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bitfld.long 0x4 16. "P16,Lock Status" "0,1"
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newline
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bitfld.long 0x4 15. "P15,Lock Status" "0,1"
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bitfld.long 0x4 14. "P14,Lock Status" "0,1"
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newline
|
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bitfld.long 0x4 13. "P13,Lock Status" "0,1"
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bitfld.long 0x4 12. "P12,Lock Status" "0,1"
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newline
|
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bitfld.long 0x4 11. "P11,Lock Status" "0,1"
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bitfld.long 0x4 10. "P10,Lock Status" "0,1"
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newline
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bitfld.long 0x4 9. "P9,Lock Status" "0,1"
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bitfld.long 0x4 8. "P8,Lock Status" "0,1"
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newline
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bitfld.long 0x4 7. "P7,Lock Status" "0,1"
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bitfld.long 0x4 6. "P6,Lock Status" "0,1"
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newline
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bitfld.long 0x4 5. "P5,Lock Status" "0,1"
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bitfld.long 0x4 4. "P4,Lock Status" "0,1"
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newline
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bitfld.long 0x4 3. "P3,Lock Status" "0,1"
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bitfld.long 0x4 2. "P2,Lock Status" "0,1"
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newline
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bitfld.long 0x4 1. "P1,Lock Status" "0,1"
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bitfld.long 0x4 0. "P0,Lock Status" "0,1"
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wgroup.long ($2+0x10)++0x7
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line.long 0x0 "P_SODR,PIO Privilege Set Output Data Register (p_iogroup = 0)"
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bitfld.long 0x0 31. "P31,Set Output Data" "0,1"
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bitfld.long 0x0 30. "P30,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 29. "P29,Set Output Data" "0,1"
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bitfld.long 0x0 28. "P28,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 27. "P27,Set Output Data" "0,1"
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bitfld.long 0x0 26. "P26,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 25. "P25,Set Output Data" "0,1"
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bitfld.long 0x0 24. "P24,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 23. "P23,Set Output Data" "0,1"
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bitfld.long 0x0 22. "P22,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 21. "P21,Set Output Data" "0,1"
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bitfld.long 0x0 20. "P20,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 19. "P19,Set Output Data" "0,1"
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bitfld.long 0x0 18. "P18,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 17. "P17,Set Output Data" "0,1"
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bitfld.long 0x0 16. "P16,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 15. "P15,Set Output Data" "0,1"
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bitfld.long 0x0 14. "P14,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 13. "P13,Set Output Data" "0,1"
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bitfld.long 0x0 12. "P12,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 11. "P11,Set Output Data" "0,1"
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bitfld.long 0x0 10. "P10,Set Output Data" "0,1"
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newline
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bitfld.long 0x0 9. "P9,Set Output Data" "0,1"
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bitfld.long 0x0 8. "P8,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 7. "P7,Set Output Data" "0,1"
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bitfld.long 0x0 6. "P6,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 5. "P5,Set Output Data" "0,1"
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bitfld.long 0x0 4. "P4,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 3. "P3,Set Output Data" "0,1"
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bitfld.long 0x0 2. "P2,Set Output Data" "0,1"
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newline
|
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bitfld.long 0x0 1. "P1,Set Output Data" "0,1"
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bitfld.long 0x0 0. "P0,Set Output Data" "0,1"
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line.long 0x4 "P_CODR,PIO Privilege Clear Output Data Register (p_iogroup = 0)"
|
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bitfld.long 0x4 31. "P31,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 30. "P30,Clear Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x4 29. "P29,Clear Output Data" "0,1"
|
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bitfld.long 0x4 28. "P28,Clear Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x4 27. "P27,Clear Output Data" "0,1"
|
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bitfld.long 0x4 26. "P26,Clear Output Data" "0,1"
|
|
newline
|
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bitfld.long 0x4 25. "P25,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 24. "P24,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 22. "P22,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 20. "P20,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 18. "P18,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 16. "P16,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 14. "P14,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 12. "P12,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 10. "P10,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 8. "P8,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 6. "P6,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 4. "P4,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 2. "P2,Clear Output Data" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Clear Output Data" "0,1"
|
|
bitfld.long 0x4 0. "P0,Clear Output Data" "0,1"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "P_ODSR,PIO Privilege Output Data Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Output Data Status" "0,1"
|
|
bitfld.long 0x0 30. "P30,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Output Data Status" "0,1"
|
|
bitfld.long 0x0 28. "P28,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Output Data Status" "0,1"
|
|
bitfld.long 0x0 26. "P26,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Output Data Status" "0,1"
|
|
bitfld.long 0x0 24. "P24,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Output Data Status" "0,1"
|
|
bitfld.long 0x0 22. "P22,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Output Data Status" "0,1"
|
|
bitfld.long 0x0 20. "P20,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Output Data Status" "0,1"
|
|
bitfld.long 0x0 18. "P18,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Output Data Status" "0,1"
|
|
bitfld.long 0x0 16. "P16,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Output Data Status" "0,1"
|
|
bitfld.long 0x0 14. "P14,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Output Data Status" "0,1"
|
|
bitfld.long 0x0 12. "P12,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Output Data Status" "0,1"
|
|
bitfld.long 0x0 10. "P10,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Output Data Status" "0,1"
|
|
bitfld.long 0x0 8. "P8,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Output Data Status" "0,1"
|
|
bitfld.long 0x0 6. "P6,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Output Data Status" "0,1"
|
|
bitfld.long 0x0 4. "P4,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Output Data Status" "0,1"
|
|
bitfld.long 0x0 2. "P2,Output Data Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Output Data Status" "0,1"
|
|
bitfld.long 0x0 0. "P0,Output Data Status" "0,1"
|
|
wgroup.long ($2+0x20)++0x7
|
|
line.long 0x0 "P_IER,PIO Privilege Interrupt Enable Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Enable" "0,1"
|
|
line.long 0x4 "P_IDR,PIO Privilege Interrupt Disable Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Disable" "0,1"
|
|
rgroup.long ($2+0x28)++0x7
|
|
line.long 0x0 "P_IMR,PIO Privilege Interrupt Mask Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 30. "P30,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 28. "P28,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 26. "P26,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 24. "P24,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "P22,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "P20,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "P18,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "P16,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "P14,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "P12,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "P10,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "P8,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "P6,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "P4,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "P2,Input Change Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Input Change Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "P0,Input Change Interrupt Mask" "0,1"
|
|
line.long 0x4 "P_ISR,PIO Privilege Interrupt Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 30. "P30,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 28. "P28,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 26. "P26,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 24. "P24,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 22. "P22,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 20. "P20,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 18. "P18,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 16. "P16,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 14. "P14,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 12. "P12,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 10. "P10,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 8. "P8,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 6. "P6,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 4. "P4,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "P2,Input Change Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Input Change Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "P0,Input Change Interrupt Status" "0,1"
|
|
wgroup.long ($2+0x30)++0x7
|
|
line.long 0x0 "P_SIO_UAR,PIO Privilege Set I/O User Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 30. "P30,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "P29,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 28. "P28,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "P27,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 26. "P26,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "P25,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 24. "P24,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "P23,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 22. "P22,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "P21,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 20. "P20,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "P19,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 18. "P18,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "P17,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 16. "P16,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "P15,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 14. "P14,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "P13,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 12. "P12,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "P11,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 10. "P10,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "P9,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 8. "P8,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "P7,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 6. "P6,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "P5,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 4. "P4,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "P3,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 2. "P2,Set I/O in User-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "P1,Set I/O in User-Access mode" "0,1"
|
|
bitfld.long 0x0 0. "P0,Set I/O in User-Access mode" "0,1"
|
|
line.long 0x4 "P_SIO_PAR,PIO Privilege Set I/O Privilege Register (p_iogroup = 0)"
|
|
bitfld.long 0x4 31. "P31,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 30. "P30,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "P29,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 28. "P28,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "P27,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 26. "P26,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "P25,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 24. "P24,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "P23,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 22. "P22,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "P21,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 20. "P20,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "P19,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 18. "P18,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "P17,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 16. "P16,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "P15,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 14. "P14,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "P13,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 12. "P12,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "P11,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 10. "P10,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "P9,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 8. "P8,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "P7,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 6. "P6,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "P5,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 4. "P4,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "P3,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 2. "P2,Set I/O in Privileged-Access mode" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "P1,Set I/O in Privileged-Access mode" "0,1"
|
|
bitfld.long 0x4 0. "P0,Set I/O in Privileged-Access mode" "0,1"
|
|
rgroup.long ($2+0x38)++0x3
|
|
line.long 0x0 "P_IOSSR,PIO Privilege I/O Security Status Register (p_iogroup = 0)"
|
|
bitfld.long 0x0 31. "P31,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 30. "P30,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 29. "P29,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 28. "P28,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 27. "P27,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 26. "P26,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 25. "P25,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 24. "P24,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 23. "P23,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 22. "P22,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 21. "P21,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 20. "P20,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 19. "P19,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 18. "P18,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 17. "P17,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 16. "P16,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 15. "P15,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 14. "P14,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 13. "P13,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 12. "P12,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 11. "P11,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 10. "P10,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 9. "P9,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 8. "P8,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 7. "P7,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 6. "P6,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 5. "P5,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 4. "P4,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 3. "P3,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 2. "P2,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
newline
|
|
bitfld.long 0x0 1. "P1,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
bitfld.long 0x0 0. "P0,I/O Security Status" "0: The I/O line of the I/O group 0 is in..,1: The I/O line of the I/O group 0 is in.."
|
|
wgroup.long ($2+0x3C)++0x3
|
|
line.long 0x0 "P_IOFR,PIO Privilege I/O Freeze Configuration Register (p_iogroup = 0)"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "FRZKEY,Freeze Key"
|
|
bitfld.long 0x0 1. "FINT,Freeze Interrupt Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "FPHY,Freeze Physical Configuration" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4800C000
|
|
group.long 0x1500++0x3
|
|
line.long 0x0 "P_SCDR,PIO Privilege Slow Clock Divider Debouncing Register"
|
|
hexmask.long.word 0x0 0.--13. 1. "DIV,Slow Clock Divider Selection for Debouncing"
|
|
group.long 0x15E0++0x3
|
|
line.long 0x0 "P_WPMR,PIO Privilege Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x15E4++0x3
|
|
line.long 0x0 "P_WPSR,PIO Privilege Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "PMC (Power Management Controller)"
|
|
base ad:0x46800000
|
|
wgroup.long 0x0++0x7
|
|
line.long 0x0 "SCER,System Clock Enable Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CPKEY,Coprocessor Clocks Enable Key"
|
|
bitfld.long 0x0 17. "CPBMCK,Coprocessor Bus Master Clocks Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CPCK,Coprocessor (Second Processor) Clocks Enable" "0,1"
|
|
bitfld.long 0x0 11. "PCK3,Programmable Clock 3 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Enable" "0,1"
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Enable" "0,1"
|
|
line.long 0x4 "SCDR,System Clock Disable Register"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CPKEY,Coprocessor Clocks Enable Key"
|
|
bitfld.long 0x4 17. "CPBMCK,Coprocessor Bus Master Clocks Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "CPCK,Coprocessor (Second Processor) Clocks Disable" "0,1"
|
|
bitfld.long 0x4 11. "PCK3,Programmable Clock 3 Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "PCK2,Programmable Clock 2 Output Disable" "0,1"
|
|
bitfld.long 0x4 9. "PCK1,Programmable Clock 1 Output Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PCK0,Programmable Clock 0 Output Disable" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SCSR,System Clock Status Register"
|
|
bitfld.long 0x0 17. "CPBMCK,Coprocessor Bus Master Clocks Status" "0,1"
|
|
bitfld.long 0x0 16. "CPCK,Coprocessor (Second Processor) Clocks Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PCK3,Programmable Clock 3 Output Status" "0,1"
|
|
bitfld.long 0x0 10. "PCK2,Programmable Clock 2 Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PCK1,Programmable Clock 1 Output Status" "0,1"
|
|
bitfld.long 0x0 8. "PCK0,Programmable Clock 0 Output Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CPU_CLK1S,CPU_CLK Status for Core 1" "0,1"
|
|
bitfld.long 0x0 0. "CPU_CLK0S,CPU_CLK Status for Core 0" "0,1"
|
|
group.long 0xC++0x23
|
|
line.long 0x0 "PLL_CTRL0,PLL Control Register 0"
|
|
bitfld.long 0x0 31. "ENLOCK,Enable PLL Lock" "0,1"
|
|
bitfld.long 0x0 30. "ENPLLO1,Enable PLL Clock Output 1 (PLLA only)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ENPLLO0,Enable PLL Clock Output 0" "0,1"
|
|
bitfld.long 0x0 28. "ENPLL,Enable PLL" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PLLMS,PLL Multiplexer Select" "0,1"
|
|
hexmask.long.byte 0x0 12.--19. 1. "DIVPMC1,Divider for PMC output 1 (PLLA only)"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVPMC0,Divider for PMC output 0"
|
|
line.long 0x4 "PLL_CTRL1,PLL Control Register 1"
|
|
hexmask.long.word 0x4 0.--15. 1. "MUL,Multiplier Factor Value for PLLA B and C"
|
|
line.long 0x8 "PLL_CTRL2,PLL Control Register 2"
|
|
hexmask.long.tbyte 0x8 0.--21. 1. "FRACR,Fractional Loop Divider Setting"
|
|
line.long 0xC "PLL_SSR,PLL Spread Spectrum Register"
|
|
bitfld.long 0xC 28. "ENSPREAD,Spread Spectrum Enable" "0,1"
|
|
hexmask.long.byte 0xC 16.--23. 1. "NSTEP,Spread Spectrum Number of Step"
|
|
newline
|
|
hexmask.long.word 0xC 0.--15. 1. "STEP,Spread Spectrum Step Size"
|
|
line.long 0x10 "PLL_ACR,PLL Analog Control Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. "LOOP_FILTER,PLL Loop Filter Selection"
|
|
hexmask.long.byte 0x10 16.--23. 1. "LOCK_THR,PLL Lock Threshold Value Selection"
|
|
newline
|
|
hexmask.long.word 0x10 0.--11. 1. "CONTROL,PLL Control Value Selection"
|
|
line.long 0x14 "PLL_UPDT,PLL Update Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. "STUPTIM,Start-up Time"
|
|
bitfld.long 0x14 8. "UPDATE,PLL Setting Update (write-only)" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "ID,PLL ID"
|
|
line.long 0x18 "CKGR_MOR,Main Oscillator Register"
|
|
bitfld.long 0x18 27. "BMCKRST,Bad MCK0 Clock Reset Enable" "0,1"
|
|
bitfld.long 0x18 26. "XT32KFME,32.768 kHz Crystal Oscillator Frequency Monitoring Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x18 25. "CFDEN,Clock Failure Detector Enable" "0,1"
|
|
bitfld.long 0x18 24. "MOSCSEL,Main Clock Oscillator Selection" "0: The main RC oscillator is selected.,1: The main crystal oscillator is selected."
|
|
newline
|
|
hexmask.long.byte 0x18 16.--23. 1. "KEY,Write Access Password"
|
|
hexmask.long.byte 0x18 8.--15. 1. "MOSCXTST,Main Crystal Oscillator Start-up Time"
|
|
newline
|
|
bitfld.long 0x18 3. "MOSCRCEN,Main RC Oscillator Enable" "0,1"
|
|
bitfld.long 0x18 2. "WAITMODE,Wait Mode Command (write-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x18 1. "MOSCXTBY,12 to 48 MHz Crystal Oscillator Bypass" "0,1"
|
|
bitfld.long 0x18 0. "MOSCXTEN,Main Crystal Oscillator Enable" "0,1"
|
|
line.long 0x1C "CKGR_MCFR,Main Clock Frequency Register"
|
|
bitfld.long 0x1C 24. "CCSS,Counter Clock Source Selection" "0,1"
|
|
bitfld.long 0x1C 20. "RCMEAS,RC Oscillator Frequency Measure (write-only)" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 16. "MAINFRDY,Main Clock Frequency Measure Ready" "0,1"
|
|
hexmask.long.word 0x1C 0.--15. 1. "MAINF,Main Clock Frequency"
|
|
line.long 0x20 "CPU_CKR,CPU Clock Register"
|
|
bitfld.long 0x20 26. "RATIO_MCK0DIV2,MCK0 Clock Frequency Division for MCK0DIV2 Clock" "0,1"
|
|
bitfld.long 0x20 25. "RATIO_MCK1DIV,MCK1 Clock Frequency Division for MCK1DIV Clock" "0,1"
|
|
newline
|
|
bitfld.long 0x20 24. "RATIO_MCK0DIV,MCK0 Clock Frequency Division for MCK0DIV Clock" "0,1"
|
|
hexmask.long.byte 0x20 20.--23. 1. "CPPRES,Coprocessor MCK1 Prescaler"
|
|
newline
|
|
bitfld.long 0x20 16.--18. "CPCSS,Coprocessor MCK1 Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: MCK0 is selected,3: PLLACK1 is selected,4: PLLBCK is selected,5: PLLCCK is selected,?,?"
|
|
bitfld.long 0x20 4.--6. "PRES,Processor (CPU_CLK0) and Master Clock (MCK0) Prescaler" "0: Selected clock,1: Selected clock divided by 2,2: Selected clock divided by 4,3: Selected clock divided by 8,4: Selected clock divided by 16,5: Selected clock divided by 32,6: Selected clock divided by 64,7: Selected clock divided by 3"
|
|
newline
|
|
bitfld.long 0x20 0.--1. "CSS,Processor (CPU_CLK0) and Master Clock (MCK0) Source Selection" "0: MD_SLCK is selected,1: MAINCK is selected,2: PLLACK1 is selected,3: PLLBCK is selected"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "PCK[$1],Programmable Clock Register (chid = 0)"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRES,Programmable Clock Prescaler"
|
|
hexmask.long.byte 0x0 0.--4. 1. "CSS,Programmable Clock Source Selection"
|
|
repeat.end
|
|
wgroup.long 0x64++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 23. "MCKMON,Master Clock 0 Clock Monitor Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "CPMCKRDY,Coprocessor Master Clock Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock 0 Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 23. "MCKMON,Master Clock 0 Clock Monitor Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt DIsable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt DIsable" "0,1"
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt DIsable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt DIsable" "0,1"
|
|
bitfld.long 0x4 4. "CPMCKRDY,Coprocessor Master Clock Ready Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock 0 Ready Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Disable" "0,1"
|
|
rgroup.long 0x6C++0x7
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 25. "PLL_INT,PLL Interrupt Status" "0,1"
|
|
bitfld.long 0x0 24. "GCLKRDY,GCLK Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "MCKMON,Master Clock 0 Clock Monitor Error" "0,1"
|
|
bitfld.long 0x0 21. "XT32KERR,Slow Crystal Oscillator Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "FOS,Clock Failure Detector Fault Output Status" "0,1"
|
|
bitfld.long 0x0 19. "CFDS,Clock Failure Detector Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "CFDEV,Clock Failure Detector Event" "0,1"
|
|
bitfld.long 0x0 17. "MOSCRCS,Main RC Oscillator Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "MOSCSELS,Main Clock Source Oscillator Selection Status" "0,1"
|
|
bitfld.long 0x0 11. "PCKRDY3,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PCKRDY2,Programmable Clock Ready Status" "0,1"
|
|
bitfld.long 0x0 9. "PCKRDY1,Programmable Clock Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "PCKRDY0,Programmable Clock Ready Status" "0,1"
|
|
bitfld.long 0x0 7. "OSCSELS,Monitoring Domain Slow Clock Source Oscillator Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPMCKRDY,Coprocessor Master Clock Status" "0,1"
|
|
bitfld.long 0x0 3. "MCKRDY,Master Clock 0 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "MOSCXTS,Main Crystal Oscillator Status" "0,1"
|
|
line.long 0x4 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x4 23. "MCKMON,Master Clock 0 Monitor Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 21. "XT32KERR,32.768 kHz Crystal Oscillator Error Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 18. "CFDEV,Clock Failure Detector Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 17. "MOSCRCS,Main RC Status Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "MOSCSELS,Main Clock Source Oscillator Selection Status Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 11. "PCKRDY3,Programmable Clock Ready 3 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "PCKRDY2,Programmable Clock Ready 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 9. "PCKRDY1,Programmable Clock Ready 1 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "PCKRDY0,Programmable Clock Ready 0 Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 4. "CPMCKRDY,Coprocessor Master Clock Ready Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MCKRDY,Master Clock 0 Ready Interrupt Mask" "0,1"
|
|
bitfld.long 0x4 0. "MOSCXTS,Main Crystal Oscillator Status Interrupt Mask" "0,1"
|
|
group.long 0x74++0x7
|
|
line.long 0x0 "FSMR,Fast Start-up Mode Register"
|
|
bitfld.long 0x0 23. "FFLPM,Force Flash Low-power Mode" "0,1"
|
|
bitfld.long 0x0 21.--22. "FLPM,Flash Low-power Mode" "0: Flash is in Standby Mode when system enters Wait..,1: Flash is in Deep-powerdown mode when system..,2: Idle mode,?"
|
|
newline
|
|
bitfld.long 0x0 20. "LPM,Low Power Mode" "0,1"
|
|
bitfld.long 0x0 19. "SMAL,Supply Monitor Alarm Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "XTFA,32KHz Crystal Failure Alarm Enable" "0,1"
|
|
bitfld.long 0x0 17. "RTCAL,RTC Alarm Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RTTAL,RTT Alarm Enable" "0,1"
|
|
line.long 0x4 "WCR,Wake-up Control Register"
|
|
bitfld.long 0x4 24. "CMD,Command" "0,1"
|
|
bitfld.long 0x4 20. "WIEN1,Wake-up Input Enable 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "WIP,Wake-up Input Polarity" "0,1"
|
|
bitfld.long 0x4 16. "EN,Wake-up Input Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "WKPIONB,Wake-up Input Number"
|
|
wgroup.long 0x7C++0x3
|
|
line.long 0x0 "FOCR,Fault Output Clear Register"
|
|
bitfld.long 0x0 0. "FOCLR,Fault Output Clear" "0,1"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "CPFSMR,Coprocessor Fast Start-up Mode Register"
|
|
bitfld.long 0x0 19. "SMAL,Supply Monitor Alarm Enable" "0,1"
|
|
bitfld.long 0x0 18. "XTFA,32KHz Crystal Failure Alarm Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RTCAL,RTC Alarm Enable" "0,1"
|
|
bitfld.long 0x0 16. "RTTAL,RTT Alarm Enable" "0,1"
|
|
line.long 0x4 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x4 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x88++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x8C++0x7
|
|
line.long 0x0 "PCR,Peripheral Control Register"
|
|
bitfld.long 0x0 31. "CMD,Command" "0,1"
|
|
bitfld.long 0x0 29. "GCLKEN,Generic Clock Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "EN,Enable" "0,1"
|
|
hexmask.long.byte 0x0 20.--27. 1. "GCLKDIV,Generic Clock Division Ratio"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "MCKID,Master Clock Index (Read-only)"
|
|
hexmask.long.byte 0x0 8.--12. 1. "GCLKCSS,Generic Clock Source Selection"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
line.long 0x4 "OCR,Oscillator Calibration Register"
|
|
bitfld.long 0x4 23. "SEL12,Selection of Main RC Oscillator Calibration Bits" "0,1"
|
|
hexmask.long.byte 0x4 16.--22. 1. "CAL12,Main RC Oscillator Calibration Bits"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "SLPWK_AIPR,Partial Wake-up Activity In Progress Register"
|
|
bitfld.long 0x0 0. "AIP,Activity In Progress" "0,1"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "SLPWKCR,Partial Wake-up Control Register"
|
|
bitfld.long 0x0 28. "SLPWKSR,Partial Wake-up Sleep Register" "0,1"
|
|
bitfld.long 0x0 16. "ASR,Activity Status Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMD,Command" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "PID,Peripheral ID"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "MCKLIM,MCK0 Monitor Limits Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "MCK_HIGH_RES,MCK0 Monitoring High Reset Limit"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MCK_LOW_RES,MCK0 Monitoring Low RESET Limit"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "MCK_HIGH_IT,MCK0 Monitoring High IT Limit"
|
|
hexmask.long.byte 0x0 0.--7. 1. "MCK_LOW_IT,MCK0 Monitoring Low IT Limit"
|
|
rgroup.long 0xA4++0xF
|
|
line.long 0x0 "CSR0,Peripheral Clock Status Register 0"
|
|
bitfld.long 0x0 31. "PID31,Peripheral Clock 31 Status" "0,1"
|
|
bitfld.long 0x0 30. "PID30,Peripheral Clock 30 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "PID28,Peripheral Clock 28 Status" "0,1"
|
|
bitfld.long 0x0 25. "PID25,Peripheral Clock 25 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PID24,Peripheral Clock 24 Status" "0,1"
|
|
bitfld.long 0x0 23. "PID23,Peripheral Clock 23 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PID17,Peripheral Clock 17 Status" "0,1"
|
|
bitfld.long 0x0 16. "PID16,Peripheral Clock 16 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PID15,Peripheral Clock 15 Status" "0,1"
|
|
bitfld.long 0x0 14. "PID14,Peripheral Clock 14 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "PID13,Peripheral Clock 13 Status" "0,1"
|
|
bitfld.long 0x0 12. "PID12,Peripheral Clock 12 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "PID11,Peripheral Clock 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "PID10,Peripheral Clock 10 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "PID9,Peripheral Clock 9 Status" "0,1"
|
|
line.long 0x4 "CSR1,Peripheral Clock Status Register 1"
|
|
bitfld.long 0x4 27. "PID59,Peripheral Clock 59 Status" "0,1"
|
|
bitfld.long 0x4 25. "PID57,Peripheral Clock 57 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "PID55,Peripheral Clock 55 Status" "0,1"
|
|
bitfld.long 0x4 21. "PID53,Peripheral Clock 53 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "PID51,Peripheral Clock 51 Status" "0,1"
|
|
bitfld.long 0x4 17. "PID49,Peripheral Clock 49 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PID39,Peripheral Clock 39 Status" "0,1"
|
|
bitfld.long 0x4 6. "PID38,Peripheral Clock 38 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "PID37,Peripheral Clock 37 Status" "0,1"
|
|
bitfld.long 0x4 4. "PID36,Peripheral Clock 36 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "PID35,Peripheral Clock 35 Status" "0,1"
|
|
bitfld.long 0x4 2. "PID34,Peripheral Clock 34 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "PID33,Peripheral Clock 33 Status" "0,1"
|
|
bitfld.long 0x4 0. "PID32,Peripheral Clock 32 Status" "0,1"
|
|
line.long 0x8 "CSR2,Peripheral Clock Status Register 2"
|
|
bitfld.long 0x8 27. "PID91,Peripheral Clock 91 Status" "0,1"
|
|
bitfld.long 0x8 26. "PID90,Peripheral Clock 90 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "PID89,Peripheral Clock 89 Status" "0,1"
|
|
bitfld.long 0x8 24. "PID88,Peripheral Clock 88 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "PID87,Peripheral Clock 87 Status" "0,1"
|
|
bitfld.long 0x8 21. "PID85,Peripheral Clock 85 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "PID81,Peripheral Clock 81 Status" "0,1"
|
|
bitfld.long 0x8 16. "PID80,Peripheral Clock 80 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "PID79,Peripheral Clock 79 Status" "0,1"
|
|
bitfld.long 0x8 14. "PID78,Peripheral Clock 78 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "PID75,Peripheral Clock 75 Status" "0,1"
|
|
line.long 0xC "CSR3,Peripheral Clock Status Register 3"
|
|
bitfld.long 0xC 0. "PID96,Peripheral Clock 96 Status" "0,1"
|
|
rgroup.long 0xC4++0xF
|
|
line.long 0x0 "GCSR0,Generic Clock Status Register 0"
|
|
bitfld.long 0x0 31. "GPID31,Generic Clock 31 Status" "0,1"
|
|
bitfld.long 0x0 24. "GPID24,Generic Clock 24 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "GPID23,Generic Clock 23 Status" "0,1"
|
|
bitfld.long 0x0 16. "GPID16,Generic Clock 16 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "GPID15,Generic Clock 15 Status" "0,1"
|
|
bitfld.long 0x0 14. "GPID14,Generic Clock 14 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "GPID13,Generic Clock 13 Status" "0,1"
|
|
bitfld.long 0x0 12. "GPID12,Generic Clock 12 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "GPID11,Generic Clock 11 Status" "0,1"
|
|
bitfld.long 0x0 10. "GPID10,Generic Clock 10 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "GPID9,Generic Clock 9 Status" "0,1"
|
|
line.long 0x4 "GCSR1,Generic Clock Status Register 1"
|
|
bitfld.long 0x4 5. "GPID37,Generic Clock 37 Status" "0,1"
|
|
bitfld.long 0x4 2. "GPID34,Generic Clock 34 Status" "0,1"
|
|
line.long 0x8 "GCSR2,Generic Clock Status Register 2"
|
|
bitfld.long 0x8 26. "GPID90,Generic Clock 90 Status" "0,1"
|
|
bitfld.long 0x8 25. "GPID89,Generic Clock 89 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "GPID87,Generic Clock 87 Status" "0,1"
|
|
bitfld.long 0x8 15. "GPID79,Generic Clock 79 Status" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "GPID75,Generic Clock 75 Status" "0,1"
|
|
line.long 0xC "GCSR3,Generic Clock Status Register 3"
|
|
bitfld.long 0xC 0. "GPID96,Generic Clock 96 Status" "0,1"
|
|
wgroup.long 0xE4++0x7
|
|
line.long 0x0 "PLL_IER,PLL Interrupt Enable Register"
|
|
bitfld.long 0x0 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "LOCK2,PLL of Index 2 Lock Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK1,PLL of Index 1 Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "LOCK0,PLL of Index 0 Lock Interrupt Enable" "0,1"
|
|
line.long 0x4 "PLL_IDR,PLL Interrupt Disable Register"
|
|
bitfld.long 0x4 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "LOCK2,PLL of Index 2 Lock Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK1,PLL of Index 1 Lock Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "LOCK0,PLL of Index 0 Lock Interrupt Disable" "0,1"
|
|
rgroup.long 0xEC++0xB
|
|
line.long 0x0 "PLL_IMR,PLL Interrupt Mask Register"
|
|
bitfld.long 0x0 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "LOCK2,PLL of Index 2 Lock Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOCK1,PLL of Index 1 Lock Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "LOCK0,PLL of Index 0 Lock Interrupt Mask" "0,1"
|
|
line.long 0x4 "PLL_ISR0,PLL Interrupt Status Register 0"
|
|
bitfld.long 0x4 18. "UNLOCK2,PLL of Index 2 Unlock Interrupt Status" "0,1"
|
|
bitfld.long 0x4 17. "UNLOCK1,PLL of Index 1 Unlock Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "UNLOCK0,PLL of Index 0 Unlock Interrupt Status" "0,1"
|
|
bitfld.long 0x4 2. "LOCK2,PLL of Index 2 Lock Interrupt Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "LOCK1,PLL of Index 1 Lock Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "LOCK0,PLL of Index 0 Lock Interrupt Status" "0,1"
|
|
line.long 0x8 "PLL_ISR1,PLL Interrupt Status Register 1"
|
|
bitfld.long 0x8 18. "OVR2,PLLx Overflow" "0,1"
|
|
bitfld.long 0x8 17. "OVR1,PLLx Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "OVR0,PLLx Overflow" "0,1"
|
|
bitfld.long 0x8 2. "UDR2,PLLx Underflow" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "UDR1,PLLx Underflow" "0,1"
|
|
bitfld.long 0x8 0. "UDR0,PLLx Underflow" "0,1"
|
|
tree.end
|
|
tree "PWM (Pulse Width Modulation Controller)"
|
|
base ad:0x4801C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CLK,PWM Clock Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "PREB,CLKB Source Clock Selection"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DIVB,CLKB Divide Factor"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "PREA,CLKA Source Clock Selection"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DIVA,CLKA Divide Factor"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "ENA,PWM Enable Register"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
line.long 0x4 "DIS,PWM Disable Register"
|
|
bitfld.long 0x4 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x4 1. "CHID1,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "CHID0,Channel ID" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,PWM Status Register"
|
|
bitfld.long 0x0 2. "CHID2,Channel ID" "0,1"
|
|
bitfld.long 0x0 1. "CHID1,Channel ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CHID0,Channel ID" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER1,PWM Interrupt Enable Register 1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR1,PWM Interrupt Disable Register 1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2 Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1 Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0 Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR1,PWM Interrupt Mask Register 1"
|
|
bitfld.long 0x0 18. "FCHID2,Fault Protection Trigger on Channel 2 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 17. "FCHID1,Fault Protection Trigger on Channel 1 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "FCHID0,Fault Protection Trigger on Channel 0 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "CHID2,Counter Event on Channel 2 Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHID1,Counter Event on Channel 1 Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "CHID0,Counter Event on Channel 0 Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR1,PWM Interrupt Status Register 1"
|
|
bitfld.long 0x4 18. "FCHID2,Fault Protection Trigger on Channel 2" "0,1"
|
|
bitfld.long 0x4 17. "FCHID1,Fault Protection Trigger on Channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "FCHID0,Fault Protection Trigger on Channel 0" "0,1"
|
|
bitfld.long 0x4 2. "CHID2,Counter Event on Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CHID1,Counter Event on Channel 1" "0,1"
|
|
bitfld.long 0x4 0. "CHID0,Counter Event on Channel 0" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "SCM,PWM Sync Channels Mode Register"
|
|
bitfld.long 0x0 21.--23. "PTRCS,Peripheral DMA Controller Transfer Request Comparison Selection" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 20. "PTRM,Peripheral DMA Controller Transfer Request Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "UPDM,Synchronous Channels Update Mode" "0: Manual write of double buffer registers and..,1: Manual write of double buffer registers and..,2: Automatic write of duty-cycle update registers..,?"
|
|
bitfld.long 0x0 2. "SYNC2,Synchronous Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "SYNC1,Synchronous Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "SYNC0,Synchronous Channel 0" "0,1"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "SCUC,PWM Sync Channels Update Control Register"
|
|
bitfld.long 0x0 0. "UPDULOCK,Synchronous Channels Update Unlock" "0,1"
|
|
line.long 0x4 "SCUP,PWM Sync Channels Update Period Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "UPRCNT,Update Period Counter"
|
|
hexmask.long.byte 0x4 0.--3. 1. "UPR,Update Period"
|
|
wgroup.long 0x30++0xB
|
|
line.long 0x0 "SCUPUPD,PWM Sync Channels Update Period Update Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "UPRUPD,Update Period Update"
|
|
line.long 0x4 "IER2,PWM Interrupt Enable Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "TXBUFE,PDC TX Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENDTX,PDC End of TX Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR2,PWM Interrupt Disable Register 2"
|
|
bitfld.long 0x8 23. "CMPU7,Comparison 7 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 22. "CMPU6,Comparison 6 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 21. "CMPU5,Comparison 5 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 20. "CMPU4,Comparison 4 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CMPU3,Comparison 3 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 18. "CMPU2,Comparison 2 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "CMPU1,Comparison 1 Update Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 16. "CMPU0,Comparison 0 Update Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CMPM7,Comparison 7 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 14. "CMPM6,Comparison 6 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "CMPM5,Comparison 5 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 12. "CMPM4,Comparison 4 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CMPM3,Comparison 3 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 10. "CMPM2,Comparison 2 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "CMPM1,Comparison 1 Match Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 8. "CMPM0,Comparison 0 Match Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 2. "TXBUFE,PDC TX Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ENDTX,PDC End of TX Buffer Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x3C++0x7
|
|
line.long 0x0 "IMR2,PWM Interrupt Mask Register 2"
|
|
bitfld.long 0x0 23. "CMPU7,Comparison 7 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 22. "CMPU6,Comparison 6 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CMPU5,Comparison 5 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 20. "CMPU4,Comparison 4 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CMPU3,Comparison 3 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 18. "CMPU2,Comparison 2 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "CMPU1,Comparison 1 Update Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CMPU0,Comparison 0 Update Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CMPM7,Comparison 7 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 14. "CMPM6,Comparison 6 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "CMPM5,Comparison 5 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 12. "CMPM4,Comparison 4 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMPM3,Comparison 3 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 10. "CMPM2,Comparison 2 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPM1,Comparison 1 Match Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CMPM0,Comparison 0 Match Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "UNRE,Synchronous Channels Update Underrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXBUFE,PDC TX Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENDTX,PDC End of TX Buffer Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "WRDY,Write Ready for Synchronous Channels Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR2,PWM Interrupt Status Register 2"
|
|
bitfld.long 0x4 23. "CMPU7,Comparison 7 Update" "0,1"
|
|
bitfld.long 0x4 22. "CMPU6,Comparison 6 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CMPU5,Comparison 5 Update" "0,1"
|
|
bitfld.long 0x4 20. "CMPU4,Comparison 4 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CMPU3,Comparison 3 Update" "0,1"
|
|
bitfld.long 0x4 18. "CMPU2,Comparison 2 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CMPU1,Comparison 1 Update" "0,1"
|
|
bitfld.long 0x4 16. "CMPU0,Comparison 0 Update" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CMPM7,Comparison 7 Match" "0,1"
|
|
bitfld.long 0x4 14. "CMPM6,Comparison 6 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CMPM5,Comparison 5 Match" "0,1"
|
|
bitfld.long 0x4 12. "CMPM4,Comparison 4 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CMPM3,Comparison 3 Match" "0,1"
|
|
bitfld.long 0x4 10. "CMPM2,Comparison 2 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CMPM1,Comparison 1 Match" "0,1"
|
|
bitfld.long 0x4 8. "CMPM0,Comparison 0 Match" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "UNRE,Synchronous Channels Update Underrun Error" "0,1"
|
|
bitfld.long 0x4 2. "TXBUFE,PDC TX Buffer Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENDTX,PDC End of TX Buffer" "0,1"
|
|
bitfld.long 0x4 0. "WRDY,Write Ready for Synchronous Channels Update" "0,1"
|
|
group.long 0x44++0x7
|
|
line.long 0x0 "OOV,PWM Output Override Value Register"
|
|
bitfld.long 0x0 18. "OOVL2,Output Override Value for PWML output of the channel 2" "0,1"
|
|
bitfld.long 0x0 17. "OOVL1,Output Override Value for PWML output of the channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "OOVL0,Output Override Value for PWML output of the channel 0" "0,1"
|
|
bitfld.long 0x0 2. "OOVH2,Output Override Value for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OOVH1,Output Override Value for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OOVH0,Output Override Value for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OS,PWM Output Selection Register"
|
|
bitfld.long 0x4 18. "OSL2,Output Selection for PWML output of the channel 2" "0,1"
|
|
bitfld.long 0x4 17. "OSL1,Output Selection for PWML output of the channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OSL0,Output Selection for PWML output of the channel 0" "0,1"
|
|
bitfld.long 0x4 2. "OSH2,Output Selection for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSH1,Output Selection for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSH0,Output Selection for PWMH output of the channel 0" "0,1"
|
|
wgroup.long 0x4C++0xF
|
|
line.long 0x0 "OSS,PWM Output Selection Set Register"
|
|
bitfld.long 0x0 18. "OSSL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
bitfld.long 0x0 17. "OSSL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "OSSL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
bitfld.long 0x0 2. "OSSH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "OSSH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x0 0. "OSSH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0x4 "OSC,PWM Output Selection Clear Register"
|
|
bitfld.long 0x4 18. "OSCL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
bitfld.long 0x4 17. "OSCL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "OSCL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
bitfld.long 0x4 2. "OSCH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "OSCH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x4 0. "OSCH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
line.long 0x8 "OSSUPD,PWM Output Selection Set Update Register"
|
|
bitfld.long 0x8 18. "OSSUPL2,Output Selection Set for PWML output of the channel 2" "0,1"
|
|
bitfld.long 0x8 17. "OSSUPL1,Output Selection Set for PWML output of the channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "OSSUPL0,Output Selection Set for PWML output of the channel 0" "0,1"
|
|
bitfld.long 0x8 2. "OSSUPH2,Output Selection Set for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "OSSUPH1,Output Selection Set for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0x8 0. "OSSUPH0,Output Selection Set for PWMH output of the channel 0" "0,1"
|
|
line.long 0xC "OSCUPD,PWM Output Selection Clear Update Register"
|
|
bitfld.long 0xC 18. "OSCUPL2,Output Selection Clear for PWML output of the channel 2" "0,1"
|
|
bitfld.long 0xC 17. "OSCUPL1,Output Selection Clear for PWML output of the channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "OSCUPL0,Output Selection Clear for PWML output of the channel 0" "0,1"
|
|
bitfld.long 0xC 2. "OSCUPH2,Output Selection Clear for PWMH output of the channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "OSCUPH1,Output Selection Clear for PWMH output of the channel 1" "0,1"
|
|
bitfld.long 0xC 0. "OSCUPH0,Output Selection Clear for PWMH output of the channel 0" "0,1"
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "FMR,PWM Fault Mode Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "FFIL,Fault Filtering"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FMOD,Fault Activation Mode"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "FPOL,Fault Polarity"
|
|
rgroup.long 0x60++0x3
|
|
line.long 0x0 "FSR,PWM Fault Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FS,Fault Status"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FIV,Fault Input Value"
|
|
wgroup.long 0x64++0x3
|
|
line.long 0x0 "FCR,PWM Fault Clear Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCLR,Fault Clear"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "FPV1,PWM Fault Protection Value Register 1"
|
|
bitfld.long 0x0 18. "FPVL2,Fault Protection Value for PWML output on channel 2" "0,1"
|
|
bitfld.long 0x0 17. "FPVL1,Fault Protection Value for PWML output on channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "FPVL0,Fault Protection Value for PWML output on channel 0" "0,1"
|
|
bitfld.long 0x0 2. "FPVH2,Fault Protection Value for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPVH1,Fault Protection Value for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPVH0,Fault Protection Value for PWMH output on channel 0" "0,1"
|
|
line.long 0x4 "FPE,PWM Fault Protection Enable Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "FPE2,Fault Protection Enable for channel 2"
|
|
hexmask.long.byte 0x4 8.--15. 1. "FPE1,Fault Protection Enable for channel 1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--7. 1. "FPE0,Fault Protection Enable for channel 0"
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "ELMR0,PWM Event Line 0 Mode Register"
|
|
bitfld.long 0x0 7. "CSEL7,Comparison 7 Selection" "0,1"
|
|
bitfld.long 0x0 6. "CSEL6,Comparison 6 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "CSEL5,Comparison 5 Selection" "0,1"
|
|
bitfld.long 0x0 4. "CSEL4,Comparison 4 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CSEL3,Comparison 3 Selection" "0,1"
|
|
bitfld.long 0x0 2. "CSEL2,Comparison 2 Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CSEL1,Comparison 1 Selection" "0,1"
|
|
bitfld.long 0x0 0. "CSEL0,Comparison 0 Selection" "0,1"
|
|
group.long 0xA0++0x3
|
|
line.long 0x0 "SSPR,PWM Spread Spectrum Register"
|
|
bitfld.long 0x0 24. "SPRDM,Spread Spectrum Counter Mode" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRD,Spread Spectrum Limit Value"
|
|
wgroup.long 0xA4++0x3
|
|
line.long 0x0 "SSPUP,PWM Spread Spectrum Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "SPRDUP,Spread Spectrum Limit Value Update"
|
|
group.long 0xAC++0x7
|
|
line.long 0x0 "DEBUG,Debug Register"
|
|
bitfld.long 0x0 0. "OUTMODE,PWM Output Mode when System is in Debug Mode" "0: Keeps the PWM outputs running when the processor..,?"
|
|
line.long 0x4 "SMMR,PWM Stepper Motor Mode Register"
|
|
bitfld.long 0x4 16. "DOWN0,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN0,Gray Count Enable" "0,1"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FPV2,PWM Fault Protection Value 2 Register"
|
|
bitfld.long 0x0 18. "FPZL2,Fault Protection to Hi-Z for PWML output on channel 2" "0,1"
|
|
bitfld.long 0x0 17. "FPZL1,Fault Protection to Hi-Z for PWML output on channel 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "FPZL0,Fault Protection to Hi-Z for PWML output on channel 0" "0,1"
|
|
bitfld.long 0x0 2. "FPZH2,Fault Protection to Hi-Z for PWMH output on channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FPZH1,Fault Protection to Hi-Z for PWMH output on channel 1" "0,1"
|
|
bitfld.long 0x0 0. "FPZH0,Fault Protection to Hi-Z for PWMH output on channel 0" "0,1"
|
|
wgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPCR,PWM Write Protection Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "WPRG5,Write Protection Register Group 5" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "WPRG4,Write Protection Register Group 4" "0,1"
|
|
bitfld.long 0x0 5. "WPRG3,Write Protection Register Group 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "WPRG2,Write Protection Register Group 2" "0,1"
|
|
bitfld.long 0x0 3. "WPRG1,Write Protection Register Group 1" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "WPRG0,Write Protection Register Group 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "WPCMD,Write Protection Command" "0: Disables the software write protection of the..,1: Enables the software write protection of the..,2: Enables the hardware write protection of the..,?"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,PWM Write Protection Status Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WPVSRC,Write Protect Violation Source"
|
|
bitfld.long 0x0 13. "WPHWS5,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WPHWS4,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 11. "WPHWS3,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "WPHWS2,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 9. "WPHWS1,Write Protect HW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "WPHWS0,Write Protect HW Status" "0,1"
|
|
bitfld.long 0x0 7. "WPVS,Write Protect Violation Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "WPSWS5,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 4. "WPSWS4,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "WPSWS3,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 2. "WPSWS2,Write Protect SW Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPSWS1,Write Protect SW Status" "0,1"
|
|
bitfld.long 0x0 0. "WPSWS0,Write Protect SW Status" "0,1"
|
|
group.long 0x108++0x7
|
|
line.long 0x0 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0x4 "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
group.long 0x118++0x7
|
|
line.long 0x0 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x4 "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4801C130 ad:0x4801C140 ad:0x4801C150 ad:0x4801C160 ad:0x4801C170 ad:0x4801C180 ad:0x4801C190 ad:0x4801C1A0)
|
|
tree "PWM_CMP[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CMPV,PWM Comparison 0 Value Register"
|
|
bitfld.long 0x0 24. "CVM,Comparison x Value Mode" "0: Compare when counter is incrementing,1: Compare when counter is decrementing"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CV,Comparison x Value"
|
|
wgroup.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMPVUPD,PWM Comparison 0 Value Update Register"
|
|
bitfld.long 0x0 24. "CVMUPD,Comparison x Value Mode Update" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CVUPD,Comparison x Value Update"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "CMPM,PWM Comparison 0 Mode Register"
|
|
hexmask.long.byte 0x0 20.--23. 1. "CUPRCNT,Comparison x Update Period Counter"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPR,Comparison x Update Period"
|
|
hexmask.long.byte 0x0 12.--15. 1. "CPRCNT,Comparison x Period Counter"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPR,Comparison x Period"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTR,Comparison x Trigger"
|
|
bitfld.long 0x0 0. "CEN,Comparison x Enable" "0,1"
|
|
wgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "CMPMUPD,PWM Comparison 0 Mode Update Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CUPRUPD,Comparison x Update Period Update"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CPRUPD,Comparison x Period Update"
|
|
hexmask.long.byte 0x0 4.--7. 1. "CTRUPD,Comparison x Trigger Update"
|
|
bitfld.long 0x0 0. "CENUPD,Comparison x Enable Update" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x4801C200 ad:0x4801C220 ad:0x4801C240)
|
|
tree "PWM_CH_NUM[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "CMR,PWM Channel Mode Register"
|
|
bitfld.long 0x0 19. "PPM,Push-Pull Mode" "0,1"
|
|
bitfld.long 0x0 18. "DTLI,Dead-Time PWMLx Output Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "DTHI,Dead-Time PWMHx Output Inverted" "0,1"
|
|
bitfld.long 0x0 16. "DTE,Dead-Time Generator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCTS,Timer Counter Trigger Selection" "0,1"
|
|
bitfld.long 0x0 12. "DPOLI,Disabled Polarity Inverted" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "UPDS,Update Selection" "0: At the next end of PWM period,1: At the next end of Half PWM period"
|
|
bitfld.long 0x0 10. "CES,Counter Event Selection" "0: At the end of PWM period,1: At half of PWM period AND at the end of PWM period"
|
|
newline
|
|
bitfld.long 0x0 9. "CPOL,Channel Polarity" "0: Waveform starts at low level,1: Waveform starts at high level"
|
|
bitfld.long 0x0 8. "CALG,Channel Alignment" "0: Left aligned,1: Center aligned"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "CPRE,Channel Prescaler"
|
|
line.long 0x4 "CDTY,PWM Channel Duty Cycle Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "CDTY,Channel Duty-Cycle"
|
|
wgroup.long ($2+0x8)++0x3
|
|
line.long 0x0 "CDTYUPD,PWM Channel Duty Cycle Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CDTYUPD,Channel Duty-Cycle Update"
|
|
group.long ($2+0xC)++0x3
|
|
line.long 0x0 "CPRD,PWM Channel Period Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRD,Channel Period"
|
|
wgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CPRDUPD,PWM Channel Period Update Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CPRDUPD,Channel Period Update"
|
|
rgroup.long ($2+0x14)++0x3
|
|
line.long 0x0 "CCNT,PWM Channel Counter Register"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Channel Counter Register"
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "DT,PWM Channel Dead Time Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTL,Dead-Time Value for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTH,Dead-Time Value for PWMHx Output"
|
|
wgroup.long ($2+0x1C)++0x3
|
|
line.long 0x0 "DTUPD,PWM Channel Dead Time Update Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "DTLUPD,Dead-Time Value Update for PWMLx Output"
|
|
hexmask.long.word 0x0 0.--15. 1. "DTHUPD,Dead-Time Value Update for PWMHx Output"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4801C000
|
|
wgroup.long 0x400++0x3
|
|
line.long 0x0 "CMUPD0,PWM Channel Mode Update Register (ch_num = 0)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
wgroup.long 0x420++0x3
|
|
line.long 0x0 "CMUPD1,PWM Channel Mode Update Register (ch_num = 1)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x42C++0x7
|
|
line.long 0x0 "ETRG1,PWM External Trigger Register 1"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR1,PWM Leading-Edge Blanking Register 1"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
wgroup.long 0x440++0x3
|
|
line.long 0x0 "CMUPD2,PWM Channel Mode Update Register (ch_num = 2)"
|
|
bitfld.long 0x0 13. "CPOLINVUP,Channel Polarity Inversion Update" "0,1"
|
|
bitfld.long 0x0 9. "CPOLUP,Channel Polarity Update" "0,1"
|
|
group.long 0x44C++0x7
|
|
line.long 0x0 "ETRG2,PWM External Trigger Register 2"
|
|
bitfld.long 0x0 31. "RFEN,Recoverable Fault Enable" "0,1"
|
|
bitfld.long 0x0 30. "TRGSRC,Trigger Source" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRGFILT,Filtered input" "0,1"
|
|
bitfld.long 0x0 28. "TRGEDGE,Edge Selection" "0: TRGMODE = 1: TRGINx event detection on falling..,1: TRGMODE = 1: TRGINx event detection on rising.."
|
|
newline
|
|
bitfld.long 0x0 24.--25. "TRGMODE,External Trigger Mode" "0: External trigger is not enabled.,1: External PWM Reset Mode,2: External PWM Start Mode,3: Cycle-by-cycle Duty Mode"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "MAXCNT,Maximum Counter value"
|
|
line.long 0x4 "LEBR2,PWM Leading-Edge Blanking Register 2"
|
|
bitfld.long 0x4 19. "PWMHREN,PWMH Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 18. "PWMHFEN,PWMH Falling Edge Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "PWMLREN,PWML Rising Edge Enable" "0,1"
|
|
bitfld.long 0x4 16. "PWMLFEN,PWML Falling Edge Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "LEBDELAY,Leading-Edge Blanking Delay for TRGINx"
|
|
tree.end
|
|
tree "QSPI (Quad Serial Peripheral Interface)"
|
|
base ad:0x40020000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "LASTXFER,Last Transfer" "0,1"
|
|
bitfld.long 0x0 10. "RTOUT,Reset Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "STTFR,Start Transfer" "0,1"
|
|
bitfld.long 0x0 8. "UPDCFG,Update Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SWRST,QSPI Software Reset" "0,1"
|
|
bitfld.long 0x0 1. "QSPIDIS,QSPI Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "QSPIEN,QSPI Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "DLYCS,Minimum Inactive QCS Delay"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBCT,Delay Between Consecutive Transfers"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "NBBITS,Number Of Bits Per Transfer"
|
|
bitfld.long 0x0 7. "TAMPCLR,Tamper Clear Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CSMODE,Chip Select Mode" "0: The chip select is deasserted if QSPI_TDR.TD has..,1: The chip select is deasserted when the bit..,2: The chip select is deasserted systematically..,?"
|
|
bitfld.long 0x0 2. "WDRBT,Wait Data Read Before Transfer" "0: No effect. In SPI mode a transfer can be..,1: In SPI mode a transfer can start only if.."
|
|
newline
|
|
bitfld.long 0x0 0. "SMM,Serial Memory Mode" "0: The QSPI is in SPI mode.,1: The QSPI is in Serial Memory mode."
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "RDR,Receive Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RD,Receive Data"
|
|
wgroup.long 0xC++0x3
|
|
line.long 0x0 "TDR,Transmit Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TD,Transmit Data"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out" "0,1"
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear" "0,1"
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall" "0,1"
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,TX Buffer Empty" "0,1"
|
|
bitfld.long 0x0 6. "RXBUFF,RX Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of TX buffer" "0,1"
|
|
bitfld.long 0x0 4. "ENDRX,End of RX buffer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty (cleared by writing QSPI_TDR)" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full (cleared by reading QSPI_RDR)" "0,1"
|
|
wgroup.long 0x14++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 17. "TOUT,QSPI Time-out Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 15. "CSRA,Chip Select Rise Autoclear Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14. "CSFA,Chip Select Fall Autoclear Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 13. "QITR,QSPI Interrupt Rise Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "QITF,QSPI Interrupt Fall Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 11. "LWRA,Last Write Access Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "INSTRE,Instruction End Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 8. "CSR,Chip Select Rise Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 6. "RXBUFF,Receive Buffer Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 4. "ENDRX,End of Receive Buffer Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OVRES,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXEMPTY,Transmission Registers Empty Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TDRE,Transmit Data Register Empty Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "RDRF,Receive Data Register Full Interrupt Disable" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 17. "TOUT,QSPI Time-out Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 15. "CSRA,Chip Select Rise Autoclear Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CSFA,Chip Select Fall Autoclear Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 13. "QITR,QSPI Interrupt Rise Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "QITF,QSPI Interrupt Fall Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 11. "LWRA,Last Write Access Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "INSTRE,Instruction End Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 8. "CSR,Chip Select Rise Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 6. "RXBUFF,Receive Buffer Full Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 4. "ENDRX,End of Receive Buffer Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "OVRES,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXEMPTY,Transmission Registers Empty Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TDRE,Transmit Data Register Empty Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "RDRF,Receive Data Register Full Interrupt Mask" "0,1"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "SCR,Serial Clock Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "DLYBS,Delay Before QSCK"
|
|
bitfld.long 0x0 1. "CPHA,Clock Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CPOL,Clock Polarity" "0,1"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 4. "HIDLE,QSPI Idle" "0,1"
|
|
bitfld.long 0x4 3. "RBUSY,Read Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CSS,Chip Select Status" "0,1"
|
|
bitfld.long 0x4 1. "QSPIENS,QSPI Enable Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SYNCBSY,Synchronization Busy" "0,1"
|
|
group.long 0x30++0x13
|
|
line.long 0x0 "IAR,Instruction Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Address"
|
|
line.long 0x4 "WICR,Write Instruction Code Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "WROPT,Write Option Code"
|
|
hexmask.long.byte 0x4 0.--7. 1. "WRINST,Write Instruction Code"
|
|
line.long 0x8 "IFR,Instruction Frame Register"
|
|
bitfld.long 0x8 28.--29. "PROTTYP,Protocol Type" "0: Standard (Q)SPI Protocol,?,?,?"
|
|
bitfld.long 0x8 26. "DDRCMDEN,DDR Mode Command Enable" "0: Transfer of instruction field is performed in..,1: Transfer of instruction field is performed in.."
|
|
newline
|
|
bitfld.long 0x8 25. "DQSEN,DQS Sampling Enable" "0,1"
|
|
bitfld.long 0x8 24. "APBTFRTYP,Peripheral BusTransfer Type" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "SMRM,Serial Memory Register Mode" "0,1"
|
|
hexmask.long.byte 0x8 16.--20. 1. "NBDUM,Number Of Dummy Cycles"
|
|
newline
|
|
bitfld.long 0x8 15. "DDREN,DDR Mode Enable" "0: Transfers are performed in Single Data Rate mode.,1: Transfers are performed in Double Data Rate mode.."
|
|
bitfld.long 0x8 14. "CRM,Continuous Read Mode" "0: Continuous Read mode is disabled.,1: Continuous Read mode is enabled."
|
|
newline
|
|
bitfld.long 0x8 12. "TFRTYP,Data Transfer Type" "0: Read/Write of memory register write of memory..,1: Read/Write accesses to the memory space. This.."
|
|
bitfld.long 0x8 10.--11. "ADDRL,Address Length" "0: 8-bit address size,1: 16-bit address size,2: 24-bit address size,3: 32-bit address size"
|
|
newline
|
|
bitfld.long 0x8 8.--9. "OPTL,Option Code Length" "0: The option code is 1 bit long.,1: The option code is 2 bits long.,2: The option code is 4 bits long.,3: The option code is 8 bits long."
|
|
bitfld.long 0x8 7. "DATAEN,Data Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 6. "OPTEN,Option Enable" "0,1"
|
|
bitfld.long 0x8 5. "ADDREN,Address Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "INSTEN,Instruction Enable" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "WIDTH,Width of Instruction Code Address Option Code and Data"
|
|
line.long 0xC "RICR,Read Instruction Code Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "RDOPT,Read Option Code"
|
|
hexmask.long.byte 0xC 0.--7. 1. "RDINST,Read Instruction Code"
|
|
line.long 0x10 "SMR,Scrambling Mode Register"
|
|
bitfld.long 0x10 2. "SCRKL,Scrambling Key Lock" "0,1"
|
|
bitfld.long 0x10 1. "RVDIS,Scrambling/Unscrambling Random Value Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "SCREN,Scrambling/Unscrambling Enable" "0: The scrambling/unscrambling is disabled.,1: The scrambling/unscrambling is enabled."
|
|
wgroup.long 0x44++0x3
|
|
line.long 0x0 "SKR,Scrambling Key Register"
|
|
hexmask.long 0x0 0.--31. 1. "USRK,User Scrambling Key"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "WRACNT,Write Access Counter Register"
|
|
hexmask.long 0x0 0.--31. 1. "NBWRA,Number of Write Accesses"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "TOUT,Timeout Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TCNTM,Time-out Counter Maximum Value"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x40053000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,System Reset Key"
|
|
bitfld.long 0x0 3. "EXTRST,External Reset" "0,1"
|
|
bitfld.long 0x0 2. "PERRST,Peripheral Reset" "0,1"
|
|
bitfld.long 0x0 0. "PROCRST,Processor Reset" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 17. "SRCMP,Software Reset Command in Progress" "0,1"
|
|
bitfld.long 0x0 16. "NRSTL,NRST Pin Level" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "RSTTYP,Reset Type"
|
|
bitfld.long 0x0 1. "CORESMS,VDDCORE Supply Monitor Reset Flag Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "URSTS,User Reset Status (cleared on read)" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Write Access Password"
|
|
bitfld.long 0x0 22. "BADXTRST,Bad XTAL Fail Reset" "0,1"
|
|
bitfld.long 0x0 21. "PWRSW,Backup Area Power Switch Control" "0: VDDBU is supplied by VDD3V3,1: VDDBU is supplied by VBAT"
|
|
bitfld.long 0x0 18. "CPROCEN,Coprocessor (Second Processor) Enable" "0,1"
|
|
bitfld.long 0x0 17. "CPEREN,Coprocessor Peripheral Enable" "0,1"
|
|
bitfld.long 0x0 16. "CORSMIEN,VDDCORE Supply Monitor Interrupt Enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "ERSTL,External Reset Length"
|
|
bitfld.long 0x0 7. "WDTPMC1,WDT1 PMC Reset" "0,1"
|
|
bitfld.long 0x0 6. "WDTPMC0,WDT0 PMC Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "SFTPMCRS,Software PMC Reset" "0,1"
|
|
bitfld.long 0x0 4. "URSTIEN,User Reset Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "CPUFEN,CPU Fail Enable" "0,1"
|
|
bitfld.long 0x0 2. "URSTASYNC,User Reset Asynchronous Control" "0,1"
|
|
bitfld.long 0x0 1. "SCKSW,Slow Clock Switching" "0,1"
|
|
bitfld.long 0x0 0. "URSTEN,User Reset Enable" "0,1"
|
|
tree.end
|
|
tree "RTC (Real-Time Controller)"
|
|
base ad:0x40053100
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 16.--17. "CALEVSEL,Calendar Event Selection" "0: Week change (every Monday at time 00:00:00),1: Month change (every 01 of each month at time..,2: Year change (every January 1 at time 00:00:00),?"
|
|
bitfld.long 0x0 8.--9. "TIMEVSEL,Time Event Selection" "0: Minute change,1: Hour change,2: Every day at midnight,3: Every day at noon"
|
|
newline
|
|
bitfld.long 0x0 1. "UPDCAL,Update Request Calendar Register" "0: No effect or if UPDCAL has been previously..,1: Stops the RTC calendar counting."
|
|
bitfld.long 0x0 0. "UPDTIM,Update Request Time Register" "0: No effect or if UPDTIM has been previously..,1: Stops the RTC time counting. Second minute and.."
|
|
line.long 0x4 "MR,Mode Register"
|
|
bitfld.long 0x4 28.--29. "TPERIOD,Period of the Output Pulse" "0: 1 second,1: 500 ms,2: 250 ms,3: 125 ms"
|
|
bitfld.long 0x4 24.--26. "THIGH,High Duration of the Output Pulse" "0: 31.2 ms,1: 15.6 ms,2: 3.91 ms,3: 976 us,4: 488 us,5: 122 us,6: 30.5 us,7: 15.2 us"
|
|
newline
|
|
bitfld.long 0x4 20.--22. "OUT1,RTCOUT1 Output Source Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
bitfld.long 0x4 16.--18. "OUT0,RTCOUT0 OutputSource Selection" "0: No waveform stuck at '0',1: 1 Hz square wave,2: 32 Hz square wave,3: 64 Hz square wave,4: 512 Hz square wave,5: Output toggles when alarm flag rises,6: Output is a copy of the alarm flag,7: Duty cycle programmable pulse"
|
|
newline
|
|
bitfld.long 0x4 15. "HIGHPPM,HIGH PPM Correction" "0: Lower range ppm correction with accurate..,1: Higher range ppm correction with accurate.."
|
|
hexmask.long.byte 0x4 8.--14. 1. "CORRECTION,Slow Clock Correction"
|
|
newline
|
|
bitfld.long 0x4 4. "NEGPPM,NEGative PPM Correction" "0: Positive correction (the divider will be..,1: Negative correction (the divider will be.."
|
|
bitfld.long 0x4 2. "UTC,UTC Time Format" "0: Gregorian or Persian calendar.,1: UTC format."
|
|
newline
|
|
bitfld.long 0x4 1. "PERSIAN,PERSIAN Calendar" "0: Gregorian calendar.,1: Persian calendar."
|
|
bitfld.long 0x4 0. "HRMOD,12-/24-hour Mode" "0: 24-hour mode is selected.,1: 12-hour mode is selected."
|
|
line.long 0x8 "TIMR,Time Register"
|
|
bitfld.long 0x8 22. "AMPM,Ante Meridiem Post Meridiem Indicator" "0: AM.,1: PM."
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Current Hour"
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Current Minute"
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Current Second"
|
|
group.long 0x8++0xB
|
|
line.long 0x0 "TIMR_UTC_MODE_MODE,Time Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Current UTC Time"
|
|
line.long 0x4 "CALR,Calendar Register"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Current Day in Current Month"
|
|
bitfld.long 0x4 21.--23. "DAY,Current Day in Current Week" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Current Month"
|
|
hexmask.long.byte 0x4 8.--15. 1. "YEAR,Current Year"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Current Century"
|
|
line.long 0x8 "TIMALR,Time Alarm Register"
|
|
bitfld.long 0x8 23. "HOUREN,Hour Alarm Enable" "0: The hour-matching alarm is disabled.,1: The hour-matching alarm is enabled."
|
|
bitfld.long 0x8 22. "AMPM,AM/PM Indicator" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "HOUR,Hour Alarm"
|
|
bitfld.long 0x8 15. "MINEN,Minute Alarm Enable" "0: The minute-matching alarm is disabled.,1: The minute-matching alarm is enabled."
|
|
newline
|
|
hexmask.long.byte 0x8 8.--14. 1. "MIN,Minute Alarm"
|
|
bitfld.long 0x8 7. "SECEN,Second Alarm Enable" "0: The second-matching alarm is disabled.,1: The second-matching alarm is enabled."
|
|
newline
|
|
hexmask.long.byte 0x8 0.--6. 1. "SEC,Second Alarm"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "TIMALR_UTC_MODE_MODE,Time Alarm Register"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,UTC_TIME Alarm"
|
|
line.long 0x4 "CALALR,Calendar Alarm Register"
|
|
bitfld.long 0x4 31. "DATEEN,Date Alarm Enable" "0: The date-matching alarm is disabled.,1: The date-matching alarm is enabled."
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date Alarm"
|
|
newline
|
|
bitfld.long 0x4 23. "MTHEN,Month Alarm Enable" "0: The month-matching alarm is disabled.,1: The month-matching alarm is enabled."
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month Alarm"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CALALR_UTC_MODE_MODE,Calendar Alarm Register"
|
|
bitfld.long 0x0 0. "UTCEN,UTC Alarm Enable" "0: The UTC-matching alarm is disabled.,1: The UTC-matching alarm is enabled."
|
|
rgroup.long 0x18++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Free Running Error" "0: The internal free running counters are carrying..,1: The internal free running counters have been.."
|
|
bitfld.long 0x0 4. "CALEV,Calendar Event" "0: No calendar event has occurred since the last..,1: At least one calendar event has occurred since.."
|
|
newline
|
|
bitfld.long 0x0 3. "TIMEV,Time Event" "0: No time event has occurred since the last clear.,1: At least one time event has occurred since the.."
|
|
bitfld.long 0x0 2. "SEC,Second Event" "0: No second event has occurred since the last clear.,1: At least one second event has occurred since the.."
|
|
newline
|
|
bitfld.long 0x0 1. "ALARM,Alarm Flag" "0: No alarm matching condition occurred.,1: An alarm matching condition has occurred."
|
|
bitfld.long 0x0 0. "ACKUPD,Acknowledge for Update" "0: Time and calendar registers cannot be updated.,1: Time and calendar registers can be updated."
|
|
wgroup.long 0x1C++0xB
|
|
line.long 0x0 "SCCR,Status Clear Command Register"
|
|
bitfld.long 0x0 5. "TDERRCLR,Time and/or Date Free Running Error Clear" "0,1"
|
|
bitfld.long 0x0 4. "CALCLR,Calendar Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIMCLR,Time Clear" "0,1"
|
|
bitfld.long 0x0 2. "SECCLR,Second Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALRCLR,Alarm Clear" "0,1"
|
|
bitfld.long 0x0 0. "ACKCLR,Acknowledge Clear" "0,1"
|
|
line.long 0x4 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x4 5. "TDERREN,Time and/or Date Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "CALEN,Calendar Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TIMEN,Time Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "SECEN,Second Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALREN,Alarm Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "ACKEN,Acknowledge Update Interrupt Enable" "0,1"
|
|
line.long 0x8 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x8 5. "TDERRDIS,Time and/or Date Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 4. "CALDIS,Calendar Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "TIMDIS,Time Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 2. "SECDIS,Second Event Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "ALRDIS,Alarm Interrupt Disable" "0,1"
|
|
bitfld.long 0x8 0. "ACKDIS,Acknowledge Update Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 5. "TDERR,Time and/or Date Error Mask" "0,1"
|
|
bitfld.long 0x0 4. "CAL,Calendar Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIM,Time Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "SEC,Second Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ALR,Alarm Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "ACK,Acknowledge Update Interrupt Mask" "0,1"
|
|
line.long 0x4 "VER,Valid Entry Register"
|
|
bitfld.long 0x4 3. "NVCALALR,Non-valid Calendar Alarm" "0,1"
|
|
bitfld.long 0x4 2. "NVTIMALR,Non-valid Time Alarm" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "NVCAL,Non-valid Calendar" "0,1"
|
|
bitfld.long 0x4 0. "NVTIM,Non-valid Time" "0,1"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "TCR,Tamper Control Register"
|
|
bitfld.long 0x0 17. "FGPBRCLR,Full GPBR Clear" "0: If TAMPCLR is set to '1' a tamper event..,1: If TAMPCLR is set to '1' a tamper event.."
|
|
bitfld.long 0x0 16. "TAMPCLR,Tamper Clear" "0: A Tamper event does not create an immediate..,1: Tamper event on TMP0 or TMP4 generates an.."
|
|
newline
|
|
bitfld.long 0x0 4. "TAMPEN4,Timestamping on TMPx input is enabled" "0: Tamper event on TMPx input is not timestamped.,1: Tamper event on TMPx input is timestamped."
|
|
bitfld.long 0x0 3. "TAMPEN3,Timestamping on TMPx input is enabled" "0: Tamper event on TMPx input is not timestamped.,1: Tamper event on TMPx input is timestamped."
|
|
newline
|
|
bitfld.long 0x0 2. "TAMPEN2,Timestamping on TMPx input is enabled" "0: Tamper event on TMPx input is not timestamped.,1: Tamper event on TMPx input is timestamped."
|
|
bitfld.long 0x0 1. "TAMPEN1,Timestamping on TMPx input is enabled" "0: Tamper event on TMPx input is not timestamped.,1: Tamper event on TMPx input is timestamped."
|
|
newline
|
|
bitfld.long 0x0 0. "TAMPEN0,Timestamping on TMPx input is enabled" "0: Tamper event on TMPx input is not timestamped.,1: Tamper event on TMPx input is timestamped."
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "TISR,Tamper Input Status Register"
|
|
bitfld.long 0x0 4. "TISR4,TMPx Input Status Register" "0,1"
|
|
bitfld.long 0x0 3. "TISR3,TMPx Input Status Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TISR2,TMPx Input Status Register" "0,1"
|
|
bitfld.long 0x0 1. "TISR1,TMPx Input Status Register" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TISR0,TMPx Input Status Register" "0,1"
|
|
repeat 5. (list 0x0 0x1 0x2 0x3 0x4)(list ad:0x40053140 ad:0x40053150 ad:0x40053160 ad:0x40053170 ad:0x40053180)
|
|
tree "RTC_SUB0[$1]"
|
|
base $2
|
|
rgroup.long ($2)++0x3
|
|
line.long 0x0 "FSTR,First Stamping Time Register of Source 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_LSDRx)" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_LSDRx)"
|
|
bitfld.long 0x0 22. "AMPM,AM/PM Indicator of the Tamper (cleared by reading RTC_LSDRx)" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "HOUR,Hours of the Tamper (cleared by reading RTC_LSDRx)"
|
|
hexmask.long.byte 0x0 8.--14. 1. "MIN,Minutes of the Tamper (cleared by reading RTC_LSDRx)"
|
|
hexmask.long.byte 0x0 0.--6. 1. "SEC,Seconds of the Tamper (cleared by reading RTC_LSDRx)"
|
|
rgroup.long ($2)++0x7
|
|
line.long 0x0 "FSTR_UTC_MODE_MODE,First Stamping Time Register of Source 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_LSDRx)" "0,1"
|
|
hexmask.long.byte 0x0 24.--27. 1. "TEVCNT,Tamper Events Counter (cleared by reading RTC_LSDRx)"
|
|
line.long 0x4 "FSDR,First Stamping Date Register of Source 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date of the Tamper (cleared by reading RTC_LSDRx)"
|
|
bitfld.long 0x4 21.--23. "DAY,Day of the Tamper (cleared by reading RTC_LSDRx)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month of the Tamper (cleared by reading RTC_LSDRx)"
|
|
hexmask.long.byte 0x4 8.--14. 1. "YEAR,Year of the Tamper (cleared by reading RTC_LSDRx)"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Century of the Tamper (cleared by reading RTC_LSDRx)"
|
|
rgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "FSDR_UTC_MODE_MODE,First Stamping Date Register of Source 0"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Time of the Tamper (cleared by reading RTC_LSDRx)"
|
|
line.long 0x4 "LSTR,Last Stamping Time Register of Source 0"
|
|
bitfld.long 0x4 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_LSDRx)" "0,1"
|
|
bitfld.long 0x4 22. "AMPM,AM/PM Indicator of the Tamper (cleared by reading RTC_LSDRx)" "0,1"
|
|
hexmask.long.byte 0x4 16.--21. 1. "HOUR,Hours of the Tamper (cleared by reading RTC_LSDRx)"
|
|
hexmask.long.byte 0x4 8.--14. 1. "MIN,Minutes of the Tamper (cleared by reading RTC_LSDRx)"
|
|
hexmask.long.byte 0x4 0.--6. 1. "SEC,Seconds of the Tamper (cleared by reading RTC_LSDRx)"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "LSTR_UTC_MODE_MODE,Last Stamping Time Register of Source 0"
|
|
bitfld.long 0x0 31. "BACKUP,System Mode of the Tamper (cleared by reading RTC_LSDRx)" "0,1"
|
|
line.long 0x4 "LSDR,Last Stamping Date Register of Source 0"
|
|
hexmask.long.byte 0x4 24.--29. 1. "DATE,Date of the Tamper (cleared on read)"
|
|
bitfld.long 0x4 21.--23. "DAY,Day of the Tamper (cleared on read)" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 16.--20. 1. "MONTH,Month of the Tamper (cleared on read)"
|
|
hexmask.long.byte 0x4 8.--14. 1. "YEAR,Year of the Tamper (cleared on read)"
|
|
hexmask.long.byte 0x4 0.--6. 1. "CENT,Century of the Tamper (cleared on read)"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "LSDR_UTC_MODE_MODE,Last Stamping Date Register of Source 0"
|
|
hexmask.long 0x0 0.--31. 1. "UTC_TIME,Time of the Tamper (cleared on read)"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "RTT (Real-Time Timer)"
|
|
base ad:0x40053020
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24. "RTC1HZ,Real-Time Clock 1Hz Clock Selection" "0,1"
|
|
bitfld.long 0x0 21. "INC2AEN,RTTINC2 Alarm and Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 20. "RTTDIS,Real-time Timer Disable" "0,1"
|
|
bitfld.long 0x0 18. "RTTRST,Real-time Timer Restart" "0,1"
|
|
bitfld.long 0x0 17. "RTTINCIEN,Real-time Timer Increment Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "ALMIEN,Alarm Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "RTPRES,Real-time Timer Prescaler Value"
|
|
line.long 0x4 "AR,Alarm Register"
|
|
hexmask.long 0x4 0.--31. 1. "ALMV,Alarm Value"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "VR,Value Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRTV,Current Real-time Value"
|
|
line.long 0x4 "SR,Status Register"
|
|
bitfld.long 0x4 2. "RTTINC2,Predefined Number of Prescaler Roll-overs Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "RTTINC,Prescaler Roll-over Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "ALMS,Real-time Alarm Status (cleared on read)" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "MODR,Modulo Selection Register"
|
|
bitfld.long 0x0 0.--2. "SELINC2,Selection of the 32-bit Counter Modulo to generate RTTINC2 Flag" "0: The RTTINC2 flag never rises,1: The RTTINC2 flag is set when CRTV modulo 64..,2: The RTTINC2 flag is set when CRTV modulo 128..,3: The RTTINC2 flag is set when CRTV modulo 256..,4: The RTTINC2 flag is set when CRTV modulo 512..,5: The RTTINC2 flag is set when CRTV modulo 1024..,6: The RTTINC2 flag is set when CRTV modulo 2048..,7: The RTTINC2 flag is set when CRTV modulo 4096.."
|
|
tree.end
|
|
tree "SEFC (Secure Embedded Flash Controller)"
|
|
base ad:0x0
|
|
tree "SEFC0"
|
|
base ad:0x460E0000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "EEFC_FMR,SEFC Flash Mode Register"
|
|
bitfld.long 0x0 27. "ALWAYS1,Always Written to One" "0,1"
|
|
bitfld.long 0x0 26. "CLOE,Code Loop Optimization Enable" "0,1"
|
|
bitfld.long 0x0 16. "SCOD,Sequential Code Optimization Disable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FWS,Flash Wait State"
|
|
bitfld.long 0x0 0. "FRDY,Flash Ready Interrupt Enable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "EEFC_FCR,SEFC Flash Command Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FKEY,Flash Writing Protection Key"
|
|
hexmask.long.word 0x0 8.--23. 1. "FARG,Flash Command Argument"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCMD,Flash Command"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "EEFC_FSR,SEFC Flash Status Register"
|
|
bitfld.long 0x0 23. "MECCEMSBL,Multiple ECC Error on MSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 22. "SECCEMSBL,Single ECC Error on MSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 21. "MECCELSBL,Multiple ECC Error on LSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 20. "SECCELSBL,Single ECC Error on LSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 19. "MECCEMSBD,Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x0 18. "SECCEMSBD,Single ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x0 17. "MECCELSBD,Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "SECCELSBD,Single ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FLSUSP,Flash Suspended Status (cleared when resuming the programming operation)" "0,1"
|
|
bitfld.long 0x0 4. "WPERR,Write Protection Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "FLERR,Flash Error Status (cleared when a programming operation starts)" "0,1"
|
|
bitfld.long 0x0 2. "FLOCKE,Flash Lock Error Status (cleared on read or by writing EEFC_FCR)" "0,1"
|
|
bitfld.long 0x0 1. "FCMDE,Flash Command Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "FRDY,Flash Ready Status (cleared when Flash is busy)" "0,1"
|
|
line.long 0x4 "EEFC_FRR,SEFC Flash Result Register"
|
|
hexmask.long 0x4 0.--31. 1. "FVALUE,Flash Result Value"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "EEFC_USR,SEFC User Signature Rights Register"
|
|
bitfld.long 0x0 31. "LOCKUSRB7,Lock User Signature Rights for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 30. "LOCKUSRB6,Lock User Signature Rights for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 29. "LOCKUSRB5,Lock User Signature Rights for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 28. "LOCKUSRB4,Lock User Signature Rights for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 27. "LOCKUSRB3,Lock User Signature Rights for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 26. "LOCKUSRB2,Lock User Signature Rights for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 25. "LOCKUSRB1,Lock User Signature Rights for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 24. "LOCKUSRB0,Lock User Signature Rights for User Signature Block 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PRIVUSB7,Privileged Access for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 22. "PRIVUSB6,Privileged Access for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 21. "PRIVUSB5,Privileged Access for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 20. "PRIVUSB4,Privileged Access for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 19. "PRIVUSB3,Privileged Access for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 18. "PRIVUSB2,Privileged Access for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 17. "PRIVUSB1,Privileged Access for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 16. "PRIVUSB0,Privileged Access for User Signature Block 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "WRENUSB7,Write Enable for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 14. "WRENUSB6,Write Enable for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 13. "WRENUSB5,Write Enable for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 12. "WRENUSB4,Write Enable for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 11. "WRENUSB3,Write Enable for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 10. "WRENUSB2,Write Enable for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 9. "WRENUSB1,Write Enable for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 8. "WRENUSB0,Write Enable for User Signature Block 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RDENUSB7,Read Enable for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 6. "RDENUSB6,Read Enable for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 5. "RDENUSB5,Read Enable for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 4. "RDENUSB4,Read Enable for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 3. "RDENUSB3,Read Enable for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 2. "RDENUSB2,Read Enable for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 1. "RDENUSB1,Read Enable for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 0. "RDENUSB0,Read Enable for User Signature Block 0" "0,1"
|
|
line.long 0x4 "EEFC_KBLR,SEFC Key Bus Lock Register"
|
|
bitfld.long 0x4 7. "KBTLUSB7,Key Bus Transfer Lock from User Signature Block 7" "0,1"
|
|
bitfld.long 0x4 6. "KBTLUSB6,Key Bus Transfer Lock from User Signature Block 6" "0,1"
|
|
bitfld.long 0x4 5. "KBTLUSB5,Key Bus Transfer Lock from User Signature Block 5" "0,1"
|
|
bitfld.long 0x4 4. "KBTLUSB4,Key Bus Transfer Lock from User Signature Block 4" "0,1"
|
|
bitfld.long 0x4 3. "KBTLUSB3,Key Bus Transfer Lock from User Signature Block 3" "0,1"
|
|
bitfld.long 0x4 2. "KBTLUSB2,Key Bus Transfer Lock from User Signature Block 2" "0,1"
|
|
bitfld.long 0x4 1. "KBTLUSB1,Key Bus Transfer Lock from User Signature Block 1" "0,1"
|
|
bitfld.long 0x4 0. "KBTLUSB0,Key Bus Transfer Lock from User Signature Block 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "EEFC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "ERASEWL,Erase and Write Lock" "0,1"
|
|
bitfld.long 0x0 4. "USRWP,User Signature Write Protection" "0,1"
|
|
bitfld.long 0x0 3. "ERASEWP,Erase and Write Protection" "0,1"
|
|
bitfld.long 0x0 2. "LOCKWP,Lock Bit Write Protection" "0,1"
|
|
bitfld.long 0x0 1. "GPNVMWP,GPNVM Bit Write Protection" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree "SEFC1"
|
|
base ad:0x460E0200
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "EEFC_FMR,SEFC Flash Mode Register"
|
|
bitfld.long 0x0 27. "ALWAYS1,Always Written to One" "0,1"
|
|
bitfld.long 0x0 26. "CLOE,Code Loop Optimization Enable" "0,1"
|
|
bitfld.long 0x0 16. "SCOD,Sequential Code Optimization Disable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FWS,Flash Wait State"
|
|
bitfld.long 0x0 0. "FRDY,Flash Ready Interrupt Enable" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "EEFC_FCR,SEFC Flash Command Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "FKEY,Flash Writing Protection Key"
|
|
hexmask.long.word 0x0 8.--23. 1. "FARG,Flash Command Argument"
|
|
hexmask.long.byte 0x0 0.--7. 1. "FCMD,Flash Command"
|
|
rgroup.long 0x8++0x7
|
|
line.long 0x0 "EEFC_FSR,SEFC Flash Status Register"
|
|
bitfld.long 0x0 23. "MECCEMSBL,Multiple ECC Error on MSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 22. "SECCEMSBL,Single ECC Error on MSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 21. "MECCELSBL,Multiple ECC Error on LSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 20. "SECCELSBL,Single ECC Error on LSB Part of the Memory Lock Bits" "0,1"
|
|
bitfld.long 0x0 19. "MECCEMSBD,Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x0 18. "SECCEMSBD,Single ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x0 17. "MECCELSBD,Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "SECCELSBD,Single ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "FLSUSP,Flash Suspended Status (cleared when resuming the programming operation)" "0,1"
|
|
bitfld.long 0x0 4. "WPERR,Write Protection Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "FLERR,Flash Error Status (cleared when a programming operation starts)" "0,1"
|
|
bitfld.long 0x0 2. "FLOCKE,Flash Lock Error Status (cleared on read or by writing EEFC_FCR)" "0,1"
|
|
bitfld.long 0x0 1. "FCMDE,Flash Command Error Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "FRDY,Flash Ready Status (cleared when Flash is busy)" "0,1"
|
|
line.long 0x4 "EEFC_FRR,SEFC Flash Result Register"
|
|
hexmask.long 0x4 0.--31. 1. "FVALUE,Flash Result Value"
|
|
group.long 0x10++0x7
|
|
line.long 0x0 "EEFC_USR,SEFC User Signature Rights Register"
|
|
bitfld.long 0x0 31. "LOCKUSRB7,Lock User Signature Rights for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 30. "LOCKUSRB6,Lock User Signature Rights for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 29. "LOCKUSRB5,Lock User Signature Rights for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 28. "LOCKUSRB4,Lock User Signature Rights for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 27. "LOCKUSRB3,Lock User Signature Rights for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 26. "LOCKUSRB2,Lock User Signature Rights for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 25. "LOCKUSRB1,Lock User Signature Rights for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 24. "LOCKUSRB0,Lock User Signature Rights for User Signature Block 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "PRIVUSB7,Privileged Access for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 22. "PRIVUSB6,Privileged Access for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 21. "PRIVUSB5,Privileged Access for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 20. "PRIVUSB4,Privileged Access for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 19. "PRIVUSB3,Privileged Access for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 18. "PRIVUSB2,Privileged Access for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 17. "PRIVUSB1,Privileged Access for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 16. "PRIVUSB0,Privileged Access for User Signature Block 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "WRENUSB7,Write Enable for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 14. "WRENUSB6,Write Enable for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 13. "WRENUSB5,Write Enable for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 12. "WRENUSB4,Write Enable for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 11. "WRENUSB3,Write Enable for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 10. "WRENUSB2,Write Enable for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 9. "WRENUSB1,Write Enable for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 8. "WRENUSB0,Write Enable for User Signature Block 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RDENUSB7,Read Enable for User Signature Block 7" "0,1"
|
|
bitfld.long 0x0 6. "RDENUSB6,Read Enable for User Signature Block 6" "0,1"
|
|
bitfld.long 0x0 5. "RDENUSB5,Read Enable for User Signature Block 5" "0,1"
|
|
bitfld.long 0x0 4. "RDENUSB4,Read Enable for User Signature Block 4" "0,1"
|
|
bitfld.long 0x0 3. "RDENUSB3,Read Enable for User Signature Block 3" "0,1"
|
|
bitfld.long 0x0 2. "RDENUSB2,Read Enable for User Signature Block 2" "0,1"
|
|
bitfld.long 0x0 1. "RDENUSB1,Read Enable for User Signature Block 1" "0,1"
|
|
bitfld.long 0x0 0. "RDENUSB0,Read Enable for User Signature Block 0" "0,1"
|
|
line.long 0x4 "EEFC_KBLR,SEFC Key Bus Lock Register"
|
|
bitfld.long 0x4 7. "KBTLUSB7,Key Bus Transfer Lock from User Signature Block 7" "0,1"
|
|
bitfld.long 0x4 6. "KBTLUSB6,Key Bus Transfer Lock from User Signature Block 6" "0,1"
|
|
bitfld.long 0x4 5. "KBTLUSB5,Key Bus Transfer Lock from User Signature Block 5" "0,1"
|
|
bitfld.long 0x4 4. "KBTLUSB4,Key Bus Transfer Lock from User Signature Block 4" "0,1"
|
|
bitfld.long 0x4 3. "KBTLUSB3,Key Bus Transfer Lock from User Signature Block 3" "0,1"
|
|
bitfld.long 0x4 2. "KBTLUSB2,Key Bus Transfer Lock from User Signature Block 2" "0,1"
|
|
bitfld.long 0x4 1. "KBTLUSB1,Key Bus Transfer Lock from User Signature Block 1" "0,1"
|
|
bitfld.long 0x4 0. "KBTLUSB0,Key Bus Transfer Lock from User Signature Block 0" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "EEFC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 7. "ERASEWL,Erase and Write Lock" "0,1"
|
|
bitfld.long 0x0 4. "USRWP,User Signature Write Protection" "0,1"
|
|
bitfld.long 0x0 3. "ERASEWP,Erase and Write Protection" "0,1"
|
|
bitfld.long 0x0 2. "LOCKWP,Lock Bit Write Protection" "0,1"
|
|
bitfld.long 0x0 1. "GPNVMWP,GPNVM Bit Write Protection" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SFR (Special Function Registers)"
|
|
base ad:0x40050400
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "SRAM0_SW_CFG,SRAM0 Software Config Register"
|
|
bitfld.long 0x0 16. "CLKG_DIS,Clock Gating Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "M512SD,512 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "M512DS,512 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "M512LS,512 KB Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "M384SD,384 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M384DS,384 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M384LS,384 KB Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "M256SD,256 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "M256DS,256 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "M256LS,256 KB Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M128SD,128 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M128DS,128 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M128LS,128 KB Light Sleep Mode" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "SRAM0_HW_CFG,SRAM0 Hardware Status Register"
|
|
bitfld.long 0x0 14. "M512SD,512 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "M512DS,512 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "M512LS,512 KB Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "M384SD,384 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "M384DS,384 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "M384LS,384 KB Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "M256SD,256 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "M256DS,256 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "M256LS,256 KB Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "M128SD,128 KB Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "M128DS,128 KB Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "M128LS,128 KB Light Sleep Mode" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "SRAM0_CH[$1],SRAM0 Read Margin Register Channel"
|
|
bitfld.long 0x0 28. "RME3,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "RM3,Read Margin"
|
|
newline
|
|
bitfld.long 0x0 20. "RME2,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "RM2,Read Margin"
|
|
newline
|
|
bitfld.long 0x0 12. "RME1,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RM1,Read Margin"
|
|
newline
|
|
bitfld.long 0x0 4. "RME0,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RM0,Read Margin"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "SRAM[$1],SRAM Configuration Register"
|
|
bitfld.long 0x0 26. "SD,Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DS,Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "LS,Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "RME3,Read Margin Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "RME2,Read Margin Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RME1,Read Margin Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RME0,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--15. 1. "RM3,Read Margin"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "RM2,Read Margin"
|
|
newline
|
|
hexmask.long.byte 0x0 4.--7. 1. "RM1,Read Margin"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RM0,Read Margin"
|
|
repeat.end
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CPKCC,CPKCC Memory Configuration Register"
|
|
bitfld.long 0x0 26. "RAM_SD,Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "RAM_DS,RAM Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "RAM_LS,RAM Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "RAM_RME,RAM Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "RAM_RM,RAM Read Margin"
|
|
newline
|
|
bitfld.long 0x0 9. "ROM_SD,Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ROM_LS,ROM Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "ROM_RME,ROM Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "ROM_RM,ROM Read Margin"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "HROMC,HROMC Memory Configuration Register"
|
|
bitfld.long 0x0 9. "SD,Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LS,HROMC Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RME,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RM,Read Margin"
|
|
group.long 0x50++0xB
|
|
line.long 0x0 "HCACHEI_VALID,HCACHEI Valid Memory Configuration Register"
|
|
bitfld.long 0x0 10. "SD,Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DS,Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LS,Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RME,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RM,Read Margin"
|
|
line.long 0x4 "HCACHEI_DATA,HCACHEI Data Memory Configuration Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SD,Shutdown Mode"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "DS,Deep Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "LS,Light Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RME,Read Margin Enable"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RM,Read Margin"
|
|
line.long 0x8 "HCACHEI_TAG,HCACHEI Tag Memory Configuration Register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SD,Shutdown Mode"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--27. 1. "DS,Deep Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "LS,Light Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "RME,Read Margin Enable"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RM,Read Margin"
|
|
group.long 0x60++0xB
|
|
line.long 0x0 "HCACHED_VALID,HCACHED Valid Memory Configuration Register"
|
|
bitfld.long 0x0 10. "SD,Shutdown Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "DS,Deep Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LS,Light Sleep Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RME,Read Margin Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RM,Read Margin"
|
|
line.long 0x4 "HCACHED_DATA,HCACHED Data Memory Configuration Register"
|
|
hexmask.long.byte 0x4 28.--31. 1. "SD,Shutdown Mode"
|
|
newline
|
|
hexmask.long.byte 0x4 24.--27. 1. "DS,Deep Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x4 20.--23. 1. "LS,Light Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x4 16.--19. 1. "RME,Read Margin Enable"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "RM,Read Margin"
|
|
line.long 0x8 "HCACHED_TAG,HCACHEDTag Memory Configuration Register"
|
|
hexmask.long.byte 0x8 28.--31. 1. "SD,Shutdown Mode"
|
|
newline
|
|
hexmask.long.byte 0x8 24.--27. 1. "DS,Deep Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x8 20.--23. 1. "LS,Light Sleep Mode"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "RME,Read Margin Enable"
|
|
newline
|
|
hexmask.long.word 0x8 0.--15. 1. "RM,Read Margin"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "FLASH,Flash Memory Configuration Register"
|
|
bitfld.long 0x0 0. "PATCH_BYPASS," "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "OPT_LINK,Optical Link Register"
|
|
bitfld.long 0x0 0. "CLK_SELECT,Clock Selection" "0,1"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "JTAG,JTAG Register"
|
|
bitfld.long 0x0 0. "JTAG_LOCK,JTAG Lock" "0,1"
|
|
group.long 0xA0++0xB
|
|
line.long 0x0 "CORE_DEBUG_CFG,Core Debug Configuration Register"
|
|
bitfld.long 0x0 2. "XTRG0,From Core 0 to Core 1 Cross Triggering" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "XTRG1,From Core 1 to Core 0 Cross Triggering" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWV,SWV Selection" "0,1"
|
|
line.long 0x4 "EMAHB2AHB,AHB2AHB Configuration Register"
|
|
bitfld.long 0x4 1. "PFETCH8_1_0,AHB MASTER1_0 Converter Prefetch" "0: INCR undefined burst converted to burst of 4 data.,1: INCR undefined burst converted to burst of 8 data."
|
|
newline
|
|
bitfld.long 0x4 0. "PFETCH8_0_1,AHB MASTER0_1 Converter Prefetch" "0: INCR undefined burst converted to burst of 4 data.,1: INCR undefined burst converted to burst of 8 data."
|
|
line.long 0x8 "SECURE,Secure Register"
|
|
bitfld.long 0x8 0. "ROM_ENA,ROM Access Enable" "0,1"
|
|
rgroup.long 0xAC++0x3
|
|
line.long 0x0 "SECURE_BIT,Secure Bit Register"
|
|
bitfld.long 0x0 0. "MODE_DIS,Secure Mode" "0,1"
|
|
group.long 0xB0++0x7
|
|
line.long 0x0 "ERASE_FLASH_SRAM,Erase Flash/SRAM Register"
|
|
bitfld.long 0x0 1. "SRAM0,Erase SRAM0 Content" "0: If HW_ERASE = 1 and HW erase signal assertion..,1: If HW_ERASE = 1 and HW erase signal assertion.."
|
|
newline
|
|
bitfld.long 0x0 0. "HW_ERASE,PB2/Peripherals or Hardware Erase Signal Assignment" "0: Hardware erase signal disabled. PB2 pin can be..,1: Hardware erase signal enabled. PB2 pin is.."
|
|
line.long 0x4 "PWM_DEBUG,PWM Debug Register"
|
|
bitfld.long 0x4 1. "CORE1,Debug Information Propagation Mode" "0: Core x does not send the debug signal to the PWM.,1: Core x sends the debug signal to PWM. Refer to.."
|
|
newline
|
|
bitfld.long 0x4 0. "CORE0,Debug Information Propagation Mode" "0: Core x does not send the debug signal to the PWM.,1: Core x sends the debug signal to PWM. Refer to.."
|
|
rgroup.long 0xB8++0x3
|
|
line.long 0x0 "FFPI,FFPI Register"
|
|
bitfld.long 0x0 0. "MODE,FFPI Status" "0,1"
|
|
group.long 0xBC++0x3
|
|
line.long 0x0 "WAIT_MODE,Improved Wait Mode Register"
|
|
bitfld.long 0x0 0. "CONTROL,Improved Wait Mode Control" "0,1"
|
|
rgroup.long 0xC0++0x3
|
|
line.long 0x0 "ROM_CODE,ROM Code Register"
|
|
bitfld.long 0x0 3. "FORCE_BYPASS_VALUE," "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FORCE_BYPASS," "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "PLLA_STATUS,PLLA Status" "0,1,2,3"
|
|
group.long 0xE4++0x7
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
newline
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
line.long 0x4 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x4 8.--23. 1. "WPSRC,Write Protection Source"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "SPARE,Spare Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Spare"
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x0 "VERSION,Version Register"
|
|
bitfld.long 0x0 16.--18. "MFN,Metal Fix Number" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.word 0x0 0.--11. 1. "VERSION,Version of the Hardware Module"
|
|
tree.end
|
|
tree "SFRBU (Special Function Registers Backup)"
|
|
base ad:0x40050600
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "XTAL_TRIM,XTAL Oscillator Trimming Register"
|
|
bitfld.long 0x0 0.--1. "XTAL_TRIM,32 kHz Crystal Oscillator Trimming Value" "0,1,2,3"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "TRIM,Trimming Bits Register"
|
|
hexmask.long.byte 0x0 24.--27. 1. "LCD,LDO Internal Bandgap Trimming for LCD Driver"
|
|
hexmask.long.byte 0x0 16.--19. 1. "LDO,Power Management IP LDO Trimming Value"
|
|
hexmask.long.byte 0x0 8.--11. 1. "CONVBG,Conversion IP Bandgap Trimming Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "RC32,RC Oscillator Trimming Value"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BOOT,Boot Register"
|
|
bitfld.long 0x0 0. "SOURCE,Source for Booting Sequence" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "IO_RETENTION,IO Retention Register"
|
|
bitfld.long 0x0 16. "NRST,Keep Function on NRST" "0,1"
|
|
bitfld.long 0x0 15. "PD_30_24,Keep Function on PD24 to PD30" "0,1"
|
|
bitfld.long 0x0 14. "PD_23_16,Keep Function on PD16 to PD23" "0,1"
|
|
bitfld.long 0x0 13. "PD_15_8,Keep Function on PD8 to PD15" "0,1"
|
|
bitfld.long 0x0 12. "PD_7_0,Keep Function on PD0 to PD7" "0,1"
|
|
bitfld.long 0x0 10. "PC_22_16,Keep Function on PC16 to PC22" "0,1"
|
|
bitfld.long 0x0 9. "PC_15_8,Keep Function on PC8 to PC15" "0,1"
|
|
bitfld.long 0x0 8. "PC_7_0,Keep Function on PC0 to PC7" "0,1"
|
|
bitfld.long 0x0 7. "PB_26_24,Keep Function on PB24 to PB26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "PB_23_16,Keep Function on PB216 to PB23" "0,1"
|
|
bitfld.long 0x0 5. "PB_15_8,Keep Function on PB8 to PB15" "0,1"
|
|
bitfld.long 0x0 4. "PB_7_0,Keep Function on PB0 to PB7" "0,1"
|
|
bitfld.long 0x0 3. "PA_31_24,Keep Function on PA24 to PA31" "0,1"
|
|
bitfld.long 0x0 2. "PA_23_16,Keep Function on PA16 to PA23" "0,1"
|
|
bitfld.long 0x0 1. "PA_15_8,Keep Function on PA8 to PA15" "0,1"
|
|
bitfld.long 0x0 0. "PA_7_0,Keep Function on PA0 to PA7" "0,1"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "BODCORE,BOD Core Register"
|
|
bitfld.long 0x0 0. "STATUS,Core Brownout Detector" "0,1"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PWS_CNTRL,Power Switch Control Register"
|
|
bitfld.long 0x0 0. "UNMASK,Unmask Power Switch Control Signals" "0,1"
|
|
group.long 0xE4++0x7
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
line.long 0x4 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x4 8.--23. 1. "WPSRC,Write Protection Source"
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "SPARE,Spare Register"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Spare"
|
|
tree.end
|
|
tree "SHA (Secure Hash Algorithm)"
|
|
base ad:0x44008000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 24. "UNLOCK,Unlock Processing" "0,1"
|
|
bitfld.long 0x0 13. "WUIEHV,Write User Initial or Expected Hash Values" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "WUIHV,Write User Initial Hash Values" "0,1"
|
|
bitfld.long 0x0 8. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FIRST,First Block of a Message" "0,1"
|
|
bitfld.long 0x0 0. "START,Start Processing" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "CHKCNT,Check Counter"
|
|
bitfld.long 0x0 24.--25. "CHECK,Hash Check" "0: No check is performed,1: Check is performed with expected hash stored in..,2: Check is performed with expected hash provided..,?"
|
|
newline
|
|
bitfld.long 0x0 16. "DUALBUFF,Dual Input Buffer" "0: SHA_IDATARx and SHA_IODATARx cannot be written..,1: SHA_IDATARx and SHA_IODATARx can be written.."
|
|
bitfld.long 0x0 15. "TMPLCK,Tamper Lock Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "ALGO,SHA Algorithm"
|
|
bitfld.long 0x0 7. "BPE,Block Processing End" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "UIEHV,User Initial or Expected Hash Value Registers" "0,1"
|
|
bitfld.long 0x0 5. "UIHV,User Initial Hash Value Registers" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PROCDLY,Processing Delay" "0: SHA processing runtime is the shortest one,1: SHA processing runtime is the longest one.."
|
|
bitfld.long 0x0 3. "AOE,Always ON Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SMOD,Start Mode" "0: Manual mode,1: Auto mode,2: SHA_IDATAR0 access only mode (mandatory when DMA..,?"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 24. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 2. "TXBUFE,Transmit Buffer Empty Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENDTX,End of Transmit Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 2. "TXBUFE,Transmit Buffer Empty Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENDTX,End of Transmit Buffer Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 24. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "CHECKF,Check Done Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "URAD,Unspecified Register Access Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 2. "TXBUFE,Transmit Buffer Empty Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENDTX,End of Transmit Buffer Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 24. "SECE,Security and/or Safety Event" "0,1"
|
|
hexmask.long.byte 0x4 20.--23. 1. "CHKST,Check Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)"
|
|
newline
|
|
bitfld.long 0x4 16. "CHECKF,Check Done Status (cleared by writing START or SWRST bits in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
bitfld.long 0x4 12.--14. "URAT,Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 8. "URAD,Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR)" "0,1"
|
|
bitfld.long 0x4 4. "WRDY,Input Data Register Write Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "TXBUFE,TX Buffer Empty (cleared by writing SHA_TCR or SHA_TNCR)" "0,1"
|
|
bitfld.long 0x4 1. "ENDTX,End of TX Buffer (cleared by writing SHA_TCR or SHA_TNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR or by reading SHA_IODATARx)" "0,1"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "MSR,Message Size Register"
|
|
hexmask.long 0x0 0.--31. 1. "MSGSIZE,Message Size"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "BCR,Bytes Count Register"
|
|
hexmask.long 0x0 0.--31. 1. "BYTCNT,Remaining Byte Count Before Auto Padding"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
wgroup.long ($2+0x40)++0x3
|
|
line.long 0x0 "IDATAR[$1],Input Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IDATA,Input Data"
|
|
repeat.end
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "IODATAR[$1],Input/Output Data 0 Register"
|
|
hexmask.long 0x0 0.--31. 1. "IODATA,Input/Output Data"
|
|
repeat.end
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 5.--6. "ACTION,Action on Abnormal Event Detection" "0: No action (stop or clear key) is performed when..,1: If a processing is in progress when the..,2: If a processing is in progress when the..,3: If a processing is in progress when the.."
|
|
newline
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interruption Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Configuration Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: An access is performed into key input data.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
group.long 0x108++0x7
|
|
line.long 0x0 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0x4 "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
group.long 0x118++0x7
|
|
line.long 0x0 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x4 "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
sif (cpuis("PIC32C?1025MTG128*")||cpuis("PIC32C?2051MTG128*")||cpuis("PIC32C?5112MTG128*"))
|
|
tree "SLCDC (Segment LCD Controller)"
|
|
base ad:0x40030000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "FRZKEY,Freeze Key (write-only)"
|
|
bitfld.long 0x0 7. "FRZMAP,Freeze Remap Configuration" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FRZDF,Freeze Display Panel Features Configuration" "0,1"
|
|
bitfld.long 0x0 3. "SWRST,Software Reset" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LCDDIS,Disable LCDC" "0,1"
|
|
bitfld.long 0x0 0. "LCDEN,Enable the LCDC" "0,1"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 24. "LPMODE,Low-Power Mode" "0,1"
|
|
bitfld.long 0x0 20.--21. "BIAS,LCD Display Configuration" "0: Static,1: Bias 1/2,2: Bias 1/3,3: Bias 1/4"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "BUFTIME,Buffer On-Time"
|
|
hexmask.long.byte 0x0 8.--13. 1. "SEGSEL,Selection of the Number of Segments"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "COMSEL,Selection of the Number of Commons" "0: COM0 is driven by SLCDC COM1:7 are driven by..,1: COM0:1 are driven by SLCDC COM2:7 are driven by..,2: COM0:2 are driven by SLCDC COM3:7 are driven by..,3: COM0:3 are driven by SLCDC COM4:7 are driven by..,4: COM0:4 are driven by SLCDC COM5:7 are driven by..,5: COM0:5 are driven by SLCDC COM6:7 are driven by..,6: COM0:6 are driven by SLCDC COM7 driven by..,7: COM0:7 are driven by SLCDC no COM pin driven by.."
|
|
line.long 0x4 "FRR,Frame Rate Register"
|
|
bitfld.long 0x4 8.--10. "DIV,Clock Division" "0: Clock output from prescaler is divided by 1,1: Clock output from prescaler is divided by 2,2: Clock output from prescaler is divided by 3,3: Clock output from prescaler is divided by 4,4: Clock output from prescaler is divided by 5,5: Clock output from prescaler is divided by 6,6: Clock output from prescaler is divided by 7,7: Clock output from prescaler is divided by 8"
|
|
bitfld.long 0x4 0.--2. "PRESC,Clock Prescaler" "0: Slow clock is divided by 8,1: Slow clock is divided by 16,2: Slow clock is divided by 32,3: Slow clock is divided by 64,4: Slow clock is divided by 128,5: Slow clock is divided by 256,6: Slow clock is divided by 512,7: Slow clock is divided by 1024"
|
|
line.long 0x8 "DR,Display Register"
|
|
hexmask.long.byte 0x8 8.--15. 1. "LCDBLKFREQ,LCD Blinking Frequency Selection"
|
|
bitfld.long 0x8 0.--2. "DISPMODE,Display Mode Register" "0: Normal Mode-Latched data are displayed.,1: Force Off Mode-All pixels are invisible. (The..,2: Force On Mode-All pixels are visible. (The SLCDC..,3: Blinking Mode-All pixels are alternately turned..,4: Inverted Mode-All pixels are set in the inverted..,5: Inverted Blinking Mode-All pixels are..,6: User Buffer Only Load Mode-Blocks the automatic..,7: Buffer Swap Mode-All pixels are alternatively.."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SR,Status Register"
|
|
bitfld.long 0x0 7. "MAPFRZS,Remapping Configuration Freeze Status" "0,1"
|
|
bitfld.long 0x0 6. "DFFRZS,Display Panel Features Configuration Freeze Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "ENA,Enable Status (Automatically Set/Reset)" "0,1"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "DIS,Disable Completion Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "ENDFRAME,End of Frame Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "DIS,Disable Completion Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "ENDFRAME,End of Frame Interrupt Disable" "0,1"
|
|
rgroup.long 0x28++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "DIS,Disable Completion Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "ENDFRAME,End of Frame Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 2. "DIS,Disable Completion Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "ENDFRAME,End of Frame Interrupt Status" "0,1"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "SMR0,Segment Map Register 0"
|
|
bitfld.long 0x0 31. "LCD31,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 30. "LCD30,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "LCD29,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 28. "LCD28,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "LCD27,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 26. "LCD26,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "LCD25,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 24. "LCD24,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "LCD23,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 22. "LCD22,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "LCD21,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 20. "LCD20,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "LCD19,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 18. "LCD18,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "LCD17,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 16. "LCD16,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "LCD15,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 14. "LCD14,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "LCD13,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 12. "LCD12,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "LCD11,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 10. "LCD10,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "LCD9,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 8. "LCD8,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "LCD7,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 6. "LCD6,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LCD5,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 4. "LCD4,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "LCD3,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 2. "LCD2,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LCD1,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
bitfld.long 0x0 0. "LCD0,LCD Segment Mapped on SEGx I/O Pin" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
group.long 0x200++0x3
|
|
line.long 0x0 "LMEMR0,LSB Memory Register (com = 0)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x208++0x3
|
|
line.long 0x0 "LMEMR1,LSB Memory Register (com = 1)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x210++0x3
|
|
line.long 0x0 "LMEMR2,LSB Memory Register (com = 2)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x218++0x3
|
|
line.long 0x0 "LMEMR3,LSB Memory Register (com = 3)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x220++0x3
|
|
line.long 0x0 "LMEMR4,LSB Memory Register (com = 4)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x228++0x3
|
|
line.long 0x0 "LMEMR5,LSB Memory Register (com = 5)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x230++0x3
|
|
line.long 0x0 "LMEMR6,LSB Memory Register (com = 6)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
group.long 0x238++0x3
|
|
line.long 0x0 "LMEMR7,LSB Memory Register (com = 7)"
|
|
hexmask.long 0x0 0.--31. 1. "LPIXEL,LSB Pixels Pattern Associated to COMx Terminal"
|
|
tree.end
|
|
endif
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x400531D0
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "KEY,Password"
|
|
bitfld.long 0x0 3. "TDXTALSEL,Timing Domain Slow Clock Selector" "0: Slow clock of the timing domain is driven by the..,1: Slow clock of the timing domain is driven by the.."
|
|
newline
|
|
bitfld.long 0x0 2. "VROFF,Voltage Regulator Off" "0: No effect.,1: If KEY=0xA5 VROFF asserts the VDDCORE domain.."
|
|
bitfld.long 0x0 1. "SHDWEOF,Shutdown End Of Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SHDW,Shutdown" "0,1"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "SMMR,Supply Monitor Mode Register"
|
|
bitfld.long 0x0 13. "VDD3V3SMPWRM,VDD3V3 Supply Monitor Power Supply Mode" "0: The VDDBU power source selection is controlled..,1: The VDDBU power source is VBAT when a VDD3V3.."
|
|
bitfld.long 0x0 12. "VDD3V3SMRSTEN,VDD3V3 Supply Monitor Reset Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "VDD3V3SMSMPL,VDD3V3 Supply Monitor Sampling Period" "0: VDD3V3 supply monitor is disabled,1: Continuous VDD3V3 supply monitoring,2: VDD3V3 supply monitor is enabled for 1 period..,3: VDD3V3 supply monitor is enabled for 1 period..,4: VDD3V3 supply monitor is enabled for 1 period..,?,?,?"
|
|
hexmask.long.byte 0x0 0.--3. 1. "VDD3V3SMTH,VDD3V3 Supply Monitor Threshold"
|
|
line.long 0x4 "MR,Mode Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. "KEY,Password Key"
|
|
bitfld.long 0x4 20. "OSCBYPASS,Slow Crystal Oscillator Bypass" "0: No effect. Clock selection depends on the value..,1: The slow crystal oscillator is bypassed if.."
|
|
newline
|
|
bitfld.long 0x4 14. "IO_BACKUP_ISO,Backup Domain IO Isolation Control" "0,1"
|
|
bitfld.long 0x4 13. "CORSMDIS,VDDCORE Supply Monitor Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CORSMRSTEN,VDDCORE Supply Monitor Reset Enable" "0,1"
|
|
bitfld.long 0x4 7. "VREGDIS,Internal VDDCORE Voltage Regulator Disable" "0: Internal VDDCORE voltage regulator is enabled.,1: Internal VDDCORE voltage regulator is disabled.."
|
|
newline
|
|
bitfld.long 0x4 6. "CORSMM,VDDCORE Supply Monitor Output Mode" "0: VDDCORE supply monitor output value has no..,1: VDDCORE supply monitor output value is checked.."
|
|
bitfld.long 0x4 4.--5. "LCDMODE,LCD Controller Mode of Operation" "0: The internal supply source and the external..,?,2: The external supply source for LCD (VDDLCD) is..,3: The internal voltage regulator for VDDLCD is.."
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "LCDOUT,LCD Voltage Regulator Output"
|
|
line.long 0x8 "WUMR,Wakeup Mode Register"
|
|
bitfld.long 0x8 28.--30. "LPDBC4,Low-power Debouncer Period of WKUPx" "0: Disables the low-power debouncers.,1: WKUPx in active state for at least 2 RTCOUTx..,2: WKUPx in active state for at least 3 RTCOUTx..,3: WKUPx in active state for at least 4 RTCOUTx..,4: WKUPx in active state for at least 5 RTCOUTx..,5: WKUPx in active state for at least 6 RTCOUTx..,6: WKUPx in active state for at least 7 RTCOUTx..,7: WKUPx in active state for at least 8 RTCOUTx.."
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bitfld.long 0x8 25.--27. "LPDBC3,Low-power Debouncer Period of WKUPx" "0: Disables the low-power debouncers.,1: WKUPx in active state for at least 2 RTCOUTx..,2: WKUPx in active state for at least 3 RTCOUTx..,3: WKUPx in active state for at least 4 RTCOUTx..,4: WKUPx in active state for at least 5 RTCOUTx..,5: WKUPx in active state for at least 6 RTCOUTx..,6: WKUPx in active state for at least 7 RTCOUTx..,7: WKUPx in active state for at least 8 RTCOUTx.."
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newline
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bitfld.long 0x8 22.--24. "LPDBC2,Low-power Debouncer Period of WKUPx" "0: Disables the low-power debouncers.,1: WKUPx in active state for at least 2 RTCOUTx..,2: WKUPx in active state for at least 3 RTCOUTx..,3: WKUPx in active state for at least 4 RTCOUTx..,4: WKUPx in active state for at least 5 RTCOUTx..,5: WKUPx in active state for at least 6 RTCOUTx..,6: WKUPx in active state for at least 7 RTCOUTx..,7: WKUPx in active state for at least 8 RTCOUTx.."
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bitfld.long 0x8 19.--21. "LPDBC1,Low-power Debouncer Period of WKUPx" "0: Disables the low-power debouncers.,1: WKUPx in active state for at least 2 RTCOUTx..,2: WKUPx in active state for at least 3 RTCOUTx..,3: WKUPx in active state for at least 4 RTCOUTx..,4: WKUPx in active state for at least 5 RTCOUTx..,5: WKUPx in active state for at least 6 RTCOUTx..,6: WKUPx in active state for at least 7 RTCOUTx..,7: WKUPx in active state for at least 8 RTCOUTx.."
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newline
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bitfld.long 0x8 16.--18. "LPDBC0,Low-power Debouncer Period of WKUPx" "0: Disables the low-power debouncers.,1: WKUPx in active state for at least 2 RTCOUTx..,2: WKUPx in active state for at least 3 RTCOUTx..,3: WKUPx in active state for at least 4 RTCOUTx..,4: WKUPx in active state for at least 5 RTCOUTx..,5: WKUPx in active state for at least 6 RTCOUTx..,6: WKUPx in active state for at least 7 RTCOUTx..,7: WKUPx in active state for at least 8 RTCOUTx.."
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bitfld.long 0x8 12.--14. "WKUPDBC,Wake-up Inputs Debouncer Period" "0: Immediate no debouncing detected active at least..,1: WKUPx shall be in its active state for at least..,2: WKUPx shall be in its active state for at least..,3: WKUPx shall be in its active state for at least..,4: WKUPx shall be in its active state for at least..,5: WKUPx shall be in its active state for at least..,?,?"
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newline
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bitfld.long 0x8 8.--10. "FWUPDBC,Force Wake-up Inputs Debouncer Period" "0: Immediate no debouncing detected active at least..,1: WKUPx shall be in its active state for at least..,2: WKUPx shall be in its active state for at least..,3: WKUPx shall be in its active state for at least..,4: WKUPx shall be in its active state for at least..,5: WKUPx shall be in its active state for at least..,?,?"
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bitfld.long 0x8 4. "LPDBCEN4,Tamper Enable for WKUPx Pin" "0,1"
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newline
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bitfld.long 0x8 3. "LPDBCEN3,Tamper Enable for WKUPx Pin" "0,1"
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bitfld.long 0x8 2. "LPDBCEN2,Tamper Enable for WKUPx Pin" "0,1"
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newline
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bitfld.long 0x8 1. "LPDBCEN1,Tamper Enable for WKUPx Pin" "0,1"
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bitfld.long 0x8 0. "LPDBCEN0,Tamper Enable for WKUPx Pin" "0,1"
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line.long 0xC "WUIR,Wakeup Inputs Register"
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bitfld.long 0xC 30. "WKUPT14,Wake-up Input Type 14" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 29. "WKUPT13,Wake-up Input Type 13" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 28. "WKUPT12,Wake-up Input Type 12" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 27. "WKUPT11,Wake-up Input Type 11" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 26. "WKUPT10,Wake-up Input Type 10" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 25. "WKUPT9,Wake-up Input Type 9" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 24. "WKUPT8,Wake-up Input Type 8" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 23. "WKUPT7,Wake-up Input Type 7" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 22. "WKUPT6,Wake-up Input Type 6" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 21. "WKUPT5,Wake-up Input Type 5" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 20. "WKUPT4,Wake-up Input Type 4" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 19. "WKUPT3,Wake-up Input Type 3" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 18. "WKUPT2,Wake-up Input Type 2" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 17. "WKUPT1,Wake-up Input Type 1" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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newline
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bitfld.long 0xC 16. "WKUPT0,Wake-up Input Type 0" "0: A falling edge followed by a low level for a..,1: A rising edge followed by a high level for a.."
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bitfld.long 0xC 14. "WKUPEN14,Wake-up Input Enable 14" "0,1"
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newline
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bitfld.long 0xC 13. "WKUPEN13,Wake-up Input Enable 13" "0,1"
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bitfld.long 0xC 12. "WKUPEN12,Wake-up Input Enable 12" "0,1"
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newline
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bitfld.long 0xC 11. "WKUPEN11,Wake-up Input Enable 11" "0,1"
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bitfld.long 0xC 10. "WKUPEN10,Wake-up Input Enable 10" "0,1"
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newline
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bitfld.long 0xC 9. "WKUPEN9,Wake-up Input Enable 9" "0,1"
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bitfld.long 0xC 8. "WKUPEN8,Wake-up Input Enable 8" "0,1"
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newline
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bitfld.long 0xC 7. "WKUPEN7,Wake-up Input Enable 7" "0,1"
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bitfld.long 0xC 6. "WKUPEN6,Wake-up Input Enable 6" "0,1"
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newline
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bitfld.long 0xC 5. "WKUPEN5,Wake-up Input Enable 5" "0,1"
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bitfld.long 0xC 4. "WKUPEN4,Wake-up Input Enable 4" "0,1"
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newline
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bitfld.long 0xC 3. "WKUPEN3,Wake-up Input Enable 3" "0,1"
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bitfld.long 0xC 2. "WKUPEN2,Wake-up Input Enable 2" "0,1"
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newline
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bitfld.long 0xC 1. "WKUPEN1,Wake-up Input Enable 1" "0,1"
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bitfld.long 0xC 0. "WKUPEN0,Wake-up Input Enable 0" "0,1"
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rgroup.long 0x14++0x3
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line.long 0x0 "SR,Status Register"
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bitfld.long 0x0 31. "RTCS,RTC Wake-up Status (cleared by reading SUPC_WUSR)" "0,1"
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bitfld.long 0x0 30. "RTTS,RTT Wake-up Status (cleared by reading SUPC_WUSR)" "0,1"
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newline
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bitfld.long 0x0 29. "FWKUPS,FWUP Wake-up Status (cleared by reading SUPC_WUSR)" "0,1"
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bitfld.long 0x0 28. "BADXTS,Slow Crystal Oscillator Wake-up Status (cleared by reading SUPC_WUSR)" "0,1"
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newline
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bitfld.long 0x0 27. "WKUPS,WKUP Wake-up Status (cleared by reading SUPC_WUSR)" "0,1"
|
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bitfld.long 0x0 26. "SXFME,Slow Crystal Oscillator Frequency Monitor Error (cleared on read)" "0,1"
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newline
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bitfld.long 0x0 24.--25. "SXFMS,Slow Crystal Oscillator Frequency Monitor Status (cleared on read)" "0: No frequency error detected.,1: The frequency has not been correct over 4..,2: No edge detected in the slow crystal oscillator..,?"
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bitfld.long 0x0 20. "LPDBCS4,Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)" "0,1"
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newline
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bitfld.long 0x0 19. "LPDBCS3,Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)" "0,1"
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bitfld.long 0x0 18. "LPDBCS2,Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)" "0,1"
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newline
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bitfld.long 0x0 17. "LPDBCS1,Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)" "0,1"
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bitfld.long 0x0 16. "LPDBCS0,Tamper Detection Wake-up Status (cleared by reading SUPC_ISR)" "0,1"
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newline
|
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bitfld.long 0x0 12. "FWUPS,Force Wake-up Pin Status" "0,1"
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|
bitfld.long 0x0 8. "LCDS,LCD Power Domain Status" "0,1"
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newline
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bitfld.long 0x0 6. "VDD3V3SMS,VDD3V3 Supply Monitor Output Status" "0,1"
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bitfld.long 0x0 5. "VDD3V3SMIS,VDD3V3 Supply Monitor Interrupt Status (cleared by reading SUPC_ISR)" "0,1"
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newline
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bitfld.long 0x0 4. "VDD3V3SMRSTS,VDD3V3 Supply Monitor Reset Status (cleared by reading SUPC_WUSR)" "0,1"
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bitfld.long 0x0 3. "CORSMRSTS,VDDCORE Supply Monitor Reset Status (cleared by reading SUPC_WUSR)" "0,1"
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newline
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bitfld.long 0x0 2. "VDD3V3SMWS,VDD3V3 Supply Monitor Wake-up Status (cleared by reading SUPC_WUSR)" "0,1"
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bitfld.long 0x0 0. "TDOSCSEL,Timing Domain 32 kHz Oscillator Selection Status" "0: The timing domain slow clock (TD_SLCK) source is..,1: The timing domain slow clock source is the.."
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group.long 0x1C++0x7
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line.long 0x0 "EMR,Extended Mode Register"
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bitfld.long 0x0 18. "COREBGEN,VDDCORE Voltage Regulator Bandgap Enable" "0,1"
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bitfld.long 0x0 17. "FULLGPBRC,Full GPBR Clean" "0,1"
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newline
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bitfld.long 0x0 16. "FLRSGPBR,Flash Erase GPBR" "0,1"
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line.long 0x4 "BMR,Backup Mode Register"
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hexmask.long.byte 0x4 24.--31. 1. "KEY,Password Key"
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bitfld.long 0x4 10. "BADXTWKEN,Slow Crystal Oscillator Frequency Error Wake-up Enable" "0,1"
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newline
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bitfld.long 0x4 9. "MRTCOUT,RTCOUT0 Outputs Drive Mode" "0: RTCOUT0 output is driven according to the..,?"
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bitfld.long 0x4 8. "VBATREN,Battery Voltage Event Report Enable" "0: Disables the report of event on VBAT voltage.,1: Enables the report of event on VBAT voltage."
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newline
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bitfld.long 0x4 6. "VDD3V3SMWKEN,VDD3V3 Supply Monitor Wake-up Enable" "0: Wake-up on VDD3V3 supply monitor under voltage..,1: Wake-up on VDD3V3 supply monitor under voltage.."
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bitfld.long 0x4 5. "CORPORWKEN,VDDCORE POR Wake-up Enable" "0: Wake-up on VDDCORE Power-On Reset Event is..,1: Wake-up on VDDCORE Power-On Reset Event is.."
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newline
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bitfld.long 0x4 4. "FWUPEN,Force Wake-up Pin Wake-up Enable" "0: The fwup signal has no wake-up effect.,1: The fwup signal forces the wake-up of the core.."
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bitfld.long 0x4 2. "VBATWKEN,VBAT Supply Monitor Wake-up Enable" "0: Wake-up on VBAT supply monitor under voltage..,1: Wake-up on VBAT supply monitor under voltage.."
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newline
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bitfld.long 0x4 1. "RTCWKEN,Real-time Clock Wake-up Enable" "0: The RTC alarm signal has no wake-up effect.,1: The RTC alarm signal forces the wake-up of the.."
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bitfld.long 0x4 0. "RTTWKEN,Real-time Timer Wake-up Enable" "0: The RTT alarm signal has no wake-up effect.,1: The RTT alarm signal forces the wake-up of the.."
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rgroup.long 0x24++0x3
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line.long 0x0 "WUSR,Wakeup Status Register"
|
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bitfld.long 0x0 31. "WKUPIS15,WKUPx Input Wake-up Status (cleared on read)" "0,1"
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bitfld.long 0x0 30. "WKUPIS14,WKUPx Input Wake-up Status (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 29. "WKUPIS13,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
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bitfld.long 0x0 28. "WKUPIS12,WKUPx Input Wake-up Status (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 27. "WKUPIS11,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
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bitfld.long 0x0 26. "WKUPIS10,WKUPx Input Wake-up Status (cleared on read)" "0,1"
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newline
|
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bitfld.long 0x0 25. "WKUPIS9,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
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bitfld.long 0x0 24. "WKUPIS8,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 23. "WKUPIS7,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
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bitfld.long 0x0 22. "WKUPIS6,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
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newline
|
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bitfld.long 0x0 21. "WKUPIS5,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 20. "WKUPIS4,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "WKUPIS3,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 18. "WKUPIS2,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "WKUPIS1,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 16. "WKUPIS0,WKUPx Input Wake-up Status (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "VDD3V3SMRSTS,VDD3V3 Supply Monitor Reset Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 5. "RTCS,RTC Wake-up Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RTTS,RTT Wake-up Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 3. "VDD3V3SMWS,VDD3V3 Supply Monitor Wake-up Status (cleared on read)" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "FWUPS,FWUP Wake-up Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "BADXTWKS,Slow Crystal Oscillator Frequency Error Wake-up Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WKUPS,WKUP Wake-up Status (cleared on read)" "0,1"
|
|
wgroup.long 0x28++0x7
|
|
line.long 0x0 "IER,Enable Interrupt Register"
|
|
bitfld.long 0x0 17. "VBATSMEV,VBAT Supply Monitor Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 16. "VDD3V3SMEV,VDD3V3 Supply Monitor Event Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LPDBC4,WKUPx Pin Tamper Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "LPDBC3,WKUPx Pin Tamper Detection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 2. "LPDBC2,WKUPx Pin Tamper Detection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "LPDBC1,WKUPx Pin Tamper Detection Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 0. "LPDBC0,WKUPx Pin Tamper Detection Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Disable Interrupt Register"
|
|
bitfld.long 0x4 17. "VBATSMEV,VBAT Supply Monitor Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 16. "VDD3V3SMEV,VDD3V3 Supply Monitor Event Interrupt Disable" "0,1"
|
|
newline
|
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bitfld.long 0x4 4. "LPDBC4,WKUPx Pin Tamper Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 3. "LPDBC3,WKUPx Pin Tamper Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LPDBC2,WKUPx Pin Tamper Detection Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "LPDBC1,WKUPx Pin Tamper Detection Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPDBC0,WKUPx Pin Tamper Detection Interrupt Disable" "0,1"
|
|
rgroup.long 0x30++0x7
|
|
line.long 0x0 "IMR,Mask Interrupt Register"
|
|
bitfld.long 0x0 17. "VBATSMEV,VBAT Supply Monitor Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 16. "VDD3V3SMEV,VDD3V3 Supply Monitor Event Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "LPDBC4,WKUPx Pin Tamper Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 3. "LPDBC3,WKUPx Pin Tamper Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "LPDBC2,WKUPx Pin Tamper Detection Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "LPDBC1,WKUPx Pin Tamper Detection Interrupt Mask" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LPDBC0,WKUPx Pin Tamper Detection Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Status Interrupt Register"
|
|
bitfld.long 0x4 17. "VBATSMEV,VBAT Supply Monitor Event Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 16. "VDD3V3SMEV,VDD3V3 Supply Monitor Event Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "LPDBC4,WKUPx Pin Tamper Detection Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 3. "LPDBC3,WKUPx Pin Tamper Detection Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "LPDBC2,WKUPx Pin Tamper Detection Interrupt Status (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "LPDBC1,WKUPx Pin Tamper Detection Interrupt Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LPDBC0,WKUPx Pin Tamper Detection Interrupt Status (cleared on read)" "0,1"
|
|
tree.end
|
|
tree "SYSCWP (System Controller Write Protection)"
|
|
base ad:0x400531A0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SYSC_WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SYSC_WPSR,Write Protection Status Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "WVSRC,Write Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Register Violation Status" "0,1"
|
|
tree.end
|
|
tree "SystemControl (System Control)"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ICTR,Interrupt Controller Type Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTLINESNUM,"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x0 9. "DISOOFP,Disable out-of-order FP instructions" "0,1"
|
|
bitfld.long 0x0 8. "DISFPCA,Disable automatic update of CONTROL.FPCA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DISFOLD,Disable IT folding" "0,1"
|
|
bitfld.long 0x0 1. "DISDEFWBUF,Disable wruite buffer use during default memory map accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "DISMCYCINT,Disable interruption of LDM/STM instructions" "0,1"
|
|
rgroup.long 0xD00++0x3
|
|
line.long 0x0 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer code 0x41=ARM"
|
|
hexmask.long.byte 0x0 20.--23. 1. "VARIANT,Variant number"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "CONSTANT,Constant"
|
|
hexmask.long.word 0x0 4.--15. 1. "PARTNO,Process Part Number 0xC24=Cortex-M4"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Processor revision number"
|
|
group.long 0xD04++0x3B
|
|
line.long 0x0 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x0 31. "NMIPENDSET,NMI set-pending bit" "0: Write: no effect; read: NMI exception is not..,1: Write: changes NMI exception state to pending;.."
|
|
bitfld.long 0x0 28. "PENDSVSET,PendSV set-pending bit" "0: Write: no effect; read: PendSV exception is not..,1: Write: changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x0 27. "PENDSVCLR,PendSV clear-pending bit" "0: No effect,1: Removes the pending state from the PendSV.."
|
|
bitfld.long 0x0 26. "PENDSTSET,SysTick set-pending bit" "0: Write: no effect; read: SysTick exception is not..,1: Write: changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x0 25. "PENDSTCLR,SysTick clear-pending bit" "0: No effect,1: Removes the pending state from the SysTick.."
|
|
bitfld.long 0x0 23. "ISRPREEMPT,Debug only" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "ISRPENDING,Interrupt pending flag" "0,1"
|
|
hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Exception number of the highest priority pending enabled exception"
|
|
newline
|
|
bitfld.long 0x0 11. "RETTOBASE,No preempted active exceptions to execute" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Active exception number"
|
|
line.long 0x4 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x4 7.--31. 1. "TBLOFF,Vector table base offset"
|
|
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "VECTKEY,Register key"
|
|
bitfld.long 0x8 15. "ENDIANNESS,Data endianness 0=little 1=big" "0: little,1: big"
|
|
newline
|
|
bitfld.long 0x8 8.--10. "PRIGROUP,Interrupt priority grouping" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 2. "SYSRESETREQ,System Reset Request" "0: No system reset request,1: Asserts a signal to the outer system that.."
|
|
newline
|
|
bitfld.long 0x8 1. "VECTCLRACTIVE,Must write 0" "0,1"
|
|
bitfld.long 0x8 0. "VECTRESET,Must write 0" "0,1"
|
|
line.long 0xC "SCR,System Control Register"
|
|
bitfld.long 0xC 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup the..,1: Enabled events and all interrupts including.."
|
|
bitfld.long 0xC 2. "SLEEPDEEP,Deep Sleep used as low power mode" "0: Sleep,1: Deep sleep"
|
|
newline
|
|
bitfld.long 0xC 1. "SLEEPONEXIT,Sleep-on-exit on handler return" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 9. "STKALIGN,Indicates stack alignment on exception entry" "0: 4-byte aligned,1: 8-byte aligned"
|
|
bitfld.long 0x10 8. "BFHFNMIGN,Ignore LDM/STM BusFault for -1/-2 priority handlers" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "DIV_0_TRP,Enables divide by 0 trap" "0,1"
|
|
bitfld.long 0x10 3. "UNALIGN_TRP,Enables unaligned access traps" "0: Do not trap unaligned halfword and word accesses,1: Trap unaligned halfword and word accesses"
|
|
newline
|
|
bitfld.long 0x10 1. "USERSETMPEND,Enables unprivileged software access to STIR register" "0,1"
|
|
bitfld.long 0x10 0. "NONBASETHRDENA,Indicates how processor enters Thread mode" "0,1"
|
|
line.long 0x14 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
|
|
hexmask.long.byte 0x14 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick exception"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. "USGFAULTENA,UsageFault enable bit" "0,1"
|
|
bitfld.long 0x20 17. "BUSFAULTENA,BusFault enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 16. "MEMFAULTENA,MemManage enable bit" "0,1"
|
|
bitfld.long 0x20 15. "SVCALLPENDED,SVCall pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 14. "BUSFAULTPENDED,BusFault exception pending bit" "0,1"
|
|
bitfld.long 0x20 13. "MEMFAULTPENDED,MemManage exception pending bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 12. "USGFAULTPENDED,UsageFault exception pending bit" "0,1"
|
|
bitfld.long 0x20 11. "SYSTICKACT,SysTick exception active bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 10. "PENDSVACT,PendSV exception active bit" "0,1"
|
|
bitfld.long 0x20 8. "MONITORACT,DebugMonitor exception active bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "SVCALLACT,SVCall active bit" "0,1"
|
|
bitfld.long 0x20 3. "USGFAULTACT,UsageFault exception active bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 1. "BUSFAULTACT,BusFault exception active bit" "0,1"
|
|
bitfld.long 0x20 0. "MEMFAULTACT,MemManage exception active bit" "0,1"
|
|
line.long 0x24 "CFSR,Configurable Fault Status Register"
|
|
bitfld.long 0x24 25. "DIVBYZERO,Divide by zero UsageFault" "0,1"
|
|
bitfld.long 0x24 24. "UNALIGNED,Unaligned access UsageFault" "0,1"
|
|
newline
|
|
bitfld.long 0x24 19. "NOCP,No coprocessor UsageFault" "0,1"
|
|
bitfld.long 0x24 18. "INVPC,Invalid PC load UsageFault" "0,1"
|
|
newline
|
|
bitfld.long 0x24 17. "INVSTATE,Invalid state UsageFault" "0,1"
|
|
bitfld.long 0x24 16. "UNDEFINSTR,Undefined instruction UsageFault" "0,1"
|
|
newline
|
|
bitfld.long 0x24 15. "BFARVALID,BusFault Address Register valid" "0,1"
|
|
bitfld.long 0x24 13. "LSPERR,BusFault occured during FP lazy state preservation" "0,1"
|
|
newline
|
|
bitfld.long 0x24 12. "STKERR,BusFault on stacking for exception entry" "0,1"
|
|
bitfld.long 0x24 11. "UNSTKERR,BusFault on unstacking for exception return" "0,1"
|
|
newline
|
|
bitfld.long 0x24 10. "IMPRECISERR,Imprecise data bus error" "0,1"
|
|
bitfld.long 0x24 9. "PRECISERR,Precise data bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 8. "IBUSERR,Instruction bus error" "0,1"
|
|
bitfld.long 0x24 7. "MMARVALID,MemManage Fault Address Register valid" "0,1"
|
|
newline
|
|
bitfld.long 0x24 5. "MLSPERR,MemManager Fault occured during FP lazy state preservation" "0,1"
|
|
bitfld.long 0x24 4. "MSTKERR,MemManage Fault on stacking for exception entry" "0,1"
|
|
newline
|
|
bitfld.long 0x24 3. "MUNSTKERR,MemManage Fault on unstacking for exception return" "0,1"
|
|
bitfld.long 0x24 1. "DACCVIOL,Data access violation" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "IACCVIOL,Instruction access violation" "0,1"
|
|
line.long 0x28 "HFSR,HardFault Status Register"
|
|
bitfld.long 0x28 31. "DEBUGEVT,Debug: always write 0" "0,1"
|
|
bitfld.long 0x28 30. "FORCED,Forced Hard Fault" "0,1"
|
|
newline
|
|
bitfld.long 0x28 1. "VECTTBL,BusFault on a Vector Table read during exception processing" "0,1"
|
|
line.long 0x2C "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x2C 4. "EXTERNAL," "0,1"
|
|
bitfld.long 0x2C 3. "VCATCH," "0,1"
|
|
newline
|
|
bitfld.long 0x2C 2. "DWTTRAP," "0,1"
|
|
bitfld.long 0x2C 1. "BKPT," "0,1"
|
|
newline
|
|
bitfld.long 0x2C 0. "HALTED," "0,1"
|
|
line.long 0x30 "MMFAR,MemManage Fault Address Register"
|
|
hexmask.long 0x30 0.--31. 1. "ADDRESS,Address that generated the MemManage fault"
|
|
line.long 0x34 "BFAR,BusFault Address Register"
|
|
hexmask.long 0x34 0.--31. 1. "ADDRESS,Address that generated the BusFault"
|
|
line.long 0x38 "AFSR,Auxiliary Fault Status Register"
|
|
hexmask.long 0x38 0.--31. 1. "IMPDEF,AUXFAULT input signals"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xD40)++0x3
|
|
line.long 0x0 "PFR[$1],Processor Feature Register"
|
|
repeat.end
|
|
rgroup.long 0xD48++0x7
|
|
line.long 0x0 "DFR,Debug Feature Register"
|
|
line.long 0x4 "ADR,Auxiliary Feature Register"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xD50)++0x3
|
|
line.long 0x0 "MMFR[$1],Memory Model Feature Register"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0xD60)++0x3
|
|
line.long 0x0 "ISAR[$1],Instruction Set Attributes Register"
|
|
repeat.end
|
|
group.long 0xD88++0x3
|
|
line.long 0x0 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x0 22.--23. "CP11,Access privileges for coprocessor 11" "0: Access denied,1: Privileged access only,?,3: Full access"
|
|
bitfld.long 0x0 20.--21. "CP10,Access privileges for coprocessor 10" "0: Access denied,1: Privileged access only,?,3: Full access"
|
|
tree.end
|
|
tree "SysTick (SysTick Clock)"
|
|
base ad:0xE000E010
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,Timer counted to 0 since last read of register" "0,1"
|
|
bitfld.long 0x0 2. "CLKSOURCE,Clock Source 0=external 1=processor" "0: external,1: processor"
|
|
newline
|
|
bitfld.long 0x0 1. "TICKINT,SysTick Exception Request Enable" "0: Counting down to 0 does not assert the SysTick..,1: Counting down to 0 asserts the SysTick exception.."
|
|
bitfld.long 0x0 0. "ENABLE,SysTick Counter Enable" "0: Counter disabled,1: Counter enabled"
|
|
line.long 0x4 "RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0"
|
|
line.long 0x8 "CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x0 31. "NOREF,No Separate Reference Clock" "0: The reference clock is provided,1: The reference clock is not provided"
|
|
bitfld.long 0x0 30. "SKEW,TENMS is rounded from non-integer ratio" "0: 10ms calibration value is exact,1: 10ms calibration value is inexact because of the.."
|
|
newline
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Reload value to use for 10ms timing"
|
|
tree.end
|
|
tree "TC (Timer/Counter)"
|
|
base ad:0x0
|
|
tree "TC0"
|
|
base ad:0x40038000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40038000 ad:0x40038040 ad:0x40038080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CV,Counter Value"
|
|
hexmask.long 0x0 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40038000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x4 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree "TC1"
|
|
base ad:0x4003C000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x4003C000 ad:0x4003C040 ad:0x4003C080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CV,Counter Value"
|
|
hexmask.long 0x0 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4003C000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x4 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree "TC2"
|
|
base ad:0x40040000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x40040000 ad:0x40040040 ad:0x40040080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CV,Counter Value"
|
|
hexmask.long 0x0 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x40040000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x4 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree "TC3"
|
|
base ad:0x48008000
|
|
repeat 3. (list 0x0 0x1 0x2)(list ad:0x48008000 ad:0x48008040 ad:0x48008080)
|
|
tree "TC_CHANNEL[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "CCR,Channel Control Register"
|
|
bitfld.long 0x0 2. "SWTRG,Software Trigger Command" "0,1"
|
|
bitfld.long 0x0 1. "CLKDIS,Counter Clock Disable Command" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "CLKEN,Counter Clock Enable Command" "0,1"
|
|
group.long ($2+0x4)++0x3
|
|
line.long 0x0 "CMR_CAPTURE_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 20.--22. "SBSMPLR,Loading Edge Subsampling Ratio" "0: Load a Capture register each selected edge,1: Load a Capture register every 2 selected edges,2: Load a Capture register every 4 selected edges,3: Load a Capture register every 8 selected edges,4: Load a Capture register every 16 selected edges,?,?,?"
|
|
bitfld.long 0x0 18.--19. "LDRB,RB Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "LDRA,RA Loading Edge Selection" "0: None,1: Rising edge of TIOAx,2: Falling edge of TIOAx,3: Each edge of TIOAx"
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "CPCTRG,RC Compare Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10. "ABETRG,TIOAx or TIOBx External Trigger Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "ETRGEDG,External Trigger Edge Selection" "0: The clock is not gated by an external signal.,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "LDBDIS,Counter Clock Disable with RB Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDBSTOP,Counter Clock Stopped with RB Loading" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
group.long ($2+0x4)++0x7
|
|
line.long 0x0 "CMR_WAVEFORM_MODE,Channel Mode Register"
|
|
bitfld.long 0x0 30.--31. "BSWTRG,Software Trigger Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 28.--29. "BEEVT,External Event Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 26.--27. "BCPC,RC Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 24.--25. "BCPB,RB Compare Effect on TIOBx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "ASWTRG,Software Trigger Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 20.--21. "AEEVT,External Event Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "ACPC,RC Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
bitfld.long 0x0 16.--17. "ACPA,RA Compare Effect on TIOAx" "0: None,1: Set,2: Clear,3: Toggle"
|
|
newline
|
|
bitfld.long 0x0 15. "WAVE,Waveform Mode" "0,1"
|
|
bitfld.long 0x0 13.--14. "WAVSEL,Waveform Selection" "0: UP mode without automatic trigger on RC Compare,1: UPDOWN mode without automatic trigger on RC..,2: UP mode with automatic trigger on RC Compare,3: UPDOWN mode with automatic trigger on RC Compare"
|
|
newline
|
|
bitfld.long 0x0 12. "ENETRG,External Event Trigger Enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "EEVT,External Event Selection" "0: TIOB,1: XC0,2: XC1,3: XC2"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "EEVTEDG,External Event Edge Selection" "0: None,1: Rising edge,2: Falling edge,3: Each edge"
|
|
bitfld.long 0x0 7. "CPCDIS,Counter Clock Disable with RC Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "CPCSTOP,Counter Clock Stopped with RC Compare" "0,1"
|
|
bitfld.long 0x0 4.--5. "BURST,Burst Signal Selection" "0: The clock is not gated by an external signal.,1: XC0 is ANDed with the selected clock.,2: XC1 is ANDed with the selected clock.,3: XC2 is ANDed with the selected clock."
|
|
newline
|
|
bitfld.long 0x0 3. "CLKI,Clock Invert" "0,1"
|
|
bitfld.long 0x0 0.--2. "TCCLKS,Clock Selection" "0: Clock selected: internal GCLK [TC_ID] clock..,1: Clock selected: internal MCK/8 clock signal..,2: Clock selected: internal MCK/32 clock signal..,3: Clock selected: internal MCK/128 clock signal..,4: Clock selected: internal MD_SLCK clock signal..,5: Clock selected: XC0,6: Clock selected: XC1,7: Clock selected: XC2"
|
|
line.long 0x4 "SMMR,Stepper Motor Mode Register"
|
|
bitfld.long 0x4 1. "DOWN,Down Count" "0,1"
|
|
bitfld.long 0x4 0. "GCEN,Gray Count Enable" "0,1"
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "CV,Counter Value"
|
|
hexmask.long 0x0 0.--31. 1. "CV,Counter Value"
|
|
group.long ($2+0x14)++0xB
|
|
line.long 0x0 "RA,Register A"
|
|
hexmask.long 0x0 0.--31. 1. "RA,Register A"
|
|
line.long 0x4 "RB,Register B"
|
|
hexmask.long 0x4 0.--31. 1. "RB,Register B"
|
|
line.long 0x8 "RC,Register C"
|
|
hexmask.long 0x8 0.--31. 1. "RC,Register C"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "SR,Interrupt Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer (cleared by writing TC_RCR or TC_RNCR)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 4. "CPCS,RC Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CPBS,RB Compare Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "CPAS,RA Compare Status (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun Status (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow Status (cleared on read)" "0,1"
|
|
wgroup.long ($2+0x24)++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 10. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x4 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x4 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x4 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x4 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "COVFS,Counter Overflow" "0,1"
|
|
rgroup.long ($2+0x2C)++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 10. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 9. "RXBUFF,Reception Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x0 7. "ETRGS,External Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "LDRBS,RB Loading" "0,1"
|
|
bitfld.long 0x0 5. "LDRAS,RA Loading" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CPCS,RC Compare" "0,1"
|
|
bitfld.long 0x0 3. "CPBS,RB Compare" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CPAS,RA Compare" "0,1"
|
|
bitfld.long 0x0 1. "LOVRS,Load Overrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "COVFS,Counter Overflow" "0,1"
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "EMR,Extended Mode Register"
|
|
bitfld.long 0x0 8. "NODIVCLK,No Divided Clock" "0,1"
|
|
bitfld.long 0x0 4.--5. "TRIGSRCB,Trigger Source for Input B" "0: The trigger/capture input B is driven by..,1: The trigger/capture input B is driven internally..,?,?"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "TRIGSRCA,Trigger Source for Input A" "0: The trigger/capture input A is driven by..,1: The trigger/capture input A is driven internally..,?,?"
|
|
rgroup.long ($2+0x34)++0x7
|
|
line.long 0x0 "CSR,Channel Status Register"
|
|
bitfld.long 0x0 18. "MTIOB,TIOBx Mirror" "0,1"
|
|
bitfld.long 0x0 17. "MTIOA,TIOAx Mirror" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "CLKSTA,Clock Enabling Status" "0,1"
|
|
line.long 0x4 "SSR,Safety Status Register"
|
|
bitfld.long 0x4 31. "ECLASS,Software Error Class" "0: An abnormal access that does not have any impact.,1: An abnormal access that may have an impact."
|
|
hexmask.long.byte 0x4 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
newline
|
|
hexmask.long.word 0x4 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x4 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x48008000
|
|
wgroup.long 0xC0++0x3
|
|
line.long 0x0 "BCR,Block Control Register"
|
|
bitfld.long 0x0 0. "SYNC,Synchro Command" "0,1"
|
|
group.long 0xC4++0x3
|
|
line.long 0x0 "BMR,Block Mode Register"
|
|
hexmask.long.byte 0x0 20.--25. 1. "MAXFILT,Maximum Filter"
|
|
bitfld.long 0x0 17. "IDXPHB,Index Pin is PHB Pin" "0,1"
|
|
bitfld.long 0x0 16. "SWAP,Swap PHA and PHB" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "INVIDX,Inverted Index" "0,1"
|
|
bitfld.long 0x0 14. "INVB,Inverted PHB" "0,1"
|
|
bitfld.long 0x0 13. "INVA,Inverted PHA" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "EDGPHA,Edge on PHA Count Mode" "0,1"
|
|
bitfld.long 0x0 11. "QDTRANS,Quadrature Decoding Transparent" "0,1"
|
|
bitfld.long 0x0 10. "SPEEDEN,Speed Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "POSEN,Position Enabled" "0,1"
|
|
bitfld.long 0x0 8. "QDEN,Quadrature Decoder Enabled" "0,1"
|
|
bitfld.long 0x0 4.--5. "TC2XC2S,External Clock Signal 2 Selection" "0: Signal connected to XC2: TCLK2,?,2: Signal connected to XC2: TIOA0,3: Signal connected to XC2: TIOA1"
|
|
newline
|
|
bitfld.long 0x0 2.--3. "TC1XC1S,External Clock Signal 1 Selection" "0: Signal connected to XC1: TCLK1,?,2: Signal connected to XC1: TIOA0,3: Signal connected to XC1: TIOA2"
|
|
bitfld.long 0x0 0.--1. "TC0XC0S,External Clock Signal 0 Selection" "0: Signal connected to XC0: TCLK0,?,2: Signal connected to XC0: TIOA1,3: Signal connected to XC0: TIOA2"
|
|
wgroup.long 0xC8++0x7
|
|
line.long 0x0 "QIER,QDEC Interrupt Enable Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QIDR,QDEC Interrupt Disable Register"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
rgroup.long 0xD0++0x7
|
|
line.long 0x0 "QIMR,QDEC Interrupt Mask Register"
|
|
bitfld.long 0x0 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x0 6. "FIDX,Filtered Index Line" "0,1"
|
|
bitfld.long 0x0 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x0 2. "QERR,Quadrature Error" "0,1"
|
|
bitfld.long 0x0 1. "DIRCHG,Direction Change" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "IDX,Index" "0,1"
|
|
line.long 0x4 "QISR,QDEC Interrupt Status Register"
|
|
bitfld.long 0x4 8. "DIR,Direction" "0,1"
|
|
bitfld.long 0x4 7. "FMP,Filtered Missing Pulse" "0,1"
|
|
bitfld.long 0x4 6. "FIDX,Filtered Index Line" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "FPHB,Filtered Phase B Line" "0,1"
|
|
bitfld.long 0x4 4. "FPHA,Filtered Phase A Line" "0,1"
|
|
bitfld.long 0x4 2. "QERR,Quadrature Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DIRCHG,Direction Change" "0,1"
|
|
bitfld.long 0x4 0. "IDX,Index" "0,1"
|
|
group.long 0xD8++0x3
|
|
line.long 0x0 "FMR,Fault Mode Register"
|
|
bitfld.long 0x0 1. "ENCF1,Enable Compare Fault Channel 1" "0,1"
|
|
bitfld.long 0x0 0. "ENCF0,Enable Compare Fault Channel 0" "0,1"
|
|
rgroup.long 0xDC++0x3
|
|
line.long 0x0 "QSR,QDEC Status Register"
|
|
bitfld.long 0x0 8. "DIR,Direction" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
group.long 0x110++0x7
|
|
line.long 0x0 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x4 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "TPI (Trace Port Interface)"
|
|
base ad:0xE0040000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SSPSR,Supported Parallel Port Size Register"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CSPSR,Current Parallel Port Size Register"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ACPR,Asynchronous Clock Prescaler Register"
|
|
hexmask.long.word 0x0 0.--12. 1. "PRESCALER,"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "SPPR,Selected Pin Protocol Register"
|
|
bitfld.long 0x0 0.--1. "TXMODE," "0,1,2,3"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "FFSR,Formatter and Flush Status Register"
|
|
bitfld.long 0x0 3. "FtNonStop," "0,1"
|
|
bitfld.long 0x0 2. "TCPresent," "0,1"
|
|
bitfld.long 0x0 1. "FtStopped," "0,1"
|
|
bitfld.long 0x0 0. "FlInProg," "0,1"
|
|
group.long 0x304++0x3
|
|
line.long 0x0 "FFCR,Formatter and Flush Control Register"
|
|
bitfld.long 0x0 8. "TrigIn," "0,1"
|
|
bitfld.long 0x0 1. "EnFCont," "0,1"
|
|
rgroup.long 0x308++0x3
|
|
line.long 0x0 "FSCR,Formatter Synchronization Counter Register"
|
|
rgroup.long 0xEE8++0xB
|
|
line.long 0x0 "TRIGGER,TRIGGER"
|
|
bitfld.long 0x0 0. "TRIGGER," "0,1"
|
|
line.long 0x4 "FIFO0,Integration ETM Data"
|
|
bitfld.long 0x4 29. "ITM_ATVALID," "0,1"
|
|
bitfld.long 0x4 27.--28. "ITM_bytecount," "0,1,2,3"
|
|
bitfld.long 0x4 26. "ETM_ATVALID," "0,1"
|
|
bitfld.long 0x4 24.--25. "ETM_bytecount," "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "ETM2,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ETM1,"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ETM0,"
|
|
line.long 0x8 "ITATBCTR2,ITATBCTR2"
|
|
bitfld.long 0x8 0. "ATREADY," "0,1"
|
|
rgroup.long 0xEF8++0x7
|
|
line.long 0x0 "ITATBCTR0,ITATBCTR0"
|
|
bitfld.long 0x0 0. "ATREADY," "0,1"
|
|
line.long 0x4 "FIFO1,Integration ITM Data"
|
|
bitfld.long 0x4 29. "ITM_ATVALID," "0,1"
|
|
bitfld.long 0x4 27.--28. "ITM_bytecount," "0,1,2,3"
|
|
bitfld.long 0x4 26. "ETM_ATVALID," "0,1"
|
|
bitfld.long 0x4 24.--25. "ETM_bytecount," "0,1,2,3"
|
|
hexmask.long.byte 0x4 16.--23. 1. "ITM2,"
|
|
hexmask.long.byte 0x4 8.--15. 1. "ITM1,"
|
|
hexmask.long.byte 0x4 0.--7. 1. "ITM0,"
|
|
group.long 0xF00++0x3
|
|
line.long 0x0 "ITCTRL,Integration Mode Control"
|
|
bitfld.long 0x0 0. "Mode," "0,1"
|
|
group.long 0xFA0++0x7
|
|
line.long 0x0 "CLAIMSET,Claim tag set"
|
|
line.long 0x4 "CLAIMCLR,Claim tag clear"
|
|
rgroup.long 0xFC8++0x7
|
|
line.long 0x0 "DEVID,TPIU_DEVID"
|
|
bitfld.long 0x0 11. "NRZVALID," "0,1"
|
|
bitfld.long 0x0 10. "MANCVALID," "0,1"
|
|
bitfld.long 0x0 9. "PTINVALID," "0,1"
|
|
bitfld.long 0x0 6.--8. "MinBufSz," "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 5. "AsynClkIn," "0,1"
|
|
bitfld.long 0x0 0. "NrTraceInput," "0,1"
|
|
line.long 0x4 "DEVTYPE,TPIU_DEVTYPE"
|
|
hexmask.long.byte 0x4 4.--7. 1. "MajorType,"
|
|
hexmask.long.byte 0x4 0.--3. 1. "SubType,"
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x4400C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WAKEY,Register Write Access Key"
|
|
bitfld.long 0x0 0. "ENABLE,Enable TRNG to Provide Random Values" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 0. "HALFR,Half Rate Enable" "0: Maximum stream rate provided (1 sample every 84..,1: Half maximum stream rate provided if the.."
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PKBCR,Private Key Bus Control Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "WAKEY,Register Write Access Key"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KLENGTH,Key Length"
|
|
bitfld.long 0x0 4.--5. "KSLAVE,Key Bus Client" "0: AES,1: AESB,?,?"
|
|
bitfld.long 0x0 0. "KID,Key ID (Must be Always Written to 0)" "0,1"
|
|
wgroup.long 0x10++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 2. "EOTPKB,End Of Transfer on Private Key Bus Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 1. "SECE,Security and/or Safety Event Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DATRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 2. "EOTPKB,End Of Transfer on Private Key Bus (cleared on read)" "0,1"
|
|
bitfld.long 0x4 1. "SECE,Security and/or Safety Event (cleared on read)" "0,1"
|
|
bitfld.long 0x4 0. "DATRDY,Data Ready (cleared on read)" "0,1"
|
|
rgroup.long 0x50++0x3
|
|
line.long 0x0 "ODATA,Output Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "ODATA,Output Data"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 4. "FIRSTE,First Error Report Enable" "0,1"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Enable" "0,1"
|
|
bitfld.long 0x0 1. "WPITEN,Write Protection Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
bitfld.long 0x0 31. "ECLASS,Software Error Class (cleared on read)" "0: An abnormal access that does not affect system..,1: Reading TRNG_ODATA when TRNG was disabled or.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "SWETYP,Software Error Type (cleared on read)"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source (cleared on read)"
|
|
bitfld.long 0x0 3. "SWE,Software Control Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 2. "SEQE,Internal Sequencer Error (cleared on read)" "0,1"
|
|
bitfld.long 0x0 1. "CGD,Clock Glitch Detected (cleared on read)" "0,1"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status (cleared on read)" "0,1"
|
|
tree.end
|
|
sif (cpuis("PIC32C?1025MTG128*")||cpuis("PIC32C?2051MTG128*")||cpuis("PIC32C?5112MTG128*"))
|
|
tree "UART (Universal Asynchronous Receiver Transmitter)"
|
|
base ad:0x48010000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CR,Control Register"
|
|
bitfld.long 0x0 14. "OPT_SLEEP,Optical Logic Sleep Mode Command" "0,1"
|
|
bitfld.long 0x0 12. "REQCLR,Request Clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "STTTO,Start Time-out" "0,1"
|
|
bitfld.long 0x0 10. "RETTO,Rearm Time-out" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "RSTSTA,Reset Status" "0,1"
|
|
bitfld.long 0x0 7. "TXDIS,Transmitter Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TXEN,Transmitter Enable" "0,1"
|
|
bitfld.long 0x0 5. "RXDIS,Receiver Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x0 3. "RSTTX,Reset Transmitter" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "RSTRX,Reset Receiver" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 28.--30. "OPT_CMPTH,Receive Path Comparator Threshold" "0: Comparator threshold is VDD3V3/2 volts.,1: Comparator threshold is VDD3V3/2.5 volts.,2: Comparator threshold is VDD3V3/3.3 volts.,3: Comparator threshold is VDD3V3/5 volts.,4: Comparator threshold is VDD3V3/10 volts.,?,?,?"
|
|
bitfld.long 0x0 24.--26. "OPT_DUTY,Optical Link Modulation Clock Duty Cycle" "0: Modulation clock duty cycle Is 50%.,1: Modulation clock duty cycle Is 43.75%.,2: Modulation clock duty cycle Is 37.5%.,3: Modulation clock duty cycle Is 31.75%.,4: Modulation clock duty cycle Is 25%.,5: Modulation clock duty cycle Is 18.75%.,6: Modulation clock duty cycle Is 12.5%.,7: Modulation clock duty cycle Is 6.25%."
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "OPT_CLKDIV,Optical Link Clock Divider"
|
|
bitfld.long 0x0 14.--15. "CHMODE,Channel Mode" "0: Normal mode,1: Automatic echo,2: Local loopback,3: Remote loopback"
|
|
newline
|
|
bitfld.long 0x0 12. "BRSRCCK,Baud Rate Source Clock" "0: The baud rate is driven by the peripheral clock,1: The baud rate is driven by a PMC-programmable.."
|
|
bitfld.long 0x0 9.--11. "PAR,Parity Type" "0: Even Parity,1: Odd Parity,2: Space: parity forced to 0,3: Mark: parity forced to 1,4: No parity,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 8. "OPT_WKUP,Optical Link Activity Wake-up Enable" "0: To detect any activity on the output of analog..,1: If OPT_EN=0 and a logical 1 is detected after.."
|
|
bitfld.long 0x0 6.--7. "EDGESEL,Analog Comparator Output Edge Selection" "0: The UART_SR.ACE is set if a rising edge is..,1: The UART_SR.ACE is set if a falling edge is..,2: The UART_SR.ACE is set as soon as an edge is..,?"
|
|
newline
|
|
bitfld.long 0x0 5. "ACON,Analog Comparator Enable" "0: The analog comparator is disabled. If OPT_EN=1..,1: The analog comparator is enabled."
|
|
bitfld.long 0x0 4. "FILTER,Receiver Digital Filter" "0: UART does not filter the receive line.,1: UART filters the receive line using a.."
|
|
newline
|
|
bitfld.long 0x0 3. "OPT_DMOD,Optical Demodulation Enable" "0: The optical demodulator is disabled. External..,1: The optical demodulator is enabled."
|
|
bitfld.long 0x0 2. "OPT_MDINV,UART Modulated Data Inverted" "0: The output of the modulator is not inverted.,1: The output of the modulator is inverted."
|
|
newline
|
|
bitfld.long 0x0 1. "OPT_RXINV,UART Receive Data Inverted" "0: The comparator data output is not inverted..,1: The comparator data output is inverted before.."
|
|
bitfld.long 0x0 0. "OPT_EN,UART Optical Interface Enable" "0: Disables the UART optical link.,1: Enables the UART optical link."
|
|
wgroup.long 0x8++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 16. "ACE,Enable Analog Comparator Event Interrupt" "0,1"
|
|
bitfld.long 0x0 15. "CMP,Enable Comparison Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Enable Buffer Full Interrupt" "0,1"
|
|
bitfld.long 0x0 11. "TXBUFE,Enable Buffer Empty Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Enable TXEMPTY Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "TIMEOUT,Enable Time-out Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Enable Parity Error Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "FRAME,Enable Framing Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Enable Overrun Error Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ENDTX,Enable End of Transmit Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,Enable End of Receive Transfer Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "TXRDY,Enable TXRDY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Enable RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 16. "ACE,Disable Analog Comparator Event Interrupt" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Disable Comparison Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,Disable Buffer Full Interrupt" "0,1"
|
|
bitfld.long 0x4 11. "TXBUFE,Disable Buffer Empty Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Disable TXEMPTY Interrupt" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Disable Time-out Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Disable Parity Error Interrupt" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Disable Framing Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Disable Overrun Error Interrupt" "0,1"
|
|
bitfld.long 0x4 4. "ENDTX,Disable End of Transmit Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,Disable End of Receive Transfer Interrupt" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Disable TXRDY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Disable RXRDY Interrupt" "0,1"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 16. "ACE,Mask Analog Comparator Event Interrupt" "0,1"
|
|
bitfld.long 0x0 15. "CMP,Mask Comparison Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "RXBUFF,Mask RXBUFF Interrupt" "0,1"
|
|
bitfld.long 0x0 11. "TXBUFE,Mask TXBUFE Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TXEMPTY,Mask TXEMPTY Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "TIMEOUT,Mask Time-out Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PARE,Mask Parity Error Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "FRAME,Mask Framing Error Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "OVRE,Mask Overrun Error Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "ENDTX,Mask End of Transmit Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENDRX,Mask End of Receive Transfer Interrupt" "0,1"
|
|
bitfld.long 0x0 1. "TXRDY,Mask TXRDY Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXRDY,Mask RXRDY Interrupt" "0,1"
|
|
line.long 0x4 "SR,Interrupt Status Register"
|
|
bitfld.long 0x4 16. "ACE,Analog Comparator Event Interrupt (Cleared by writing UART_CR.RSTSTA)" "0,1"
|
|
bitfld.long 0x4 15. "CMP,Comparison Match (Cleared by writing the UART_CR.RSTSTA)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "RXBUFF,Receive Buffer Full" "0,1"
|
|
bitfld.long 0x4 11. "TXBUFE,Transmission Buffer Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TXEMPTY,Transmitter Empty (Cleared by writing the UART_THR)" "0,1"
|
|
bitfld.long 0x4 8. "TIMEOUT,Receiver Time-out (Cleared by writing the UART_CR.STTTO)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "PARE,Parity Error (Cleared by writing UART_CR.RSTSTA)" "0,1"
|
|
bitfld.long 0x4 6. "FRAME,Framing Error (Cleared by writing UART_CR.RSTSTA)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "OVRE,Overrun Error (Cleared by writing UART_CR.RSTSTA)" "0,1"
|
|
bitfld.long 0x4 4. "ENDTX,End of Transmitter Transfer" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ENDRX,End of Receiver Transfer" "0,1"
|
|
bitfld.long 0x4 1. "TXRDY,Transmitter Ready (Cleared by writing the UART_THR)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "RXRDY,Receiver Ready (Cleared by reading the UART_RHR)" "0,1"
|
|
line.long 0x8 "RHR,Receive Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "RXCHR,Received Character"
|
|
wgroup.long 0x1C++0x3
|
|
line.long 0x0 "THR,Transmit Holding Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TXCHR,Character to be Transmitted"
|
|
group.long 0x20++0xB
|
|
line.long 0x0 "BRGR,Baud Rate Generator Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CD,Clock Divisor"
|
|
line.long 0x4 "CMPR,Comparison Register"
|
|
hexmask.long.byte 0x4 16.--23. 1. "VAL2,Second Comparison Value for Received Character"
|
|
bitfld.long 0x4 14. "CMPPAR,Compare Parity" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "CMPMODE,Comparison Mode" "0: Any character is received and comparison..,1: Comparison condition must be met to start.."
|
|
hexmask.long.byte 0x4 0.--7. 1. "VAL1,First Comparison Value for Received Character"
|
|
line.long 0x8 "RTOR,Receiver Time-out Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "TO,Time-out Value"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "CSR,Current Status Register"
|
|
bitfld.long 0x0 0. "ACO,Analog Comparator Output" "0,1"
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
group.long 0x100++0x1F
|
|
line.long 0x0 "RPR,Receive Pointer Register"
|
|
hexmask.long 0x0 0.--31. 1. "RXPTR,Receive Pointer Register"
|
|
line.long 0x4 "RCR,Receive Counter Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXCTR,Receive Counter Register"
|
|
line.long 0x8 "TPR,Transmit Pointer Register"
|
|
hexmask.long 0x8 0.--31. 1. "TXPTR,Transmit Counter Register"
|
|
line.long 0xC "TCR,Transmit Counter Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "TXCTR,Transmit Counter Register"
|
|
line.long 0x10 "RNPR,Receive Next Pointer Register"
|
|
hexmask.long 0x10 0.--31. 1. "RXNPTR,Receive Next Pointer"
|
|
line.long 0x14 "RNCR,Receive Next Counter Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "RXNCTR,Receive Next Counter"
|
|
line.long 0x18 "TNPR,Transmit Next Pointer Register"
|
|
hexmask.long 0x18 0.--31. 1. "TXNPTR,Transmit Next Pointer"
|
|
line.long 0x1C "TNCR,Transmit Next Counter Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. "TXNCTR,Transmit Counter Next"
|
|
wgroup.long 0x120++0x3
|
|
line.long 0x0 "PTCR,Transfer Control Register"
|
|
bitfld.long 0x0 24. "ERRCLR,Transfer Bus Error Clear" "0,1"
|
|
bitfld.long 0x0 19. "TXCBDIS,Transmitter Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 17. "RXCBDIS,Receiver Circular Buffer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 9. "TXTDIS,Transmitter Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
bitfld.long 0x0 1. "RXTDIS,Receiver Transfer Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
rgroup.long 0x124++0x3
|
|
line.long 0x0 "PTSR,Transfer Status Register"
|
|
bitfld.long 0x0 24. "ERR,Transfer Bus Error" "0,1"
|
|
bitfld.long 0x0 18. "TXCBEN,Transmitter Circular Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "RXCBEN,Receiver Circular Buffer Enable" "0,1"
|
|
bitfld.long 0x0 8. "TXTEN,Transmitter Transfer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "RXTEN,Receiver Transfer Enable" "0,1"
|
|
group.long 0x128++0x3
|
|
line.long 0x0 "PWPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 2. "WPCREN,Write Protection Control Register Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "WPCTREN,Write Protection Counter Registers Enable" "0,1"
|
|
bitfld.long 0x0 0. "WPPTREN,Write Protection Pointer Registers Enable" "0,1"
|
|
tree.end
|
|
endif
|
|
AUTOINDENT.OFF
|