25773 lines
1.4 MiB
25773 lines
1.4 MiB
; --------------------------------------------------------------------------------
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; @Title: PIC32CK On-Chip Peripherals
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; @Props: Released
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; @Author: NEJ
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; @Changelog: 2024-01-19 NEJ
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; @Manufacturer: MICROCHIP - Microchip Technology Inc.
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; @Doc: Generated (TRACE32, build: 166062.), based on:
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; PIC32CK0512GC00064.svd (Ver. 0), PIC32CK0512GC00100.svd (Ver. 0),
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; PIC32CK0512GC01064.svd (Ver. 0), PIC32CK0512GC01100.svd (Ver. 0),
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; PIC32CK0512SG00064.svd (Ver. 0), PIC32CK0512SG00100.svd (Ver. 0),
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; PIC32CK0512SG01064.svd (Ver. 0), PIC32CK0512SG01100.svd (Ver. 0),
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; PIC32CK1025GC00064.svd (Ver. 0), PIC32CK1025GC00100.svd (Ver. 0),
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; PIC32CK1025GC01064.svd (Ver. 0), PIC32CK1025GC01100.svd (Ver. 0),
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; PIC32CK1025SG00064.svd (Ver. 0), PIC32CK1025SG00100.svd (Ver. 0),
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; PIC32CK1025SG01064.svd (Ver. 0), PIC32CK1025SG01100.svd (Ver. 0),
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; PIC32CK2051GC00064.svd (Ver. 0), PIC32CK2051GC00100.svd (Ver. 0),
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; PIC32CK2051GC00144.svd (Ver. 0), PIC32CK2051GC01064.svd (Ver. 0),
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; PIC32CK2051GC01100.svd (Ver. 0), PIC32CK2051GC01144.svd (Ver. 0),
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; PIC32CK2051SG00064.svd (Ver. 0), PIC32CK2051SG00100.svd (Ver. 0),
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; PIC32CK2051SG00144.svd (Ver. 0), PIC32CK2051SG01064.svd (Ver. 0),
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; PIC32CK2051SG01100.svd (Ver. 0), PIC32CK2051SG01144.svd (Ver. 0)
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; @Core: Cortex-M33F
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; @Chip: PIC32CK0512GC00064, PIC32CK0512GC00100, PIC32CK0512GC01064,
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; PIC32CK0512GC01100, PIC32CK0512SG00064, PIC32CK0512SG00100,
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; PIC32CK0512SG01064, PIC32CK0512SG01100, PIC32CK1025GC00064,
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; PIC32CK1025GC00100, PIC32CK1025GC01064, PIC32CK1025GC01100,
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; PIC32CK1025SG00064, PIC32CK1025SG00100, PIC32CK1025SG01064,
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; PIC32CK1025SG01100, PIC32CK2051GC00064, PIC32CK2051GC00100,
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; PIC32CK2051GC00144, PIC32CK2051GC01064, PIC32CK2051GC01100,
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; PIC32CK2051GC01144, PIC32CK2051SG00064, PIC32CK2051SG00100,
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; PIC32CK2051SG00144, PIC32CK2051SG01064, PIC32CK2051SG01100,
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; PIC32CK2051SG01144
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; @Copyright: (C) 1989-2024 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perpic32ck.per 17367 2024-01-22 12:14:37Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M33F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,Allows external exclusive operations to be used in a configuration with no MPU" "No,Yes"
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bitfld.long 0x00 12. " DISITMATBFLUSH ,Disables ITM and DWT ATB flush" "No,Yes"
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bitfld.long 0x00 10. " FPEXCODIS ,Disables FPU exception outputs" "No,Yes"
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textline " "
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bitfld.long 0x00 9. " DISOOFP ,Disables floating-point" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables dual-issue functionality" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle" "No,Yes"
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group.long 0x0C++0x0F
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line.long 0x00 "CPPWR,Coprocessor Power Control Register"
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bitfld.long 0x00 21. " SUS10 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 20. " SU10 ,This bit indicates and allows modification of whether the state associated with the floating point unit is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 15. " SUS7 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 14. " SU7 ,This bit indicates and allows modification of whether the state associated with the coprocessor 7 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 13. " SUS6 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 12. " SU6 ,This bit indicates and allows modification of whether the state associated with the coprocessor 6 is permitted to become UNKNOWN" "Not permitted,Permitted"
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textline " "
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bitfld.long 0x00 11. " SUS5 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 10. " SU5 ,This bit indicates and allows modification of whether the state associated with the coprocessor 5 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 9. " SUS4 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 8. " SU4 ,This bit indicates and allows modification of whether the state associated with the coprocessor 4 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 7. " SUS3 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 6. " SU3 ,This bit indicates and allows modification of whether the state associated with the coprocessor 3 is permitted to become UNKNOWN" "Not permitted,Permitted"
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textline " "
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bitfld.long 0x00 5. " SUS2 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 4. " SU2 ,This bit indicates and allows modification of whether the state associated with the coprocessor 2 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 3. " SUS1 ,State unknown Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x00 2. " SU1 ,This bit indicates and allows modification of whether the state associated with the coprocessor 1 is permitted to become UNKNOWN" "Not permitted,Permitted"
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bitfld.long 0x00 1. " SUS0 ,State unknown Secure only" "Both states,Secure only"
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bitfld.long 0x00 0. " SU0 ,This bit indicates and allows modification of whether the state associated with the coprocessor 0 is permitted to become UNKNOWN" "Not permitted,Permitted"
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line.long 0x04 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x04 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x04 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x04 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x04 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x08 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x0C "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x0C 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/ Main extension"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "Reserved,Reserved,Patch 2,?..."
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET , On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET , On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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textline " "
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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textline " "
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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textline " "
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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line.long 0x14 "SHPR1,System Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of system handler 7, SecureFault"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6, UsageFault"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5, BusFault"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4, MemManage"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x20 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x20 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x20 5. " NMIACT ,NMI exception status" "Not active,Active"
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textline " "
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bitfld.long 0x20 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x20 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,Stacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstacking Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault (exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault (exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "UFSR,Usage Fault Status Register"
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eventfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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eventfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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eventfld.word 0x00 4. " STKOF ,Stack overflow error" "No error,Error"
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textline " "
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eventfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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eventfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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eventfld.word 0x00 1. " INVSTATE , Invalid Combination of EPSR and Instruction" "No error,Error"
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textline " "
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eventfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x03
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line.long 0x00 "HFSR,HardFault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority has been escalated to a HardFault exception" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Denied,Privileged,,Full"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Denied,Privileged,,Full"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Denied,Privileged,,Full"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Denied,Privileged,,Full"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Denied,Privileged,,Full"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Denied,Privileged,,Full"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Denied,Privileged,,Full"
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if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD48)
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group.long 0xD8C++0x03
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line.long 0x00 "NSACR,Non-Secure Access Control Register"
|
|
bitfld.long 0x00 11. " CP11 ,Enables Non-secure access to coprocessor CP11" "Disabled,Enabled"
|
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bitfld.long 0x00 10. " CP10 ,Enables Non-secure access to coprocessor CP10" "Disabled,Enabled"
|
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bitfld.long 0x00 7. " CP7 ,Enables Non-secure access to coprocessor CP7" "Disabled,Enabled"
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textline " "
|
|
bitfld.long 0x00 6. " CP6 ,Enables Non-secure access to coprocessor CP6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CP5 ,Enables Non-secure access to coprocessor CP5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CP4 ,Enables Non-secure access to coprocessor CP4" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CP3 ,Enables Non-secure access to coprocessor CP3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CP2 ,Enables Non-secure access to coprocessor CP2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CP1 ,Enables Non-secure access to coprocessor CP1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CP0 ,Enables Non-secure access to coprocessor CP0" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD8C++0x03
|
|
hide.long 0x00 "NSACR,Non-Secure Access Control Register (not accessible)"
|
|
endif
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Triggered Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be pended"
|
|
tree "Memory System"
|
|
width 10.
|
|
rgroup.long 0xD78++0x03
|
|
line.long 0x00 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
|
|
bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
|
|
bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
|
|
bitfld.long 0x00 15.--17. " CL6 ,Cache type field level 6" "No cache,?..."
|
|
bitfld.long 0x00 12.--14. " CL5 ,Cache type field level 5" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CL4 ,Cache type field level 4" "No cache,?..."
|
|
bitfld.long 0x00 6.--8. " CL3 ,Cache type field level 3" "No cache,?..."
|
|
bitfld.long 0x00 3.--5. " CL2 ,Cache type field level 2" "No cache,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CL1 ,Cache type field level 1" "No cache,Instr. only,Data only,Data and Instr.,?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD7C)&0xE0000000)==0x80000000)
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0xD7C++0x03
|
|
line.long 0x00 "CTR,Cache Type Register"
|
|
bitfld.long 0x00 29.--31. " FORMAT ,Indicates the implemented CTR format" "No Cache,,,,Cache,?..."
|
|
endif
|
|
rgroup.long 0xD80++0x03
|
|
line.long 0x00 "CCSIDR,Cache Size ID Register"
|
|
bitfld.long 0x00 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
|
|
bitfld.long 0x00 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
|
|
bitfld.long 0x00 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
|
|
hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
|
|
hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
|
|
group.long 0xD84++0x03
|
|
line.long 0x00 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
|
|
bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
|
|
wgroup.long 0xF50++0x03
|
|
line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
|
|
wgroup.long 0xF58++0x23
|
|
line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
|
|
line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
|
|
line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
|
|
hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
|
|
line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
|
|
line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
|
|
hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
|
|
line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
|
|
hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
|
|
bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
|
|
line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
|
|
tree.end
|
|
tree "Feature Registers"
|
|
width 10.
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,T32 instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
bitfld.long 0x04 4.--7. " SECURITY ,Security support" "Not implemented,Implemented,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " MPROFDBG ,M-profile debug. Indicates the supported M-profile debug architecture" "Not supported,ARMv8-M Debug architecture,?..."
|
|
rgroup.long 0xD4C++0x03
|
|
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TCM ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "1 level,2 levels,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,HW coherency,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,,PMSAv8,?..."
|
|
rgroup.long 0xD54++0x03
|
|
line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD5C++0x03
|
|
line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3"
|
|
bitfld.long 0x00 8.--11. " BPMAINT ,Indicates the supported branch predictor maintenance" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " CMAINTSW ,Indicates the supported cache maintenance operations by set/way" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " CMAINTVA ,Indicates the supported cache maintenance operations by virtual-address" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x03
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
rgroup.long 0xD64++0x03
|
|
line.long 0x00 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x00 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x00 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x00 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Basic,Extended,?..."
|
|
rgroup.long 0xD68++0x03
|
|
line.long 0x00 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x00 28.--31. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x00 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x00 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,SMULL/SMLAL,,SMULL/SMLAL/DSP,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MUL,MUL/MLA/MLS,?..."
|
|
bitfld.long 0x00 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x00 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,,Load-acquire/Store-release/Exclusive,?..."
|
|
rgroup.long 0xD6C++0x03
|
|
line.long 0x00 "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x00 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x00 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Extended,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB/Q-bit,?..."
|
|
rgroup.long 0xD70++0x03
|
|
line.long 0x00 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x00 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,CPS/MRS/MSR,?..."
|
|
bitfld.long 0x00 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" ",,,Supported,?..."
|
|
bitfld.long 0x00 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,,,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x00 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,,,Load/store,?..."
|
|
bitfld.long 0x00 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,?..."
|
|
tree.end
|
|
tree "CoreSight Identification Registers"
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 11.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DDEVARCH,SCS CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DPIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DPIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DPIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DPIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DCIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DCIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DCIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
textline " "
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Execute,Not Execute"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
textline " "
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
bitfld.long 0x00 28.--31. " ATTR3H ,Attribute 3 High. Outer memory attributes for MPU regions with an AttrIndex of 3" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 24.--27. " ATTR3L ,Attribute 3 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 3 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 20.--23. " ATTR2H ,Attribute 2 High. Outer memory attributes for MPU regions with an AttrIndex of 2" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 16.--19. " ATTR2L ,Attribute 2 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 2 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ATTR1H ,Attribute 1 High. Outer memory attributes for MPU regions with an AttrIndex of 1" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 8.--11. " ATTR1L ,Attribute 1 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 1 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x00 4.--7. " ATTR0H ,Attribute 0 High. Outer memory attributes for MPU regions with an AttrIndex of 0" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x00 0.--3. " ATTR0L ,Attribute 0 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 0 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
bitfld.long 0x04 28.--31. " ATTR7H ,Attribute 7 High. Outer memory attributes for MPU regions with an AttrIndex of 7" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 24.--27. " ATTR7L ,Attribute 7 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 7 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 20.--23. " ATTR6H ,Attribute 6 High. Outer memory attributes for MPU regions with an AttrIndex of 6" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 16.--19. " ATTR6L ,Attribute 6 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 6 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 12.--15. " ATTR5H ,Attribute 5 High. Outer memory attributes for MPU regions with an AttrIndex of 5" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 8.--11. " ATTR5L ,Attribute 5 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 5 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
newline
|
|
bitfld.long 0x04 4.--7. " ATTR4H ,Attribute 4 High. Outer memory attributes for MPU regions with an AttrIndex of 4" "Device memory,Normal memory/Write-through transient/W-allocate,Normal memory/Write-through transient/R-allocate,Normal memory/Write-through transient/RW-allocate,Normal memory/Non-cacheable,Normal memory/Write-back transient/W-allocate,Normal memory/Write-back transient/R-allocate,Normal memory/Write-back transient/RW-allocate,Normal memory/Write-through non-transient,Normal memory/Write-through non-transient/W-allocate,Normal memory/Write-through non-transient/R-allocate,Normal memory/Write-through non-transient/RW-allocate,Normal memory/Write-back non-transient,Normal memory/Write-back non-transient/W-allocate,Normal memory/Write-back non-transient/R-allocate,Normal memory/Write-back non-transient/RW-allocate"
|
|
bitfld.long 0x04 0.--3. " ATTR4L ,Attribute 4 Low. Device memory/Inner memory attributes for MPU regions with an AttrIndex of 4 [Device memory/Normal memory]" "Device-nGnRnE/Unpredictable,---/Write-through transient/W-allocate,---/Write-through transient/R-allocate,---/Write-through transient/RW-allocate,Device-nGnRE/Non-cacheable,---/Write-back transient/W-allocate,---/Write-back transient/R-allocate,---/Write-back transient/RW-allocate,Device-nGRE/Write-through non-transient,---/Write-through non-transient/W-allocate,---/Write-through non-transient/R-allocate,---/Write-through non-transient/RW-allocate,Device-GRE/Write-back non-transient,---/Write-back non-transient/W-allocate,---/Write-back non-transient/R-allocate,---/Write-back non-transient/RW-allocate"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if PER.ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(COMPonent.BASE("COREDEBUG",-1)+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
tree.end
|
|
group.long 0xDE4++0x03
|
|
line.long 0x00 "SFSR,Secure Fault Status Register"
|
|
bitfld.long 0x00 7. " LSERR ,Lazy state error flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " SFARVALID ,Secure fault address valid" "Not valid,Valid"
|
|
bitfld.long 0x00 5. " LSPERR ,Lazy state preservation error flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " INVTRAN ,Invalid transition flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " AUVIOL ,Attribution unit violation flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " INVER ,Invalid exception return flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " INVIS ,Invalid integrity signature flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " INVEP ,Invalid entry point" "Not occurred,Occurred"
|
|
group.long 0xDE8++0x03
|
|
line.long 0x00 "SFAR,Secure Fault Address Register"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-255,0-287,0-319,0-351,0-383,0-415,0-447,0-479,0-511"
|
|
width 24.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA255 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA254 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA253 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA252 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA251 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA250 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA249 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA248 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA247 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA246 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA245 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA244 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA243 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA242 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA241 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA240 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_255_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA287 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA286 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA285 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA284 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA283 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA282 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA281 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA280 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA279 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA278 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA277 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA276 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA275 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA274 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA273 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA272 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA271 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA270 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA269 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA268 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA267 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA266 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA265 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA264 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA263 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA262 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA261 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA260 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA259 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA258 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA257 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA256 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x120++0x03
|
|
hide.long 0x00 "IRQ256_287_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA319 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA318 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA317 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA316 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA315 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA314 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA313 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA312 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA311 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA310 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA309 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA308 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA307 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA306 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA305 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA304 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA303 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA302 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA301 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA300 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA299 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA298 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA297 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA296 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA295 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA294 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA293 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA292 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA291 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA290 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA289 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA288 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x124++0x03
|
|
hide.long 0x00 "IRQ288_319_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA351 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA350 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA349 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA348 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA347 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA346 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA345 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA344 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA343 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA342 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA341 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA340 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA339 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA338 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA337 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA336 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA335 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA334 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA333 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA332 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA331 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA330 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA329 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA328 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA327 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA326 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA325 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA324 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA323 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA322 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA321 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA320 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x128++0x03
|
|
hide.long 0x00 "IRQ320_351_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA383 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA382 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA381 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA380 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA379 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA378 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA377 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA376 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA375 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA374 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA373 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA372 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA371 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA370 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA369 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA368 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA367 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA366 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA365 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA364 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA363 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA362 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA361 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA360 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA359 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA358 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA357 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA356 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA355 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA354 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA353 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA352 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x12C++0x03
|
|
hide.long 0x00 "IRQ352_383_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA415 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA414 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA413 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA412 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA411 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA410 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA409 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA408 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA407 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA406 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA405 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA404 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA403 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA402 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA401 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA400 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA399 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA398 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA397 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA396 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA395 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA394 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA393 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA392 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA391 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA390 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA389 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA388 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA387 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA386 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA385 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA384 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x130++0x03
|
|
hide.long 0x00 "IRQ384_415_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA447 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA446 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA445 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA444 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA443 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA442 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA441 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA440 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA439 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA438 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA437 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA436 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA435 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA434 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA433 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA432 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA431 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA430 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA429 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA428 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA427 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA426 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA425 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA424 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA423 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA422 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA421 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA420 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA419 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA418 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA417 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA416 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x134++0x03
|
|
hide.long 0x00 "IRQ416_447_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA479 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA478 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA477 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA476 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA475 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA474 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA473 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA472 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA471 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA470 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA469 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA468 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA467 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA466 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA465 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA464 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA463 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA462 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA461 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA460 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA459 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA458 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA457 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA456 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA455 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA454 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA453 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA452 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA451 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA450 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA449 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA448 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x138++0x03
|
|
hide.long 0x00 "IRQ448_479_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA511 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA510 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA509 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA508 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA507 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA506 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA505 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA504 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA503 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA502 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA501 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA500 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA499 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA498 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA497 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA496 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA495 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA494 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA493 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA492 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA491 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA490 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA489 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA488 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA487 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA486 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA485 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA484 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA483 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA482 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA481 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA480 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x13C++0x03
|
|
hide.long 0x00 "IRQ480_511_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
width 24.
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN255 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN254 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN253 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN252 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN251 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN250 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN249 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN248 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN247 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN246 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN245 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN244 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN243 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN242 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN241 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN240 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_255_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN287 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN286 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN285 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN284 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN283 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN282 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN281 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN280 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN279 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN278 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN277 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN276 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN275 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN274 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN273 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN272 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN271 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN270 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN269 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN268 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN267 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN266 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN265 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN264 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN263 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN262 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN261 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN260 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN259 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN258 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN257 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN256 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x220++0x03
|
|
hide.long 0x00 "IRQ256_287_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN319 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN318 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN317 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN316 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN315 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN314 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN313 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN312 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN311 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN310 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN309 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN308 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN307 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN306 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN305 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN304 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN303 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN302 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN301 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN300 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN299 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN298 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN297 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN296 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN295 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN294 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN293 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN292 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN291 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN290 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN289 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN288 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x224++0x03
|
|
hide.long 0x00 "IRQ288_319_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN351 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN350 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN349 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN348 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN347 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN346 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN345 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN344 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN343 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN342 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN341 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN340 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN339 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN338 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN337 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN336 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN335 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN334 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN333 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN332 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN331 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN330 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN329 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN328 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN327 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN326 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN325 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN324 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN323 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN322 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN321 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN320 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x228++0x03
|
|
hide.long 0x00 "IRQ320_351_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x22C++0x03
|
|
line.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN383 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN382 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN381 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN380 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN379 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN378 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN377 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN376 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN375 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN374 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN373 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN372 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN371 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN370 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN369 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN368 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN367 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN366 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN365 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN364 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN363 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN362 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN361 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN360 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN359 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN358 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN357 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN356 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN355 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN354 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN353 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN352 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x22C++0x03
|
|
hide.long 0x00 "IRQ352_383_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN415 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN414 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN413 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN412 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN411 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN410 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN409 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN408 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN407 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN406 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN405 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN404 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN403 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN402 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN401 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN400 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN399 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN398 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN397 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN396 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN395 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN394 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN393 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN392 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN391 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN390 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN389 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN388 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN387 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN386 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN385 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN384 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x230++0x03
|
|
hide.long 0x00 "IRQ384_415_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN447 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN446 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN445 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN444 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN443 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN442 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN441 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN440 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN439 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN438 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN437 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN436 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN435 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN434 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN433 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN432 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN431 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN430 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN429 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN428 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN427 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN426 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN425 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN424 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN423 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN422 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN421 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN420 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN419 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN418 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN417 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN416 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x234++0x03
|
|
hide.long 0x00 "IRQ416_447_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x238++0x03
|
|
line.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN479 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN478 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN477 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN476 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN475 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN474 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN473 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN472 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN471 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN470 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN469 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN468 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN467 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN466 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN465 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN464 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN463 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN462 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN461 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN460 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN459 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN458 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN457 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN456 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN455 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN454 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN453 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN452 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN451 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN450 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN449 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN448 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x238++0x03
|
|
hide.long 0x00 "IRQ448_479_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
group.long 0x23C++0x03
|
|
line.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN511 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN510 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN509 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN508 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN507 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN506 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN505 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN504 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN503 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN502 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN501 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN500 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN499 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN498 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN497 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN496 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN495 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN494 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN493 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN492 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN491 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN490 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN489 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN488 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN487 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN486 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN485 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN484 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN483 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN482 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN481 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN480 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x23C++0x03
|
|
hide.long 0x00 "IRQ480_511_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
width 11.
|
|
tree "Interrupt Active Bit Registers"
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 31. " ACTIVE255 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE254 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE253 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE252 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE251 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE250 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE249 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE248 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE247 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE246 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE245 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE244 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE243 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE242 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE241 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE240 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
rgroup.long 0x320++0x03
|
|
line.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x00 31. " ACTIVE287 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE286 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE285 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE284 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE283 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE282 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE281 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE280 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE279 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE278 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE277 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE276 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE275 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE274 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE273 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE272 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE271 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE270 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE269 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE268 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE267 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE266 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE265 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE264 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE263 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE262 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE261 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE260 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE259 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE258 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE257 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE256 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x320++0x03
|
|
hide.long 0x00 "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
rgroup.long 0x324++0x03
|
|
line.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
bitfld.long 0x00 31. " ACTIVE319 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE318 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE317 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE316 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE315 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE314 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE313 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE312 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE311 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE310 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE309 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE308 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE307 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE306 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE305 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE304 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE303 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE302 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE301 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE300 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE299 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE298 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE297 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE296 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE295 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE294 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE293 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE292 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE291 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE290 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE289 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE288 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x324++0x03
|
|
hide.long 0x00 "ACTIVE9,Active Bit Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
rgroup.long 0x328++0x03
|
|
line.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
bitfld.long 0x00 31. " ACTIVE351 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE350 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE349 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE348 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE347 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE346 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE345 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE344 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE343 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE342 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE341 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE340 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE339 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE338 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE337 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE336 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE335 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE334 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE333 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE332 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE331 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE330 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE329 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE328 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE327 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE326 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE325 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE324 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE323 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE322 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE321 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE320 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x328++0x03
|
|
hide.long 0x00 "ACTIVE10,Active Bit Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
rgroup.long 0x32C++0x03
|
|
line.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
bitfld.long 0x00 31. " ACTIVE383 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE382 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE381 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE380 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE379 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE378 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE377 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE376 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE375 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE374 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE373 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE372 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE371 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE370 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE369 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE368 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE367 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE366 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE365 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE364 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE363 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE362 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE361 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE360 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE359 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE358 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE357 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE356 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE355 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE354 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE353 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE352 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x32C++0x03
|
|
hide.long 0x00 "ACTIVE11,Active Bit Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
rgroup.long 0x330++0x03
|
|
line.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
bitfld.long 0x00 31. " ACTIVE415 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE414 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE413 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE412 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE411 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE410 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE409 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE408 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE407 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE406 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE405 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE404 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE403 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE402 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE401 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE400 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE399 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE398 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE397 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE396 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE395 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE394 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE393 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE392 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE391 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE390 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE389 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE388 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE387 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE386 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE385 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE384 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x330++0x03
|
|
hide.long 0x00 "ACTIVE12,Active Bit Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
rgroup.long 0x334++0x03
|
|
line.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
bitfld.long 0x00 31. " ACTIVE447 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE446 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE445 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE444 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE443 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE442 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE441 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE440 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE439 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE438 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE437 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE436 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE435 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE434 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE433 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE432 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE431 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE430 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE429 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE428 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE427 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE426 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE425 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE424 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE423 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE422 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE421 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE420 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE419 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE418 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE417 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE416 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x334++0x03
|
|
hide.long 0x00 "ACTIVE13,Active Bit Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
rgroup.long 0x338++0x03
|
|
line.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
bitfld.long 0x00 31. " ACTIVE479 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE478 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE477 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE476 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE475 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE474 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE473 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE472 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE471 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE470 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE469 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE468 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE467 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE466 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE465 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE464 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE463 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE462 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE461 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE460 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE459 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE458 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE457 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE456 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE455 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE454 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE453 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE452 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE451 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE450 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE449 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE448 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x338++0x03
|
|
hide.long 0x00 "ACTIVE14,Active Bit Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0F)
|
|
rgroup.long 0x33C++0x03
|
|
line.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
bitfld.long 0x00 31. " ACTIVE511 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE510 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE509 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE508 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE507 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE506 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE505 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE504 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE503 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE502 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE501 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE500 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE499 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE498 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE497 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE496 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE495 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE494 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE493 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE492 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE491 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE490 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE489 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE488 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE487 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE486 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE485 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE484 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE483 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE482 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE481 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE480 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x33C++0x03
|
|
hide.long 0x00 "ACTIVE15,Active Bit Register 15"
|
|
endif
|
|
tree.end
|
|
width 13.
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 31. " ITNS255 ,Interrupt Targets Non-secure 255" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS254 ,Interrupt Targets Non-secure 254" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS253 ,Interrupt Targets Non-secure 253" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS252 ,Interrupt Targets Non-secure 252" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS251 ,Interrupt Targets Non-secure 251" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS250 ,Interrupt Targets Non-secure 250" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS249 ,Interrupt Targets Non-secure 249" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS248 ,Interrupt Targets Non-secure 248" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS247 ,Interrupt Targets Non-secure 247" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS246 ,Interrupt Targets Non-secure 246" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS245 ,Interrupt Targets Non-secure 245" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS244 ,Interrupt Targets Non-secure 244" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS243 ,Interrupt Targets Non-secure 243" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS242 ,Interrupt Targets Non-secure 242" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS241 ,Interrupt Targets Non-secure 241" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS240 ,Interrupt Targets Non-secure 240" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
bitfld.long 0x00 31. " ITNS287 ,Interrupt Targets Non-secure 287" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS286 ,Interrupt Targets Non-secure 286" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS285 ,Interrupt Targets Non-secure 285" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS284 ,Interrupt Targets Non-secure 284" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS283 ,Interrupt Targets Non-secure 283" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS282 ,Interrupt Targets Non-secure 282" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS281 ,Interrupt Targets Non-secure 281" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS280 ,Interrupt Targets Non-secure 280" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS279 ,Interrupt Targets Non-secure 279" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS278 ,Interrupt Targets Non-secure 278" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS277 ,Interrupt Targets Non-secure 277" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS276 ,Interrupt Targets Non-secure 276" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS275 ,Interrupt Targets Non-secure 275" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS274 ,Interrupt Targets Non-secure 274" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS273 ,Interrupt Targets Non-secure 273" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS272 ,Interrupt Targets Non-secure 272" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS271 ,Interrupt Targets Non-secure 271" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS270 ,Interrupt Targets Non-secure 270" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS269 ,Interrupt Targets Non-secure 269" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS268 ,Interrupt Targets Non-secure 268" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS267 ,Interrupt Targets Non-secure 267" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS266 ,Interrupt Targets Non-secure 266" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS265 ,Interrupt Targets Non-secure 265" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS264 ,Interrupt Targets Non-secure 264" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS263 ,Interrupt Targets Non-secure 263" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS262 ,Interrupt Targets Non-secure 262" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS261 ,Interrupt Targets Non-secure 261" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS260 ,Interrupt Targets Non-secure 260" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS259 ,Interrupt Targets Non-secure 259" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS258 ,Interrupt Targets Non-secure 258" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS257 ,Interrupt Targets Non-secure 257" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS256 ,Interrupt Targets Non-secure 256" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A0++0x03
|
|
hide.long 0x00 "NVIC_ITNS8,Interrupt Target Non-Secure Register 8"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x3A4++0x03
|
|
line.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
bitfld.long 0x00 31. " ITNS319 ,Interrupt Targets Non-secure 319" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS318 ,Interrupt Targets Non-secure 318" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS317 ,Interrupt Targets Non-secure 317" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS316 ,Interrupt Targets Non-secure 316" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS315 ,Interrupt Targets Non-secure 315" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS314 ,Interrupt Targets Non-secure 314" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS313 ,Interrupt Targets Non-secure 313" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS312 ,Interrupt Targets Non-secure 312" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS311 ,Interrupt Targets Non-secure 311" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS310 ,Interrupt Targets Non-secure 310" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS309 ,Interrupt Targets Non-secure 309" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS308 ,Interrupt Targets Non-secure 308" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS307 ,Interrupt Targets Non-secure 307" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS306 ,Interrupt Targets Non-secure 306" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS305 ,Interrupt Targets Non-secure 305" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS304 ,Interrupt Targets Non-secure 304" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS303 ,Interrupt Targets Non-secure 303" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS302 ,Interrupt Targets Non-secure 302" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS301 ,Interrupt Targets Non-secure 301" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS300 ,Interrupt Targets Non-secure 300" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS299 ,Interrupt Targets Non-secure 299" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS298 ,Interrupt Targets Non-secure 298" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS297 ,Interrupt Targets Non-secure 297" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS296 ,Interrupt Targets Non-secure 296" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS295 ,Interrupt Targets Non-secure 295" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS294 ,Interrupt Targets Non-secure 294" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS293 ,Interrupt Targets Non-secure 293" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS292 ,Interrupt Targets Non-secure 292" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS291 ,Interrupt Targets Non-secure 291" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS290 ,Interrupt Targets Non-secure 290" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS289 ,Interrupt Targets Non-secure 289" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS288 ,Interrupt Targets Non-secure 288" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A4++0x03
|
|
hide.long 0x00 "NVIC_ITNS9,Interrupt Target Non-Secure Register 9"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x3A8++0x03
|
|
line.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
bitfld.long 0x00 31. " ITNS351 ,Interrupt Targets Non-secure 351" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS350 ,Interrupt Targets Non-secure 350" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS349 ,Interrupt Targets Non-secure 349" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS348 ,Interrupt Targets Non-secure 348" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS347 ,Interrupt Targets Non-secure 347" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS346 ,Interrupt Targets Non-secure 346" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS345 ,Interrupt Targets Non-secure 345" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS344 ,Interrupt Targets Non-secure 344" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS343 ,Interrupt Targets Non-secure 343" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS342 ,Interrupt Targets Non-secure 342" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS341 ,Interrupt Targets Non-secure 341" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS340 ,Interrupt Targets Non-secure 340" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS339 ,Interrupt Targets Non-secure 339" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS338 ,Interrupt Targets Non-secure 338" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS337 ,Interrupt Targets Non-secure 337" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS336 ,Interrupt Targets Non-secure 336" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS335 ,Interrupt Targets Non-secure 335" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS334 ,Interrupt Targets Non-secure 334" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS333 ,Interrupt Targets Non-secure 333" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS332 ,Interrupt Targets Non-secure 332" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS331 ,Interrupt Targets Non-secure 331" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS330 ,Interrupt Targets Non-secure 330" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS329 ,Interrupt Targets Non-secure 329" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS328 ,Interrupt Targets Non-secure 328" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS327 ,Interrupt Targets Non-secure 327" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS326 ,Interrupt Targets Non-secure 326" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS325 ,Interrupt Targets Non-secure 325" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS324 ,Interrupt Targets Non-secure 324" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS323 ,Interrupt Targets Non-secure 323" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS322 ,Interrupt Targets Non-secure 322" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS321 ,Interrupt Targets Non-secure 321" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS320 ,Interrupt Targets Non-secure 320" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3A8++0x03
|
|
hide.long 0x00 "NVIC_ITNS10,Interrupt Target Non-Secure Register 10"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x3AC++0x03
|
|
line.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
bitfld.long 0x00 31. " ITNS383 ,Interrupt Targets Non-secure 383" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS382 ,Interrupt Targets Non-secure 382" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS381 ,Interrupt Targets Non-secure 381" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS380 ,Interrupt Targets Non-secure 380" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS379 ,Interrupt Targets Non-secure 379" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS378 ,Interrupt Targets Non-secure 378" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS377 ,Interrupt Targets Non-secure 377" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS376 ,Interrupt Targets Non-secure 376" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS375 ,Interrupt Targets Non-secure 375" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS374 ,Interrupt Targets Non-secure 374" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS373 ,Interrupt Targets Non-secure 373" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS372 ,Interrupt Targets Non-secure 372" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS371 ,Interrupt Targets Non-secure 371" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS370 ,Interrupt Targets Non-secure 370" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS369 ,Interrupt Targets Non-secure 369" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS368 ,Interrupt Targets Non-secure 368" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS367 ,Interrupt Targets Non-secure 367" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS366 ,Interrupt Targets Non-secure 366" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS365 ,Interrupt Targets Non-secure 365" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS364 ,Interrupt Targets Non-secure 364" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS363 ,Interrupt Targets Non-secure 363" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS362 ,Interrupt Targets Non-secure 362" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS361 ,Interrupt Targets Non-secure 361" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS360 ,Interrupt Targets Non-secure 360" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS359 ,Interrupt Targets Non-secure 359" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS358 ,Interrupt Targets Non-secure 358" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS357 ,Interrupt Targets Non-secure 357" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS356 ,Interrupt Targets Non-secure 356" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS355 ,Interrupt Targets Non-secure 355" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS354 ,Interrupt Targets Non-secure 354" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS353 ,Interrupt Targets Non-secure 353" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS352 ,Interrupt Targets Non-secure 352" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3AC++0x03
|
|
hide.long 0x00 "NVIC_ITNS11,Interrupt Target Non-Secure Register 11"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
bitfld.long 0x00 31. " ITNS415 ,Interrupt Targets Non-secure 415" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS414 ,Interrupt Targets Non-secure 414" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS413 ,Interrupt Targets Non-secure 413" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS412 ,Interrupt Targets Non-secure 412" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS411 ,Interrupt Targets Non-secure 411" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS410 ,Interrupt Targets Non-secure 410" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS409 ,Interrupt Targets Non-secure 409" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS408 ,Interrupt Targets Non-secure 408" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS407 ,Interrupt Targets Non-secure 407" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS406 ,Interrupt Targets Non-secure 406" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS405 ,Interrupt Targets Non-secure 405" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS404 ,Interrupt Targets Non-secure 404" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS403 ,Interrupt Targets Non-secure 403" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS402 ,Interrupt Targets Non-secure 402" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS401 ,Interrupt Targets Non-secure 401" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS400 ,Interrupt Targets Non-secure 400" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS399 ,Interrupt Targets Non-secure 399" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS398 ,Interrupt Targets Non-secure 398" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS397 ,Interrupt Targets Non-secure 397" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS396 ,Interrupt Targets Non-secure 396" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS395 ,Interrupt Targets Non-secure 395" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS394 ,Interrupt Targets Non-secure 394" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS393 ,Interrupt Targets Non-secure 393" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS392 ,Interrupt Targets Non-secure 392" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS391 ,Interrupt Targets Non-secure 391" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS390 ,Interrupt Targets Non-secure 390" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS389 ,Interrupt Targets Non-secure 389" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS388 ,Interrupt Targets Non-secure 388" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS387 ,Interrupt Targets Non-secure 387" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS386 ,Interrupt Targets Non-secure 386" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS385 ,Interrupt Targets Non-secure 385" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS384 ,Interrupt Targets Non-secure 384" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B0++0x03
|
|
hide.long 0x00 "NVIC_ITNS12,Interrupt Target Non-Secure Register 12"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x3B4++0x03
|
|
line.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
bitfld.long 0x00 31. " ITNS447 ,Interrupt Targets Non-secure 447" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS446 ,Interrupt Targets Non-secure 446" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS445 ,Interrupt Targets Non-secure 445" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS444 ,Interrupt Targets Non-secure 444" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS443 ,Interrupt Targets Non-secure 443" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS442 ,Interrupt Targets Non-secure 442" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS441 ,Interrupt Targets Non-secure 441" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS440 ,Interrupt Targets Non-secure 440" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS439 ,Interrupt Targets Non-secure 439" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS438 ,Interrupt Targets Non-secure 438" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS437 ,Interrupt Targets Non-secure 437" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS436 ,Interrupt Targets Non-secure 436" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS435 ,Interrupt Targets Non-secure 435" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS434 ,Interrupt Targets Non-secure 434" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS433 ,Interrupt Targets Non-secure 433" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS432 ,Interrupt Targets Non-secure 432" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS431 ,Interrupt Targets Non-secure 431" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS430 ,Interrupt Targets Non-secure 430" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS429 ,Interrupt Targets Non-secure 429" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS428 ,Interrupt Targets Non-secure 428" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS427 ,Interrupt Targets Non-secure 427" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS426 ,Interrupt Targets Non-secure 426" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS425 ,Interrupt Targets Non-secure 425" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS424 ,Interrupt Targets Non-secure 424" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS423 ,Interrupt Targets Non-secure 423" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS422 ,Interrupt Targets Non-secure 422" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS421 ,Interrupt Targets Non-secure 421" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS420 ,Interrupt Targets Non-secure 420" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS419 ,Interrupt Targets Non-secure 419" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS418 ,Interrupt Targets Non-secure 418" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS417 ,Interrupt Targets Non-secure 417" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS416 ,Interrupt Targets Non-secure 416" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B4++0x03
|
|
hide.long 0x00 "NVIC_ITNS13,Interrupt Target Non-Secure Register 13"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x3B8++0x03
|
|
line.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
bitfld.long 0x00 31. " ITNS479 ,Interrupt Targets Non-secure 479" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS478 ,Interrupt Targets Non-secure 478" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS477 ,Interrupt Targets Non-secure 477" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS476 ,Interrupt Targets Non-secure 476" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS475 ,Interrupt Targets Non-secure 475" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS474 ,Interrupt Targets Non-secure 474" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS473 ,Interrupt Targets Non-secure 473" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS472 ,Interrupt Targets Non-secure 472" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS471 ,Interrupt Targets Non-secure 471" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS470 ,Interrupt Targets Non-secure 470" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS469 ,Interrupt Targets Non-secure 469" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS468 ,Interrupt Targets Non-secure 468" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS467 ,Interrupt Targets Non-secure 467" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS466 ,Interrupt Targets Non-secure 466" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS465 ,Interrupt Targets Non-secure 465" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS464 ,Interrupt Targets Non-secure 464" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS463 ,Interrupt Targets Non-secure 463" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS462 ,Interrupt Targets Non-secure 462" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS461 ,Interrupt Targets Non-secure 461" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS460 ,Interrupt Targets Non-secure 460" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS459 ,Interrupt Targets Non-secure 459" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS458 ,Interrupt Targets Non-secure 458" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS457 ,Interrupt Targets Non-secure 457" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS456 ,Interrupt Targets Non-secure 456" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS455 ,Interrupt Targets Non-secure 455" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS454 ,Interrupt Targets Non-secure 454" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS453 ,Interrupt Targets Non-secure 453" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS452 ,Interrupt Targets Non-secure 452" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS451 ,Interrupt Targets Non-secure 451" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS450 ,Interrupt Targets Non-secure 450" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS449 ,Interrupt Targets Non-secure 449" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS448 ,Interrupt Targets Non-secure 448" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3B8++0x03
|
|
hide.long 0x00 "NVIC_ITNS14,Interrupt Target Non-Secure Register 14"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x0F)
|
|
group.long 0x3BC++0x03
|
|
line.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
bitfld.long 0x00 31. " ITNS511 ,Interrupt Targets Non-secure 511" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS510 ,Interrupt Targets Non-secure 510" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS509 ,Interrupt Targets Non-secure 509" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS508 ,Interrupt Targets Non-secure 508" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS507 ,Interrupt Targets Non-secure 507" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS506 ,Interrupt Targets Non-secure 506" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS505 ,Interrupt Targets Non-secure 505" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS504 ,Interrupt Targets Non-secure 504" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS503 ,Interrupt Targets Non-secure 503" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS502 ,Interrupt Targets Non-secure 502" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS501 ,Interrupt Targets Non-secure 501" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS500 ,Interrupt Targets Non-secure 500" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS499 ,Interrupt Targets Non-secure 499" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS498 ,Interrupt Targets Non-secure 498" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS497 ,Interrupt Targets Non-secure 497" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS496 ,Interrupt Targets Non-secure 496" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS495 ,Interrupt Targets Non-secure 495" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS494 ,Interrupt Targets Non-secure 494" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS493 ,Interrupt Targets Non-secure 493" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS492 ,Interrupt Targets Non-secure 492" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS491 ,Interrupt Targets Non-secure 491" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS490 ,Interrupt Targets Non-secure 490" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS489 ,Interrupt Targets Non-secure 489" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS488 ,Interrupt Targets Non-secure 488" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS487 ,Interrupt Targets Non-secure 487" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS486 ,Interrupt Targets Non-secure 486" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS485 ,Interrupt Targets Non-secure 485" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS484 ,Interrupt Targets Non-secure 484" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS483 ,Interrupt Targets Non-secure 483" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS482 ,Interrupt Targets Non-secure 482" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS481 ,Interrupt Targets Non-secure 481" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS480 ,Interrupt Targets Non-secure 480" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x3BC++0x03
|
|
hide.long 0x00 "NVIC_ITNS15,Interrupt Target Non-Secure Register 15"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x1F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
line.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_243 ,Interrupt 243 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_242 ,Interrupt 242 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_241 ,Interrupt 241 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_240 ,Interrupt 240 Priority"
|
|
line.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_247 ,Interrupt 247 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_246 ,Interrupt 246 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_245 ,Interrupt 245 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_244 ,Interrupt 244 Priority"
|
|
line.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_251 ,Interrupt 251 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_250 ,Interrupt 250 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_249 ,Interrupt 249 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_248 ,Interrupt 248 Priority"
|
|
line.long 0x1C "IPR63,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_255 ,Interrupt 255 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_254 ,Interrupt 254 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_253 ,Interrupt 253 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_252 ,Interrupt 252 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x1F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR60,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR61,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR62,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR63,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x08)
|
|
group.long 0x500++0x1F
|
|
line.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_259 ,Interrupt 259 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_258 ,Interrupt 258 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_257 ,Interrupt 257 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_256 ,Interrupt 256 Priority"
|
|
line.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_263 ,Interrupt 263 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_262 ,Interrupt 262 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_261 ,Interrupt 261 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_260 ,Interrupt 260 Priority"
|
|
line.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_267 ,Interrupt 267 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_266 ,Interrupt 266 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_265 ,Interrupt 265 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_264 ,Interrupt 264 Priority"
|
|
line.long 0xC "IPR67,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_271 ,Interrupt 271 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_270 ,Interrupt 270 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_269 ,Interrupt 269 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_268 ,Interrupt 268 Priority"
|
|
line.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_275 ,Interrupt 275 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_274 ,Interrupt 274 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_273 ,Interrupt 273 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_272 ,Interrupt 272 Priority"
|
|
line.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_279 ,Interrupt 279 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_278 ,Interrupt 278 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_277 ,Interrupt 277 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_276 ,Interrupt 276 Priority"
|
|
line.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_283 ,Interrupt 283 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_282 ,Interrupt 282 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_281 ,Interrupt 281 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_280 ,Interrupt 280 Priority"
|
|
line.long 0x1C "IPR71,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_287 ,Interrupt 287 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_286 ,Interrupt 286 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_285 ,Interrupt 285 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_284 ,Interrupt 284 Priority"
|
|
else
|
|
hgroup.long 0x500++0x1F
|
|
hide.long 0x0 "IPR64,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR65,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR66,Interrupt Priority Register"
|
|
hide.long 0xC "IPR67,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR68,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR69,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR70,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR71,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x09)
|
|
group.long 0x520++0x1F
|
|
line.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_291 ,Interrupt 291 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_290 ,Interrupt 290 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_289 ,Interrupt 289 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_288 ,Interrupt 288 Priority"
|
|
line.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_295 ,Interrupt 295 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_294 ,Interrupt 294 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_293 ,Interrupt 293 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_292 ,Interrupt 292 Priority"
|
|
line.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_299 ,Interrupt 299 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_298 ,Interrupt 298 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_297 ,Interrupt 297 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_296 ,Interrupt 296 Priority"
|
|
line.long 0xC "IPR75,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_303 ,Interrupt 303 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_302 ,Interrupt 302 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_301 ,Interrupt 301 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_300 ,Interrupt 300 Priority"
|
|
line.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_307 ,Interrupt 307 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_306 ,Interrupt 306 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_305 ,Interrupt 305 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_304 ,Interrupt 304 Priority"
|
|
line.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_311 ,Interrupt 311 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_310 ,Interrupt 310 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_309 ,Interrupt 309 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_308 ,Interrupt 308 Priority"
|
|
line.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_315 ,Interrupt 315 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_314 ,Interrupt 314 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_313 ,Interrupt 313 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_312 ,Interrupt 312 Priority"
|
|
line.long 0x1C "IPR79,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_319 ,Interrupt 319 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_318 ,Interrupt 318 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_317 ,Interrupt 317 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_316 ,Interrupt 316 Priority"
|
|
else
|
|
hgroup.long 0x520++0x1F
|
|
hide.long 0x0 "IPR72,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR73,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR74,Interrupt Priority Register"
|
|
hide.long 0xC "IPR75,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR76,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR77,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR78,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR79,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0A)
|
|
group.long 0x540++0x1F
|
|
line.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_323 ,Interrupt 323 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_322 ,Interrupt 322 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_321 ,Interrupt 321 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_320 ,Interrupt 320 Priority"
|
|
line.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_327 ,Interrupt 327 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_326 ,Interrupt 326 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_325 ,Interrupt 325 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_324 ,Interrupt 324 Priority"
|
|
line.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_331 ,Interrupt 331 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_330 ,Interrupt 330 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_329 ,Interrupt 329 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_328 ,Interrupt 328 Priority"
|
|
line.long 0xC "IPR83,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_335 ,Interrupt 335 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_334 ,Interrupt 334 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_333 ,Interrupt 333 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_332 ,Interrupt 332 Priority"
|
|
line.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_339 ,Interrupt 339 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_338 ,Interrupt 338 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_337 ,Interrupt 337 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_336 ,Interrupt 336 Priority"
|
|
line.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_343 ,Interrupt 343 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_342 ,Interrupt 342 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_341 ,Interrupt 341 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_340 ,Interrupt 340 Priority"
|
|
line.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_347 ,Interrupt 347 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_346 ,Interrupt 346 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_345 ,Interrupt 345 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_344 ,Interrupt 344 Priority"
|
|
line.long 0x1C "IPR87,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_351 ,Interrupt 351 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_350 ,Interrupt 350 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_349 ,Interrupt 349 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_348 ,Interrupt 348 Priority"
|
|
else
|
|
hgroup.long 0x540++0x1F
|
|
hide.long 0x0 "IPR80,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR81,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR82,Interrupt Priority Register"
|
|
hide.long 0xC "IPR83,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR84,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR85,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR86,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR87,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0B)
|
|
group.long 0x560++0x1F
|
|
line.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_355 ,Interrupt 355 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_354 ,Interrupt 354 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_353 ,Interrupt 353 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_352 ,Interrupt 352 Priority"
|
|
line.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_359 ,Interrupt 359 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_358 ,Interrupt 358 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_357 ,Interrupt 357 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_356 ,Interrupt 356 Priority"
|
|
line.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_363 ,Interrupt 363 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_362 ,Interrupt 362 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_361 ,Interrupt 361 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_360 ,Interrupt 360 Priority"
|
|
line.long 0xC "IPR91,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_367 ,Interrupt 367 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_366 ,Interrupt 366 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_365 ,Interrupt 365 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_364 ,Interrupt 364 Priority"
|
|
line.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_371 ,Interrupt 371 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_370 ,Interrupt 370 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_369 ,Interrupt 369 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_368 ,Interrupt 368 Priority"
|
|
line.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_375 ,Interrupt 375 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_374 ,Interrupt 374 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_373 ,Interrupt 373 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_372 ,Interrupt 372 Priority"
|
|
line.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_379 ,Interrupt 379 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_378 ,Interrupt 378 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_377 ,Interrupt 377 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_376 ,Interrupt 376 Priority"
|
|
line.long 0x1C "IPR95,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_383 ,Interrupt 383 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_382 ,Interrupt 382 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_381 ,Interrupt 381 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_380 ,Interrupt 380 Priority"
|
|
else
|
|
hgroup.long 0x560++0x1F
|
|
hide.long 0x0 "IPR88,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR89,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR90,Interrupt Priority Register"
|
|
hide.long 0xC "IPR91,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR92,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR93,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR94,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR95,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0C)
|
|
group.long 0x580++0x1F
|
|
line.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_387 ,Interrupt 387 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_386 ,Interrupt 386 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_385 ,Interrupt 385 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_384 ,Interrupt 384 Priority"
|
|
line.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_391 ,Interrupt 391 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_390 ,Interrupt 390 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_389 ,Interrupt 389 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_388 ,Interrupt 388 Priority"
|
|
line.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_395 ,Interrupt 395 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_394 ,Interrupt 394 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_393 ,Interrupt 393 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_392 ,Interrupt 392 Priority"
|
|
line.long 0xC "IPR99,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_399 ,Interrupt 399 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_398 ,Interrupt 398 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_397 ,Interrupt 397 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_396 ,Interrupt 396 Priority"
|
|
line.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_403 ,Interrupt 403 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_402 ,Interrupt 402 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_401 ,Interrupt 401 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_400 ,Interrupt 400 Priority"
|
|
line.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_407 ,Interrupt 407 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_406 ,Interrupt 406 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_405 ,Interrupt 405 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_404 ,Interrupt 404 Priority"
|
|
line.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_411 ,Interrupt 411 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_410 ,Interrupt 410 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_409 ,Interrupt 409 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_408 ,Interrupt 408 Priority"
|
|
line.long 0x1C "IPR103,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_415 ,Interrupt 415 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_414 ,Interrupt 414 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_413 ,Interrupt 413 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_412 ,Interrupt 412 Priority"
|
|
else
|
|
hgroup.long 0x580++0x1F
|
|
hide.long 0x0 "IPR96,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR97,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR98,Interrupt Priority Register"
|
|
hide.long 0xC "IPR99,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR100,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR101,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR102,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR103,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0D)
|
|
group.long 0x5A0++0x1F
|
|
line.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_419 ,Interrupt 419 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_418 ,Interrupt 418 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_417 ,Interrupt 417 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_416 ,Interrupt 416 Priority"
|
|
line.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_423 ,Interrupt 423 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_422 ,Interrupt 422 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_421 ,Interrupt 421 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_420 ,Interrupt 420 Priority"
|
|
line.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_427 ,Interrupt 427 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_426 ,Interrupt 426 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_425 ,Interrupt 425 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_424 ,Interrupt 424 Priority"
|
|
line.long 0xC "IPR107,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_431 ,Interrupt 431 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_430 ,Interrupt 430 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_429 ,Interrupt 429 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_428 ,Interrupt 428 Priority"
|
|
line.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_435 ,Interrupt 435 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_434 ,Interrupt 434 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_433 ,Interrupt 433 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_432 ,Interrupt 432 Priority"
|
|
line.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_439 ,Interrupt 439 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_438 ,Interrupt 438 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_437 ,Interrupt 437 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_436 ,Interrupt 436 Priority"
|
|
line.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_443 ,Interrupt 443 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_442 ,Interrupt 442 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_441 ,Interrupt 441 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_440 ,Interrupt 440 Priority"
|
|
line.long 0x1C "IPR111,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_447 ,Interrupt 447 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_446 ,Interrupt 446 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_445 ,Interrupt 445 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_444 ,Interrupt 444 Priority"
|
|
else
|
|
hgroup.long 0x5A0++0x1F
|
|
hide.long 0x0 "IPR104,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR105,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR106,Interrupt Priority Register"
|
|
hide.long 0xC "IPR107,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR108,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR109,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR110,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR111,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x0E)
|
|
group.long 0x5C0++0x1F
|
|
line.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_451 ,Interrupt 451 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_450 ,Interrupt 450 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_449 ,Interrupt 449 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_448 ,Interrupt 448 Priority"
|
|
line.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_455 ,Interrupt 455 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_454 ,Interrupt 454 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_453 ,Interrupt 453 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_452 ,Interrupt 452 Priority"
|
|
line.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_459 ,Interrupt 459 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_458 ,Interrupt 458 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_457 ,Interrupt 457 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_456 ,Interrupt 456 Priority"
|
|
line.long 0xC "IPR115,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_463 ,Interrupt 463 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_462 ,Interrupt 462 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_461 ,Interrupt 461 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_460 ,Interrupt 460 Priority"
|
|
line.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_467 ,Interrupt 467 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_466 ,Interrupt 466 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_465 ,Interrupt 465 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_464 ,Interrupt 464 Priority"
|
|
line.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_471 ,Interrupt 471 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_470 ,Interrupt 470 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_469 ,Interrupt 469 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_468 ,Interrupt 468 Priority"
|
|
line.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_475 ,Interrupt 475 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_474 ,Interrupt 474 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_473 ,Interrupt 473 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_472 ,Interrupt 472 Priority"
|
|
line.long 0x1C "IPR119,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_479 ,Interrupt 479 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_478 ,Interrupt 478 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_477 ,Interrupt 477 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_476 ,Interrupt 476 Priority"
|
|
else
|
|
hgroup.long 0x5C0++0x1F
|
|
hide.long 0x0 "IPR112,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR113,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR114,Interrupt Priority Register"
|
|
hide.long 0xC "IPR115,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR116,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR117,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR118,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR119,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif (CORENAME()=="CORTEXM33F")
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " LSPENS ,This bit controls whether the LSPEN bit is writeable from the Non-secure state" "Writeable,Write ignored"
|
|
newline
|
|
bitfld.long 0x00 28. " CLRONRET ,Clear floating point caller saved registers on exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " CLRONRETS ,Clear on return Secure only" "Both states,Secure only"
|
|
bitfld.long 0x00 26. " TS ,Treat as Secure" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 10. " UFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the UsageFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 9. " SPLIMVIOL ,Indicates whether the FP context violates the stack pointer limit that was active when lazy state preservation was activated" "Low,High"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 7. " SFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the SecureFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
newline
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 2. " S ,Indicates the FP context belongs to the specified security state" "Non-secure,Secure"
|
|
newline
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
newline
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x0B
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
newline
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Fully denormalized,?..."
|
|
line.long 0x08 "MVFR2,Media and FP Feature Register 2"
|
|
bitfld.long 0x08 4.--7. " VFP_MISC ,Indicates the hardware support for FP miscellaneous features" "Not supported,,,,Supported,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 13.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,?..."
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x04))&0x20000000)==0x20000000)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
hexmask.long 0x00 5.--28. 0x20 " REMAP ,Remap address"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x00 29. " RMPSPT ,Indicates whether the FPB unit supports Flash Patch remap" "Not supported,Supported"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
textfld " "
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "FP_DEVTYPE,FPB CoreSight Device Type Register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,?..."
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x1000000)==0x0000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DWT_CYCCNT,Cycle Count register"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)))&0x2000000)==0x0000000)
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x04 "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x08 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x10 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x14 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
endif
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value (R),Reserved"
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFCC++0x03
|
|
line.long 0x00 "DWT_DEVTYPE,Device Type Identifier register"
|
|
hexmask.long.byte 0x00 4.--7. 1. " SUB ,Sub-type"
|
|
hexmask.long.byte 0x00 0.--3. 1. " MAJOR ,Major type"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "AC (Analog Comparator)"
|
|
base ad:0x45012000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,Control B"
|
|
bitfld.long 0x4 1. "START1,Comparator 1 Start Comparison" "0,1"
|
|
bitfld.long 0x4 0. "START0,Comparator 0 Start Comparison" "0,1"
|
|
line.long 0x8 "CTRLC,Control C"
|
|
hexmask.long.byte 0x8 28.--31. 1. "CONFIG,Configuration Extension"
|
|
bitfld.long 0x8 27. "AIPMPEN,Analog Input Charge Pump Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 24.--26. "PRESCALER,Prescaling Factor" "0: Sampling rate is GCLK_AC (No division),1: Sampling rate is GCLK_AC/2,2: Sampling rate is GCLK_AC/4,3: Sampling rate is GCLK_AC/8,4: Sampling rate is GCLK_AC/16,5: Sampling rate is GCLK_AC/32,6: Sampling rate is GCLK_AC/64,7: Sampling rate is GCLK_AC/128"
|
|
hexmask.long.word 0x8 12.--21. 1. "PER,Sample and Hold Clock Period"
|
|
newline
|
|
hexmask.long.word 0x8 0.--9. 1. "WIDTH,Sample and Hold Clock Pulse Width"
|
|
line.long 0xC "EVCTRL,Event Control"
|
|
bitfld.long 0xC 25. "INVEI1,Inverted Event Input Enable 1" "0,1"
|
|
bitfld.long 0xC 24. "INVEI0,Inverted Event Input Enable 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "COMPEI1,Comparator 1 Event Input Enable" "0,1"
|
|
bitfld.long 0xC 16. "COMPEI0,Comparator 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 8. "WINEO0,Window 0 Event Output Enable" "0,1"
|
|
bitfld.long 0xC 1. "COMPEO1,Comparator 1 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "COMPEO0,Comparator 0 Event Output Enable" "0,1"
|
|
line.long 0x10 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x10 8. "WIN0,Window 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 1. "COMP1,Comparator 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "COMP0,Comparator 0 Interrupt Enable" "0,1"
|
|
line.long 0x14 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x14 8. "WIN0,Window 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x14 1. "COMP1,Comparator 1 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "COMP0,Comparator 0 Interrupt Enable" "0,1"
|
|
line.long 0x18 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x18 8. "WIN0,Window 0" "0,1"
|
|
bitfld.long 0x18 1. "COMP1,Comparator 1" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0. "COMP0,Comparator 0" "0,1"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x0 "STATUSA,Status A"
|
|
bitfld.long 0x0 16.--17. "WSTATE0,Window 0 Current State" "0: Signal is above window,1: Signal is inside window,2: Signal is below window,?"
|
|
bitfld.long 0x0 1. "STATE1,Comparator 1 Current State" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "STATE0,Comparator 0 Current State" "0,1"
|
|
line.long 0x4 "STATUSB,Status B"
|
|
bitfld.long 0x4 1. "READY1,Comparator 1 Ready" "0,1"
|
|
bitfld.long 0x4 0. "READY0,Comparator 0 Ready" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.long 0x0 0. "DBGRUN,Debug Run" "0,1"
|
|
rgroup.long 0x28++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 10. "WINCTRL0,WINCTRL 0 Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "COMPCTRL1,COMPCTRL 1 Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "COMPCTRL0,COMPCTRL 0 Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "COMPCTRL[$1],Pair n Comparator Control 0"
|
|
hexmask.long.byte 0x0 26.--31. 1. "SUT,Start-up Time"
|
|
bitfld.long 0x0 24.--25. "OUT,Output" "0: The output of COMPn is not routed to the COMPn..,1: The asynchronous output of COMPn is routed to..,2: The synchronous output (including filtering) of..,?"
|
|
newline
|
|
bitfld.long 0x0 21.--23. "FLEN,Filter Length" "0: No filtering,1: 3-bit majority function (2 of 3),2: 5-bit majority function (3 of 5),?,?,?,?,?"
|
|
bitfld.long 0x0 19.--20. "HYST,Hysteresis Level" "0: 10mV,1: 20mV,2: 40mV,3: 60mV"
|
|
newline
|
|
bitfld.long 0x0 17. "SPEED,Speed Selection" "0: High speed high power,1: Low speed low power"
|
|
bitfld.long 0x0 16. "SWAP,Swap Inputs and Invert" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--14. "MUXPOS,Positive Input Mux Selection" "0: I/O pin 0,1: I/O pin 1,2: I/O pin 2,3: I/O pin 3,4: Internal connection 0 device specific,5: Internal connection 1 device specific,6: Internal connection 2 device specific,7: Internal DAC"
|
|
bitfld.long 0x0 8.--10. "MUXNEG,Negative Input Mux Selection" "0: I/O pin 0,1: I/O pin 1,2: I/O pin 2,3: I/O pin 3,4: Internal connection 0 device specific,5: Bangap,6: Ground,7: Internal DAC"
|
|
newline
|
|
bitfld.long 0x0 6. "RUNSTDBY,Run in Standby" "0,1"
|
|
bitfld.long 0x0 4.--5. "INTSEL,Interrupt Selection" "0: Interrupt on comparator output toggle,1: Interrupt on comparator output rising,2: Interrupt on comparator output falling,3: Interrupt on end of comparison (single-shot mode.."
|
|
newline
|
|
bitfld.long 0x0 3. "SINGLE,Single-Shot Mode" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
repeat.end
|
|
group.long 0x38++0x7
|
|
line.long 0x0 "DACCTRL,Dac Control"
|
|
bitfld.long 0x0 31. "SHEN1,DAC1 Sample and Hold Enable Operating Mode" "0,1"
|
|
hexmask.long.byte 0x0 16.--22. 1. "VALUE1,DAC1 Output Value"
|
|
newline
|
|
bitfld.long 0x0 15. "SHEN0,DAC0 Sample and Hold Enable Operating Mode" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "VALUE0,DAC0 Output Value"
|
|
line.long 0x4 "WINCTRL,Window Monitor Control"
|
|
bitfld.long 0x4 1.--2. "WINTSEL,Window n Interrupt Selection" "0: Interrupt on signal above window,1: Interrupt on signal inside window,2: Interrupt on signal below window,3: Interrupt on signal outside window"
|
|
bitfld.long 0x4 0. "WEN,Window n Mode Enable" "0,1"
|
|
tree.end
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
base ad:0x45010000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,CONTROL A REGISTER"
|
|
bitfld.long 0x0 7. "ONDEMAND,On Demand Control" "0,1"
|
|
bitfld.long 0x0 6. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "AIPMPEN,Charge Pump Enable" "0,1"
|
|
bitfld.long 0x0 2. "ANAEN,Analog Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,ENABLE BIT" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,SOFTWARE RESET BIT" "0,1"
|
|
line.long 0x4 "CTRLB,CONTROL B REGISTER"
|
|
bitfld.long 0x4 15. "SWCNVEN,Software Conversion Enable" "0,1"
|
|
bitfld.long 0x4 11. "STRGEN,Synchronous Trigger Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "TRGSUSP,Trigger Suspend" "0,1"
|
|
bitfld.long 0x4 9. "LSWTRG,Level Global Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "GSWTRG,Global Software Trigger" "0,1"
|
|
bitfld.long 0x4 7. "SAMP,Channel Sample" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "RQCNVRT,Request Channel Convert" "0,1"
|
|
bitfld.long 0x4 4.--5. "ADCORSEL,Software Trigger Core Select" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "ADCHSEL,Software Trigger Channel Select"
|
|
line.long 0x8 "CTRLC,Control C Register"
|
|
bitfld.long 0x8 28.--30. "COREINTERLEAVED,Number of Core to Interleave Triggers" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.word 0x8 0.--15. 1. "CNT,Clock Divider for Synchronous Trigger"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CTRLD,Control D Register"
|
|
bitfld.long 0x0 28.--30. "VREFSEL,Voltage Reference Select" "0: AVDD and AVSS,1: External VREFH and AVSS,?,?,?,?,?,?"
|
|
hexmask.long.byte 0x0 24.--27. 1. "WKUPEXP,Wakeup cycles"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "ANLEN,Analog Channel Enable"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CHNEN,Digital Channel Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "CTLCKDIV,Control Clock Divider"
|
|
tree "CONFIG"
|
|
base ad:0x45010020
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CORCTRL,SARCORE Control"
|
|
hexmask.long.byte 0x0 24.--30. 1. "ADCDIV,Division Ratio for SARCORE clock"
|
|
bitfld.long 0x0 22. "SCNRTDS,SCAN Re-trigger Disable" "0,1"
|
|
bitfld.long 0x0 21. "STRGLVL,Scan Trigger Level Sensitivity" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "STRGSRC,SCAN trigger source selection"
|
|
newline
|
|
bitfld.long 0x0 15. "EIRQOVR,Interrupt Type Select" "0,1"
|
|
bitfld.long 0x0 12.--14. "EIS,Early Interrupt Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 10.--11. "SELRES,Selects Resolution" "0: 6 bits,1: 8 bits,2: 10 bits,3: 12 bits (default)"
|
|
hexmask.long.word 0x0 0.--9. 1. "SAMC,Sample Count"
|
|
line.long 0x4 "CHNCFG1,Channel Configuration 1 (LVL/CMPEN)"
|
|
hexmask.long.word 0x4 16.--31. 1. "LVL,Channel Level"
|
|
hexmask.long.word 0x4 0.--15. 1. "CHNCMPEN,Channel Comparator Enable"
|
|
line.long 0x8 "CHNCFG2,Channel Configuration 2(FRACT/CSS)"
|
|
hexmask.long.word 0x8 16.--31. 1. "FRACT,Channel Fractional"
|
|
hexmask.long.word 0x8 0.--15. 1. "CSS,Channel SCAN Select"
|
|
line.long 0xC "CHNCFG3,Channel Configuration3 (SIGN/DIFF)"
|
|
hexmask.long.word 0xC 16.--31. 1. "SIGN,SIGN setting"
|
|
hexmask.long.word 0xC 0.--15. 1. "DIFF,Differential Mode"
|
|
line.long 0x10 "CHNCFG4,Channel Configuration 4 (TRGSRC)"
|
|
hexmask.long.byte 0x10 28.--31. 1. "TRGSRC7,Channel 7 Trigger Source"
|
|
hexmask.long.byte 0x10 24.--27. 1. "TRGSRC6,Channel 6 Trigger Source"
|
|
hexmask.long.byte 0x10 20.--23. 1. "TRGSRC5,Channel 5 Trigger Source"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TRGSRC4,Channel 4 Trigger Source"
|
|
newline
|
|
hexmask.long.byte 0x10 12.--15. 1. "TRGSRC3,Channel 3 Trigger Source"
|
|
hexmask.long.byte 0x10 8.--11. 1. "TRGSRC2,Channel 2 Trigger Source"
|
|
hexmask.long.byte 0x10 4.--7. 1. "TRGSRC1,Channel 1 Trigger Source"
|
|
hexmask.long.byte 0x10 0.--3. 1. "TRGSRC0,Channel 0 Trigger Source"
|
|
line.long 0x14 "CHNCFG5,Channel Configuration 5 (TRGSRC)"
|
|
hexmask.long.byte 0x14 28.--31. 1. "TRGSRC15,Channel 15 Trigger Source"
|
|
hexmask.long.byte 0x14 24.--27. 1. "TRGSRC14,Channel 14 Trigger Source"
|
|
hexmask.long.byte 0x14 20.--23. 1. "TRGSRC13,Channel 13 Trigger Source"
|
|
hexmask.long.byte 0x14 16.--19. 1. "TRGSRC12,Channel 12 Trigger Source"
|
|
newline
|
|
hexmask.long.byte 0x14 12.--15. 1. "TRGSRC11,Channel 11 Trigger Source"
|
|
hexmask.long.byte 0x14 8.--11. 1. "TRGSRC10,Channel 10 Trigger Source"
|
|
hexmask.long.byte 0x14 4.--7. 1. "TRGSRC9,Channel 9 Trigger Source"
|
|
hexmask.long.byte 0x14 0.--3. 1. "TRGSRC8,Channel 8 Trigger Source"
|
|
line.long 0x18 "CALCTRL,SARCORE Calibration Value"
|
|
hexmask.long 0x18 0.--31. 1. "CALBITS,Calibration Values"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CALCTRL_FUSES_ADC_SARCORE_12BIT_V7A0_MODE,SARCORE Calibration Value"
|
|
bitfld.long 0x0 31. "en_ext_bias,Disable Internal Bias Circuit" "0,1"
|
|
bitfld.long 0x0 28.--29. "icmbf,Bias Current Common Mode Buffer" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "icmp_2,Bias Current Stage 2" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "icmp_1,Bias Current Stage 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "iadc_2,Current Consumption 2" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "iadc_1,Current Consumption 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 11.--15. 1. "tclk_div,Test Clock Divider"
|
|
bitfld.long 0x0 9.--10. "t1_dly,Regen Latch Delay" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "sel_del,Scan Mode comp_out" "0,1"
|
|
bitfld.long 0x0 7. "dbg_sel,Debug Bus Select" "0,1"
|
|
bitfld.long 0x0 6. "en_rdac,Disable Power Cycling" "0,1"
|
|
bitfld.long 0x0 5. "dis_laz,Disable auto-zeroing" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dis_saz,Disable auto-zeroing" "0,1"
|
|
bitfld.long 0x0 3. "dis_faz,Disable auto-zeroing" "0,1"
|
|
bitfld.long 0x0 2. "en_dither,Enable Dither" "0,1"
|
|
bitfld.long 0x0 0. "en_cmbf,Enable Common Mode Buffer" "0,1"
|
|
group.long 0x18++0x7
|
|
line.long 0x0 "CALCTRL_FUSES_ADC_SARCORE_12BIT_V7C0_MODE,SARCORE Calibration Value"
|
|
bitfld.long 0x0 31. "en_ext_bias,Disable Internal Bias Circuit" "0,1"
|
|
bitfld.long 0x0 28.--29. "icmbf,Bias Current Common Mode Buffer" "0,1,2,3"
|
|
bitfld.long 0x0 26.--27. "icmp_2,Bias Current Stage 2" "0,1,2,3"
|
|
bitfld.long 0x0 24.--25. "icmp_1,Bias Current Stage 1" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "iadc_2,Current Consumption 2" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "iadc_1,Current Consumption 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 11.--15. 1. "tclk_div,Test Clock Divider"
|
|
bitfld.long 0x0 9.--10. "t1_dly,Regen Latch Delay" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x0 8. "sel_del,Scan Mode comp_out" "0,1"
|
|
bitfld.long 0x0 7. "dbg_sel,Debug Bus Select" "0,1"
|
|
bitfld.long 0x0 6. "en_rdac,Disable Power Cycling" "0,1"
|
|
bitfld.long 0x0 5. "dis_laz,Disable auto-zeroing" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "dis_saz,Disable auto-zeroing" "0,1"
|
|
bitfld.long 0x0 3. "dis_faz,Disable auto-zeroing" "0,1"
|
|
bitfld.long 0x0 2. "en_dither,Enable Dither" "0,1"
|
|
bitfld.long 0x0 0. "en_cmbf,Enable Common Mode Buffer" "0,1"
|
|
line.long 0x4 "EVCTRL,Event Control"
|
|
bitfld.long 0x4 5. "CMPEO,Comparator Window Event Out" "0,1"
|
|
bitfld.long 0x4 4. "RESRDYEO,Result Ready Event Out" "0,1"
|
|
bitfld.long 0x4 3. "STARTINV,Start Conversion Invert" "0,1"
|
|
bitfld.long 0x4 0. "STARTEI,Start Event conversion input enable" "0,1"
|
|
tree.end
|
|
base ad:0x45010000
|
|
group.long 0xB0++0x3
|
|
line.long 0x0 "CMPCTRL,Comparator Control"
|
|
bitfld.long 0x0 29. "IEHIHI,Enable VAL >= CMPHI" "0,1"
|
|
bitfld.long 0x0 28. "IEHILO,Enable VAL < CMPHI" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 16.--27. 1. "ADCMPHI,High Limit of Digital Comparator"
|
|
bitfld.long 0x0 15. "IEBTWN,Enable CMPLO <= VAL < CMPHI" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "IELOHI,Enable VAL >= CMPLO" "0,1"
|
|
bitfld.long 0x0 13. "IELOLO,Enable VAL < CMPLO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "CMPEN,Comparator Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "ADCMPLO,Low Limit of Digital Comparator"
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "FLTCTRL,Filter Control"
|
|
hexmask.long.byte 0x0 10.--13. 1. "FLTCHNID,Channel ID"
|
|
bitfld.long 0x0 8. "FLTEN,Filter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DATA16EN,16bit Averaging Mode" "0,1"
|
|
bitfld.long 0x0 3. "FMODE,Filter Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "OVRSAM,Oversampling Ratio" "0: (If FMODE is 0) 4 samples (shift sum 1 bit to..,1: (If FMODE is 0) 16 samples (shift sum 2 bits to..,2: (If FMODE is 0) 64 samples (shift sum 3 bits to..,3: (If FMODE is 0) 256 samples (shift sum 4 bits to..,4: (If FMODE is 0) 2 samples (shift sum 0 bits to..,5: (If FMODE is 0) 8 samples (shift sum 1 bit to..,6: (If FMODE is 0) 32 samples (shift sum 2 bits to..,7: (If FMODE is 0) 128 samples (shift sum 3 bits to.."
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "CORCHDATAID,Channel Ready DATA ID"
|
|
bitfld.long 0x0 4.--5. "CORDYID,Core Read ID" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "CHRDYID,Channel Read ID"
|
|
line.long 0x4 "CHRDYDAT,Channel Ready Data Register"
|
|
bitfld.long 0x4 27. "FRACT,Fractional Setting" "0,1"
|
|
bitfld.long 0x4 26. "SIGN,Sign Setting" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "DIFF,Differential Setting" "0,1"
|
|
bitfld.long 0x4 24. "LVL,Level Setting" "0,1"
|
|
newline
|
|
hexmask.long.word 0x4 0.--15. 1. "CHRDYDAT,Channel Output Data"
|
|
rgroup.long 0xD8++0x3
|
|
line.long 0x0 "PFFDATA,APB FIFO Output Data"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PFFCNT,Current Data Entries in APB FIFO"
|
|
bitfld.long 0x0 23. "PFFFRACT,Fractional Setting from APB FIFO" "0,1"
|
|
newline
|
|
bitfld.long 0x0 22. "PFFSIGN,Channel Sign from the APB FIFO" "0,1"
|
|
bitfld.long 0x0 20.--21. "PFFCORID,Core ID from APB FIFO" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "PFFCHNID,Channel ID from APB FIFO"
|
|
hexmask.long.word 0x0 0.--15. 1. "PFFDATA,SARCORE Conversion data from the APB FIFO"
|
|
group.long 0xDC++0xB
|
|
line.long 0x0 "DMABASE,DMA Sample Base Address"
|
|
hexmask.long 0x0 0.--31. 1. "DMABASE,DMA Sample Value Base Address"
|
|
line.long 0x4 "DMACTRL,DMA Control Register"
|
|
bitfld.long 0x4 8.--10. "DMABL,DMA System RAM Buffer Length" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DMACR,DMA CORE Enables"
|
|
newline
|
|
bitfld.long 0x4 1. "DMAEN,DMA Enable" "0,1"
|
|
line.long 0x8 "PFFCTRL,APB FIFO Control Register"
|
|
bitfld.long 0x8 16. "PFFRDYDM,DMA APB FIFO Data Ready" "0: Selects CTLINTFLAG.PFFHFUL for the ADC DMA..,1: Selects CTLINTFLAG.PFFRDY for the ADC DMA PFFRDY.."
|
|
hexmask.long.byte 0x8 4.--7. 1. "PFFCR,APB CORE FIFO Enable"
|
|
newline
|
|
bitfld.long 0x8 1. "PFFEN,APB FIFO Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "SYNCBUSY,CORE SYNC Busy Status Register"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB sync busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable bit Sync Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Sync Busy" "0,1"
|
|
group.long 0xF0++0x17
|
|
line.long 0x0 "DMAINTENCLR,DMA Interrupt Enable Clear"
|
|
bitfld.long 0x0 16. "SOVFL,Synchronizer Overflow" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "RBF,Ram Buffer B Full"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "RAF,Ram Buffer A Full"
|
|
line.long 0x4 "DMAINTSET,DMA Interrupt Enable Set"
|
|
bitfld.long 0x4 16. "SOVFL,Synchronizer Overflow" "0,1"
|
|
hexmask.long.byte 0x4 4.--7. 1. "RBF,Ram Buffer B Full"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "RAF,Ram Buffer A Full"
|
|
line.long 0x8 "DMAINTFLAG,DMA Interrupt Flag and Status"
|
|
bitfld.long 0x8 17. "DMAERR,DMA Bus Error" "0,1"
|
|
bitfld.long 0x8 16. "SOVFL,Synchronizer overflow" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 12.--15. 1. "EBF,Ram Buffer B Overflow Error"
|
|
hexmask.long.byte 0x8 8.--11. 1. "EAF,Ram Buffer A Overflow Error"
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "RBF,Ram Buffer B Full"
|
|
hexmask.long.byte 0x8 0.--3. 1. "RAF,Ram Buffer A Full"
|
|
line.long 0xC "CTLINTENSET,CORE Controller Interrupt Enable Set"
|
|
bitfld.long 0xC 11. "PFFHFUL,APB FIFO Half Full" "0,1"
|
|
bitfld.long 0xC 10. "PFFRDY,APB FIFO Ready" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "PFFOVF,APB FIFO Overflow" "0,1"
|
|
bitfld.long 0xC 8. "PFFUNF,APB FIFO Underflow" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "VREFRDY,VREF Ready" "0,1"
|
|
bitfld.long 0xC 6. "VREFUPD,VREF update" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "CRRDY,Core Ready"
|
|
line.long 0x10 "CTLINTENCLR,CORE Controller Interrupt Enable Clear"
|
|
bitfld.long 0x10 11. "PFFHFUL,APB FIFO Half Full" "0,1"
|
|
bitfld.long 0x10 10. "PFFRDY,APB FIFO Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "PFFOVF,APB FIFO overflow" "0,1"
|
|
bitfld.long 0x10 8. "PFFUNF,APB FIFO underflow" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "VREFRDY,VREF Ready" "0,1"
|
|
bitfld.long 0x10 6. "VREFUPD,VREF Update" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--3. 1. "CRRDY,Core Ready Disable"
|
|
line.long 0x14 "CTLINTFLAG,CORE Controller Interrupt Flags"
|
|
bitfld.long 0x14 11. "PFFHFUL,APB FIFO Half Full" "0,1"
|
|
bitfld.long 0x14 10. "PFFRDY,APB FIFO Ready" "0,1"
|
|
newline
|
|
bitfld.long 0x14 9. "PFFOVF,APB FIFO overflow" "0,1"
|
|
bitfld.long 0x14 8. "PFFUNF,APB FIFO underflow" "0,1"
|
|
newline
|
|
bitfld.long 0x14 7. "VREFRDY,VREF Ready" "0,1"
|
|
bitfld.long 0x14 6. "VREFUPD,VREF update" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--3. 1. "CRRDY,Core Ready"
|
|
tree "INT"
|
|
base ad:0x45010120
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
hexmask.long.word 0x0 12.--27. 1. "CHRDY,Channel Ready Disable"
|
|
bitfld.long 0x0 11. "EOSRDY,Endo of Scan Disable" "0,1"
|
|
bitfld.long 0x0 10. "CHNERRC,Channel Overwrite Error Disable" "0,1"
|
|
bitfld.long 0x0 9. "FLTRDY,Filter Ready Disable" "0,1"
|
|
bitfld.long 0x0 8. "CHRDYC,Core Current Channel Disable" "0,1"
|
|
bitfld.long 0x0 7. "SOVFL,Synchronizer Overflow Disable" "0,1"
|
|
bitfld.long 0x0 4. "CMPHIT,Compare Hit Disable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
hexmask.long.word 0x4 16.--31. 1. "CHRDY,Channel Ready Enable"
|
|
bitfld.long 0x4 11. "EOSRDY,End of Scan Enable" "0,1"
|
|
bitfld.long 0x4 10. "CHNERRC,Channel Overwrite Enable" "0,1"
|
|
bitfld.long 0x4 9. "FLTRDY,Filter Ready Enable" "0,1"
|
|
bitfld.long 0x4 8. "CHRDYC,Current Channel Ready Enable" "0,1"
|
|
bitfld.long 0x4 7. "SOVFL,Synchronizer Overflow Enable" "0,1"
|
|
bitfld.long 0x4 4. "CMPHIT,Compare Hit Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flags"
|
|
hexmask.long.word 0x8 16.--31. 1. "CHRDY,Channel Ready"
|
|
hexmask.long.byte 0x8 12.--15. 1. "CRDYID,Channel Ready ID"
|
|
bitfld.long 0x8 11. "EOSRDY,End of Scan Ready" "0,1"
|
|
bitfld.long 0x8 10. "CHNERRC,Channel Overwrite Error" "0,1"
|
|
bitfld.long 0x8 9. "FLTRDY,Filter Ready" "0,1"
|
|
bitfld.long 0x8 8. "CHRDYC,Current Channel Ready" "0,1"
|
|
bitfld.long 0x8 7. "SOVFL,Synchronizer Overflow" "0,1"
|
|
bitfld.long 0x8 4. "CMPHIT,Compare Hit" "0,1"
|
|
hexmask.long.byte 0x8 0.--3. 1. "CMPINTID,Compare Channel ID"
|
|
tree.end
|
|
base ad:0x45010000
|
|
group.long 0x168++0x3
|
|
line.long 0x0 "DBGCTRL,Debug Control Register"
|
|
bitfld.long 0x0 0. "DBGRUN,Debug Running State" "0,1"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512GC01064*")||cpuis("PIC32CK0512GC01100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025GC01064*")||cpuis("PIC32CK1025GC01100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051GC01064*")||cpuis("PIC32CK2051GC01100*")||cpuis("PIC32CK2051GC01144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x0
|
|
tree "CAN0"
|
|
base ad:0x4501E000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
line.long 0x4 "ENDN,Endian"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "MRCFG,Message RAM Configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OFFSET,Base address offset"
|
|
line.long 0x4 "DBTP,Fast Bit Timing and Prescaler"
|
|
bitfld.long 0x4 23. "TDC,Tranceiver Delay Compensation" "0,1"
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x8 "TEST,Test"
|
|
bitfld.long 0x8 7. "RX,Receive Pin" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0: TX controlled by CAN core,1: TX monitoring sample point,2: Dominant (0) level at pin CAN_TX,3: Recessive (1) level at pin CAN_TX"
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1"
|
|
line.long 0xC "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0x10 "CCCR,CC Control"
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1"
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1"
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1"
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "ASM,ASM Restricted Operation Mode" "0,1"
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "INIT,Initialization" "0,1"
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented by TCP,?,?"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSC,Timestamp Counter"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x0 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x0 1.--2. "TOS,Timeout Select" "0: Continuout operation,1: Timeout controlled by TX Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x0 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
line.long 0x4 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x4 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0: No Error,1: Stuff Error,2: Form Error,3: Ack Error,4: Bit1 Error,5: Bit0 Error,6: CRC Error,7: No Change"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error,1: Stuff Error,2: Form Error,3: Ack Error,4: Bit1 Error,5: Bit0 Error,6: CRC Error,7: No Change"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Timestamp Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Timestamp Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Timestamp Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 0.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 0.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
bitfld.long 0x0 31. "ND31,New Data 31" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data 29" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data 27" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data 25" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data 23" "0,1"
|
|
bitfld.long 0x0 22. "ND22,New Data 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data 21" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data 19" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data 17" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data 15" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data 13" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data 11" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data 9" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data 7" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data 5" "0,1"
|
|
bitfld.long 0x0 4. "ND4,New Data 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data 3" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data 1" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data 0" "0,1"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
bitfld.long 0x4 31. "ND63,New Data 63" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data 61" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data 59" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data 57" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data 55" "0,1"
|
|
bitfld.long 0x4 22. "ND54,New Data 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data 53" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data 51" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data 49" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data 47" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data 45" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data 43" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data 41" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data 39" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data 37" "0,1"
|
|
bitfld.long 0x4 4. "ND36,New Data 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data 35" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data 33" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data 32" "0,1"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 0.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 0.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 0.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,2: Debug message A/B received,3: Debug message A/B/C received DMA request set"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 0.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO / Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending 23" "0,1"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending 5" "0,1"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
bitfld.long 0x0 31. "AR31,Add Request 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request 23" "0,1"
|
|
bitfld.long 0x0 22. "AR22,Add Request 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request 5" "0,1"
|
|
bitfld.long 0x0 4. "AR4,Add Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request 0" "0,1"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request 23" "0,1"
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request 5" "0,1"
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred 23" "0,1"
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred 5" "0,1"
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred 0" "0,1"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x4 31. "CF31,Tx Buffer Cancellation Finished 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Tx Buffer Cancellation Finished 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Tx Buffer Cancellation Finished 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Tx Buffer Cancellation Finished 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Tx Buffer Cancellation Finished 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Tx Buffer Cancellation Finished 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Tx Buffer Cancellation Finished 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Tx Buffer Cancellation Finished 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Tx Buffer Cancellation Finished 23" "0,1"
|
|
bitfld.long 0x4 22. "CF22,Tx Buffer Cancellation Finished 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Tx Buffer Cancellation Finished 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Tx Buffer Cancellation Finished 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Tx Buffer Cancellation Finished 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Tx Buffer Cancellation Finished 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Tx Buffer Cancellation Finished 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Tx Buffer Cancellation Finished 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Tx Buffer Cancellation Finished 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Tx Buffer Cancellation Finished 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Tx Buffer Cancellation Finished 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Tx Buffer Cancellation Finished 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Tx Buffer Cancellation Finished 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Tx Buffer Cancellation Finished 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Tx Buffer Cancellation Finished 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Tx Buffer Cancellation Finished 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Tx Buffer Cancellation Finished 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Tx Buffer Cancellation Finished 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Tx Buffer Cancellation Finished 5" "0,1"
|
|
bitfld.long 0x4 4. "CF4,Tx Buffer Cancellation Finished 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Tx Buffer Cancellation Finished 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Tx Buffer Cancellation Finished 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Tx Buffer Cancellation Finished 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Tx Buffer Cancellation Finished 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "ERROR,Error Interrupt Flag"
|
|
bitfld.long 0x0 0. "BERR,AHB Bus Error Detection" "0,1"
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x45020000
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x0 "CREL,Core Release"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REL,Core Release"
|
|
hexmask.long.byte 0x0 24.--27. 1. "STEP,Step of Core Release"
|
|
newline
|
|
hexmask.long.byte 0x0 20.--23. 1. "SUBSTEP,Sub-step of Core Release"
|
|
line.long 0x4 "ENDN,Endian"
|
|
hexmask.long 0x4 0.--31. 1. "ETV,Endianness Test Value"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "MRCFG,Message RAM Configuration"
|
|
hexmask.long.byte 0x0 16.--23. 1. "OFFSET,Base address offset"
|
|
line.long 0x4 "DBTP,Fast Bit Timing and Prescaler"
|
|
bitfld.long 0x4 23. "TDC,Tranceiver Delay Compensation" "0,1"
|
|
hexmask.long.byte 0x4 16.--20. 1. "DBRP,Data Baud Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--12. 1. "DTSEG1,Data time segment before sample point"
|
|
hexmask.long.byte 0x4 4.--7. 1. "DTSEG2,Data time segment after sample point"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--3. 1. "DSJW,Data (Re)Synchronization Jump Width"
|
|
line.long 0x8 "TEST,Test"
|
|
bitfld.long 0x8 7. "RX,Receive Pin" "0,1"
|
|
bitfld.long 0x8 5.--6. "TX,Control of Transmit Pin" "0: TX controlled by CAN core,1: TX monitoring sample point,2: Dominant (0) level at pin CAN_TX,3: Recessive (1) level at pin CAN_TX"
|
|
newline
|
|
bitfld.long 0x8 4. "LBCK,Loop Back Mode" "0,1"
|
|
line.long 0xC "RWD,RAM Watchdog"
|
|
hexmask.long.byte 0xC 8.--15. 1. "WDV,Watchdog Value"
|
|
hexmask.long.byte 0xC 0.--7. 1. "WDC,Watchdog Configuration"
|
|
line.long 0x10 "CCCR,CC Control"
|
|
bitfld.long 0x10 14. "TXP,Transmit Pause" "0,1"
|
|
bitfld.long 0x10 13. "EFBI,Edge Filtering during Bus Integration" "0,1"
|
|
newline
|
|
bitfld.long 0x10 12. "PXHD,Protocol Exception Handling Disable" "0,1"
|
|
bitfld.long 0x10 9. "BRSE,Bit Rate Switch Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "FDOE,FD Operation Enable" "0,1"
|
|
bitfld.long 0x10 7. "TEST,Test Mode Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 6. "DAR,Disable Automatic Retransmission" "0,1"
|
|
bitfld.long 0x10 5. "MON,Bus Monitoring Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "CSR,Clock Stop Request" "0,1"
|
|
bitfld.long 0x10 3. "CSA,Clock Stop Acknowledge" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "ASM,ASM Restricted Operation Mode" "0,1"
|
|
bitfld.long 0x10 1. "CCE,Configuration Change Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "INIT,Initialization" "0,1"
|
|
line.long 0x14 "NBTP,Nominal Bit Timing and Prescaler"
|
|
hexmask.long.byte 0x14 25.--31. 1. "NSJW,Nominal (Re)Synchronization Jump Width"
|
|
hexmask.long.word 0x14 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
|
|
hexmask.long.byte 0x14 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
|
|
line.long 0x18 "TSCC,Timestamp Counter Configuration"
|
|
hexmask.long.byte 0x18 16.--19. 1. "TCP,Timestamp Counter Prescaler"
|
|
bitfld.long 0x18 0.--1. "TSS,Timestamp Select" "0: Timestamp counter value always 0x0000,1: Timestamp counter value incremented by TCP,?,?"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "TSCV,Timestamp Counter Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSC,Timestamp Counter"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "TOCC,Timeout Counter Configuration"
|
|
hexmask.long.word 0x0 16.--31. 1. "TOP,Timeout Period"
|
|
bitfld.long 0x0 1.--2. "TOS,Timeout Select" "0: Continuout operation,1: Timeout controlled by TX Event FIFO,2: Timeout controlled by Rx FIFO 0,3: Timeout controlled by Rx FIFO 1"
|
|
newline
|
|
bitfld.long 0x0 0. "ETOC,Enable Timeout Counter" "0,1"
|
|
line.long 0x4 "TOCV,Timeout Counter Value"
|
|
hexmask.long.word 0x4 0.--15. 1. "TOC,Timeout Counter"
|
|
rgroup.long 0x40++0x7
|
|
line.long 0x0 "ECR,Error Counter"
|
|
hexmask.long.byte 0x0 16.--23. 1. "CEL,CAN Error Logging"
|
|
bitfld.long 0x0 15. "RP,Receive Error Passive" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--14. 1. "REC,Receive Error Counter"
|
|
hexmask.long.byte 0x0 0.--7. 1. "TEC,Transmit Error Counter"
|
|
line.long 0x4 "PSR,Protocol Status"
|
|
hexmask.long.byte 0x4 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
|
|
bitfld.long 0x4 14. "PXE,Protocol Exception Event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "RFDF,Received a CAN FD Message" "0,1"
|
|
bitfld.long 0x4 12. "RBRS,BRS flag of last received CAN FD Message" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "RESI,ESI flag of last received CAN FD Message" "0,1"
|
|
bitfld.long 0x4 8.--10. "DLEC,Data Phase Last Error Code" "0: No Error,1: Stuff Error,2: Form Error,3: Ack Error,4: Bit1 Error,5: Bit0 Error,6: CRC Error,7: No Change"
|
|
newline
|
|
bitfld.long 0x4 7. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x4 6. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x4 3.--4. "ACT,Activity" "0: Node is synchronizing on CAN communication,1: Node is neither receiver nor transmitter,2: Node is operating as receiver,3: Node is operating as transmitter"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "LEC,Last Error Code" "0: No Error,1: Stuff Error,2: Form Error,3: Ack Error,4: Bit1 Error,5: Bit0 Error,6: CRC Error,7: No Change"
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "TDCR,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x0 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
|
|
hexmask.long.byte 0x0 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Length"
|
|
group.long 0x50++0xF
|
|
line.long 0x0 "IR,Interrupt"
|
|
bitfld.long 0x0 29. "ARA,Access to Reserved Address" "0,1"
|
|
bitfld.long 0x0 28. "PED,Protocol Error in Data Phase" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
|
|
bitfld.long 0x0 26. "WDI,Watchdog Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "BO,Bus_Off Status" "0,1"
|
|
bitfld.long 0x0 24. "EW,Warning Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "EP,Error Passive" "0,1"
|
|
bitfld.long 0x0 22. "ELO,Error Logging Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
|
|
bitfld.long 0x0 18. "TOO,Timeout Occurred" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MRAF,Message RAM Access Failure" "0,1"
|
|
bitfld.long 0x0 16. "TSW,Timestamp Wraparound" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 14. "TEFF,Tx Event FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
|
|
bitfld.long 0x0 12. "TEFN,Tx Event FIFO New Entry" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TFE,Tx FIFO Empty" "0,1"
|
|
bitfld.long 0x0 10. "TCF,Transmission Cancellation Finished" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TC,Timestamp Completed" "0,1"
|
|
bitfld.long 0x0 8. "HPM,High Priority Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
bitfld.long 0x0 6. "RF1F,Rx FIFO 1 FIFO Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 4. "RF1N,Rx FIFO 1 New Message" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 2. "RF0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
|
|
bitfld.long 0x0 0. "RF0N,Rx FIFO 0 New Message" "0,1"
|
|
line.long 0x4 "IE,Interrupt Enable"
|
|
bitfld.long 0x4 29. "ARAE,Access to Reserved Address Enable" "0,1"
|
|
bitfld.long 0x4 28. "PEDE,Protocol Error in Data Phase Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "PEAE,Protocol Error in Arbitration Phase Enable" "0,1"
|
|
bitfld.long 0x4 26. "WDIE,Watchdog Interrupt Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "EWE,Warning Status Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "EPE,Error Passive Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "DRXE,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "TEFLE,Tx Event FIFO Element Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "TCFE,Transmission Cancellation Finished Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "TCE,Timestamp Completed Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "HPME,High Priority Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "RF1LE,Rx FIFO 1 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 6. "RF1FE,Rx FIFO 1 FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
|
|
line.long 0x8 "ILS,Interrupt Line Select"
|
|
bitfld.long 0x8 29. "ARAL,Access to Reserved Address Line" "0,1"
|
|
bitfld.long 0x8 28. "PEDL,Protocol Error in Data Phase Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 27. "PEAL,Protocol Error in Arbitration Phase Line" "0,1"
|
|
bitfld.long 0x8 26. "WDIL,Watchdog Interrupt Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
|
|
bitfld.long 0x8 24. "EWL,Warning Status Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 23. "EPL,Error Passive Interrupt Line" "0,1"
|
|
bitfld.long 0x8 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
|
|
bitfld.long 0x8 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
|
|
bitfld.long 0x8 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "TEFLL,Tx Event FIFO Element Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
|
|
bitfld.long 0x8 10. "TCFL,Transmission Cancellation Finished Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "TCL,Timestamp Completed Interrupt Line" "0,1"
|
|
bitfld.long 0x8 8. "HPML,High Priority Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "RF1LL,Rx FIFO 1 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 6. "RF1FL,Rx FIFO 1 FIFO Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
|
|
bitfld.long 0x8 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
|
|
bitfld.long 0x8 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
|
|
line.long 0xC "ILE,Interrupt Line Enable"
|
|
bitfld.long 0xC 1. "EINT1,Enable Interrupt Line 1" "0,1"
|
|
bitfld.long 0xC 0. "EINT0,Enable Interrupt Line 0" "0,1"
|
|
group.long 0x80++0xB
|
|
line.long 0x0 "GFC,Global Filter Configuration"
|
|
bitfld.long 0x0 4.--5. "ANFS,Accept Non-matching Frames Standard" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,?"
|
|
bitfld.long 0x0 2.--3. "ANFE,Accept Non-matching Frames Extended" "0: Accept in Rx FIFO 0,1: Accept in Rx FIFO 1,2: Reject,?"
|
|
newline
|
|
bitfld.long 0x0 1. "RRFS,Reject Remote Frames Standard" "0,1"
|
|
bitfld.long 0x0 0. "RRFE,Reject Remote Frames Extended" "0,1"
|
|
line.long 0x4 "SIDFC,Standard ID Filter Configuration"
|
|
hexmask.long.byte 0x4 16.--23. 1. "LSS,List Size Standard"
|
|
hexmask.long.word 0x4 0.--15. 1. "FLSSA,Filter List Standard Start Address"
|
|
line.long 0x8 "XIDFC,Extended ID Filter Configuration"
|
|
hexmask.long.byte 0x8 16.--22. 1. "LSE,List Size Extended"
|
|
hexmask.long.word 0x8 0.--15. 1. "FLESA,Filter List Extended Start Address"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "XIDAM,Extended ID AND Mask"
|
|
hexmask.long 0x0 0.--28. 1. "EIDM,Extended ID Mask"
|
|
rgroup.long 0x94++0x3
|
|
line.long 0x0 "HPMS,High Priority Message Status"
|
|
bitfld.long 0x0 15. "FLST,Filter List" "0,1"
|
|
hexmask.long.byte 0x0 8.--14. 1. "FIDX,Filter Index"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "MSI,Message Storage Indicator" "0: No FIFO selected,1: FIFO message lost,2: Message stored in FIFO 0,3: Message stored in FIFO 1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "BIDX,Buffer Index"
|
|
group.long 0x98++0xB
|
|
line.long 0x0 "NDAT1,New Data 1"
|
|
bitfld.long 0x0 31. "ND31,New Data 31" "0,1"
|
|
bitfld.long 0x0 30. "ND30,New Data 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "ND29,New Data 29" "0,1"
|
|
bitfld.long 0x0 28. "ND28,New Data 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "ND27,New Data 27" "0,1"
|
|
bitfld.long 0x0 26. "ND26,New Data 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "ND25,New Data 25" "0,1"
|
|
bitfld.long 0x0 24. "ND24,New Data 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "ND23,New Data 23" "0,1"
|
|
bitfld.long 0x0 22. "ND22,New Data 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "ND21,New Data 21" "0,1"
|
|
bitfld.long 0x0 20. "ND20,New Data 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "ND19,New Data 19" "0,1"
|
|
bitfld.long 0x0 18. "ND18,New Data 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "ND17,New Data 17" "0,1"
|
|
bitfld.long 0x0 16. "ND16,New Data 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "ND15,New Data 15" "0,1"
|
|
bitfld.long 0x0 14. "ND14,New Data 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "ND13,New Data 13" "0,1"
|
|
bitfld.long 0x0 12. "ND12,New Data 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ND11,New Data 11" "0,1"
|
|
bitfld.long 0x0 10. "ND10,New Data 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ND9,New Data 9" "0,1"
|
|
bitfld.long 0x0 8. "ND8,New Data 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "ND7,New Data 7" "0,1"
|
|
bitfld.long 0x0 6. "ND6,New Data 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ND5,New Data 5" "0,1"
|
|
bitfld.long 0x0 4. "ND4,New Data 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ND3,New Data 3" "0,1"
|
|
bitfld.long 0x0 2. "ND2,New Data 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ND1,New Data 1" "0,1"
|
|
bitfld.long 0x0 0. "ND0,New Data 0" "0,1"
|
|
line.long 0x4 "NDAT2,New Data 2"
|
|
bitfld.long 0x4 31. "ND63,New Data 63" "0,1"
|
|
bitfld.long 0x4 30. "ND62,New Data 62" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "ND61,New Data 61" "0,1"
|
|
bitfld.long 0x4 28. "ND60,New Data 60" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "ND59,New Data 59" "0,1"
|
|
bitfld.long 0x4 26. "ND58,New Data 58" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "ND57,New Data 57" "0,1"
|
|
bitfld.long 0x4 24. "ND56,New Data 56" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "ND55,New Data 55" "0,1"
|
|
bitfld.long 0x4 22. "ND54,New Data 54" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "ND53,New Data 53" "0,1"
|
|
bitfld.long 0x4 20. "ND52,New Data 52" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "ND51,New Data 51" "0,1"
|
|
bitfld.long 0x4 18. "ND50,New Data 50" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "ND49,New Data 49" "0,1"
|
|
bitfld.long 0x4 16. "ND48,New Data 48" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "ND47,New Data 47" "0,1"
|
|
bitfld.long 0x4 14. "ND46,New Data 46" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "ND45,New Data 45" "0,1"
|
|
bitfld.long 0x4 12. "ND44,New Data 44" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "ND43,New Data 43" "0,1"
|
|
bitfld.long 0x4 10. "ND42,New Data 42" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "ND41,New Data 41" "0,1"
|
|
bitfld.long 0x4 8. "ND40,New Data 40" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "ND39,New Data 39" "0,1"
|
|
bitfld.long 0x4 6. "ND38,New Data 38" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ND37,New Data 37" "0,1"
|
|
bitfld.long 0x4 4. "ND36,New Data 36" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ND35,New Data 35" "0,1"
|
|
bitfld.long 0x4 2. "ND34,New Data 34" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ND33,New Data 33" "0,1"
|
|
bitfld.long 0x4 0. "ND32,New Data 32" "0,1"
|
|
line.long 0x8 "RXF0C,Rx FIFO 0 Configuration"
|
|
bitfld.long 0x8 31. "F0OM,FIFO 0 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F0S,Rx FIFO 0 Size"
|
|
hexmask.long.word 0x8 0.--15. 1. "F0SA,Rx FIFO 0 Start Address"
|
|
rgroup.long 0xA4++0x3
|
|
line.long 0x0 "RXF0S,Rx FIFO 0 Status"
|
|
bitfld.long 0x0 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
|
|
bitfld.long 0x0 24. "F0F,Rx FIFO 0 Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--21. 1. "F0PI,Rx FIFO 0 Put Index"
|
|
hexmask.long.byte 0x0 8.--13. 1. "F0GI,Rx FIFO 0 Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
|
|
group.long 0xA8++0xB
|
|
line.long 0x0 "RXF0A,Rx FIFO 0 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F0AI,Rx FIFO 0 Acknowledge Index"
|
|
line.long 0x4 "RXBC,Rx Buffer Configuration"
|
|
hexmask.long.word 0x4 0.--15. 1. "RBSA,Rx Buffer Start Address"
|
|
line.long 0x8 "RXF1C,Rx FIFO 1 Configuration"
|
|
bitfld.long 0x8 31. "F1OM,FIFO 1 Operation Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--30. 1. "F1WM,Rx FIFO 1 Watermark"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--22. 1. "F1S,Rx FIFO 1 Size"
|
|
hexmask.long.word 0x8 0.--15. 1. "F1SA,Rx FIFO 1 Start Address"
|
|
rgroup.long 0xB4++0x3
|
|
line.long 0x0 "RXF1S,Rx FIFO 1 Status"
|
|
bitfld.long 0x0 30.--31. "DMS,Debug Message Status" "0: Idle state,1: Debug message A received,2: Debug message A/B received,3: Debug message A/B/C received DMA request set"
|
|
bitfld.long 0x0 25. "RF1L,Rx FIFO 1 Message Lost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "F1F,Rx FIFO 1 Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--21. 1. "F1PI,Rx FIFO 1 Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "F1GI,Rx FIFO 1 Get Index"
|
|
hexmask.long.byte 0x0 0.--6. 1. "F1FL,Rx FIFO 1 Fill Level"
|
|
group.long 0xB8++0xB
|
|
line.long 0x0 "RXF1A,Rx FIFO 1 Acknowledge"
|
|
hexmask.long.byte 0x0 0.--5. 1. "F1AI,Rx FIFO 1 Acknowledge Index"
|
|
line.long 0x4 "RXESC,Rx Buffer / FIFO Element Size Configuration"
|
|
bitfld.long 0x4 8.--10. "RBDS,Rx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
bitfld.long 0x4 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
line.long 0x8 "TXBC,Tx Buffer Configuration"
|
|
bitfld.long 0x8 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
|
|
hexmask.long.byte 0x8 24.--29. 1. "TFQS,Transmit FIFO/Queue Size"
|
|
newline
|
|
hexmask.long.byte 0x8 16.--21. 1. "NDTB,Number of Dedicated Transmit Buffers"
|
|
hexmask.long.word 0x8 0.--15. 1. "TBSA,Tx Buffers Start Address"
|
|
rgroup.long 0xC4++0x3
|
|
line.long 0x0 "TXFQS,Tx FIFO / Queue Status"
|
|
bitfld.long 0x0 21. "TFQF,Tx FIFO/Queue Full" "0,1"
|
|
hexmask.long.byte 0x0 16.--20. 1. "TFQPI,Tx FIFO/Queue Put Index"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--12. 1. "TFGI,Tx FIFO Get Index"
|
|
hexmask.long.byte 0x0 0.--5. 1. "TFFL,Tx FIFO Free Level"
|
|
group.long 0xC8++0x3
|
|
line.long 0x0 "TXESC,Tx Buffer Element Size Configuration"
|
|
bitfld.long 0x0 0.--2. "TBDS,Tx Buffer Data Field Size" "0: 8 byte data field,1: 12 byte data field,2: 16 byte data field,3: 20 byte data field,4: 24 byte data field,5: 32 byte data field,6: 48 byte data field,7: 64 byte data field"
|
|
rgroup.long 0xCC++0x3
|
|
line.long 0x0 "TXBRP,Tx Buffer Request Pending"
|
|
bitfld.long 0x0 31. "TRP31,Transmission Request Pending 31" "0,1"
|
|
bitfld.long 0x0 30. "TRP30,Transmission Request Pending 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TRP29,Transmission Request Pending 29" "0,1"
|
|
bitfld.long 0x0 28. "TRP28,Transmission Request Pending 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TRP27,Transmission Request Pending 27" "0,1"
|
|
bitfld.long 0x0 26. "TRP26,Transmission Request Pending 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TRP25,Transmission Request Pending 25" "0,1"
|
|
bitfld.long 0x0 24. "TRP24,Transmission Request Pending 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TRP23,Transmission Request Pending 23" "0,1"
|
|
bitfld.long 0x0 22. "TRP22,Transmission Request Pending 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TRP21,Transmission Request Pending 21" "0,1"
|
|
bitfld.long 0x0 20. "TRP20,Transmission Request Pending 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TRP19,Transmission Request Pending 19" "0,1"
|
|
bitfld.long 0x0 18. "TRP18,Transmission Request Pending 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TRP17,Transmission Request Pending 17" "0,1"
|
|
bitfld.long 0x0 16. "TRP16,Transmission Request Pending 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TRP15,Transmission Request Pending 15" "0,1"
|
|
bitfld.long 0x0 14. "TRP14,Transmission Request Pending 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TRP13,Transmission Request Pending 13" "0,1"
|
|
bitfld.long 0x0 12. "TRP12,Transmission Request Pending 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TRP11,Transmission Request Pending 11" "0,1"
|
|
bitfld.long 0x0 10. "TRP10,Transmission Request Pending 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TRP9,Transmission Request Pending 9" "0,1"
|
|
bitfld.long 0x0 8. "TRP8,Transmission Request Pending 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TRP7,Transmission Request Pending 7" "0,1"
|
|
bitfld.long 0x0 6. "TRP6,Transmission Request Pending 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TRP5,Transmission Request Pending 5" "0,1"
|
|
bitfld.long 0x0 4. "TRP4,Transmission Request Pending 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TRP3,Transmission Request Pending 3" "0,1"
|
|
bitfld.long 0x0 2. "TRP2,Transmission Request Pending 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TRP1,Transmission Request Pending 1" "0,1"
|
|
bitfld.long 0x0 0. "TRP0,Transmission Request Pending 0" "0,1"
|
|
group.long 0xD0++0x7
|
|
line.long 0x0 "TXBAR,Tx Buffer Add Request"
|
|
bitfld.long 0x0 31. "AR31,Add Request 31" "0,1"
|
|
bitfld.long 0x0 30. "AR30,Add Request 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "AR29,Add Request 29" "0,1"
|
|
bitfld.long 0x0 28. "AR28,Add Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "AR27,Add Request 27" "0,1"
|
|
bitfld.long 0x0 26. "AR26,Add Request 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "AR25,Add Request 25" "0,1"
|
|
bitfld.long 0x0 24. "AR24,Add Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "AR23,Add Request 23" "0,1"
|
|
bitfld.long 0x0 22. "AR22,Add Request 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "AR21,Add Request 21" "0,1"
|
|
bitfld.long 0x0 20. "AR20,Add Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "AR19,Add Request 19" "0,1"
|
|
bitfld.long 0x0 18. "AR18,Add Request 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "AR17,Add Request 17" "0,1"
|
|
bitfld.long 0x0 16. "AR16,Add Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "AR15,Add Request 15" "0,1"
|
|
bitfld.long 0x0 14. "AR14,Add Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "AR13,Add Request 13" "0,1"
|
|
bitfld.long 0x0 12. "AR12,Add Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "AR11,Add Request 11" "0,1"
|
|
bitfld.long 0x0 10. "AR10,Add Request 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "AR9,Add Request 9" "0,1"
|
|
bitfld.long 0x0 8. "AR8,Add Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "AR7,Add Request 7" "0,1"
|
|
bitfld.long 0x0 6. "AR6,Add Request 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "AR5,Add Request 5" "0,1"
|
|
bitfld.long 0x0 4. "AR4,Add Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "AR3,Add Request 3" "0,1"
|
|
bitfld.long 0x0 2. "AR2,Add Request 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "AR1,Add Request 1" "0,1"
|
|
bitfld.long 0x0 0. "AR0,Add Request 0" "0,1"
|
|
line.long 0x4 "TXBCR,Tx Buffer Cancellation Request"
|
|
bitfld.long 0x4 31. "CR31,Cancellation Request 31" "0,1"
|
|
bitfld.long 0x4 30. "CR30,Cancellation Request 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CR29,Cancellation Request 29" "0,1"
|
|
bitfld.long 0x4 28. "CR28,Cancellation Request 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CR27,Cancellation Request 27" "0,1"
|
|
bitfld.long 0x4 26. "CR26,Cancellation Request 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CR25,Cancellation Request 25" "0,1"
|
|
bitfld.long 0x4 24. "CR24,Cancellation Request 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CR23,Cancellation Request 23" "0,1"
|
|
bitfld.long 0x4 22. "CR22,Cancellation Request 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CR21,Cancellation Request 21" "0,1"
|
|
bitfld.long 0x4 20. "CR20,Cancellation Request 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CR19,Cancellation Request 19" "0,1"
|
|
bitfld.long 0x4 18. "CR18,Cancellation Request 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CR17,Cancellation Request 17" "0,1"
|
|
bitfld.long 0x4 16. "CR16,Cancellation Request 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CR15,Cancellation Request 15" "0,1"
|
|
bitfld.long 0x4 14. "CR14,Cancellation Request 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CR13,Cancellation Request 13" "0,1"
|
|
bitfld.long 0x4 12. "CR12,Cancellation Request 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CR11,Cancellation Request 11" "0,1"
|
|
bitfld.long 0x4 10. "CR10,Cancellation Request 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CR9,Cancellation Request 9" "0,1"
|
|
bitfld.long 0x4 8. "CR8,Cancellation Request 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CR7,Cancellation Request 7" "0,1"
|
|
bitfld.long 0x4 6. "CR6,Cancellation Request 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CR5,Cancellation Request 5" "0,1"
|
|
bitfld.long 0x4 4. "CR4,Cancellation Request 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CR3,Cancellation Request 3" "0,1"
|
|
bitfld.long 0x4 2. "CR2,Cancellation Request 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CR1,Cancellation Request 1" "0,1"
|
|
bitfld.long 0x4 0. "CR0,Cancellation Request 0" "0,1"
|
|
rgroup.long 0xD8++0x7
|
|
line.long 0x0 "TXBTO,Tx Buffer Transmission Occurred"
|
|
bitfld.long 0x0 31. "TO31,Transmission Occurred 31" "0,1"
|
|
bitfld.long 0x0 30. "TO30,Transmission Occurred 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TO29,Transmission Occurred 29" "0,1"
|
|
bitfld.long 0x0 28. "TO28,Transmission Occurred 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TO27,Transmission Occurred 27" "0,1"
|
|
bitfld.long 0x0 26. "TO26,Transmission Occurred 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TO25,Transmission Occurred 25" "0,1"
|
|
bitfld.long 0x0 24. "TO24,Transmission Occurred 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TO23,Transmission Occurred 23" "0,1"
|
|
bitfld.long 0x0 22. "TO22,Transmission Occurred 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TO21,Transmission Occurred 21" "0,1"
|
|
bitfld.long 0x0 20. "TO20,Transmission Occurred 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TO19,Transmission Occurred 19" "0,1"
|
|
bitfld.long 0x0 18. "TO18,Transmission Occurred 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TO17,Transmission Occurred 17" "0,1"
|
|
bitfld.long 0x0 16. "TO16,Transmission Occurred 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TO15,Transmission Occurred 15" "0,1"
|
|
bitfld.long 0x0 14. "TO14,Transmission Occurred 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TO13,Transmission Occurred 13" "0,1"
|
|
bitfld.long 0x0 12. "TO12,Transmission Occurred 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TO11,Transmission Occurred 11" "0,1"
|
|
bitfld.long 0x0 10. "TO10,Transmission Occurred 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TO9,Transmission Occurred 9" "0,1"
|
|
bitfld.long 0x0 8. "TO8,Transmission Occurred 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TO7,Transmission Occurred 7" "0,1"
|
|
bitfld.long 0x0 6. "TO6,Transmission Occurred 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TO5,Transmission Occurred 5" "0,1"
|
|
bitfld.long 0x0 4. "TO4,Transmission Occurred 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TO3,Transmission Occurred 3" "0,1"
|
|
bitfld.long 0x0 2. "TO2,Transmission Occurred 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TO1,Transmission Occurred 1" "0,1"
|
|
bitfld.long 0x0 0. "TO0,Transmission Occurred 0" "0,1"
|
|
line.long 0x4 "TXBCF,Tx Buffer Cancellation Finished"
|
|
bitfld.long 0x4 31. "CF31,Tx Buffer Cancellation Finished 31" "0,1"
|
|
bitfld.long 0x4 30. "CF30,Tx Buffer Cancellation Finished 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CF29,Tx Buffer Cancellation Finished 29" "0,1"
|
|
bitfld.long 0x4 28. "CF28,Tx Buffer Cancellation Finished 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CF27,Tx Buffer Cancellation Finished 27" "0,1"
|
|
bitfld.long 0x4 26. "CF26,Tx Buffer Cancellation Finished 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CF25,Tx Buffer Cancellation Finished 25" "0,1"
|
|
bitfld.long 0x4 24. "CF24,Tx Buffer Cancellation Finished 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CF23,Tx Buffer Cancellation Finished 23" "0,1"
|
|
bitfld.long 0x4 22. "CF22,Tx Buffer Cancellation Finished 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CF21,Tx Buffer Cancellation Finished 21" "0,1"
|
|
bitfld.long 0x4 20. "CF20,Tx Buffer Cancellation Finished 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CF19,Tx Buffer Cancellation Finished 19" "0,1"
|
|
bitfld.long 0x4 18. "CF18,Tx Buffer Cancellation Finished 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CF17,Tx Buffer Cancellation Finished 17" "0,1"
|
|
bitfld.long 0x4 16. "CF16,Tx Buffer Cancellation Finished 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CF15,Tx Buffer Cancellation Finished 15" "0,1"
|
|
bitfld.long 0x4 14. "CF14,Tx Buffer Cancellation Finished 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CF13,Tx Buffer Cancellation Finished 13" "0,1"
|
|
bitfld.long 0x4 12. "CF12,Tx Buffer Cancellation Finished 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CF11,Tx Buffer Cancellation Finished 11" "0,1"
|
|
bitfld.long 0x4 10. "CF10,Tx Buffer Cancellation Finished 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CF9,Tx Buffer Cancellation Finished 9" "0,1"
|
|
bitfld.long 0x4 8. "CF8,Tx Buffer Cancellation Finished 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CF7,Tx Buffer Cancellation Finished 7" "0,1"
|
|
bitfld.long 0x4 6. "CF6,Tx Buffer Cancellation Finished 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CF5,Tx Buffer Cancellation Finished 5" "0,1"
|
|
bitfld.long 0x4 4. "CF4,Tx Buffer Cancellation Finished 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CF3,Tx Buffer Cancellation Finished 3" "0,1"
|
|
bitfld.long 0x4 2. "CF2,Tx Buffer Cancellation Finished 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CF1,Tx Buffer Cancellation Finished 1" "0,1"
|
|
bitfld.long 0x4 0. "CF0,Tx Buffer Cancellation Finished 0" "0,1"
|
|
group.long 0xE0++0x7
|
|
line.long 0x0 "TXBTIE,Tx Buffer Transmission Interrupt Enable"
|
|
bitfld.long 0x0 31. "TIE31,Transmission Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x0 30. "TIE30,Transmission Interrupt Enable 30" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "TIE29,Transmission Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x0 28. "TIE28,Transmission Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "TIE27,Transmission Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x0 26. "TIE26,Transmission Interrupt Enable 26" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "TIE25,Transmission Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x0 24. "TIE24,Transmission Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TIE23,Transmission Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x0 22. "TIE22,Transmission Interrupt Enable 22" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TIE21,Transmission Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x0 20. "TIE20,Transmission Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TIE19,Transmission Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x0 18. "TIE18,Transmission Interrupt Enable 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TIE17,Transmission Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x0 16. "TIE16,Transmission Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TIE15,Transmission Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x0 14. "TIE14,Transmission Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TIE13,Transmission Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x0 12. "TIE12,Transmission Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "TIE11,Transmission Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x0 10. "TIE10,Transmission Interrupt Enable 10" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "TIE9,Transmission Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x0 8. "TIE8,Transmission Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "TIE7,Transmission Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x0 6. "TIE6,Transmission Interrupt Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "TIE5,Transmission Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x0 4. "TIE4,Transmission Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TIE3,Transmission Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x0 2. "TIE2,Transmission Interrupt Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "TIE1,Transmission Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x0 0. "TIE0,Transmission Interrupt Enable 0" "0,1"
|
|
line.long 0x4 "TXBCIE,Tx Buffer Cancellation Finished Interrupt Enable"
|
|
bitfld.long 0x4 31. "CFIE31,Cancellation Finished Interrupt Enable 31" "0,1"
|
|
bitfld.long 0x4 30. "CFIE30,Cancellation Finished Interrupt Enable 30" "0,1"
|
|
newline
|
|
bitfld.long 0x4 29. "CFIE29,Cancellation Finished Interrupt Enable 29" "0,1"
|
|
bitfld.long 0x4 28. "CFIE28,Cancellation Finished Interrupt Enable 28" "0,1"
|
|
newline
|
|
bitfld.long 0x4 27. "CFIE27,Cancellation Finished Interrupt Enable 27" "0,1"
|
|
bitfld.long 0x4 26. "CFIE26,Cancellation Finished Interrupt Enable 26" "0,1"
|
|
newline
|
|
bitfld.long 0x4 25. "CFIE25,Cancellation Finished Interrupt Enable 25" "0,1"
|
|
bitfld.long 0x4 24. "CFIE24,Cancellation Finished Interrupt Enable 24" "0,1"
|
|
newline
|
|
bitfld.long 0x4 23. "CFIE23,Cancellation Finished Interrupt Enable 23" "0,1"
|
|
bitfld.long 0x4 22. "CFIE22,Cancellation Finished Interrupt Enable 22" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "CFIE21,Cancellation Finished Interrupt Enable 21" "0,1"
|
|
bitfld.long 0x4 20. "CFIE20,Cancellation Finished Interrupt Enable 20" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CFIE19,Cancellation Finished Interrupt Enable 19" "0,1"
|
|
bitfld.long 0x4 18. "CFIE18,Cancellation Finished Interrupt Enable 18" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "CFIE17,Cancellation Finished Interrupt Enable 17" "0,1"
|
|
bitfld.long 0x4 16. "CFIE16,Cancellation Finished Interrupt Enable 16" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CFIE15,Cancellation Finished Interrupt Enable 15" "0,1"
|
|
bitfld.long 0x4 14. "CFIE14,Cancellation Finished Interrupt Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "CFIE13,Cancellation Finished Interrupt Enable 13" "0,1"
|
|
bitfld.long 0x4 12. "CFIE12,Cancellation Finished Interrupt Enable 12" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CFIE11,Cancellation Finished Interrupt Enable 11" "0,1"
|
|
bitfld.long 0x4 10. "CFIE10,Cancellation Finished Interrupt Enable 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "CFIE9,Cancellation Finished Interrupt Enable 9" "0,1"
|
|
bitfld.long 0x4 8. "CFIE8,Cancellation Finished Interrupt Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CFIE7,Cancellation Finished Interrupt Enable 7" "0,1"
|
|
bitfld.long 0x4 6. "CFIE6,Cancellation Finished Interrupt Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "CFIE5,Cancellation Finished Interrupt Enable 5" "0,1"
|
|
bitfld.long 0x4 4. "CFIE4,Cancellation Finished Interrupt Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CFIE3,Cancellation Finished Interrupt Enable 3" "0,1"
|
|
bitfld.long 0x4 2. "CFIE2,Cancellation Finished Interrupt Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "CFIE1,Cancellation Finished Interrupt Enable 1" "0,1"
|
|
bitfld.long 0x4 0. "CFIE0,Cancellation Finished Interrupt Enable 0" "0,1"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "TXEFC,Tx Event FIFO Configuration"
|
|
hexmask.long.byte 0x0 24.--29. 1. "EFWM,Event FIFO Watermark"
|
|
hexmask.long.byte 0x0 16.--21. 1. "EFS,Event FIFO Size"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "EFSA,Event FIFO Start Address"
|
|
rgroup.long 0xF4++0x3
|
|
line.long 0x0 "TXEFS,Tx Event FIFO Status"
|
|
bitfld.long 0x0 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
|
|
bitfld.long 0x0 24. "EFF,Event FIFO Full" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--20. 1. "EFPI,Event FIFO Put Index"
|
|
hexmask.long.byte 0x0 8.--12. 1. "EFGI,Event FIFO Get Index"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "EFFL,Event FIFO Fill Level"
|
|
group.long 0xF8++0x3
|
|
line.long 0x0 "TXEFA,Tx Event FIFO Acknowledge"
|
|
hexmask.long.byte 0x0 0.--4. 1. "EFAI,Event FIFO Acknowledge Index"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "ERROR,Error Interrupt Flag"
|
|
bitfld.long 0x0 0. "BERR,AHB Bus Error Detection" "0,1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "CCL (Configurable Custom Logic)"
|
|
base ad:0x4501A000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "CTRL,Control"
|
|
bitfld.byte 0x0 6. "RUNSTDBY,Run in Standby" "0: Generic clock is not required in standby sleep..,1: Generic clock is required in standby sleep mode"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0: The peripheral is disabled,1: The peripheral is enabled"
|
|
newline
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0: The peripheral is not reset,1: The peripheral is reset"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "SEQCTRL[$1],SEQ Control x"
|
|
hexmask.byte 0x0 0.--3. 1. "SEQSEL,Sequential Selection"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "LUTCTRL[$1],LUT Control x"
|
|
hexmask.long.byte 0x0 24.--31. 1. "TRUTH,Truth Value"
|
|
bitfld.long 0x0 22. "LUTEO,LUT Event Output Enable" "0: LUT event output is disabled,1: LUT event output is enabled"
|
|
newline
|
|
bitfld.long 0x0 21. "LUTEI,LUT Event Input Enable" "0: LUT incoming event is disabled,1: LUT incoming event is enabled"
|
|
bitfld.long 0x0 20. "INVEI,Inverted Event Input Enable" "0: Incoming event is not inverted,1: Incoming event is inverted"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "INSEL2,Input Selection 2"
|
|
hexmask.long.byte 0x0 12.--15. 1. "INSEL1,Input Selection 1"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "INSEL0,Input Selection 0"
|
|
bitfld.long 0x0 7. "EDGESEL,Edge Selection" "0: Edge detector is disabled,1: Edge detector is enabled"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "FILTSEL,Filter Selection" "0: Filter disabled,1: Synchronizer enabled,2: Filter enabled,?"
|
|
bitfld.long 0x0 1. "ENABLE,LUT Enable" "0: LUT block is disabled,1: LUT block is enabled"
|
|
repeat.end
|
|
tree.end
|
|
tree "CMCC (Cortex M Cache Controller)"
|
|
base ad:0x44808000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TYPE,Cache Type Register"
|
|
bitfld.long 0x0 11.--13. "CLSIZE,Cache Line Size" "0: Cache Line Size is 4 bytes,1: Cache Line Size is 8 bytes,2: Cache Line Size is 16 bytes,3: Cache Line Size is 32 bytes,4: Cache Line Size is 64 bytes,5: Cache Line Size is 128 bytes,?,?"
|
|
bitfld.long 0x0 8.--10. "CSIZE,Cache Size" "0: Cache Size is 1 KB,1: Cache Size is 2 KB,2: Cache Size is 4 KB,3: Cache Size is 8 KB,4: Cache Size is 16 KB,5: Cache Size is 32 KB,6: Cache Size is 64 KB,?"
|
|
bitfld.long 0x0 7. "LCKDOWN,Lock Down supported" "0,1"
|
|
bitfld.long 0x0 5.--6. "WAYNUM,Number of Way" "0: Direct Mapped Cache,1: 2-WAY set associative,2: 4-WAY set associative,?"
|
|
newline
|
|
bitfld.long 0x0 4. "RRP,Round Robin Policy supported" "0,1"
|
|
bitfld.long 0x0 1. "GCLK,dynamic Clock Gating supported" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CFG,Cache Configuration Register"
|
|
bitfld.long 0x0 4.--6. "CSIZESW,Cache size configured by software" "0: The Cache Size is configured to 1KB,1: The Cache Size is configured to 2KB,2: The Cache Size is configured to 4KB,3: The Cache Size is configured to 8KB,4: The Cache Size is configured to 16KB,5: The Cache Size is configured to 32KB,6: The Cache Size is configured to 64KB,?"
|
|
bitfld.long 0x0 2. "DCDIS,Data Cache Disable" "0,1"
|
|
bitfld.long 0x0 1. "ICDIS,Instruction Cache Disable" "0,1"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "CTRL,Cache Control Register"
|
|
bitfld.long 0x0 0. "CEN,Cache Controller Enable" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "SR,Cache Status Register"
|
|
bitfld.long 0x0 0. "CSTS,Cache Controller Status" "0,1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "LCKWAY,Cache Lock per Way Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "LCKWAY,Lockdown way Register"
|
|
wgroup.long 0x20++0x7
|
|
line.long 0x0 "MAINT0,Cache Maintenance Register 0"
|
|
bitfld.long 0x0 0. "INVALL,Cache Controller invalidate All" "0,1"
|
|
line.long 0x4 "MAINT1,Cache Maintenance Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "WAY,Invalidate Way"
|
|
hexmask.long.byte 0x4 4.--11. 1. "INDEX,Invalidate Index"
|
|
group.long 0x28++0x7
|
|
line.long 0x0 "MCFG,Cache Monitor Configuration Register"
|
|
bitfld.long 0x0 0.--1. "MODE,Cache Controller Monitor Counter Mode" "0: Cycle counter,1: Instruction hit counter,2: Data hit counter,?"
|
|
line.long 0x4 "MEN,Cache Monitor Enable Register"
|
|
bitfld.long 0x4 0. "MENABLE,Cache Controller Monitor Enable" "0,1"
|
|
wgroup.long 0x30++0x3
|
|
line.long 0x0 "MCTRL,Cache Monitor Control Register"
|
|
bitfld.long 0x0 0. "SWRST,Cache Controller Software Reset" "0,1"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "MSR,Cache Monitor Status Register"
|
|
hexmask.long 0x0 0.--31. 1. "EVENT_CNT,Monitor Event Counter"
|
|
tree.end
|
|
tree "COREDEBUG (Debug Control Block)"
|
|
base ad:0xE000EDF0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x0 26. "S_RESTART_ST,Restart sticky status" "0,1"
|
|
bitfld.long 0x0 25. "S_RESET_ST,Reset sticky status" "0,1"
|
|
bitfld.long 0x0 24. "S_RETIRE_ST,Retire sticky status" "0,1"
|
|
bitfld.long 0x0 20. "S_SDE,Secure debug enabled" "0,1"
|
|
bitfld.long 0x0 19. "S_LOCKUP,Lockup status" "0,1"
|
|
bitfld.long 0x0 18. "S_SLEEP,Sleeping status" "0,1"
|
|
bitfld.long 0x0 17. "S_HALT,Halted status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "S_REGRDY,Register ready status" "0,1"
|
|
bitfld.long 0x0 5. "S_SNAPSTALL,Snap stall control" "0,1"
|
|
bitfld.long 0x0 3. "C_MASKINTS,Mask PendSV SysTick and external configurable interrupts" "0,1"
|
|
bitfld.long 0x0 2. "C_STEP,Enable single step" "0,1"
|
|
bitfld.long 0x0 1. "C_HALT,Halt processor" "0,1"
|
|
bitfld.long 0x0 0. "C_DEBUGEN,Enable Halting debug" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DCRSR,Debug Core Register Select Register"
|
|
bitfld.long 0x0 16. "REGWnR,Register write/not-read access" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "REGSEL,Register selector"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DBGTMP,Data temporary buffer"
|
|
line.long 0x4 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x4 24. "TRCENA,Global DWT and ITM features enable" "0,1"
|
|
bitfld.long 0x4 20. "SDME,Secure DebugMonitor enable" "0,1"
|
|
bitfld.long 0x4 19. "MON_REQ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x4 18. "MON_STEP,Enable DebugMonitor stepping" "0,1"
|
|
bitfld.long 0x4 17. "MON_PEND,DebugMonitor pending state" "0,1"
|
|
bitfld.long 0x4 16. "MON_EN,DebugMonitor enable" "0,1"
|
|
bitfld.long 0x4 11. "VC_SFERR,SecureFault exception Halting debug vector catch enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "VC_HARDERR,HardFault exception Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 9. "VC_INTERR,Excception entry and return faults Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 8. "VC_BUSERR,BusFault exception Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 7. "VC_STATERR,UsageFault exception state information error Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 6. "VC_CHKERR,UsageFault exception checking error Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 5. "VC_NOCPERR,UsageFault exception coprocessor access Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 4. "VC_MMERR,MemManage exception Halting debug vector catch enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "VC_CORERESET,Core reset Halting debug vector catch enable" "0,1"
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
endif
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x0 17. "CDSKEY,CDS field write-enable key" "0,1"
|
|
bitfld.long 0x0 16. "CDS,Current domain Secure" "0,1"
|
|
bitfld.long 0x0 1. "SBRSEL,Secure Banked register select" "0,1"
|
|
bitfld.long 0x0 0. "SBRSELEN,Secure Banked register select enable" "0,1"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "COREDEBUG_NS (Debug Control Block (Non-Secure))"
|
|
base ad:0xE002EDF0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x0 26. "S_RESTART_ST,Restart sticky status" "0,1"
|
|
bitfld.long 0x0 25. "S_RESET_ST,Reset sticky status" "0,1"
|
|
bitfld.long 0x0 24. "S_RETIRE_ST,Retire sticky status" "0,1"
|
|
bitfld.long 0x0 20. "S_SDE,Secure debug enabled" "0,1"
|
|
bitfld.long 0x0 19. "S_LOCKUP,Lockup status" "0,1"
|
|
bitfld.long 0x0 18. "S_SLEEP,Sleeping status" "0,1"
|
|
bitfld.long 0x0 17. "S_HALT,Halted status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "S_REGRDY,Register ready status" "0,1"
|
|
bitfld.long 0x0 5. "S_SNAPSTALL,Snap stall control" "0,1"
|
|
bitfld.long 0x0 3. "C_MASKINTS,Mask PendSV SysTick and external configurable interrupts" "0,1"
|
|
bitfld.long 0x0 2. "C_STEP,Enable single step" "0,1"
|
|
bitfld.long 0x0 1. "C_HALT,Halt processor" "0,1"
|
|
bitfld.long 0x0 0. "C_DEBUGEN,Enable Halting debug" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "DCRSR,Debug Core Register Select Register"
|
|
bitfld.long 0x0 16. "REGWnR,Register write/not-read access" "0,1"
|
|
hexmask.long.byte 0x0 0.--6. 1. "REGSEL,Register selector"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DBGTMP,Data temporary buffer"
|
|
line.long 0x4 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x4 24. "TRCENA,Global DWT and ITM features enable" "0,1"
|
|
bitfld.long 0x4 20. "SDME,Secure DebugMonitor enable" "0,1"
|
|
bitfld.long 0x4 19. "MON_REQ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x4 18. "MON_STEP,Enable DebugMonitor stepping" "0,1"
|
|
bitfld.long 0x4 17. "MON_PEND,DebugMonitor pending state" "0,1"
|
|
bitfld.long 0x4 16. "MON_EN,DebugMonitor enable" "0,1"
|
|
bitfld.long 0x4 11. "VC_SFERR,SecureFault exception Halting debug vector catch enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "VC_HARDERR,HardFault exception Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 9. "VC_INTERR,Excception entry and return faults Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 8. "VC_BUSERR,BusFault exception Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 7. "VC_STATERR,UsageFault exception state information error Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 6. "VC_CHKERR,UsageFault exception checking error Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 5. "VC_NOCPERR,UsageFault exception coprocessor access Halting debug vector catch enable" "0,1"
|
|
bitfld.long 0x4 4. "VC_MMERR,MemManage exception Halting debug vector catch enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "VC_CORERESET,Core reset Halting debug vector catch enable" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x0 3. "INTSPNIDEN,Internal Secure non-invasive debug enable" "0,1"
|
|
bitfld.long 0x0 2. "SPNIDENSEL,Secure non-invasive debug enable select" "0,1"
|
|
bitfld.long 0x0 1. "INTSPIDEN,Internal Secure invasive debug enable" "0,1"
|
|
bitfld.long 0x0 0. "SPIDENSEL,Secure invasive debug enable select" "0,1"
|
|
line.long 0x4 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x4 17. "CDSKEY,CDS field write-enable key" "0,1"
|
|
bitfld.long 0x4 16. "CDS,Current domain Secure" "0,1"
|
|
bitfld.long 0x4 1. "SBRSEL,Secure Banked register select" "0,1"
|
|
bitfld.long 0x4 0. "SBRSELEN,Secure Banked register select enable" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "DIB (Debug Identification Block)"
|
|
base ad:0xE000EFB0
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "DLAR,SCS Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0x4++0xB
|
|
line.long 0x0 "DLSR,SCS Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
line.long 0x4 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x4 6.--7. "SNID," "0: Security Extension not implemented,?,2: Secure non-invasive debug prohibited,3: Secure non-invasive debug allowed"
|
|
bitfld.long 0x4 4.--5. "SID," "0: Security Extension not implemented,?,2: Secure invasive debug prohibited,3: Secure invasive debug allowed"
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
endif
|
|
line.long 0x8 "DDEVARCH,SCS Device Architecture Register"
|
|
hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Architect"
|
|
bitfld.long 0x8 20. "PRESENT,DEVARCH Present" "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "REVISION,Revision"
|
|
hexmask.long.byte 0x8 12.--15. 1. "ARCHVER,Architecture Version"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "ARCHPART,Architecture Part"
|
|
rgroup.long 0x1C++0x33
|
|
line.long 0x0 "DDEVTYPE,SCS Device Type Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SUB,Sub-type"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type"
|
|
line.long 0x4 "DPIDR4,SCS Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x8 "DPIDR5,SCS Peripheral Identification Register 5"
|
|
line.long 0xC "DPIDR6,SCS Peripheral Identification Register 6"
|
|
line.long 0x10 "DPIDR7,SCS Peripheral Identification Register 7"
|
|
line.long 0x14 "DPIDR0,SCS Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x18 "DPIDR1,SCS Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x18 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x1C "DPIDR2,SCS Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x1C 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x1C 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "DPIDR3,SCS Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x24 "DCIDR0,SCS Component Identification Register 0"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x28 "DCIDR1,SCS Component Identification Register 1"
|
|
hexmask.long.byte 0x28 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x2C "DCIDR2,SCS Component Identification Register 2"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x30 "DCIDR3,SCS Component Identification Register 3"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "DIB_NS (Debug Identification Block (Non-Secure))"
|
|
base ad:0xE002EFB0
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "DLAR,SCS Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0x4++0xB
|
|
line.long 0x0 "DLSR,SCS Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
line.long 0x4 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x4 6.--7. "SNID," "0: Security Extension not implemented,?,2: Secure non-invasive debug prohibited,3: Secure non-invasive debug allowed"
|
|
bitfld.long 0x4 4.--5. "SID," "0: Security Extension not implemented,?,2: Secure invasive debug prohibited,3: Secure invasive debug allowed"
|
|
bitfld.long 0x4 2. "NSNID," "?,?"
|
|
bitfld.long 0x4 0. "NSID," "?,?"
|
|
line.long 0x8 "DDEVARCH,SCS Device Architecture Register"
|
|
hexmask.long.word 0x8 21.--31. 1. "ARCHITECT,Architect"
|
|
bitfld.long 0x8 20. "PRESENT,DEVARCH Present" "0,1"
|
|
hexmask.long.byte 0x8 16.--19. 1. "REVISION,Revision"
|
|
hexmask.long.byte 0x8 12.--15. 1. "ARCHVER,Architecture Version"
|
|
newline
|
|
hexmask.long.word 0x8 0.--11. 1. "ARCHPART,Architecture Part"
|
|
rgroup.long 0x1C++0x33
|
|
line.long 0x0 "DDEVTYPE,SCS Device Type Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SUB,Sub-type"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type"
|
|
line.long 0x4 "DPIDR4,SCS Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x8 "DPIDR5,SCS Peripheral Identification Register 5"
|
|
line.long 0xC "DPIDR6,SCS Peripheral Identification Register 6"
|
|
line.long 0x10 "DPIDR7,SCS Peripheral Identification Register 7"
|
|
line.long 0x14 "DPIDR0,SCS Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x18 "DPIDR1,SCS Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x18 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x1C "DPIDR2,SCS Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x1C 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x1C 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "DPIDR3,SCS Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x24 "DCIDR0,SCS Component Identification Register 0"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x28 "DCIDR1,SCS Component Identification Register 1"
|
|
hexmask.long.byte 0x28 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x2C "DCIDR2,SCS Component Identification Register 2"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x30 "DCIDR3,SCS Component Identification Register 3"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
endif
|
|
tree "DMA (Direct Memory Access)"
|
|
base ad:0x0
|
|
tree "DMA0"
|
|
base ad:0x44802000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTRLA,DMA CONTROL A REGISTER"
|
|
bitfld.long 0x0 1. "ENABLE,DMA Enable" "0,1"
|
|
line.long 0x4 "CTRLB,DMA CONTROL B REGISTER"
|
|
bitfld.long 0x4 24.--25. "QOS4,Priority Group 4 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
bitfld.long 0x4 16.--17. "QOS3,Priority Group 3 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
bitfld.long 0x4 8.--9. "QOS2,Priority Group 2 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
bitfld.long 0x4 0.--1. "QOS1,Priority Group 1 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
line.long 0x8 "DBGCTRL,DEBUG CONTROL REGISTER"
|
|
bitfld.long 0x8 0. "DBGRUN,Debug Run" "0,1"
|
|
line.long 0xC "CRCPOLYA,DMA CRC POLYNOMIAL A REGISTER"
|
|
hexmask.long 0xC 0.--31. 1. "POLYA,CRC Polynomial Coefficients A Register"
|
|
line.long 0x10 "CRCPOLYB,DMA CRC POLYNOMIAL B REGISTER"
|
|
hexmask.long 0x10 0.--31. 1. "POLYB,CRC Polynomial Coefficients B Register"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "INTSTAT3,DMA INTERRUPT PRIORITY 3 STATUS REGISTER"
|
|
bitfld.long 0x0 23. "CH23,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 22. "CH22,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 21. "CH21,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 20. "CH20,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CH19,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 18. "CH18,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 17. "CH17,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 16. "CH16,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH15,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 14. "CH14,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 13. "CH13,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 12. "CH12,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CH11,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 10. "CH10,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 9. "CH9,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 8. "CH8,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 6. "CH6,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 5. "CH5,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 4. "CH4,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 2. "CH2,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 1. "CH1,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 0. "CH0,DMA Channel active interrupt at priority 3" "0,1"
|
|
line.long 0x4 "INTSTAT2,DMA INTERRUPT PRIORITY 2 STATUS REGISTER"
|
|
bitfld.long 0x4 23. "CH23,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 22. "CH22,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 21. "CH21,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 20. "CH20,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CH19,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 18. "CH18,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 17. "CH17,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 16. "CH16,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH15,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 14. "CH14,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 13. "CH13,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 12. "CH12,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CH11,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 10. "CH10,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 9. "CH9,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 8. "CH8,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH7,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 6. "CH6,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 5. "CH5,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 4. "CH4,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CH3,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 2. "CH2,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 1. "CH1,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 0. "CH0,DMA Channel active interrupt at priority 2" "0,1"
|
|
line.long 0x8 "INTSTAT1,DMA INTERRUPT PRIORITY 1 STATUS REGISTER"
|
|
bitfld.long 0x8 23. "CH23,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 22. "CH22,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 21. "CH21,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 20. "CH20,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CH19,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 18. "CH18,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 17. "CH17,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 16. "CH16,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CH15,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 14. "CH14,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 13. "CH13,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 12. "CH12,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CH11,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 10. "CH10,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 9. "CH9,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 8. "CH8,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "CH7,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 6. "CH6,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 5. "CH5,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 4. "CH4,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CH3,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 2. "CH2,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 1. "CH1,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 0. "CH0,DMA Channel active interrupt at priority 1" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x44802050 ad:0x448020A0 ad:0x448020F0 ad:0x44802140 ad:0x44802190 ad:0x448021E0 ad:0x44802230 ad:0x44802280)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x3B
|
|
line.long 0x0 "CHCTRLA,CHANNEL CONTROL REGISTER A"
|
|
bitfld.long 0x0 24. "RUNSTDBY,Run In Standby" "0,1"
|
|
bitfld.long 0x0 16. "SWFRC,Software Forced Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LLEN,Linked List Enable" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Channel Enable" "0,1"
|
|
line.long 0x4 "CHCTRLB,CHANNEL CONTROL REGISTER B"
|
|
bitfld.long 0x4 31. "CRCEN,CRC Enable bit" "0,1"
|
|
bitfld.long 0x4 29. "CASTEN,Cell Auto Start Enable of Ensuing Transfers for this channel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PATEN,Channel Pattern Match Abort Enable." "0,1"
|
|
bitfld.long 0x4 25. "PATLEN,Pattern Match Length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "PIGNEN,Enable Pattern Ignore Byte" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "TRIG,Trigger that can Start a Channel Transfer"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "BYTORD,Byte Order" "0: Bytes are processed AS IS,1: Bytes are swapped as: BYTE3 to BYTE0 BYTE2 to..,2: Bytes are swapped as: BYTE3 to BYTE1 BYTE2 to..,3: Bytes are swapped as: BYTE3 to BYTE2 BYTE2 to.."
|
|
bitfld.long 0x4 13. "WBOEN,Write Byte Order Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "PRI,Channel Priority level." "0: Channel Priority is 1,1: Channel Priority is 2,2: Channel Priority is 3 (HIGHEST),?"
|
|
bitfld.long 0x4 4.--6. "RAS,Channel Read Address Sequence" "0: Incrementing Address+1 with Transfers of Byte..,1: Incrementing Address+2 with Transfers of..,2: Auto Increment Address and Transfer Size,3: Fixed Byte Address (Single Byte Address with..,4: Fixed Address of HalfWord Operand (Single..,5: Fixed Address Word Burst Transfer,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "WAS,Channel Write Address Sequence." "0: Incrementing Address+1 with Transfers of Byte..,1: Incrementing Address+2 with Transfers of..,2: Auto Increment Address and Transfer Size,3: Fixed Byte Address (Single Byte Address with..,4: Fixed Address of HalfWord Operand (Single..,5: Fixed Address Word Burst Transfer,?,?"
|
|
line.long 0x8 "CHEVCTRL,CHANNEL EVENT CONTROL REGISTER"
|
|
bitfld.long 0x8 7. "EVOE,Channel Event Output Enable (0: disable; 1: enable)" "0: disable,1: enable"
|
|
bitfld.long 0x8 6. "EVSTRIE,Channel Start Event Input Enable (0: disable; 1:enable)" "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x8 5. "EVAUXIE,Channel Auxiliary Event Enable (0: disable; 1: enable)" "0: disable,1: enable"
|
|
bitfld.long 0x8 2.--3. "EVOMODE,Channel Event Output Mode" "0: Generate a channel event strobe for 1 clock..,1: Generate a channel event strobe for 1 clock..,2: Generate a channel event strobe from start event..,3: Generate a channel event strobe from start event.."
|
|
newline
|
|
bitfld.long 0x8 0.--1. "EVAUXACT,Channel Auxiliary Event Input Action" "0: Event Aborts Bock Transfer,1: Event Increments Channel Priority,2: Event acts as a Conditional Trigger,?"
|
|
line.long 0xC "CHINTENCLR,CHANNEL INTERRUPT ENABLE CLEAR REGISTER"
|
|
bitfld.long 0xC 5. "LL,Clear Linked List Done Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 4. "BH,Clear Block Transfer Half Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "BC,Clear Cell Transfer Complete Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 2. "CC,Clear Cell Transfer Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TA,Clear Transfer Abort Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 0. "SD,Channel Event Output Enable" "0,1"
|
|
line.long 0x10 "CHINTENSET,CHANNEL INTERRUPT ENABLE SET REGISTER"
|
|
bitfld.long 0x10 5. "LL,set Linked List Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 4. "BH,set Block Transfer Half Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "BC,set Cell Transfer Complete Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 2. "CC,set Cell Transfer Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TA,Set Transfer Abort Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 0. "SD,Channel Event Output Enable" "0,1"
|
|
line.long 0x14 "CHINTF,CHANNEL INTERRUPT FLAG REGISTER"
|
|
bitfld.long 0x14 18. "RDE,Read Error Flag (0: none; 1: Read Error)" "0: none,1: Read Error"
|
|
bitfld.long 0x14 17. "WRE,Write Error Flag (0: none; 1: Write Error)" "0: none,1: Write Error"
|
|
newline
|
|
bitfld.long 0x14 5. "LL,Linked List Done Interrupt Flag (0: none; 1: done)" "0: none,1: done"
|
|
bitfld.long 0x14 4. "BH,Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete)" "0: none,1: half complete"
|
|
newline
|
|
bitfld.long 0x14 3. "BC,Block Transfer Complete Interrupt Flag (0: none; 1:complete;)" "0: none,1: complete"
|
|
bitfld.long 0x14 2. "CC,Cell Transfer Complete Interrupt Flag (0: none ; 1: complete)" "0: none,1: complete"
|
|
newline
|
|
bitfld.long 0x14 1. "TA,Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted)" "0: none,1: Transfer Aborted"
|
|
bitfld.long 0x14 0. "SD,Start Detected Interrupt Flag (0: none ; 1: Start Detected)" "0: none,1: Start Detected"
|
|
line.long 0x18 "CHSSA,CHANNEL SOURCE START ADDRESS"
|
|
hexmask.long 0x18 0.--31. 1. "SSA,Channel Source Start Address"
|
|
line.long 0x1C "CHDSA,CHANNEL DESTINATION START ADDRESS"
|
|
hexmask.long 0x1C 0.--31. 1. "DSA,Channel Destination Start Address"
|
|
line.long 0x20 "CHSSTRD,CHANNEL SOURCE CELL STRIDE SIZE REGISTER"
|
|
hexmask.long.word 0x20 0.--15. 1. "SSTRD,Source Cell Stride Size"
|
|
line.long 0x24 "CHDSTRD,CHANNEL DESTINATION CELL STRIDE SIZE REGISTER"
|
|
hexmask.long.word 0x24 0.--15. 1. "DSTRD,Destination Cell Stride Size"
|
|
line.long 0x28 "CHXSIZ,CHANNEL TRANSFER SIZE REGISTER"
|
|
hexmask.long.word 0x28 16.--31. 1. "BLKSZ,Block transfer size in bytes."
|
|
hexmask.long.word 0x28 0.--9. 1. "CSZ,Cell transfer size in bytes."
|
|
line.long 0x2C "CHPDAT,CHANNEL PATTERN MATCH DATA"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "PIGN,Channel Pattern Ignore Value"
|
|
hexmask.long.word 0x2C 0.--15. 1. "PDAT,Channel Pattern Match Data"
|
|
line.long 0x30 "CHCTRLCRC,CHANNEL CONTROL CRC"
|
|
bitfld.long 0x30 7. "CRCRIN,CRC Reflect Input Selection" "0,1"
|
|
bitfld.long 0x30 6. "CRCROUT,CRC Reflected Output Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x30 5. "CRCXOR,CRC XOR Mode" "0,1"
|
|
bitfld.long 0x30 3. "CRCAPP,CRC Append Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x30 0.--2. "CRCMD,CRC/Checksum Mode" "0: Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI,1: Normal (0x1021) CRC-16-CCITT,2: CRC-16 based on polynomial provided in CRCPOLYA..,3: CRC-16 based on polynomial provided in CRCPOLYB..,4: Normal (0x04C11DB7) CRC-32,5: CRC-32 based on polynomial provided in CRCPOLYA..,6: CRC-32 based on polynomial provided in CRCPOLYB..,7: Calculate IP header checksum"
|
|
line.long 0x34 "CHCRCDAT,CHANNEL CRC/CHECKSUM DATA REGISTER"
|
|
hexmask.long 0x34 0.--31. 1. "CRCDAT,CRC Data"
|
|
line.long 0x38 "CHNXT,CHANNEL NEXT DESCRIPTOR ADDRESS POINTER"
|
|
hexmask.long 0x38 0.--31. 1. "NXT,Channel Address Pointer to Next Descriptor"
|
|
rgroup.long ($2+0x3C)++0xF
|
|
line.long 0x0 "CHLLCFGSTAT,CHANNEL LINKED LIST CONFIGURATION STATUS REGISTER"
|
|
bitfld.long 0x0 9. "CRCDAT,CRC Data Descriptor Load" "0,1"
|
|
bitfld.long 0x0 8. "CTRLCRC,Control CRC Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PDAT,Match Pattern Descriptor Load" "0,1"
|
|
bitfld.long 0x0 6. "XSIZ,Transfer Size Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DSTRD,Destination Cell Stride Size Descriptor Load" "0,1"
|
|
bitfld.long 0x0 4. "SSTRD,Source Cell Stride Size Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSA,Destination Start Address Descriptor Load" "0,1"
|
|
bitfld.long 0x0 2. "SSA,Source Start Address Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EVCTRL,EVCTRL Register Descriptor Load" "0,1"
|
|
bitfld.long 0x0 0. "CTRLB,CTRLB Register Descriptor Load" "0,1"
|
|
line.long 0x4 "CHSTATBC,CHANNEL STATUS BLOCK COUNT REGISTER"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "BBTC,Bytes Transfered in the Block Counter"
|
|
line.long 0x8 "CHSTATCC,CHANNEL STATUS CELL COUNT REGISTER"
|
|
hexmask.long.word 0x8 0.--10. 1. "CBTC,Bytes Transfered in the Cell Counter"
|
|
line.long 0xC "CHSTAT,CHANNEL STATUS REGISTER"
|
|
bitfld.long 0xC 2. "DREAD,Descriptor Read Status Bit (0: not read or not avail 1: read and loaded)" "0: not read or not avail,1: read and loaded"
|
|
bitfld.long 0xC 1. "CELLBUSY,Channel Cell Transfer Busy Status Bit (0: none; 1: busy)" "0: none,1: busy"
|
|
newline
|
|
bitfld.long 0xC 0. "BLKBUSY,Channel Block Transfer Busy Status Bit (0: none; 1: busy)" "0: none,1: busy"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "DMA1"
|
|
base ad:0x44804000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTRLA,DMA CONTROL A REGISTER"
|
|
bitfld.long 0x0 1. "ENABLE,DMA Enable" "0,1"
|
|
line.long 0x4 "CTRLB,DMA CONTROL B REGISTER"
|
|
bitfld.long 0x4 24.--25. "QOS4,Priority Group 4 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
bitfld.long 0x4 16.--17. "QOS3,Priority Group 3 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
bitfld.long 0x4 8.--9. "QOS2,Priority Group 2 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
bitfld.long 0x4 0.--1. "QOS1,Priority Group 1 Quality Of Service Control" "0: QoS level is 0 (lowest),1: QoS level is 1 (lower),2: QoS level is 2 (medium),3: QoS level is 3 (high)"
|
|
line.long 0x8 "DBGCTRL,DEBUG CONTROL REGISTER"
|
|
bitfld.long 0x8 0. "DBGRUN,Debug Run" "0,1"
|
|
line.long 0xC "CRCPOLYA,DMA CRC POLYNOMIAL A REGISTER"
|
|
hexmask.long 0xC 0.--31. 1. "POLYA,CRC Polynomial Coefficients A Register"
|
|
line.long 0x10 "CRCPOLYB,DMA CRC POLYNOMIAL B REGISTER"
|
|
hexmask.long 0x10 0.--31. 1. "POLYB,CRC Polynomial Coefficients B Register"
|
|
rgroup.long 0x18++0xB
|
|
line.long 0x0 "INTSTAT3,DMA INTERRUPT PRIORITY 3 STATUS REGISTER"
|
|
bitfld.long 0x0 23. "CH23,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 22. "CH22,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 21. "CH21,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 20. "CH20,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "CH19,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 18. "CH18,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 17. "CH17,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 16. "CH16,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CH15,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 14. "CH14,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 13. "CH13,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 12. "CH12,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CH11,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 10. "CH10,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 9. "CH9,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 8. "CH8,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CH7,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 6. "CH6,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 5. "CH5,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 4. "CH4,DMA Channel active interrupt at priority 3" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "CH3,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 2. "CH2,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 1. "CH1,DMA Channel active interrupt at priority 3" "0,1"
|
|
bitfld.long 0x0 0. "CH0,DMA Channel active interrupt at priority 3" "0,1"
|
|
line.long 0x4 "INTSTAT2,DMA INTERRUPT PRIORITY 2 STATUS REGISTER"
|
|
bitfld.long 0x4 23. "CH23,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 22. "CH22,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 21. "CH21,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 20. "CH20,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "CH19,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 18. "CH18,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 17. "CH17,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 16. "CH16,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "CH15,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 14. "CH14,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 13. "CH13,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 12. "CH12,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "CH11,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 10. "CH10,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 9. "CH9,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 8. "CH8,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "CH7,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 6. "CH6,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 5. "CH5,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 4. "CH4,DMA Channel active interrupt at priority 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "CH3,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 2. "CH2,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 1. "CH1,DMA Channel active interrupt at priority 2" "0,1"
|
|
bitfld.long 0x4 0. "CH0,DMA Channel active interrupt at priority 2" "0,1"
|
|
line.long 0x8 "INTSTAT1,DMA INTERRUPT PRIORITY 1 STATUS REGISTER"
|
|
bitfld.long 0x8 23. "CH23,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 22. "CH22,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 21. "CH21,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 20. "CH20,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "CH19,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 18. "CH18,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 17. "CH17,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 16. "CH16,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "CH15,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 14. "CH14,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 13. "CH13,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 12. "CH12,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "CH11,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 10. "CH10,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 9. "CH9,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 8. "CH8,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "CH7,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 6. "CH6,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 5. "CH5,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 4. "CH4,DMA Channel active interrupt at priority 1" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CH3,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 2. "CH2,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 1. "CH1,DMA Channel active interrupt at priority 1" "0,1"
|
|
bitfld.long 0x8 0. "CH0,DMA Channel active interrupt at priority 1" "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x44804050 ad:0x448040A0 ad:0x448040F0 ad:0x44804140 ad:0x44804190 ad:0x448041E0 ad:0x44804230 ad:0x44804280)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x3B
|
|
line.long 0x0 "CHCTRLA,CHANNEL CONTROL REGISTER A"
|
|
bitfld.long 0x0 24. "RUNSTDBY,Run In Standby" "0,1"
|
|
bitfld.long 0x0 16. "SWFRC,Software Forced Trigger" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "LLEN,Linked List Enable" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Channel Enable" "0,1"
|
|
line.long 0x4 "CHCTRLB,CHANNEL CONTROL REGISTER B"
|
|
bitfld.long 0x4 31. "CRCEN,CRC Enable bit" "0,1"
|
|
bitfld.long 0x4 29. "CASTEN,Cell Auto Start Enable of Ensuing Transfers for this channel" "0,1"
|
|
newline
|
|
bitfld.long 0x4 26. "PATEN,Channel Pattern Match Abort Enable." "0,1"
|
|
bitfld.long 0x4 25. "PATLEN,Pattern Match Length" "0,1"
|
|
newline
|
|
bitfld.long 0x4 24. "PIGNEN,Enable Pattern Ignore Byte" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "TRIG,Trigger that can Start a Channel Transfer"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "BYTORD,Byte Order" "0: Bytes are processed AS IS,1: Bytes are swapped as: BYTE3 to BYTE0 BYTE2 to..,2: Bytes are swapped as: BYTE3 to BYTE1 BYTE2 to..,3: Bytes are swapped as: BYTE3 to BYTE2 BYTE2 to.."
|
|
bitfld.long 0x4 13. "WBOEN,Write Byte Order Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "PRI,Channel Priority level." "0: Channel Priority is 1,1: Channel Priority is 2,2: Channel Priority is 3 (HIGHEST),?"
|
|
bitfld.long 0x4 4.--6. "RAS,Channel Read Address Sequence" "0: Incrementing Address+1 with Transfers of Byte..,1: Incrementing Address+2 with Transfers of..,2: Auto Increment Address and Transfer Size,3: Fixed Byte Address (Single Byte Address with..,4: Fixed Address of HalfWord Operand (Single..,5: Fixed Address Word Burst Transfer,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "WAS,Channel Write Address Sequence." "0: Incrementing Address+1 with Transfers of Byte..,1: Incrementing Address+2 with Transfers of..,2: Auto Increment Address and Transfer Size,3: Fixed Byte Address (Single Byte Address with..,4: Fixed Address of HalfWord Operand (Single..,5: Fixed Address Word Burst Transfer,?,?"
|
|
line.long 0x8 "CHEVCTRL,CHANNEL EVENT CONTROL REGISTER"
|
|
bitfld.long 0x8 7. "EVOE,Channel Event Output Enable (0: disable; 1: enable)" "0: disable,1: enable"
|
|
bitfld.long 0x8 6. "EVSTRIE,Channel Start Event Input Enable (0: disable; 1:enable)" "0: disable,1: enable"
|
|
newline
|
|
bitfld.long 0x8 5. "EVAUXIE,Channel Auxiliary Event Enable (0: disable; 1: enable)" "0: disable,1: enable"
|
|
bitfld.long 0x8 2.--3. "EVOMODE,Channel Event Output Mode" "0: Generate a channel event strobe for 1 clock..,1: Generate a channel event strobe for 1 clock..,2: Generate a channel event strobe from start event..,3: Generate a channel event strobe from start event.."
|
|
newline
|
|
bitfld.long 0x8 0.--1. "EVAUXACT,Channel Auxiliary Event Input Action" "0: Event Aborts Bock Transfer,1: Event Increments Channel Priority,2: Event acts as a Conditional Trigger,?"
|
|
line.long 0xC "CHINTENCLR,CHANNEL INTERRUPT ENABLE CLEAR REGISTER"
|
|
bitfld.long 0xC 5. "LL,Clear Linked List Done Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 4. "BH,Clear Block Transfer Half Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "BC,Clear Cell Transfer Complete Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 2. "CC,Clear Cell Transfer Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TA,Clear Transfer Abort Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 0. "SD,Channel Event Output Enable" "0,1"
|
|
line.long 0x10 "CHINTENSET,CHANNEL INTERRUPT ENABLE SET REGISTER"
|
|
bitfld.long 0x10 5. "LL,set Linked List Done Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 4. "BH,set Block Transfer Half Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "BC,set Cell Transfer Complete Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 2. "CC,set Cell Transfer Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "TA,Set Transfer Abort Interrupt Enable" "0,1"
|
|
bitfld.long 0x10 0. "SD,Channel Event Output Enable" "0,1"
|
|
line.long 0x14 "CHINTF,CHANNEL INTERRUPT FLAG REGISTER"
|
|
bitfld.long 0x14 18. "RDE,Read Error Flag (0: none; 1: Read Error)" "0: none,1: Read Error"
|
|
bitfld.long 0x14 17. "WRE,Write Error Flag (0: none; 1: Write Error)" "0: none,1: Write Error"
|
|
newline
|
|
bitfld.long 0x14 5. "LL,Linked List Done Interrupt Flag (0: none; 1: done)" "0: none,1: done"
|
|
bitfld.long 0x14 4. "BH,Block Transfer Half Complete Interrupt Flag (0: none; 1: half complete)" "0: none,1: half complete"
|
|
newline
|
|
bitfld.long 0x14 3. "BC,Block Transfer Complete Interrupt Flag (0: none; 1:complete;)" "0: none,1: complete"
|
|
bitfld.long 0x14 2. "CC,Cell Transfer Complete Interrupt Flag (0: none ; 1: complete)" "0: none,1: complete"
|
|
newline
|
|
bitfld.long 0x14 1. "TA,Transfer Abort Interrupt Flag (0: none; 1: Transfer Aborted)" "0: none,1: Transfer Aborted"
|
|
bitfld.long 0x14 0. "SD,Start Detected Interrupt Flag (0: none ; 1: Start Detected)" "0: none,1: Start Detected"
|
|
line.long 0x18 "CHSSA,CHANNEL SOURCE START ADDRESS"
|
|
hexmask.long 0x18 0.--31. 1. "SSA,Channel Source Start Address"
|
|
line.long 0x1C "CHDSA,CHANNEL DESTINATION START ADDRESS"
|
|
hexmask.long 0x1C 0.--31. 1. "DSA,Channel Destination Start Address"
|
|
line.long 0x20 "CHSSTRD,CHANNEL SOURCE CELL STRIDE SIZE REGISTER"
|
|
hexmask.long.word 0x20 0.--15. 1. "SSTRD,Source Cell Stride Size"
|
|
line.long 0x24 "CHDSTRD,CHANNEL DESTINATION CELL STRIDE SIZE REGISTER"
|
|
hexmask.long.word 0x24 0.--15. 1. "DSTRD,Destination Cell Stride Size"
|
|
line.long 0x28 "CHXSIZ,CHANNEL TRANSFER SIZE REGISTER"
|
|
hexmask.long.word 0x28 16.--31. 1. "BLKSZ,Block transfer size in bytes."
|
|
hexmask.long.word 0x28 0.--9. 1. "CSZ,Cell transfer size in bytes."
|
|
line.long 0x2C "CHPDAT,CHANNEL PATTERN MATCH DATA"
|
|
hexmask.long.byte 0x2C 24.--31. 1. "PIGN,Channel Pattern Ignore Value"
|
|
hexmask.long.word 0x2C 0.--15. 1. "PDAT,Channel Pattern Match Data"
|
|
line.long 0x30 "CHCTRLCRC,CHANNEL CONTROL CRC"
|
|
bitfld.long 0x30 7. "CRCRIN,CRC Reflect Input Selection" "0,1"
|
|
bitfld.long 0x30 6. "CRCROUT,CRC Reflected Output Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x30 5. "CRCXOR,CRC XOR Mode" "0,1"
|
|
bitfld.long 0x30 3. "CRCAPP,CRC Append Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x30 0.--2. "CRCMD,CRC/Checksum Mode" "0: Normal (0x8005) CRC-16/CRC-16-IBM/CRC-16-ANSI,1: Normal (0x1021) CRC-16-CCITT,2: CRC-16 based on polynomial provided in CRCPOLYA..,3: CRC-16 based on polynomial provided in CRCPOLYB..,4: Normal (0x04C11DB7) CRC-32,5: CRC-32 based on polynomial provided in CRCPOLYA..,6: CRC-32 based on polynomial provided in CRCPOLYB..,7: Calculate IP header checksum"
|
|
line.long 0x34 "CHCRCDAT,CHANNEL CRC/CHECKSUM DATA REGISTER"
|
|
hexmask.long 0x34 0.--31. 1. "CRCDAT,CRC Data"
|
|
line.long 0x38 "CHNXT,CHANNEL NEXT DESCRIPTOR ADDRESS POINTER"
|
|
hexmask.long 0x38 0.--31. 1. "NXT,Channel Address Pointer to Next Descriptor"
|
|
rgroup.long ($2+0x3C)++0xF
|
|
line.long 0x0 "CHLLCFGSTAT,CHANNEL LINKED LIST CONFIGURATION STATUS REGISTER"
|
|
bitfld.long 0x0 9. "CRCDAT,CRC Data Descriptor Load" "0,1"
|
|
bitfld.long 0x0 8. "CTRLCRC,Control CRC Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PDAT,Match Pattern Descriptor Load" "0,1"
|
|
bitfld.long 0x0 6. "XSIZ,Transfer Size Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "DSTRD,Destination Cell Stride Size Descriptor Load" "0,1"
|
|
bitfld.long 0x0 4. "SSTRD,Source Cell Stride Size Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "DSA,Destination Start Address Descriptor Load" "0,1"
|
|
bitfld.long 0x0 2. "SSA,Source Start Address Descriptor Load" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "EVCTRL,EVCTRL Register Descriptor Load" "0,1"
|
|
bitfld.long 0x0 0. "CTRLB,CTRLB Register Descriptor Load" "0,1"
|
|
line.long 0x4 "CHSTATBC,CHANNEL STATUS BLOCK COUNT REGISTER"
|
|
hexmask.long.tbyte 0x4 0.--16. 1. "BBTC,Bytes Transfered in the Block Counter"
|
|
line.long 0x8 "CHSTATCC,CHANNEL STATUS CELL COUNT REGISTER"
|
|
hexmask.long.word 0x8 0.--10. 1. "CBTC,Bytes Transfered in the Cell Counter"
|
|
line.long 0xC "CHSTAT,CHANNEL STATUS REGISTER"
|
|
bitfld.long 0xC 2. "DREAD,Descriptor Read Status Bit (0: not read or not avail 1: read and loaded)" "0: not read or not avail,1: read and loaded"
|
|
bitfld.long 0xC 1. "CELLBUSY,Channel Cell Transfer Busy Status Bit (0: none; 1: busy)" "0: none,1: busy"
|
|
newline
|
|
bitfld.long 0xC 0. "BLKBUSY,Channel Block Transfer Busy Status Bit (0: none; 1: busy)" "0: none,1: busy"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "DSU (Device Service Unit)"
|
|
base ad:0x44000000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMD,Command Register"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "ADDR,Address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,Address"
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "ADDR_MBIST_MODE,Address"
|
|
hexmask.long 0x0 2.--31. 1. "ADDR,Address"
|
|
bitfld.long 0x0 0.--1. "AMOD,Access Mode" "0: STATUSA.FAIL rises upon first error and..,1: STATUSA.FAIL rises when an error is detected and..,?,?"
|
|
line.long 0x4 "LENGTH,Length"
|
|
hexmask.long 0x4 2.--31. 1. "LENGTH,Length"
|
|
line.long 0x8 "DATA,Data"
|
|
hexmask.long 0x8 0.--31. 1. "DATA,Data"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "DATA_MBIST_MODE,Data"
|
|
hexmask.long.byte 0x0 8.--12. 1. "INDEX,MBIST bit Index"
|
|
hexmask.long.byte 0x0 0.--4. 1. "STATE,MBIST state"
|
|
line.long 0x4 "CFG,Configuration"
|
|
hexmask.long.tbyte 0x4 8.--31. 1. "MISC,Device Specific Configuration Register"
|
|
bitfld.long 0x4 2. "MBFI,Enables the Memory Bist Fault Injection" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "DCCDMALEVEL1,DMA Trigger 1 Level" "0: Trigger x rises when DCC is read and falls when..,1: Trigger x rises when DCC is written and falls.."
|
|
bitfld.long 0x4 0. "DCCDMALEVEL0,DMA Trigger 0 Level" "0: Trigger x rises when DCC is read and falls when..,1: Trigger x rises when DCC is written and falls.."
|
|
line.long 0x8 "MBFI0,Memory Bist Fault Injection 0"
|
|
hexmask.long.tbyte 0x8 8.--31. 1. "AMMSK,Address matching Mask (Word address)"
|
|
bitfld.long 0x8 7. "FTYPE,Fault type" "0: Stuck At 0,1: Stuck At 1"
|
|
newline
|
|
bitfld.long 0x8 6. "AMMOD,Address matching mode" "0: Address match fault injected when the masked..,1: Always matches fault injected every AHB access"
|
|
hexmask.long.byte 0x8 0.--4. 1. "BIDX,Bit Index of injected fault"
|
|
line.long 0xC "MBFI1,Memory Bist Fault Injection 1"
|
|
hexmask.long 0xC 2.--31. 1. "ADDR,Word Address"
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "STATUSA,Status A"
|
|
bitfld.long 0x0 19. "BREXT3,BootRom 3 Phase Extension" "0,1"
|
|
bitfld.long 0x0 18. "BREXT2,BootRom 2 Phase Extension" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "BREXT1,BootRom 1 Phase Extension" "0,1"
|
|
bitfld.long 0x0 16. "BREXT0,BootRom 0 Phase Extension" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CRSTEXT3,CPU 3 Reset Phase Extension" "0,1"
|
|
bitfld.long 0x0 10. "CRSTEXT2,CPU 2 Reset Phase Extension" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CRSTEXT1,CPU 1 Reset Phase Extension" "0,1"
|
|
bitfld.long 0x0 8. "CRSTEXT0,CPU 0 Reset Phase Extension" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PERR,Protection Error" "0,1"
|
|
bitfld.long 0x0 2. "BERR,Bus Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "FAIL,Failure" "0,1"
|
|
bitfld.long 0x0 0. "DONE,Done" "0,1"
|
|
rgroup.long 0x104++0x7
|
|
line.long 0x0 "STATUSB,Status B"
|
|
bitfld.long 0x0 11. "APDIS,ARM Access Ports Disabled" "0,1"
|
|
bitfld.long 0x0 10. "HPE,Hot-Plugging Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DBGPRES,Debugger Present" "0,1"
|
|
bitfld.long 0x0 3. "DCCD1,Debug Communication Channel 1 Dirty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DCCD0,Debug Communication Channel 0 Dirty" "0,1"
|
|
bitfld.long 0x0 1. "BCCD1,Boot ROM Communication Channel 1 Dirty" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "BCCD0,Boot ROM Communication Channel 0 Dirty" "0,1"
|
|
line.long 0x4 "STATUSC,Status C"
|
|
hexmask.long.byte 0x4 8.--12. 1. "INDEX,MBIST MSA PMSA bit Index"
|
|
hexmask.long.byte 0x4 0.--4. 1. "STATE,Core State"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "BCC[$1],Boot ROM Communication Channel x"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x118)++0x3
|
|
line.long 0x0 "DCC[$1],Debug Communication Channel x"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data"
|
|
repeat.end
|
|
rgroup.long 0x120++0x7
|
|
line.long 0x0 "DID,Device Identification"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REVISION,Revision"
|
|
hexmask.long.byte 0x0 20.--27. 1. "PRODUCT,Product"
|
|
newline
|
|
hexmask.long.byte 0x0 12.--19. 1. "DEVSEL,Device Select"
|
|
hexmask.long.word 0x0 1.--11. 1. "MANID,Manufacturer ID"
|
|
newline
|
|
bitfld.long 0x0 0. "MARKER,Marker Bit" "0,1"
|
|
line.long 0x4 "DAL,Debugger Access Level"
|
|
bitfld.long 0x4 6.--7. "CPU3,Per CPU Debugger Access Level" "0: Debugger targeting CPU0 domain can only access..,1: Debugger can access only non-secure regions,2: Debugger can access secure and non-secure regions,3: No CPU in this slot"
|
|
bitfld.long 0x4 4.--5. "CPU2,Per CPU Debugger Access Level" "0: Debugger targeting CPU0 domain can only access..,1: Debugger can access only non-secure regions,2: Debugger can access secure and non-secure regions,3: No CPU in this slot"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "CPU1,Per CPU Debugger Access Level" "0: Debugger targeting CPU0 domain can only access..,1: Debugger can access only non-secure regions,2: Debugger can access secure and non-secure regions,3: No CPU in this slot"
|
|
bitfld.long 0x4 0.--1. "CPU0,Per CPU Debugger Access Level" "0: Debugger targeting CPU0 domain can only access..,1: Debugger can access only non-secure regions,2: Debugger can access secure and non-secure regions,3: No CPU in this slot"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x1000)++0x3
|
|
line.long 0x0 "ENTRY[$1],Coresight ROM Table Entry x"
|
|
hexmask.long.tbyte 0x0 12.--31. 1. "ADDOFF,Address Offset"
|
|
bitfld.long 0x0 1. "FMT,Format" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "EPRES,Entry Present" "0,1"
|
|
repeat.end
|
|
rgroup.long 0x1FCC++0x33
|
|
line.long 0x0 "MEMTYPE,Coresight ROM Table Memory Type"
|
|
bitfld.long 0x0 0. "SMEMP,System Memory Present" "0,1"
|
|
line.long 0x4 "PID4,Coresight ROM Table Peripheral Identification 4"
|
|
hexmask.long.byte 0x4 4.--7. 1. "FKBC,4KB count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "JEPCC,JEP-106 Continuation Code"
|
|
line.long 0x8 "PID5,Coresight ROM Table Peripheral Identification 5"
|
|
line.long 0xC "PID6,Coresight ROM Table Peripheral Identification 6"
|
|
line.long 0x10 "PID7,Coresight ROM Table Peripheral Identification 7"
|
|
line.long 0x14 "PID0,Coresight ROM Table Peripheral Identification 0"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PARTNBL,Part Number Low"
|
|
line.long 0x18 "PID1,Coresight ROM Table Peripheral Identification 1"
|
|
hexmask.long.byte 0x18 4.--7. 1. "JEPIDCL,Low part of the JEP-106 Identity Code"
|
|
hexmask.long.byte 0x18 0.--3. 1. "PARTNBH,Part Number High"
|
|
line.long 0x1C "PID2,Coresight ROM Table Peripheral Identification 2"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Revision Number"
|
|
bitfld.long 0x1C 3. "JEPU,JEP-106 Identity Code is used" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 0.--2. "JEPIDCH,JEP-106 Identity Code High" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "PID3,Coresight ROM Table Peripheral Identification 3"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVAND,Revision Number"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CUSMOD,ARM CUSMOD"
|
|
line.long 0x24 "CID0,Coresight ROM Table Component Identification 0"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PREAMBLEB0,Preamble Byte 0"
|
|
line.long 0x28 "CID1,Coresight ROM Table Component Identification 1"
|
|
hexmask.long.byte 0x28 4.--7. 1. "CCLASS,Component Class"
|
|
hexmask.long.byte 0x28 0.--3. 1. "PREAMBLE,Preamble"
|
|
line.long 0x2C "CID2,Coresight ROM Table Component Identification 2"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PREAMBLEB2,Preamble Byte 2"
|
|
line.long 0x30 "CID3,Coresight ROM Table Component Identification 3"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PREAMBLEB3,Preamble Byte 3"
|
|
tree.end
|
|
tree "DWT (Data Watchpoint and Trace)"
|
|
base ad:0xE0001000
|
|
group.long 0x0++0x1B
|
|
line.long 0x0 "CTRL,DWT Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "NUMCOMP,Number of comparators"
|
|
bitfld.long 0x0 27. "NOTRCPKT,No trace packets" "0,1"
|
|
bitfld.long 0x0 26. "NOEXTTRIG,No external triggers" "0,1"
|
|
bitfld.long 0x0 25. "NOCYCCNT,No cycle count" "0,1"
|
|
bitfld.long 0x0 24. "NOPRFCNT,No profile counters" "0,1"
|
|
bitfld.long 0x0 23. "CYCDISS,Cycle counter disabled secure" "0,1"
|
|
bitfld.long 0x0 22. "CYCEVTENA,Cycle event enable" "0,1"
|
|
bitfld.long 0x0 21. "FOLDEVTENA,Fold event enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "LSUEVTENA,LSU event enable" "0,1"
|
|
bitfld.long 0x0 19. "SLEEPEVTENA,Sleep event enable" "0,1"
|
|
bitfld.long 0x0 18. "EXCEVTENA,Exception event enable" "0,1"
|
|
bitfld.long 0x0 17. "CPIEVTENA,CPI event enable" "0,1"
|
|
bitfld.long 0x0 16. "EXCTRCENA,Exception trace enable" "0,1"
|
|
bitfld.long 0x0 12. "PCSAMPLENA,PC sample enable" "0,1"
|
|
bitfld.long 0x0 10.--11. "SYNCTAP,Synchronization tap" "0,1,2,3"
|
|
bitfld.long 0x0 9. "CYCTAP,Cycle count tap" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 5.--8. 1. "POSTINIT,POSTCNT initial"
|
|
hexmask.long.byte 0x0 1.--4. 1. "POSTPRESET,POSTCNT preset"
|
|
bitfld.long 0x0 0. "CYCCNTENA,CYCCNT enable" "0,1"
|
|
line.long 0x4 "CYCCNT,DWT Cycle Count Register"
|
|
hexmask.long 0x4 0.--31. 1. "CYCCNT,Incrementing cycle counter value"
|
|
line.long 0x8 "CPICNT,DWT CPI Count Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "CPICNT,Base instruction overhead counter"
|
|
line.long 0xC "EXCCNT,DWT Exception Overhead Count Register"
|
|
hexmask.long.byte 0xC 0.--7. 1. "EXCCNT,Exception overhead counter"
|
|
line.long 0x10 "SLEEPCNT,DWT Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. "SLEEPCNT,Sleep counter"
|
|
line.long 0x14 "LSUCNT,DWT LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. "LSUCNT,Load-store overhead counter"
|
|
line.long 0x18 "FOLDCNT,DWT Folded Instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. "FOLDCNT,Folded instruction counter"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "PCSR,DWT Program Counter Sample Register"
|
|
hexmask.long 0x0 0.--31. 1. "EIASAMPLE,Executed instruction address sample"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0xE0001020 ad:0xE0001030 ad:0xE0001040 ad:0xE0001050)
|
|
tree "COMPARATOR[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "COMP,DWT Comparator Register n"
|
|
hexmask.long 0x0 0.--31. 1. "VALUE,Cycle/PC/data value or data address"
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "FUNCTION,DWT Function Register x"
|
|
hexmask.long.byte 0x0 27.--31. 1. "ID,Identify capability"
|
|
bitfld.long 0x0 24. "MATCHED,Comparator matched" "0,1"
|
|
bitfld.long 0x0 10.--11. "DATAVSIZE,Data value size" "0,1,2,3"
|
|
bitfld.long 0x0 4.--5. "ACTION,Action on match" "0,1,2,3"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MATCH,Match type"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0xE0001000
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "LAR,DWT Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0xFB4++0x3
|
|
line.long 0x0 "LSR,DWT Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
rgroup.long 0xFBC++0x3
|
|
line.long 0x0 "DEVARCH,DWT Device Architecture Register"
|
|
hexmask.long.word 0x0 21.--31. 1. "ARCHITECT,Architect"
|
|
bitfld.long 0x0 20. "PRESENT,DEVARCH Present" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REVISION,Revision"
|
|
hexmask.long.byte 0x0 12.--15. 1. "ARCHVER,Architecture Version"
|
|
hexmask.long.word 0x0 0.--11. 1. "ARCHPART,Architecture Part"
|
|
rgroup.long 0xFCC++0x33
|
|
line.long 0x0 "DEVTYPE,DWT Device Type Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SUB,Sub-type"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type"
|
|
line.long 0x4 "PIDR4,DWT Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x8 "PIDR5,DWT Peripheral Identification Register 5"
|
|
line.long 0xC "PIDR6,DWT Peripheral Identification Register 6"
|
|
line.long 0x10 "PIDR7,DWT Peripheral Identification Register 7"
|
|
line.long 0x14 "PIDR0,DWT Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x18 "PIDR1,DWT Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x18 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x1C "PIDR2,DWT Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x1C 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x1C 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "PIDR3,DWT Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x24 "CIDR0,DWT Component Identification Register 0"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x28 "CIDR1,DWT Component Identification Register 1"
|
|
hexmask.long.byte 0x28 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x2C "CIDR2,DWT Component Identification Register 2"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x30 "CIDR3,DWT Component Identification Register 3"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512GC00100*")||cpuis("PIC32CK0512GC01100*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025GC00100*")||cpuis("PIC32CK1025GC01100*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051GC00100*")||cpuis("PIC32CK2051GC00144*")||cpuis("PIC32CK2051GC01100*")||cpuis("PIC32CK2051GC01144*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "EBI (External Bus Interface)"
|
|
base ad:0x4502C000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x4502C000 ad:0x4502C010 ad:0x4502C020 ad:0x4502C030)
|
|
tree "CS_X[$1]"
|
|
base $2
|
|
group.long ($2)++0xF
|
|
line.long 0x0 "SMC_SETUP,SMC Setup Register"
|
|
hexmask.long.byte 0x0 24.--29. 1. "NCS_RD_SETUP,NCS Setup Length in READ Access"
|
|
hexmask.long.byte 0x0 16.--21. 1. "NRD_SETUP,NRD Setup Length"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "NCS_WR_SETUP,NCS Setup Length in WRITE Access"
|
|
hexmask.long.byte 0x0 0.--5. 1. "NWE_SETUP,NWE Setup Length"
|
|
line.long 0x4 "SMC_PULSE,SMC Pulse Register"
|
|
hexmask.long.byte 0x4 24.--30. 1. "NCS_RD_PULSE,NCS Pulse Length in READ Access"
|
|
hexmask.long.byte 0x4 16.--22. 1. "NRD_PULSE,NRD Pulse Length"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--14. 1. "NCS_WR_PULSE,NCS Pulse Length in WRITE Access"
|
|
hexmask.long.byte 0x4 0.--6. 1. "NWE_PULSE,NWE Pulse Length"
|
|
line.long 0x8 "SMC_CYCLE,SMC Cycle Register"
|
|
hexmask.long.word 0x8 16.--24. 1. "NRD_CYCLE,Total Read Cycle Length"
|
|
hexmask.long.word 0x8 0.--8. 1. "NWE_CYCLE,Total Write Cycle Length"
|
|
line.long 0xC "SMC_MODE,SMC Mode Register"
|
|
bitfld.long 0xC 28.--29. "PS,Page Size" "0: 4-byte page,1: 8-byte page,2: 16-byte page,3: 32-byte page"
|
|
bitfld.long 0xC 24. "PMEN,Page Mode Enabled" "0,1"
|
|
newline
|
|
bitfld.long 0xC 20. "TDF_MODE,TDF Optimization" "0,1"
|
|
hexmask.long.byte 0xC 16.--19. 1. "TDF_CYCLES,Data Float Time"
|
|
newline
|
|
bitfld.long 0xC 12. "DBW,Data Bus Width" "0: 8-bit Data Bus,1: 16-bit Data Bus"
|
|
bitfld.long 0xC 8. "BAT,Byte Access Type" "0: Byte select access type:- Write operation is..,1: Byte write access type:- Write operation is.."
|
|
newline
|
|
bitfld.long 0xC 4.--5. "EXNW_MODE,NWAIT Mode" "0: Disabled-The NWAIT input signal is ignored on..,?,2: Frozen Mode-If asserted the NWAIT signal freezes..,3: Ready Mode-The NWAIT signal indicates the.."
|
|
bitfld.long 0xC 1. "WRITE_MODE,Write Mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "READ_MODE,Read Mode" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4502C000
|
|
group.long 0xE4++0x3
|
|
line.long 0x0 "SMC_WPMR,SMC Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protect Enable" "0,1"
|
|
rgroup.long 0xE8++0x3
|
|
line.long 0x0 "SMC_WPSR,SMC Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Source"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Status" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "EIC (External Interrupt Controller)"
|
|
base ad:0x4401A000
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "CTRLA,Control A"
|
|
bitfld.byte 0x0 4. "CKSEL,Clock Selection" "0: Clocked by GCLK,1: Clocked by ULP32K"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.byte 0x1 "NMICTRL,Non-Maskable Interrupt Control"
|
|
bitfld.byte 0x1 4. "NMIASYNCH,Asynchronous Edge Detection Mode" "0: Edge detection is clock synchronously operated,1: Edge detection is clock asynchronously operated"
|
|
bitfld.byte 0x1 3. "NMIFILTEN,Non-Maskable Interrupt Filter Enable" "0,1"
|
|
bitfld.byte 0x1 0.--2. "NMISENSE,Non-Maskable Interrupt Sense Configuration" "0: No detection,1: Rising-edge detection,2: Falling-edge detection,3: Both-edges detection,4: High-level detection,5: Low-level detection,?,?"
|
|
group.word 0x2++0x1
|
|
line.word 0x0 "NMIFLAG,Non-Maskable Interrupt Flag Status and Clear"
|
|
bitfld.word 0x0 0. "NMI,Non-Maskable Interrupt" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Synchronization Busy Status" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy Status" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINTEO,External Interrupt Event Output Enable"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Enable"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
endif
|
|
hexmask.long.word 0x8 0.--15. 1. "EXTINT,External Interrupt Enable"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
newline
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
endif
|
|
hexmask.long.word 0xC 0.--15. 1. "EXTINT,External Interrupt"
|
|
line.long 0x10 "ASYNCH,External Interrupt Asynchronous Mode"
|
|
hexmask.long.word 0x10 0.--15. 1. "ASYNCH,Asynchronous Edge Detection Mode"
|
|
line.long 0x14 "CONFIG0,External Interrupt Sense Configuration"
|
|
bitfld.long 0x14 31. "FILTEN7,Filter Enable 7" "0,1"
|
|
bitfld.long 0x14 28.--30. "SENSE7,Input Sense Configuration 7" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 27. "FILTEN6,Filter Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24.--26. "SENSE6,Input Sense Configuration 6" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 23. "FILTEN5,Filter Enable 5" "0,1"
|
|
bitfld.long 0x14 20.--22. "SENSE5,Input Sense Configuration 5" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x14 19. "FILTEN4,Filter Enable 4" "0,1"
|
|
bitfld.long 0x14 16.--18. "SENSE4,Input Sense Configuration 4" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 15. "FILTEN3,Filter Enable 3" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12.--14. "SENSE3,Input Sense Configuration 3" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 11. "FILTEN2,Filter Enable 2" "0,1"
|
|
bitfld.long 0x14 8.--10. "SENSE2,Input Sense Configuration 2" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x14 7. "FILTEN1,Filter Enable 1" "0,1"
|
|
bitfld.long 0x14 4.--6. "SENSE1,Input Sense Configuration 1" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 3. "FILTEN0,Filter Enable 0" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "SENSE0,Input Sense Configuration 0" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
line.long 0x18 "CONFIG1,External Interrupt Sense Configuration"
|
|
bitfld.long 0x18 31. "FILTEN15,Filter Enable 15" "0,1"
|
|
bitfld.long 0x18 28.--30. "SENSE15,Input Sense Configuration 15" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 27. "FILTEN14,Filter Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24.--26. "SENSE14,Input Sense Configuration 14" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 23. "FILTEN13,Filter Enable 13" "0,1"
|
|
bitfld.long 0x18 20.--22. "SENSE13,Input Sense Configuration 13" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x18 19. "FILTEN12,Filter Enable 12" "0,1"
|
|
bitfld.long 0x18 16.--18. "SENSE12,Input Sense Configuration 12" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 15. "FILTEN11,Filter Enable 11" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12.--14. "SENSE11,Input Sense Configuration 11" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 11. "FILTEN10,Filter Enable 10" "0,1"
|
|
bitfld.long 0x18 8.--10. "SENSE10,Input Sense Configuration 10" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x18 7. "FILTEN9,Filter Enable 9" "0,1"
|
|
bitfld.long 0x18 4.--6. "SENSE9,Input Sense Configuration 9" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 3. "FILTEN8,Filter Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "SENSE8,Input Sense Configuration 8" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "DEBOUNCEN,Debouncer Enable"
|
|
hexmask.long.word 0x0 0.--15. 1. "DEBOUNCEN,Debouncer Enable"
|
|
line.long 0x4 "DPRESCALER,Debouncer Prescaler"
|
|
bitfld.long 0x4 16. "TICKON,Pin Sampler frequency selection" "0: Clocked by GCLK,1: Clocked by Low Frequency Clock"
|
|
bitfld.long 0x4 7. "STATES1,Debouncer number of states" "0: 3 low frequency samples,1: 7 low frequency samples"
|
|
bitfld.long 0x4 4.--6. "PRESCALER1,Debouncer Prescaler" "0: EIC clock divided by 2,1: EIC clock divided by 4,2: EIC clock divided by 8,3: EIC clock divided by 16,4: EIC clock divided by 32,5: EIC clock divided by 64,6: EIC clock divided by 128,7: EIC clock divided by 256"
|
|
newline
|
|
bitfld.long 0x4 3. "STATES0,Debouncer number of states" "0: 3 low frequency samples,1: 7 low frequency samples"
|
|
bitfld.long 0x4 0.--2. "PRESCALER0,Debouncer Prescaler" "0: EIC clock divided by 2,1: EIC clock divided by 4,2: EIC clock divided by 8,3: EIC clock divided by 16,4: EIC clock divided by 32,5: EIC clock divided by 64,6: EIC clock divided by 128,7: EIC clock divided by 256"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "PINSTATE,Pin State"
|
|
hexmask.long.word 0x0 0.--15. 1. "PINSTATE,Pin State"
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
endif
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "EIC_SEC (External Interrupt Controller (Secure))"
|
|
base ad:0x4401B000
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "CTRLA,Control A"
|
|
bitfld.byte 0x0 4. "CKSEL,Clock Selection" "0: Clocked by GCLK,1: Clocked by ULP32K"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.byte 0x1 "NMICTRL,Non-Maskable Interrupt Control"
|
|
bitfld.byte 0x1 4. "NMIASYNCH,Asynchronous Edge Detection Mode" "0: Edge detection is clock synchronously operated,1: Edge detection is clock asynchronously operated"
|
|
bitfld.byte 0x1 3. "NMIFILTEN,Non-Maskable Interrupt Filter Enable" "0,1"
|
|
bitfld.byte 0x1 0.--2. "NMISENSE,Non-Maskable Interrupt Sense Configuration" "0: No detection,1: Rising-edge detection,2: Falling-edge detection,3: Both-edges detection,4: High-level detection,5: Low-level detection,?,?"
|
|
group.word 0x2++0x1
|
|
line.word 0x0 "NMIFLAG,Non-Maskable Interrupt Flag Status and Clear"
|
|
bitfld.word 0x0 0. "NMI,Non-Maskable Interrupt" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Synchronization Busy Status" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy Status" "0,1"
|
|
group.long 0x8++0x1B
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINTEO,External Interrupt Event Output Enable"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Enable"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 31. "NSCHK,Non-secure Check Interrupt Enable" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "EXTINT,External Interrupt Enable"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 31. "NSCHK,Non-secure Check Interrupt" "0,1"
|
|
hexmask.long.word 0xC 0.--15. 1. "EXTINT,External Interrupt"
|
|
line.long 0x10 "ASYNCH,External Interrupt Asynchronous Mode"
|
|
hexmask.long.word 0x10 0.--15. 1. "ASYNCH,Asynchronous Edge Detection Mode"
|
|
line.long 0x14 "CONFIG0,External Interrupt Sense Configuration"
|
|
bitfld.long 0x14 31. "FILTEN7,Filter Enable 7" "0,1"
|
|
bitfld.long 0x14 28.--30. "SENSE7,Input Sense Configuration 7" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 27. "FILTEN6,Filter Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x14 24.--26. "SENSE6,Input Sense Configuration 6" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 23. "FILTEN5,Filter Enable 5" "0,1"
|
|
bitfld.long 0x14 20.--22. "SENSE5,Input Sense Configuration 5" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x14 19. "FILTEN4,Filter Enable 4" "0,1"
|
|
bitfld.long 0x14 16.--18. "SENSE4,Input Sense Configuration 4" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 15. "FILTEN3,Filter Enable 3" "0,1"
|
|
newline
|
|
bitfld.long 0x14 12.--14. "SENSE3,Input Sense Configuration 3" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 11. "FILTEN2,Filter Enable 2" "0,1"
|
|
bitfld.long 0x14 8.--10. "SENSE2,Input Sense Configuration 2" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x14 7. "FILTEN1,Filter Enable 1" "0,1"
|
|
bitfld.long 0x14 4.--6. "SENSE1,Input Sense Configuration 1" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x14 3. "FILTEN0,Filter Enable 0" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0.--2. "SENSE0,Input Sense Configuration 0" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
line.long 0x18 "CONFIG1,External Interrupt Sense Configuration"
|
|
bitfld.long 0x18 31. "FILTEN15,Filter Enable 15" "0,1"
|
|
bitfld.long 0x18 28.--30. "SENSE15,Input Sense Configuration 15" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 27. "FILTEN14,Filter Enable 14" "0,1"
|
|
newline
|
|
bitfld.long 0x18 24.--26. "SENSE14,Input Sense Configuration 14" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 23. "FILTEN13,Filter Enable 13" "0,1"
|
|
bitfld.long 0x18 20.--22. "SENSE13,Input Sense Configuration 13" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x18 19. "FILTEN12,Filter Enable 12" "0,1"
|
|
bitfld.long 0x18 16.--18. "SENSE12,Input Sense Configuration 12" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 15. "FILTEN11,Filter Enable 11" "0,1"
|
|
newline
|
|
bitfld.long 0x18 12.--14. "SENSE11,Input Sense Configuration 11" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 11. "FILTEN10,Filter Enable 10" "0,1"
|
|
bitfld.long 0x18 8.--10. "SENSE10,Input Sense Configuration 10" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
newline
|
|
bitfld.long 0x18 7. "FILTEN9,Filter Enable 9" "0,1"
|
|
bitfld.long 0x18 4.--6. "SENSE9,Input Sense Configuration 9" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
bitfld.long 0x18 3. "FILTEN8,Filter Enable 8" "0,1"
|
|
newline
|
|
bitfld.long 0x18 0.--2. "SENSE8,Input Sense Configuration 8" "0: No detection,1: Rising edge detection,2: Falling edge detection,3: Both edges detection,4: High level detection,5: Low level detection,?,?"
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "DEBOUNCEN,Debouncer Enable"
|
|
hexmask.long.word 0x0 0.--15. 1. "DEBOUNCEN,Debouncer Enable"
|
|
line.long 0x4 "DPRESCALER,Debouncer Prescaler"
|
|
bitfld.long 0x4 16. "TICKON,Pin Sampler frequency selection" "0: Clocked by GCLK,1: Clocked by Low Frequency Clock"
|
|
bitfld.long 0x4 7. "STATES1,Debouncer number of states" "0: 3 low frequency samples,1: 7 low frequency samples"
|
|
bitfld.long 0x4 4.--6. "PRESCALER1,Debouncer Prescaler" "0: EIC clock divided by 2,1: EIC clock divided by 4,2: EIC clock divided by 8,3: EIC clock divided by 16,4: EIC clock divided by 32,5: EIC clock divided by 64,6: EIC clock divided by 128,7: EIC clock divided by 256"
|
|
newline
|
|
bitfld.long 0x4 3. "STATES0,Debouncer number of states" "0: 3 low frequency samples,1: 7 low frequency samples"
|
|
bitfld.long 0x4 0.--2. "PRESCALER0,Debouncer Prescaler" "0: EIC clock divided by 2,1: EIC clock divided by 4,2: EIC clock divided by 8,3: EIC clock divided by 16,4: EIC clock divided by 32,5: EIC clock divided by 64,6: EIC clock divided by 128,7: EIC clock divided by 256"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "PINSTATE,Pin State"
|
|
hexmask.long.word 0x0 0.--15. 1. "PINSTATE,Pin State"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "NSCHK,Non-secure Interrupt Check Enable"
|
|
bitfld.long 0x0 31. "NMI,Non-Maskable External Interrupt Nonsecure Check Enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "EXTINT,External Interrupt Nonsecure Check Enable"
|
|
line.long 0x4 "NONSEC,Non-secure Interrupt"
|
|
bitfld.long 0x4 31. "NMI,Non-Maskable Interrupt Nonsecure Enable" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "EXTINT,External Interrupt Nonsecure Enable"
|
|
tree.end
|
|
endif
|
|
sif (cpuis("PIC32CK0512GC01064*")||cpuis("PIC32CK0512GC01100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025GC01064*")||cpuis("PIC32CK1025GC01100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051GC01064*")||cpuis("PIC32CK2051GC01100*")||cpuis("PIC32CK2051GC01144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "ETH (Ethernet MAC)"
|
|
base ad:0x45022000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "CTRLA,CTRLA Register"
|
|
bitfld.long 0x0 6. "RUNSTDBY,Run in standby mode" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Macro Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Bit" "0,1"
|
|
line.long 0x4 "CTRLB,CTRLB Register"
|
|
bitfld.long 0x4 6.--7. "TSUINC,Timer Adjust Mode" "0,1,2,3"
|
|
bitfld.long 0x4 5. "TSUMS,Timer Adjust" "0,1"
|
|
bitfld.long 0x4 2. "TSUCLKREQ,TSU Clock Request" "0,1"
|
|
bitfld.long 0x4 1. "GBITCLKREQ,Gigabit clock request" "0,1"
|
|
bitfld.long 0x4 0. "GMIIEN,Select GMII/MII mode" "0,1"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "EVCTRL,Event Control Register"
|
|
bitfld.long 0x0 0. "CMPEO,Compare Event Out enable" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "SYNCB,Sync Busy Register"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Sync Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Sync Busy" "0,1"
|
|
group.long 0x1000++0x7
|
|
line.long 0x0 "NCR,Network Control Register"
|
|
bitfld.long 0x0 19. "LPI,Low Power Idle Enable" "0,1"
|
|
bitfld.long 0x0 18. "FNP,Flush Next Packet" "0,1"
|
|
bitfld.long 0x0 17. "TXPBPF,Transmit PFC Priority-based Pause Frame" "0,1"
|
|
bitfld.long 0x0 16. "ENPBPR,Enable PFC Priority-based Pause Reception" "0,1"
|
|
bitfld.long 0x0 15. "SRTSM,Store Receive Time Stamp to Memory" "0,1"
|
|
bitfld.long 0x0 12. "TXZQPF,Transmit Zero Quantum Pause Frame" "0,1"
|
|
bitfld.long 0x0 11. "TXPF,Transmit Pause Frame" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "THALT,Transmit Halt" "0,1"
|
|
bitfld.long 0x0 9. "TSTART,Start Transmission" "0,1"
|
|
bitfld.long 0x0 8. "BP,Back pressure" "0,1"
|
|
bitfld.long 0x0 7. "WESTAT,Write Enable for Statistics Registers" "0,1"
|
|
bitfld.long 0x0 6. "INCSTAT,Increment Statistics Registers" "0,1"
|
|
bitfld.long 0x0 5. "CLRSTAT,Clear Statistics Registers" "0,1"
|
|
bitfld.long 0x0 4. "MPE,Management Port Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXEN,Transmit Enable" "0,1"
|
|
bitfld.long 0x0 2. "RXEN,Receive Enable" "0,1"
|
|
bitfld.long 0x0 1. "LBL,Loop Back Local" "0,1"
|
|
line.long 0x4 "NCFGR,Network Configuration Register"
|
|
bitfld.long 0x4 30. "IRXER,Ignore IPG GRXER" "0,1"
|
|
bitfld.long 0x4 29. "RXBP,Receive Bad Preamble" "0,1"
|
|
bitfld.long 0x4 28. "IPGSEN,IP Stretch Enable" "0,1"
|
|
bitfld.long 0x4 26. "IRXFCS,Ignore RX FCS" "0,1"
|
|
bitfld.long 0x4 25. "EFRHD,Enable Frames Received in Half Duplex" "0,1"
|
|
bitfld.long 0x4 24. "RXCOEN,Receive Checksum Offload Enable" "0,1"
|
|
bitfld.long 0x4 23. "DCPF,Disable Copy of Pause Frames" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21.--22. "DBW,Data Bus Width" "0,1,2,3"
|
|
bitfld.long 0x4 18.--20. "CLK,MDC CLock Division" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x4 17. "RFCS,Remove FCS" "0,1"
|
|
bitfld.long 0x4 16. "LFERD,Length Field Error Frame Discard" "0,1"
|
|
bitfld.long 0x4 14.--15. "RXBUFO,Receive Buffer Offset" "0,1,2,3"
|
|
bitfld.long 0x4 13. "PEN,Pause Enable" "0,1"
|
|
bitfld.long 0x4 12. "RTY,Retry Test" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "GIGE,Gigabit mode Enable" "0,1"
|
|
bitfld.long 0x4 8. "MAXFS,1536 Maximum Frame Size" "0,1"
|
|
bitfld.long 0x4 7. "UNIHEN,Unicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 6. "MTIHEN,Multicast Hash Enable" "0,1"
|
|
bitfld.long 0x4 5. "NBC,No Broadcast" "0,1"
|
|
bitfld.long 0x4 4. "CAF,Copy All Frames" "0,1"
|
|
bitfld.long 0x4 3. "JFRAME,Jumbo Frame Size" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DNVLAN,Discard Non-VLAN FRAMES" "0,1"
|
|
bitfld.long 0x4 1. "FD,Full Duplex" "0,1"
|
|
bitfld.long 0x4 0. "SPD,Speed" "0,1"
|
|
rgroup.long 0x1008++0x3
|
|
line.long 0x0 "NSR,Network Status Register"
|
|
bitfld.long 0x0 2. "IDLE,PHY Management Logic Idle" "0,1"
|
|
bitfld.long 0x0 1. "MDIO,MDIO Input Status" "0,1"
|
|
group.long 0x100C++0x1B
|
|
line.long 0x0 "UR,User Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "UI,User Programmable Inputs"
|
|
hexmask.long.word 0x0 0.--15. 1. "UO,User Programmable Outputs"
|
|
line.long 0x4 "DCFGR,DMA Configuration Register"
|
|
bitfld.long 0x4 24. "DDRP,DMA Discard Receive Packets" "0,1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "DRBS,DMA Receive Buffer Size"
|
|
bitfld.long 0x4 11. "TXCOEN,Transmitter Checksum Generation Offload Enable" "0,1"
|
|
bitfld.long 0x4 10. "TXPBMS,Transmitter Packet Buffer Memory Size Select" "0,1"
|
|
bitfld.long 0x4 8.--9. "RXBMS,Receiver Packet Buffer Memory Size Select" "0,1,2,3"
|
|
bitfld.long 0x4 7. "ESPA,Endian Swap Mode Enable for Packet Data Accesses" "0,1"
|
|
bitfld.long 0x4 6. "ESMA,Endian Swap Mode Enable for Management Descriptor Accesses" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x4 0.--4. 1. "FBLDO,Fixed Burst Length for DMA Data Operations:"
|
|
line.long 0x8 "TSR,Transmit Status Register"
|
|
bitfld.long 0x8 8. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x8 7. "LCOL,Late Colision Occured" "0,1"
|
|
bitfld.long 0x8 6. "UND,Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 5. "TXCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x8 4. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x8 3. "TXGO,Transmit Go" "0,1"
|
|
bitfld.long 0x8 2. "RLE,Retry Limit Exceeded" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "COL,Collision Occurred" "0,1"
|
|
bitfld.long 0x8 0. "UBR,Used Bit Read" "0,1"
|
|
line.long 0xC "RBQB,Receive Buffer Queue Base Address"
|
|
hexmask.long 0xC 2.--31. 1. "ADDR,Receive Buffer Queue Base Address"
|
|
line.long 0x10 "TBQB,Transmit Buffer Queue Base Address"
|
|
hexmask.long 0x10 2.--31. 1. "ADDR,Transmit Buffer Queue Base Address"
|
|
line.long 0x14 "RSR,Receive Status Register"
|
|
bitfld.long 0x14 3. "HNO,HRESP Not OK" "0,1"
|
|
bitfld.long 0x14 2. "RXOVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x14 1. "REC,Frame Received" "0,1"
|
|
bitfld.long 0x14 0. "BNA,Buffer Not Available" "0,1"
|
|
line.long 0x18 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x18 29. "TSUCMP,Tsu timer comparison" "0,1"
|
|
bitfld.long 0x18 28. "WOL,Wake On LAN" "0,1"
|
|
bitfld.long 0x18 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
bitfld.long 0x18 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x18 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x18 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x18 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x18 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x18 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x18 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x18 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
bitfld.long 0x18 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
bitfld.long 0x18 13. "PTZ,Pause Time Zero" "0,1"
|
|
bitfld.long 0x18 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
newline
|
|
bitfld.long 0x18 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x18 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x18 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x18 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x18 5. "RLEX,Retry Limit Exceeded" "0,1"
|
|
bitfld.long 0x18 4. "TUR,Transmit Underrun" "0,1"
|
|
bitfld.long 0x18 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
newline
|
|
bitfld.long 0x18 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x18 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x18 0. "MFS,Management Frame Sent" "0,1"
|
|
wgroup.long 0x1028++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 29. "TSUCMP,Tsu timer comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On LAN" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 29. "TSUCMP,Tsu timer comparison" "0,1"
|
|
bitfld.long 0x4 28. "WOL,Wake On LAN" "0,1"
|
|
bitfld.long 0x4 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
bitfld.long 0x4 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x4 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x4 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x4 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
bitfld.long 0x4 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x4 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
bitfld.long 0x4 13. "PTZ,Pause Time Zero" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
bitfld.long 0x4 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x4 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x4 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x4 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x4 5. "RLEX,Retry Limit Exceeded or Late Collision" "0,1"
|
|
bitfld.long 0x4 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x4 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x4 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x4 0. "MFS,Management Frame Sent" "0,1"
|
|
rgroup.long 0x1030++0x3
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 29. "TSUCMP,Tsu timer comparison" "0,1"
|
|
bitfld.long 0x0 28. "WOL,Wake On Lan" "0,1"
|
|
bitfld.long 0x0 26. "SRI,TSU Seconds Register Increment" "0,1"
|
|
bitfld.long 0x0 25. "PDRSFT,PDelay Response Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 24. "PDRQFT,PDelay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 23. "PDRSFR,PDelay Response Frame Received" "0,1"
|
|
bitfld.long 0x0 22. "PDRQFR,PDelay Request Frame Received" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "SFT,PTP Sync Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 20. "DRQFT,PTP Delay Request Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 19. "SFR,PTP Sync Frame Received" "0,1"
|
|
bitfld.long 0x0 18. "DRQFR,PTP Delay Request Frame Received" "0,1"
|
|
bitfld.long 0x0 15. "EXINT,External Interrupt" "0,1"
|
|
bitfld.long 0x0 14. "PFTR,Pause Frame Transmitted" "0,1"
|
|
bitfld.long 0x0 13. "PTZ,Pause Time Zero" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12. "PFNZ,Pause Frame with Non-zero Pause Quantum Received" "0,1"
|
|
bitfld.long 0x0 11. "HRESP,HRESP Not OK" "0,1"
|
|
bitfld.long 0x0 10. "ROVR,Receive Overrun" "0,1"
|
|
bitfld.long 0x0 7. "TCOMP,Transmit Complete" "0,1"
|
|
bitfld.long 0x0 6. "TFC,Transmit Frame Corruption Due to AHB Error" "0,1"
|
|
bitfld.long 0x0 5. "RLEX,Retry Limit Exceeded" "0,1"
|
|
bitfld.long 0x0 4. "TUR,Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "TXUBR,TX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 2. "RXUBR,RX Used Bit Read" "0,1"
|
|
bitfld.long 0x0 1. "RCOMP,Receive Complete" "0,1"
|
|
bitfld.long 0x0 0. "MFS,Management Frame Sent" "0,1"
|
|
group.long 0x1034++0x3
|
|
line.long 0x0 "MAN,PHY Maintenance Register"
|
|
bitfld.long 0x0 31. "WZO,Write ZERO" "0,1"
|
|
bitfld.long 0x0 30. "CLTTO,Clause 22 Operation" "0,1"
|
|
bitfld.long 0x0 28.--29. "OP,Operation" "0,1,2,3"
|
|
hexmask.long.byte 0x0 23.--27. 1. "PHYA,PHY Address"
|
|
hexmask.long.byte 0x0 18.--22. 1. "REGA,Register Address"
|
|
bitfld.long 0x0 16.--17. "WTN,Write Ten" "0,1,2,3"
|
|
hexmask.long.word 0x0 0.--15. 1. "DATA,PHY Data"
|
|
rgroup.long 0x1038++0x3
|
|
line.long 0x0 "RPQ,Received Pause Quantum Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RPQ,Received Pause Quantum"
|
|
group.long 0x103C++0xF
|
|
line.long 0x0 "TPQ,Transmit Pause Quantum Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TPQ,Transmit Pause Quantum"
|
|
line.long 0x4 "TPSF,TX partial store and forward Register"
|
|
bitfld.long 0x4 31. "ENTXP,Enable TX partial store and forward operation" "0,1"
|
|
hexmask.long.word 0x4 0.--9. 1. "TPB1ADR,TX packet buffer address"
|
|
line.long 0x8 "RPSF,RX partial store and forward Register"
|
|
bitfld.long 0x8 31. "ENRXP,Enable RX partial store and forward operation" "0,1"
|
|
hexmask.long.word 0x8 0.--9. 1. "RPB1ADR,RX packet buffer address"
|
|
line.long 0xC "RJFML,RX Jumbo Frame Max Length Register"
|
|
hexmask.long.word 0xC 0.--13. 1. "FML,Frame Max Length"
|
|
group.long 0x1080++0x7
|
|
line.long 0x0 "HRB,Hash Register Bottom [31:0]"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Hash Address"
|
|
line.long 0x4 "HRT,Hash Register Top [63:32]"
|
|
hexmask.long 0x4 0.--31. 1. "ADDR,Hash Address"
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x45023088 ad:0x45023090 ad:0x45023098 ad:0x450230A0)
|
|
tree "SA[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "SAB,Specific Address Bottom [31:0] Register"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,Specific Address 1"
|
|
line.long 0x4 "SAT,Specific Address Top [47:32] Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "ADDR,Specific Address 1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x45022000
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x10A8)++0x3
|
|
line.long 0x0 "TIDM[$1],Type ID Match Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TID,Type ID Match 1"
|
|
repeat.end
|
|
group.long 0x10B8++0x17
|
|
line.long 0x0 "WOL,Wake on LAN"
|
|
bitfld.long 0x0 19. "MTI,WOL LAN multicast" "0,1"
|
|
bitfld.long 0x0 18. "SA1,WOL specific address reg 1" "0,1"
|
|
bitfld.long 0x0 17. "ARP,LAN ARP req" "0,1"
|
|
bitfld.long 0x0 16. "MAG,Event enable" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "IP,IP address"
|
|
line.long 0x4 "IPGS,IPG Stretch Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "FL,Frame Length"
|
|
line.long 0x8 "SVLAN,Stacked VLAN Register"
|
|
bitfld.long 0x8 31. "ESVLAN,Enable Stacked VLAN Processing Mode" "0,1"
|
|
hexmask.long.word 0x8 0.--15. 1. "VLAN_TYPE,User Defined VLAN_TYPE Field"
|
|
line.long 0xC "TPFCP,Transmit PFC Pause Register"
|
|
hexmask.long.byte 0xC 8.--15. 1. "PQ,Pause Quantum"
|
|
hexmask.long.byte 0xC 0.--7. 1. "PEV,Priority Enable Vector"
|
|
line.long 0x10 "SAMB1,Specific Address 1 Mask Bottom [31:0] Register"
|
|
hexmask.long 0x10 0.--31. 1. "ADDR,Specific Address 1 Mask"
|
|
line.long 0x14 "SAMT1,Specific Address 1 Mask Top [47:32] Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "ADDR,Specific Address 1 Mask"
|
|
group.long 0x10DC++0xB
|
|
line.long 0x0 "NSC,Tsu timer comparison nanoseconds Register"
|
|
hexmask.long.tbyte 0x0 0.--20. 1. "NANOSEC,1588 Timer Nanosecond comparison value"
|
|
line.long 0x4 "SCL,Tsu timer second comparison Register"
|
|
hexmask.long 0x4 0.--31. 1. "SEC,1588 Timer Second comparison value"
|
|
line.long 0x8 "SCH,Tsu timer second comparison Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "SEC,1588 Timer Second comparison value"
|
|
rgroup.long 0x10E8++0xF
|
|
line.long 0x0 "EFTSH,PTP Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFRSH,PTP Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RUD,Register Update"
|
|
line.long 0x8 "PEFTSH,PTP Peer Event Frame Transmitted Seconds High Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "RUD,Register Update"
|
|
line.long 0xC "PEFRSH,PTP Peer Event Frame Received Seconds High Register"
|
|
hexmask.long.word 0xC 0.--15. 1. "RUD,Register Update"
|
|
rgroup.long 0x1100++0xB3
|
|
line.long 0x0 "OTLO,Octets Transmitted [31:0] Register"
|
|
hexmask.long 0x0 0.--31. 1. "TXO,Transmitted Octets"
|
|
line.long 0x4 "OTHI,Octets Transmitted [47:32] Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TXO,Transmitted Octets"
|
|
line.long 0x8 "FT,Frames Transmitted Register"
|
|
hexmask.long 0x8 0.--31. 1. "FTX,Frames Transmitted without Error"
|
|
line.long 0xC "BCFT,Broadcast Frames Transmitted Register"
|
|
hexmask.long 0xC 0.--31. 1. "BFTX,Broadcast Frames Transmitted without Error"
|
|
line.long 0x10 "MFT,Multicast Frames Transmitted Register"
|
|
hexmask.long 0x10 0.--31. 1. "MFTX,Multicast Frames Transmitted without Error"
|
|
line.long 0x14 "PFT,Pause Frames Transmitted Register"
|
|
hexmask.long.word 0x14 0.--15. 1. "PFTX,Pause Frames Transmitted Register"
|
|
line.long 0x18 "BFT64,64 Byte Frames Transmitted Register"
|
|
hexmask.long 0x18 0.--31. 1. "NFTX,64 Byte Frames Transmitted without Error"
|
|
line.long 0x1C "TBFT127,65 to 127 Byte Frames Transmitted Register"
|
|
hexmask.long 0x1C 0.--31. 1. "NFTX,65 to 127 Byte Frames Transmitted without Error"
|
|
line.long 0x20 "TBFT255,128 to 255 Byte Frames Transmitted Register"
|
|
hexmask.long 0x20 0.--31. 1. "NFTX,128 to 255 Byte Frames Transmitted without Error"
|
|
line.long 0x24 "TBFT511,256 to 511 Byte Frames Transmitted Register"
|
|
hexmask.long 0x24 0.--31. 1. "NFTX,256 to 511 Byte Frames Transmitted without Error"
|
|
line.long 0x28 "TBFT1023,512 to 1023 Byte Frames Transmitted Register"
|
|
hexmask.long 0x28 0.--31. 1. "NFTX,512 to 1023 Byte Frames Transmitted without Error"
|
|
line.long 0x2C "TBFT1518,1024 to 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x2C 0.--31. 1. "NFTX,1024 to 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x30 "GTBFT1518,Greater Than 1518 Byte Frames Transmitted Register"
|
|
hexmask.long 0x30 0.--31. 1. "NFTX,Greater than 1518 Byte Frames Transmitted without Error"
|
|
line.long 0x34 "TUR,Transmit Underruns Register"
|
|
hexmask.long.word 0x34 0.--9. 1. "TXUNR,Transmit Underruns"
|
|
line.long 0x38 "SCF,Single Collision Frames Register"
|
|
hexmask.long.tbyte 0x38 0.--17. 1. "SCOL,Single Collision"
|
|
line.long 0x3C "MCF,Multiple Collision Frames Register"
|
|
hexmask.long.tbyte 0x3C 0.--17. 1. "MCOL,Multiple Collision"
|
|
line.long 0x40 "EC,Excessive Collisions Register"
|
|
hexmask.long.word 0x40 0.--9. 1. "XCOL,Excessive Collisions"
|
|
line.long 0x44 "LC,Late Collisions Register"
|
|
hexmask.long.word 0x44 0.--9. 1. "LCOL,Late Collisions"
|
|
line.long 0x48 "DTF,Deferred Transmission Frames Register"
|
|
hexmask.long.tbyte 0x48 0.--17. 1. "DEFT,Deferred Transmission"
|
|
line.long 0x4C "CSE,Carrier Sense Errors Register"
|
|
hexmask.long.word 0x4C 0.--9. 1. "CSR,Carrier Sense Error"
|
|
line.long 0x50 "ORLO,Octets Received [31:0] Received"
|
|
hexmask.long 0x50 0.--31. 1. "RXO,Received Octets"
|
|
line.long 0x54 "ORHI,Octets Received [47:32] Received"
|
|
hexmask.long.word 0x54 0.--15. 1. "RXO,Received Octets"
|
|
line.long 0x58 "FR,Frames Received Register"
|
|
hexmask.long 0x58 0.--31. 1. "FRX,Frames Received without Error"
|
|
line.long 0x5C "BCFR,Broadcast Frames Received Register"
|
|
hexmask.long 0x5C 0.--31. 1. "BFRX,Broadcast Frames Received without Error"
|
|
line.long 0x60 "MFR,Multicast Frames Received Register"
|
|
hexmask.long 0x60 0.--31. 1. "MFRX,Multicast Frames Received without Error"
|
|
line.long 0x64 "PFR,Pause Frames Received Register"
|
|
hexmask.long.word 0x64 0.--15. 1. "PFRX,Pause Frames Received Register"
|
|
line.long 0x68 "BFR64,64 Byte Frames Received Register"
|
|
hexmask.long 0x68 0.--31. 1. "NFRX,64 Byte Frames Received without Error"
|
|
line.long 0x6C "TBFR127,65 to 127 Byte Frames Received Register"
|
|
hexmask.long 0x6C 0.--31. 1. "NFRX,65 to 127 Byte Frames Received without Error"
|
|
line.long 0x70 "TBFR255,128 to 255 Byte Frames Received Register"
|
|
hexmask.long 0x70 0.--31. 1. "NFRX,128 to 255 Byte Frames Received without Error"
|
|
line.long 0x74 "TBFR511,256 to 511Byte Frames Received Register"
|
|
hexmask.long 0x74 0.--31. 1. "NFRX,256 to 511 Byte Frames Received without Error"
|
|
line.long 0x78 "TBFR1023,512 to 1023 Byte Frames Received Register"
|
|
hexmask.long 0x78 0.--31. 1. "NFRX,512 to 1023 Byte Frames Received without Error"
|
|
line.long 0x7C "TBFR1518,1024 to 1518 Byte Frames Received Register"
|
|
hexmask.long 0x7C 0.--31. 1. "NFRX,1024 to 1518 Byte Frames Received without Error"
|
|
line.long 0x80 "TMXBFR,1519 to Maximum Byte Frames Received Register"
|
|
hexmask.long 0x80 0.--31. 1. "NFRX,1519 to Maximum Byte Frames Received without Error"
|
|
line.long 0x84 "UFR,Undersize Frames Received Register"
|
|
hexmask.long.word 0x84 0.--9. 1. "UFRX,Undersize Frames Received"
|
|
line.long 0x88 "OFR,Oversize Frames Received Register"
|
|
hexmask.long.word 0x88 0.--9. 1. "OFRX,Oversized Frames Received"
|
|
line.long 0x8C "JR,Jabbers Received Register"
|
|
hexmask.long.word 0x8C 0.--9. 1. "JRX,Jabbers Received"
|
|
line.long 0x90 "FCSE,Frame Check Sequence Errors Register"
|
|
hexmask.long.word 0x90 0.--9. 1. "FCKR,Frame Check Sequence Errors"
|
|
line.long 0x94 "LFFE,Length Field Frame Errors Register"
|
|
hexmask.long.word 0x94 0.--9. 1. "LFER,Length Field Frame Errors"
|
|
line.long 0x98 "RSE,Receive Symbol Errors Register"
|
|
hexmask.long.word 0x98 0.--9. 1. "RXSE,Receive Symbol Errors"
|
|
line.long 0x9C "AE,Alignment Errors Register"
|
|
hexmask.long.word 0x9C 0.--9. 1. "AER,Alignment Errors"
|
|
line.long 0xA0 "RRE,Receive Resource Errors Register"
|
|
hexmask.long.tbyte 0xA0 0.--17. 1. "RXRER,Receive Resource Errors"
|
|
line.long 0xA4 "ROE,Receive Overrun Register"
|
|
hexmask.long.word 0xA4 0.--9. 1. "RXOVR,Receive Overruns"
|
|
line.long 0xA8 "IHCE,IP Header Checksum Errors Register"
|
|
hexmask.long.byte 0xA8 0.--7. 1. "HCKER,IP Header Checksum Errors"
|
|
line.long 0xAC "TCE,TCP Checksum Errors Register"
|
|
hexmask.long.byte 0xAC 0.--7. 1. "TCKER,TCP Checksum Errors"
|
|
line.long 0xB0 "UCE,UDP Checksum Errors Register"
|
|
hexmask.long.byte 0xB0 0.--7. 1. "UCKER,UDP Checksum Errors"
|
|
group.long 0x11BC++0x7
|
|
line.long 0x0 "TISUBN,1588 Timer Increment [15:0] Sub-Nanoseconds Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "LSBTIR,Lower Significant Bits of Timer Increment"
|
|
line.long 0x4 "TSH,1588 Timer Seconds High [15:0] Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "TCS,Timer Count in Seconds"
|
|
group.long 0x11C8++0xF
|
|
line.long 0x0 "TSSSL,1588 Timer Sync Strobe Seconds [31:0] Register"
|
|
hexmask.long 0x0 0.--31. 1. "VTS,Value of Timer Seconds Register Capture"
|
|
line.long 0x4 "TSSN,1588 Timer Sync Strobe Nanoseconds Register"
|
|
hexmask.long 0x4 0.--29. 1. "VTN,Value Timer Nanoseconds Register Capture"
|
|
line.long 0x8 "TSL,1588 Timer Seconds [31:0] Register"
|
|
hexmask.long 0x8 0.--31. 1. "TCS,Timer Count in Seconds"
|
|
line.long 0xC "TN,1588 Timer Nanoseconds Register"
|
|
hexmask.long 0xC 0.--29. 1. "TNS,Timer Count in Nanoseconds"
|
|
wgroup.long 0x11D8++0x3
|
|
line.long 0x0 "TA,1588 Timer Adjust Register"
|
|
bitfld.long 0x0 31. "ADJ,Adjust 1588 Timer" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "ITDT,Increment/Decrement"
|
|
group.long 0x11DC++0x3
|
|
line.long 0x0 "TI,1588 Timer Increment Register"
|
|
hexmask.long.byte 0x0 16.--23. 1. "NIT,Number of Increments"
|
|
hexmask.long.byte 0x0 8.--15. 1. "ACNS,Alternative Count Nanoseconds"
|
|
hexmask.long.byte 0x0 0.--7. 1. "CNS,Count Nanoseconds"
|
|
rgroup.long 0x11E0++0x1F
|
|
line.long 0x0 "EFTSL,PTP Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x0 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x4 "EFTN,PTP Event Frame Transmitted Nanoseconds"
|
|
hexmask.long 0x4 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x8 "EFRSL,PTP Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x8 0.--31. 1. "RUD,Register Update"
|
|
line.long 0xC "EFRN,PTP Event Frame Received Nanoseconds"
|
|
hexmask.long 0xC 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x10 "PEFTSL,PTP Peer Event Frame Transmitted Seconds Low Register"
|
|
hexmask.long 0x10 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x14 "PEFTN,PTP Peer Event Frame Transmitted Nanoseconds"
|
|
hexmask.long 0x14 0.--29. 1. "RUD,Register Update"
|
|
line.long 0x18 "PEFRSL,PTP Peer Event Frame Received Seconds Low Register"
|
|
hexmask.long 0x18 0.--31. 1. "RUD,Register Update"
|
|
line.long 0x1C "PEFRN,PTP Peer Event Frame Received Nanoseconds"
|
|
hexmask.long 0x1C 0.--29. 1. "RUD,Register Update"
|
|
rgroup.long 0x1270++0xF
|
|
line.long 0x0 "RLPITR,Receive LPI transition Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "RLPITR,Count number of times transition from rx normal idle to low power idle"
|
|
line.long 0x4 "RLPITI,Receive LPI Time Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "RLPITI,Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode"
|
|
line.long 0x8 "TLPITR,Receive LPI transition Register"
|
|
hexmask.long.word 0x8 0.--15. 1. "TLPITR,Count number of times enable LPI tx bit 20 goes from low to high"
|
|
line.long 0xC "TLPITI,Receive LPI Time Register"
|
|
hexmask.long.tbyte 0xC 0.--23. 1. "TLPITI,Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode"
|
|
tree.end
|
|
endif
|
|
tree "EVSYS (Event System Interface)"
|
|
base ad:0x4480E000
|
|
wgroup.byte 0x0++0x0
|
|
line.byte 0x0 "CTRLA,Control"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x0 "SWEVT,Software Event"
|
|
bitfld.long 0x0 31. "CHANNEL31,Channel 31 Software Selection" "0,1"
|
|
bitfld.long 0x0 30. "CHANNEL30,Channel 30 Software Selection" "0,1"
|
|
bitfld.long 0x0 29. "CHANNEL29,Channel 29 Software Selection" "0,1"
|
|
bitfld.long 0x0 28. "CHANNEL28,Channel 28 Software Selection" "0,1"
|
|
bitfld.long 0x0 27. "CHANNEL27,Channel 27 Software Selection" "0,1"
|
|
bitfld.long 0x0 26. "CHANNEL26,Channel 26 Software Selection" "0,1"
|
|
bitfld.long 0x0 25. "CHANNEL25,Channel 25 Software Selection" "0,1"
|
|
bitfld.long 0x0 24. "CHANNEL24,Channel 24 Software Selection" "0,1"
|
|
bitfld.long 0x0 23. "CHANNEL23,Channel 23 Software Selection" "0,1"
|
|
bitfld.long 0x0 22. "CHANNEL22,Channel 22 Software Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "CHANNEL21,Channel 21 Software Selection" "0,1"
|
|
bitfld.long 0x0 20. "CHANNEL20,Channel 20 Software Selection" "0,1"
|
|
bitfld.long 0x0 19. "CHANNEL19,Channel 19 Software Selection" "0,1"
|
|
bitfld.long 0x0 18. "CHANNEL18,Channel 18 Software Selection" "0,1"
|
|
bitfld.long 0x0 17. "CHANNEL17,Channel 17 Software Selection" "0,1"
|
|
bitfld.long 0x0 16. "CHANNEL16,Channel 16 Software Selection" "0,1"
|
|
bitfld.long 0x0 15. "CHANNEL15,Channel 15 Software Selection" "0,1"
|
|
bitfld.long 0x0 14. "CHANNEL14,Channel 14 Software Selection" "0,1"
|
|
bitfld.long 0x0 13. "CHANNEL13,Channel 13 Software Selection" "0,1"
|
|
bitfld.long 0x0 12. "CHANNEL12,Channel 12 Software Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CHANNEL11,Channel 11 Software Selection" "0,1"
|
|
bitfld.long 0x0 10. "CHANNEL10,Channel 10 Software Selection" "0,1"
|
|
bitfld.long 0x0 9. "CHANNEL9,Channel 9 Software Selection" "0,1"
|
|
bitfld.long 0x0 8. "CHANNEL8,Channel 8 Software Selection" "0,1"
|
|
bitfld.long 0x0 7. "CHANNEL7,Channel 7 Software Selection" "0,1"
|
|
bitfld.long 0x0 6. "CHANNEL6,Channel 6 Software Selection" "0,1"
|
|
bitfld.long 0x0 5. "CHANNEL5,Channel 5 Software Selection" "0,1"
|
|
bitfld.long 0x0 4. "CHANNEL4,Channel 4 Software Selection" "0,1"
|
|
bitfld.long 0x0 3. "CHANNEL3,Channel 3 Software Selection" "0,1"
|
|
bitfld.long 0x0 2. "CHANNEL2,Channel 2 Software Selection" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHANNEL1,Channel 1 Software Selection" "0,1"
|
|
bitfld.long 0x0 0. "CHANNEL0,Channel 0 Software Selection" "0,1"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "PRICTRL,Priority Control"
|
|
bitfld.byte 0x0 7. "RREN,Round-Robin Scheduling Enable" "0,1"
|
|
hexmask.byte 0x0 0.--3. 1. "PRI,Channel Priority Number"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "INTPEND,Channel Pending Interrupt"
|
|
bitfld.word 0x0 15. "BUSY,Busy" "0,1"
|
|
bitfld.word 0x0 14. "READY,Ready" "0,1"
|
|
bitfld.word 0x0 9. "EVD,Channel Event Detected" "0,1"
|
|
bitfld.word 0x0 8. "OVR,Channel Overrun" "0,1"
|
|
hexmask.word.byte 0x0 0.--3. 1. "ID,Channel ID"
|
|
rgroup.long 0x14++0xB
|
|
line.long 0x0 "INTSTATUS,Interrupt Status"
|
|
bitfld.long 0x0 11. "CHINT11,Channel 11 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 10. "CHINT10,Channel 10 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 9. "CHINT9,Channel 9 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 8. "CHINT8,Channel 8 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 7. "CHINT7,Channel 7 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 6. "CHINT6,Channel 6 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 5. "CHINT5,Channel 5 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 4. "CHINT4,Channel 4 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 3. "CHINT3,Channel 3 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 2. "CHINT2,Channel 2 Pending Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "CHINT1,Channel 1 Pending Interrupt" "0,1"
|
|
bitfld.long 0x0 0. "CHINT0,Channel 0 Pending Interrupt" "0,1"
|
|
line.long 0x4 "BUSYCH,Busy Channels"
|
|
bitfld.long 0x4 11. "BUSYCH11,Busy Channel 11" "0,1"
|
|
bitfld.long 0x4 10. "BUSYCH10,Busy Channel 10" "0,1"
|
|
bitfld.long 0x4 9. "BUSYCH9,Busy Channel 9" "0,1"
|
|
bitfld.long 0x4 8. "BUSYCH8,Busy Channel 8" "0,1"
|
|
bitfld.long 0x4 7. "BUSYCH7,Busy Channel 7" "0,1"
|
|
bitfld.long 0x4 6. "BUSYCH6,Busy Channel 6" "0,1"
|
|
bitfld.long 0x4 5. "BUSYCH5,Busy Channel 5" "0,1"
|
|
bitfld.long 0x4 4. "BUSYCH4,Busy Channel 4" "0,1"
|
|
bitfld.long 0x4 3. "BUSYCH3,Busy Channel 3" "0,1"
|
|
bitfld.long 0x4 2. "BUSYCH2,Busy Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "BUSYCH1,Busy Channel 1" "0,1"
|
|
bitfld.long 0x4 0. "BUSYCH0,Busy Channel 0" "0,1"
|
|
line.long 0x8 "READYUSR,Ready Users"
|
|
bitfld.long 0x8 11. "READYUSR11,Ready User for Channel 11" "0,1"
|
|
bitfld.long 0x8 10. "READYUSR10,Ready User for Channel 10" "0,1"
|
|
bitfld.long 0x8 9. "READYUSR9,Ready User for Channel 9" "0,1"
|
|
bitfld.long 0x8 8. "READYUSR8,Ready User for Channel 8" "0,1"
|
|
bitfld.long 0x8 7. "READYUSR7,Ready User for Channel 7" "0,1"
|
|
bitfld.long 0x8 6. "READYUSR6,Ready User for Channel 6" "0,1"
|
|
bitfld.long 0x8 5. "READYUSR5,Ready User for Channel 5" "0,1"
|
|
bitfld.long 0x8 4. "READYUSR4,Ready User for Channel 4" "0,1"
|
|
bitfld.long 0x8 3. "READYUSR3,Ready User for Channel 3" "0,1"
|
|
bitfld.long 0x8 2. "READYUSR2,Ready User for Channel 2" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "READYUSR1,Ready User for Channel 1" "0,1"
|
|
bitfld.long 0x8 0. "READYUSR0,Ready User for Channel 0" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x4480E020 ad:0x4480E028 ad:0x4480E030 ad:0x4480E038 ad:0x4480E040 ad:0x4480E048 ad:0x4480E050 ad:0x4480E058 ad:0x4480E060 ad:0x4480E068 ad:0x4480E070 ad:0x4480E078 ad:0x4480E080 ad:0x4480E088 ad:0x4480E090 ad:0x4480E098)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CHANNEL,Channel n Control"
|
|
bitfld.long 0x0 15. "ONDEMAND,Generic Clock On Demand" "0,1"
|
|
bitfld.long 0x0 14. "RUNSTDBY,Run in standby" "0,1"
|
|
bitfld.long 0x0 10.--11. "EDGSEL,Edge Detection Selection" "0: No event output when using the resynchronized or..,1: Event detection only on the rising edge of the..,2: Event detection only on the falling edge of the..,3: Event detection on rising and falling edges of.."
|
|
bitfld.long 0x0 8.--9. "PATH,Path Selection" "0: Asynchronous path,1: Resynchronized path,?,?"
|
|
hexmask.long.byte 0x0 0.--6. 1. "EVGEN,Event Generator Selection"
|
|
group.byte ($2+0x4)++0x2
|
|
line.byte 0x0 "CHINTENCLR,Channel n Interrupt Enable Clear"
|
|
bitfld.byte 0x0 1. "EVD,Channel Event Detected Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "OVR,Channel Overrun Interrupt Disable" "0,1"
|
|
line.byte 0x1 "CHINTENSET,Channel n Interrupt Enable Set"
|
|
bitfld.byte 0x1 1. "EVD,Channel Event Detected Interrupt Enable" "0,1"
|
|
bitfld.byte 0x1 0. "OVR,Channel Overrun Interrupt Enable" "0,1"
|
|
line.byte 0x2 "CHINTFLAG,Channel n Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x2 1. "EVD,Channel Event Detected" "0,1"
|
|
bitfld.byte 0x2 0. "OVR,Channel Overrun" "0,1"
|
|
rgroup.byte ($2+0x7)++0x0
|
|
line.byte 0x0 "CHSTATUS,Channel n Status"
|
|
bitfld.byte 0x0 1. "BUSYCH,Busy Channel" "0,1"
|
|
bitfld.byte 0x0 0. "RDYUSR,Ready User" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F)(list ad:0x4480E0A0 ad:0x4480E0A8 ad:0x4480E0B0 ad:0x4480E0B8 ad:0x4480E0C0 ad:0x4480E0C8 ad:0x4480E0D0 ad:0x4480E0D8 ad:0x4480E0E0 ad:0x4480E0E8 ad:0x4480E0F0 ad:0x4480E0F8 ad:0x4480E100 ad:0x4480E108 ad:0x4480E110 ad:0x4480E118)
|
|
tree "CHANNEL[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "CHANNEL,Channel n Control"
|
|
bitfld.long 0x0 15. "ONDEMAND,Generic Clock On Demand" "0,1"
|
|
bitfld.long 0x0 14. "RUNSTDBY,Run in standby" "0,1"
|
|
bitfld.long 0x0 10.--11. "EDGSEL,Edge Detection Selection" "0: No event output when using the resynchronized or..,1: Event detection only on the rising edge of the..,2: Event detection only on the falling edge of the..,3: Event detection on rising and falling edges of.."
|
|
bitfld.long 0x0 8.--9. "PATH,Path Selection" "0: Asynchronous path,1: Resynchronized path,?,?"
|
|
hexmask.long.byte 0x0 0.--6. 1. "EVGEN,Event Generator Selection"
|
|
group.byte ($2+0x4)++0x2
|
|
line.byte 0x0 "CHINTENCLR,Channel n Interrupt Enable Clear"
|
|
bitfld.byte 0x0 1. "EVD,Channel Event Detected Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "OVR,Channel Overrun Interrupt Disable" "0,1"
|
|
line.byte 0x1 "CHINTENSET,Channel n Interrupt Enable Set"
|
|
bitfld.byte 0x1 1. "EVD,Channel Event Detected Interrupt Enable" "0,1"
|
|
bitfld.byte 0x1 0. "OVR,Channel Overrun Interrupt Enable" "0,1"
|
|
line.byte 0x2 "CHINTFLAG,Channel n Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x2 1. "EVD,Channel Event Detected" "0,1"
|
|
bitfld.byte 0x2 0. "OVR,Channel Overrun" "0,1"
|
|
rgroup.byte ($2+0x7)++0x0
|
|
line.byte 0x0 "CHSTATUS,Channel n Status"
|
|
bitfld.byte 0x0 1. "BUSYCH,Busy Channel" "0,1"
|
|
bitfld.byte 0x0 0. "RDYUSR,Ready User" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x4480E000
|
|
repeat 104. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x120)++0x0
|
|
line.byte 0x0 "USER[$1],User Multiplexer n"
|
|
hexmask.byte 0x0 0.--5. 1. "CHANNEL,Channel Event Selection"
|
|
repeat.end
|
|
tree.end
|
|
tree "FCR (Flash Read Controller)"
|
|
base ad:0x44002000
|
|
group.long 0x0++0x13
|
|
line.long 0x0 "CTRLA,Control A Register"
|
|
hexmask.long.byte 0x0 16.--19. 1. "RDBUFWS,Data returned from the Read Buffer match the Flash Wait States"
|
|
bitfld.long 0x0 15. "AUTOWS,Automatic Wait State Enable." "0,1"
|
|
bitfld.long 0x0 14. "ADRWS,Address Wait State Enable" "0,1"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FWS,Flash Access Time Defined in terms of AHB Clock Wait States"
|
|
bitfld.long 0x0 2. "ARB,AHB Arbitration scheme" "0,1"
|
|
line.long 0x4 "CTRLB,Control B Register"
|
|
bitfld.long 0x4 8.--9. "SLP,NVM Power Reduction Mode selection during System Standby Sleep" "0,1,2,3"
|
|
bitfld.long 0x4 1. "TEMP,NVM Operating Temperature Read Mode" "0,1"
|
|
bitfld.long 0x4 0. "PRM,Set NVM Power Reduction Mode" "0,1"
|
|
line.long 0x8 "INTENCLR,Interrupt Enable Clear Register"
|
|
bitfld.long 0x8 16. "FLTCAP,ECC Fault Capture Clear Enable" "0,1"
|
|
bitfld.long 0x8 9. "CRCERR,CRC Error Clear Enable" "0,1"
|
|
bitfld.long 0x8 8. "CRCDONE,CRC Calculation Done Clear Enable" "0,1"
|
|
bitfld.long 0x8 1. "DERR,ECC Double Error Detected Clear Enable" "0,1"
|
|
bitfld.long 0x8 0. "SERR,Flash SEC Interrupt Clear Enable" "0,1"
|
|
line.long 0xC "INTENSET,Interrupt Enable SET Register"
|
|
bitfld.long 0xC 16. "FLTCAP,ECC Fault Capture Interrupt Set Enable" "0,1"
|
|
bitfld.long 0xC 9. "CRCERR,CRC Error Interrupt Set Enable" "0,1"
|
|
bitfld.long 0xC 8. "CRCDONE,CRC Calculation Done Set Enable" "0,1"
|
|
bitfld.long 0xC 1. "DERR,ECC Double Error Detected Set Enable" "0,1"
|
|
bitfld.long 0xC 0. "SERR,Flash Single Error Corrected Set Enable" "0,1"
|
|
line.long 0x10 "INTFLAG,Interrupt Flag Register"
|
|
bitfld.long 0x10 16. "FLTCAP,ECC Fault Capture Flag" "0,1"
|
|
bitfld.long 0x10 9. "CRCERR,CRC Error Flag" "0,1"
|
|
bitfld.long 0x10 8. "CRCDONE,CRC Calculation Done Flag" "0,1"
|
|
bitfld.long 0x10 1. "DERR,ECC Double Error Detected Flag" "0,1"
|
|
bitfld.long 0x10 0. "SERR,Flash Single Error Corrected Flag" "0,1"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x0 "STATUS,NVM Status Register"
|
|
bitfld.long 0x0 1. "TEMP,NVM Operating Temperature Read Mode Status" "0,1"
|
|
bitfld.long 0x0 0. "PRM,NVM Power Reduction Mode Status" "0,1"
|
|
group.long 0x18++0x1B
|
|
line.long 0x0 "DBGCTRL,Debug Control Register"
|
|
bitfld.long 0x0 1.--2. "DBGECC,Debug ECC Mode" "0,1,2,3"
|
|
bitfld.long 0x0 0. "CRCRUN,CRC Debug Run" "0,1"
|
|
line.long 0x4 "ECCCTRL,ECC Control Register"
|
|
hexmask.long.byte 0x4 8.--15. 1. "SECCNT,Flash SEC Count"
|
|
bitfld.long 0x4 6. "ECCUNLCK,NVM ECC Mode Control Unlock" "0,1"
|
|
bitfld.long 0x4 4.--5. "ECCCTL,NVM ECC Mode Control- restricts one or more NVMOPs" "0,1,2,3"
|
|
line.long 0x8 "CRCCTRL,CRC Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "PERIOD,Read Period in GCLK counts"
|
|
bitfld.long 0x8 15. "RIN,CRC Reflected Input" "0,1"
|
|
bitfld.long 0x8 14. "ROUT,CRC Reflected Output" "0,1"
|
|
bitfld.long 0x8 13. "AUTOR,CRC Auto Repeat" "0,1"
|
|
bitfld.long 0x8 12. "PLEN32,Polynomial Length Select" "0,1"
|
|
bitfld.long 0x8 5. "RUNSTDBY,CRC Run in Standby" "0,1"
|
|
bitfld.long 0x8 1. "CRCEN,Start CRC Calculation" "0,1"
|
|
bitfld.long 0x8 0. "CRCRST,CRC Reset" "0,1"
|
|
line.long 0xC "CRCPAUSE,CRC PAUSE Register"
|
|
bitfld.long 0xC 0. "PAUSE,CRC Pause" "0,1"
|
|
line.long 0x10 "CRCMADR,CRC Message Address Register"
|
|
hexmask.long 0x10 0.--27. 1. "CRCMADR,Message Start Address in Flash"
|
|
line.long 0x14 "CRCMLEN,CRC Message Length Register"
|
|
hexmask.long.tbyte 0x14 0.--23. 1. "CRCMLEN,Message Length in Bytes"
|
|
line.long 0x18 "CRCIV,CRC Initial Value Register"
|
|
hexmask.long 0x18 0.--31. 1. "CRCIV,CRC Initial Value"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "CRCACC,CRC Accumulator Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCACC,CRC Accumulator Result"
|
|
group.long 0x38++0x17
|
|
line.long 0x0 "CRCPOLY,CRC Polynomial Register"
|
|
hexmask.long 0x0 0.--31. 1. "CRCPOLY,CRC Polynomial Coefficients for LFSR"
|
|
line.long 0x4 "CRCFXOR,CRC Final XOR Register"
|
|
hexmask.long 0x4 0.--31. 1. "CRCFXOR,CRC Final XOR"
|
|
line.long 0x8 "CRCSUM,CRC Checksum Register"
|
|
hexmask.long 0x8 0.--31. 1. "CRCSUM,CRC Checksum"
|
|
line.long 0xC "FFLTCTRL,Flash ECC Fault Control Register"
|
|
bitfld.long 0xC 12.--14. "FLTMD,Fault Mode Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 8.--10. "CTLFLT,ECC/Parity Control Fault bits" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 1. "FLTEN,ECC Fault Enable bit" "0,1"
|
|
bitfld.long 0xC 0. "FLTRST,Fault Reset" "0,1"
|
|
line.long 0x10 "FFLTPTR,Flash ECC Fault Pointer Register"
|
|
hexmask.long.word 0x10 16.--24. 1. "FLT2PTR,Fault 2 Injection Pointer"
|
|
hexmask.long.word 0x10 0.--8. 1. "FLT1PTR,Fault 1 Injection Pointer"
|
|
line.long 0x14 "FFLTADR,Flash Fault Address Register"
|
|
hexmask.long 0x14 0.--27. 1. "FLTADR,Fault Inject Mode - Physical Address"
|
|
rgroup.long 0x50++0xB
|
|
line.long 0x0 "FFLTCAP,Flash Fault Capture Address Register"
|
|
hexmask.long 0x0 0.--27. 1. "FLTADR,Fault capture Mode - Physical Address"
|
|
line.long 0x4 "FFLTPAR,Flash ECC Fault Parity Register"
|
|
bitfld.long 0x4 31. "DEDOUT,The Calculated Overall Parity used in Double Error Detection" "0,1"
|
|
hexmask.long.word 0x4 16.--24. 1. "SECOUT,The Calculated Single Error Parity bits"
|
|
bitfld.long 0x4 15. "DEDIN,The Overall Parity from Flash" "0,1"
|
|
hexmask.long.word 0x4 0.--8. 1. "SECIN,The Single Error Parity bits from Flash"
|
|
line.long 0x8 "FFLTSYN,Flash ECC Fault Syndrome Register"
|
|
hexmask.long.byte 0x8 27.--31. 1. "PERR,Per Word Parity Error Status"
|
|
bitfld.long 0x8 24.--26. "CTLSTAT,Parity vs ECC Control Status" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 18. "CERR,ECC Control bit Error" "0,1"
|
|
bitfld.long 0x8 16.--17. "DERR,Double Error Detected & Single Error Corrected" "0,1,2,3"
|
|
bitfld.long 0x8 15. "DEDSYN,DED Syndrome" "0,1"
|
|
hexmask.long.word 0x8 0.--8. 1. "SECSYN,Single Error Correction Syndrome"
|
|
group.long 0x5C++0x7
|
|
line.long 0x0 "CRP,CFM Page Read Protect Register"
|
|
bitfld.long 0x0 26. "BC2RPLOCK,Boot Configuration Page 2 RP Lock Bit" "0,1"
|
|
bitfld.long 0x0 18. "BC1RPLOCK,Boot Configuration Page 1 RP Lock Bit" "0,1"
|
|
bitfld.long 0x0 10. "BC2RP,Boot Configuration Page 2 Read Protect Bit" "0,1"
|
|
bitfld.long 0x0 2. "BC1RP,Boot Configuration Page 1 Read Protect Bit" "0,1"
|
|
line.long 0x4 "HSMCTRL,HSM CFM PAGES Control Register"
|
|
bitfld.long 0x4 1. "KEYZ,Flash Key Locations read 0\xd5 s" "0,1"
|
|
bitfld.long 0x4 0. "ECCDIS,ECC Disable for HSM Pages in CFM" "0,1"
|
|
tree.end
|
|
tree "FCW (Flash Write Controller)"
|
|
base ad:0x44004000
|
|
group.long 0x0++0x27
|
|
line.long 0x0 "CTRLA,NVM Write Control Register"
|
|
bitfld.long 0x0 7. "PREPG,NVM Pre-Program Configuration Bit" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "NVMOP,NVM Operation"
|
|
line.long 0x4 "CTRLB,NVM Control B Register"
|
|
bitfld.long 0x4 6.--7. "SDALCPU3,Set DAL for CPU n" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "SDALCPU2,Set DAL for CPU n" "0,1,2,3"
|
|
bitfld.long 0x4 2.--3. "SDALCPU1,Set DAL for CPU n" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "SDALCPU0,Set DAL for CPU n" "0,1,2,3"
|
|
line.long 0x8 "MUTEX,NVM MUTEX Register"
|
|
bitfld.long 0x8 1.--2. "OWNER,Flash Write Controller (FCW) Owner ID" "0,1,2,3"
|
|
bitfld.long 0x8 0. "LOCK,Flash Write Controller (FCW) Lock by Owner" "0,1"
|
|
line.long 0xC "INTENCLR,NVM Interrupt Enable Clear Register"
|
|
bitfld.long 0xC 13. "WRERR,Write Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 12. "BORERR,Brown Out Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 8. "HTDPGM,High Temperature Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 7. "SECERR,Security Violation Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 6. "OPERR,NVMOP Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 5. "WPERR,Write Protection Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 4. "BUSERR,AHB Bus Error during Row Write Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "FIFOERR,FIFO Underrun during Row Write Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 2. "CFGERR,Configuration Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 1. "KEYERR,Key Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0xC 0. "DONE,NVM Operation Done Interrupt Enable Bit" "0,1"
|
|
line.long 0x10 "INTENSET,NVM Interrupt Enable SET Register"
|
|
bitfld.long 0x10 13. "WRERR,Write Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 12. "BORERR,Brown Out Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 8. "HTDPGM,High Temperature Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 7. "SECERR,Security Violation Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 6. "OPERR,NVMOP Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 5. "WPERR,Write Protection Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 4. "BUSERR,AHB Bus Error during Row Write Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "FIFOERR,FIFO Underrun during Row Write Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 2. "CFGERR,Configuration Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 1. "KEYERR,Key Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x10 0. "DONE,NVM Operation Done Interrupt Enable Bit" "0,1"
|
|
line.long 0x14 "INTFLAG,NVM Interrupt Flag Register"
|
|
bitfld.long 0x14 13. "WRERR,Write Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 12. "BORERR,Brown Out Detect Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 8. "HTDPGM,High Temperature Detect Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 7. "SECERR,Security Violation Error Bit" "0,1"
|
|
bitfld.long 0x14 6. "OPERR,NVMOP Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 5. "WPERR,Write Protection Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 4. "BUSERR,AHB Bus Error during Row Write Flag Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "FIFOERR,FIFO Underrun during Row Write Flag Bit" "0,1"
|
|
bitfld.long 0x14 2. "CFGERR,Configuration Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 1. "KEYERR,Key Error Flag Bit" "0,1"
|
|
bitfld.long 0x14 0. "DONE,NVM Operation Done Flag Bit" "0,1"
|
|
line.long 0x18 "STATUS,NVM Status Register"
|
|
bitfld.long 0x18 8. "HTDRDY,High Temp Detect Ready Status" "0,1"
|
|
bitfld.long 0x18 0. "BUSY,NVM Busy Status" "0,1"
|
|
line.long 0x1C "KEY,SFR Unlock Register"
|
|
hexmask.long.tbyte 0x1C 8.--31. 1. "KEYCODE,NVM SFR Key Code"
|
|
hexmask.long.byte 0x1C 0.--7. 1. "KEYVALUE,NVM SFR Key Value"
|
|
line.long 0x20 "ADDR,Flash Address Register"
|
|
hexmask.long 0x20 2.--31. 1. "ADDR,Flash Address used by NVMOP"
|
|
line.long 0x24 "SRCADDR,Source Data Address Register"
|
|
hexmask.long 0x24 2.--31. 1. "SRCADDR,Source Data (Word) Address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "DATA[$1],Flash Write Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Flash Write Data"
|
|
repeat.end
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "SWAP,NVM Panel Swap Register"
|
|
bitfld.long 0x0 9. "PFSLOCK,PFM Swap Lock Bit" "0,1"
|
|
bitfld.long 0x0 8. "PFSWAP,PFM Swap Status/Control Bit" "0,1"
|
|
bitfld.long 0x0 1. "BFSLOCK,BFM Swap Lock Bit" "0,1"
|
|
bitfld.long 0x0 0. "BFSWAP,BFM Swap Status/Control Bit" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x4C)++0x3
|
|
line.long 0x0 "PWP[$1],PFM Write Protect Region 0"
|
|
hexmask.long.word 0x0 16.--27. 1. "PWPBASE,PWP Region 0 Base Address - 4KB Page Aligned"
|
|
bitfld.long 0x0 15. "PWPEN,PWP Region 0 Enable Bit" "0,1"
|
|
bitfld.long 0x0 14. "PWPLOCK,PWP Region 0 Lock Bit" "0,1"
|
|
bitfld.long 0x0 13. "PWPMIR,Mirror PWP 0 bit" "0,1"
|
|
hexmask.long.word 0x0 0.--11. 1. "PWPSIZE,PWP Region 0 Size in 4KB pages"
|
|
repeat.end
|
|
group.long 0x6C++0xF
|
|
line.long 0x0 "LBWP,Lower BFM Write Protect Register"
|
|
bitfld.long 0x0 31. "LBWPLOCK,LBWP Lock Bit" "0,1"
|
|
hexmask.long.word 0x0 0.--15. 1. "LBWP,Lower Boot Pages Write Protect Bits"
|
|
line.long 0x4 "UBWP,Upper BFM Write Protect Register"
|
|
bitfld.long 0x4 31. "UBWPLOCK,UBWP Register Lock Bit" "0,1"
|
|
hexmask.long.word 0x4 0.--15. 1. "UBWP,Upper Boot Pages Write Protect Bits"
|
|
line.long 0x8 "UOWP,User OTP Write Protect Register"
|
|
hexmask.long.byte 0x8 24.--27. 1. "UO2WPRLOCK,User OTP Page 2 WP Row Lock Bit"
|
|
hexmask.long.byte 0x8 16.--19. 1. "UO1WPRLOCK,User OTP Page 1 WP Row Lock Bit"
|
|
hexmask.long.byte 0x8 8.--11. 1. "UO2WP,User OTP Page 2 Write Protect Row Bit"
|
|
hexmask.long.byte 0x8 0.--3. 1. "UO1WP,User OTP Page 1 Write Protect Row Bit"
|
|
line.long 0xC "CWP,CFM Page Write Protect Register"
|
|
bitfld.long 0xC 26. "BC2WPLOCK,Boot Configuration Page 2 WP Lock Bit" "0,1"
|
|
bitfld.long 0xC 24. "UC2WPLOCK,User Configuration Page 2 WP Lock Bit" "0,1"
|
|
bitfld.long 0xC 18. "BC1WPLOCK,Boot Configuration Page 1 WP Lock Bit" "0,1"
|
|
bitfld.long 0xC 16. "UC1WPLOCK,User Configuration Page 1 WP Lock Bit" "0,1"
|
|
bitfld.long 0xC 10. "BC2WP,Boot Configuration Page 2 Write Protect Bit" "0,1"
|
|
bitfld.long 0xC 8. "UC2WP,User Configuration Page 2 Write Protect Bit" "0,1"
|
|
bitfld.long 0xC 2. "BC1WP,Boot Configuration Page 1 Write Protect Bit" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "UC1WP,User Configuration Page 1 Write Protect Bit" "0,1"
|
|
group.long 0x80++0xF
|
|
line.long 0x0 "HSMINTENCLR,HSM NVM Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 13. "WRERR,Write Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 12. "BORERR,Brown Out Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 8. "HTDPGM,High Temperature Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 7. "SECERR,Security Violation Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 6. "OPERR,NVMOP Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 5. "WPERR,Write Protection Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 4. "BUSERR,AHB Bus Error during Row Write Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "FIFOERR,FIFO Underrun during Row Write Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 2. "CFGERR,Configuration Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 1. "KEYERR,Key Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x0 0. "DONE,NVM Operation Done Interrupt Enable Bit" "0,1"
|
|
line.long 0x4 "HSMINTENSET,HSM NVM Interrupt Enable SET Register"
|
|
bitfld.long 0x4 13. "WRERR,Write Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 12. "BORERR,Brown Out Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 8. "HTDPGM,High Temperature Detect Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 7. "SECERR,Security Violation Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 6. "OPERR,NVMOP Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 5. "WPERR,Write Protection Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 4. "BUSERR,AHB Bus Error during Row Write Interrupt Enable Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "FIFOERR,FIFO Underrun during Row Write Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 2. "CFGERR,Configuration Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 1. "KEYERR,Key Error Interrupt Enable Bit" "0,1"
|
|
bitfld.long 0x4 0. "DONE,NVM Operation Done Interrupt Enable Bit" "0,1"
|
|
line.long 0x8 "HSMINTFLAG,HSM NVM Interrupt Flag Register"
|
|
bitfld.long 0x8 13. "WRERR,Write Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 12. "BORERR,Brown Out Detect Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 8. "HTDPGM,High Temperature Detect Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 7. "SECERR,Security Violation Error Bit" "0,1"
|
|
bitfld.long 0x8 6. "OPERR,NVMOP Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 5. "WPERR,Write Protection Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 4. "BUSERR,AHB Bus Error during Row Write Flag Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "FIFOERR,FIFO Underrun during Row Write Flag Bit" "0,1"
|
|
bitfld.long 0x8 2. "CFGERR,Configuration Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 1. "KEYERR,Key Error Flag Bit" "0,1"
|
|
bitfld.long 0x8 0. "DONE,NVM Operation Done Flag Bit" "0,1"
|
|
line.long 0xC "HSMCWP,HSM CFG Write Protect Register"
|
|
hexmask.long.byte 0xC 28.--31. 1. "HCWPLOCK,HSMCWP Register Lock Bit"
|
|
hexmask.long.byte 0xC 12.--15. 1. "HCWP,HSM CFG Page Write Protect Bits"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x90)++0x3
|
|
line.long 0x0 "HSMLDAT[$1],HSM Tamper Lower Overwrite Data Register"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xB0)++0x3
|
|
line.long 0x0 "HSMUDAT[$1],HSM Tamper Upper Overwrite Data Register"
|
|
repeat.end
|
|
tree.end
|
|
tree "FPB (Flash Patch and Breakpoint)"
|
|
base ad:0xE0002000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "FP_CTRL,Flash Patch Control Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "REV,Revision"
|
|
bitfld.long 0x0 12.--14. "NUM_CODE_1,Number of implemented code comparators bits [6:4]" "0,1,2,3,4,5,6,7"
|
|
hexmask.long.byte 0x0 8.--11. 1. "NUM_LIT,Number of literal comparators"
|
|
hexmask.long.byte 0x0 4.--7. 1. "NUM_CODE,Number of implemented code comparators bits [3:0]"
|
|
bitfld.long 0x0 1. "KEY,FP_CTRL write-enable key" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Flash Patch global enable" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x0 29. "RMPSPT,Remap supported" "0,1"
|
|
hexmask.long.tbyte 0x0 5.--28. 1. "REMAP,Remap address"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "FP_COMP[$1],Flash Patch Comparator Register n"
|
|
bitfld.long 0x0 31. "FE,Flash Patch enable" "0,1"
|
|
hexmask.long 0x0 2.--28. 1. "FPADDR,Flash Patch address"
|
|
bitfld.long 0x0 0. "BE,Breakpoint enable" "0,1"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x8)++0x3
|
|
line.long 0x0 "FP_COMP_BREAKPOINT_MODE[$1],Flash Patch Comparator Register n"
|
|
hexmask.long 0x0 1.--31. 1. "BPADDR,Breakpoint address"
|
|
bitfld.long 0x0 0. "BE,Breakpoint enable" "0,1"
|
|
repeat.end
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "FP_LAR,FPB Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0xFB4++0x3
|
|
line.long 0x0 "FP_LSR,FPB Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
rgroup.long 0xFBC++0x3
|
|
line.long 0x0 "FP_DEVARCH,FPB Device Architecture Register"
|
|
hexmask.long.word 0x0 21.--31. 1. "ARCHITECT,Architect"
|
|
bitfld.long 0x0 20. "PRESENT,DEVARCH Present" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REVISION,Revision"
|
|
hexmask.long.byte 0x0 12.--15. 1. "ARCHVER,Architecture Version"
|
|
hexmask.long.word 0x0 0.--11. 1. "ARCHPART,Architecture Part"
|
|
rgroup.long 0xFCC++0x33
|
|
line.long 0x0 "FP_DEVTYPE,FPB Device Type Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SUB,Sub-type"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type"
|
|
line.long 0x4 "FP_PIDR4,FP Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x8 "FP_PIDR5,FP Peripheral Identification Register 5"
|
|
line.long 0xC "FP_PIDR6,FP Peripheral Identification Register 6"
|
|
line.long 0x10 "FP_PIDR7,FP Peripheral Identification Register 7"
|
|
line.long 0x14 "FP_PIDR0,FP Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x18 "FP_PIDR1,FP Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x18 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x1C "FP_PIDR2,FP Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x1C 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x1C 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "FP_PIDR3,FP Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x24 "FP_CIDR0,FP Component Identification Register 0"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x28 "FP_CIDR1,FP Component Identification Register 1"
|
|
hexmask.long.byte 0x28 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x2C "FP_CIDR2,FP Component Identification Register 2"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x30 "FP_CIDR3,FP Component Identification Register 3"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
tree "FPU (Floating-Point Unit)"
|
|
base ad:0xE000EF30
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x0 31. "ASPEN,Automatic FP context save enable" "0,1"
|
|
bitfld.long 0x0 30. "LSPEN,Automatic lazy FP context save enable" "0,1"
|
|
bitfld.long 0x0 29. "LSPENS,LSPEN field writeable only from Secure state" "0,1"
|
|
bitfld.long 0x0 28. "CLRONRET,Clear FP caller saved registers enable" "0,1"
|
|
bitfld.long 0x0 27. "CLRONRETS,CLRONRET field writeable only from Secure state" "0,1"
|
|
bitfld.long 0x0 26. "TS,Treat FP registers as Secure enable" "0,1"
|
|
bitfld.long 0x0 10. "UFRDY,UsageFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 9. "SPLIMVIOL,FP context violates the stack pointer limit" "0,1"
|
|
bitfld.long 0x0 8. "MONRDY,DebugMonitor exception set to pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SFRDY,SecureFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 6. "BFRDY,BusFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 5. "MMRDY,MemManage exception set to pending" "0,1"
|
|
bitfld.long 0x0 4. "HFRDY,HardFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 3. "THREAD,Thread mode when FP stack frame allocated" "0,1"
|
|
bitfld.long 0x0 2. "S,Security status of FP context" "0,1"
|
|
bitfld.long 0x0 1. "USER,Privilege level when FP stack frame allocated" "0,1"
|
|
bitfld.long 0x0 0. "LSPACT,Lazy preservation of FP state active" "0,1"
|
|
line.long 0x4 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x4 3.--31. 1. "ADDRESS,Address for FP registers push to exception stack"
|
|
line.long 0x8 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x8 26. "AHP,Alternative half-precision default value" "0,1"
|
|
bitfld.long 0x8 25. "DN,NaN default value" "0,1"
|
|
bitfld.long 0x8 24. "FZ,Flush-to-zero default value" "0,1"
|
|
bitfld.long 0x8 22.--23. "RMode,Rounding mode default value" "0,1,2,3"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "MVFR0,Media and VFP Feature Register 0"
|
|
hexmask.long.byte 0x0 28.--31. 1. "FPRound,All FP rounding modes support"
|
|
hexmask.long.byte 0x0 20.--23. 1. "FPSqrt,FP square root operations support"
|
|
hexmask.long.byte 0x0 16.--19. 1. "FPDivide,FP divide operations support"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FPDP,FP double-precision operations support"
|
|
hexmask.long.byte 0x0 4.--7. 1. "FPSP,FP single-precision operations support"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIMDReg,Size of FP register file"
|
|
line.long 0x4 "MVFR1,Media and VFP Feature Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FMAC,Fused multiply accumulate instructions"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FPHP,Floating-point half-precision conversion instructions"
|
|
hexmask.long.byte 0x4 4.--7. 1. "FPDNaN,Propagation of NaN values support"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPFtZ,Floating-point subnormals flush-to-zero"
|
|
line.long 0x8 "MVFR2,Media and VFP Feature Register 2"
|
|
hexmask.long.byte 0x8 4.--7. 1. "FPMisc,Floating-point miscellaneous features support"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "FPU_NS (Floating-Point Unit (Non-Secure))"
|
|
base ad:0xE002EF30
|
|
group.long 0x4++0xB
|
|
line.long 0x0 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x0 31. "ASPEN,Automatic FP context save enable" "0,1"
|
|
bitfld.long 0x0 30. "LSPEN,Automatic lazy FP context save enable" "0,1"
|
|
bitfld.long 0x0 29. "LSPENS,LSPEN field writeable only from Secure state" "0,1"
|
|
bitfld.long 0x0 28. "CLRONRET,Clear FP caller saved registers enable" "0,1"
|
|
bitfld.long 0x0 27. "CLRONRETS,CLRONRET field writeable only from Secure state" "0,1"
|
|
bitfld.long 0x0 26. "TS,Treat FP registers as Secure enable" "0,1"
|
|
bitfld.long 0x0 10. "UFRDY,UsageFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 9. "SPLIMVIOL,FP context violates the stack pointer limit" "0,1"
|
|
bitfld.long 0x0 8. "MONRDY,DebugMonitor exception set to pending" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "SFRDY,SecureFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 6. "BFRDY,BusFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 5. "MMRDY,MemManage exception set to pending" "0,1"
|
|
bitfld.long 0x0 4. "HFRDY,HardFault exception set to pending" "0,1"
|
|
bitfld.long 0x0 3. "THREAD,Thread mode when FP stack frame allocated" "0,1"
|
|
bitfld.long 0x0 2. "S,Security status of FP context" "0,1"
|
|
bitfld.long 0x0 1. "USER,Privilege level when FP stack frame allocated" "0,1"
|
|
bitfld.long 0x0 0. "LSPACT,Lazy preservation of FP state active" "0,1"
|
|
line.long 0x4 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x4 3.--31. 1. "ADDRESS,Address for FP registers push to exception stack"
|
|
line.long 0x8 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x8 26. "AHP,Alternative half-precision default value" "0,1"
|
|
bitfld.long 0x8 25. "DN,NaN default value" "0,1"
|
|
bitfld.long 0x8 24. "FZ,Flush-to-zero default value" "0,1"
|
|
bitfld.long 0x8 22.--23. "RMode,Rounding mode default value" "0,1,2,3"
|
|
rgroup.long 0x10++0xB
|
|
line.long 0x0 "MVFR0,Media and VFP Feature Register 0"
|
|
hexmask.long.byte 0x0 28.--31. 1. "FPRound,All FP rounding modes support"
|
|
hexmask.long.byte 0x0 20.--23. 1. "FPSqrt,FP square root operations support"
|
|
hexmask.long.byte 0x0 16.--19. 1. "FPDivide,FP divide operations support"
|
|
hexmask.long.byte 0x0 8.--11. 1. "FPDP,FP double-precision operations support"
|
|
hexmask.long.byte 0x0 4.--7. 1. "FPSP,FP single-precision operations support"
|
|
hexmask.long.byte 0x0 0.--3. 1. "SIMDReg,Size of FP register file"
|
|
line.long 0x4 "MVFR1,Media and VFP Feature Register 1"
|
|
hexmask.long.byte 0x4 28.--31. 1. "FMAC,Fused multiply accumulate instructions"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FPHP,Floating-point half-precision conversion instructions"
|
|
hexmask.long.byte 0x4 4.--7. 1. "FPDNaN,Propagation of NaN values support"
|
|
hexmask.long.byte 0x4 0.--3. 1. "FPFtZ,Floating-point subnormals flush-to-zero"
|
|
line.long 0x8 "MVFR2,Media and VFP Feature Register 2"
|
|
hexmask.long.byte 0x8 4.--7. 1. "FPMisc,Floating-point miscellaneous features support"
|
|
tree.end
|
|
endif
|
|
tree "FREQM (Frequency Meter)"
|
|
base ad:0x44014000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "CTRLA,Control A Register"
|
|
bitfld.byte 0x0 7. "ONDEMAND,On Demand Control" "0,1"
|
|
bitfld.byte 0x0 6. "RUNSTDBY,Run In Standby" "0,1"
|
|
bitfld.byte 0x0 2. "FREERUN,Free Running Mode" "0,1"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
wgroup.byte 0x1++0x0
|
|
line.byte 0x0 "CTRLB,Control B Register"
|
|
bitfld.byte 0x0 0. "START,Start Measurement" "0,1"
|
|
group.word 0x2++0x1
|
|
line.word 0x0 "CFGA,Config A Register"
|
|
bitfld.word 0x0 15. "DIVREF,Divide Reference Clock" "0: The reference clock is divided by 1,1: The reference clock is divided by 8"
|
|
bitfld.word 0x0 8.--10. "MSRSEL,Measurement Clock Selection" "0: GCLK Input Clock,1: CPU Input Clock,?,?,?,?,?,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "REFNUM,Number of Reference Clock Cycles"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "CTRLC,Control C Register"
|
|
bitfld.byte 0x0 0.--2. "WINMODE,Window Monitor Mode" "0: No window mode (default),1: VALUE > WINLT,2: VALUE < WINUT,3: WINLT < VALUE < WINUT,4: !(WINLT < VALUE < WINUT),?,?,?"
|
|
group.byte 0x6++0x0
|
|
line.byte 0x0 "EVCTRL,Event Control Register"
|
|
bitfld.byte 0x0 5. "WINMONEO,Window Monitor Event Out" "0,1"
|
|
bitfld.byte 0x0 4. "DONEEO,Measurement Done Event Out" "0,1"
|
|
bitfld.byte 0x0 1. "STARTINV,Start Measurement Event Invert Enable" "0,1"
|
|
bitfld.byte 0x0 0. "STARTEI,Start Measurement Event Input Enable" "0,1"
|
|
group.byte 0x8++0x3
|
|
line.byte 0x0 "INTENCLR,Interrupt Enable Clear Register"
|
|
bitfld.byte 0x0 1. "WINMON,Window Monitor Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "DONE,Measurement Done Interrupt Disable" "0,1"
|
|
line.byte 0x1 "INTENSET,Interrupt Enable Set Register"
|
|
bitfld.byte 0x1 1. "WINMON,Window Monitor Interrupt Enable" "0,1"
|
|
bitfld.byte 0x1 0. "DONE,Measurement Done Interrupt Enable" "0,1"
|
|
line.byte 0x2 "INTFLAG,Interrupt Flag Register"
|
|
bitfld.byte 0x2 1. "WINMON,Window Monitor" "0,1"
|
|
bitfld.byte 0x2 0. "DONE,Measurement Done" "0,1"
|
|
line.byte 0x3 "STATUS,Status Register"
|
|
bitfld.byte 0x3 1. "OVF,Sticky Count Value Overflow" "0,1"
|
|
bitfld.byte 0x3 0. "BUSY,FREQM Status" "0,1"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy Register"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "VALUE,Count Value Register"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "VALUE,Measurement Value"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "WINLT,Window Monitor Lower Threshold"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "WINLT,Window Lower Threshold"
|
|
line.long 0x4 "WINUT,Window Monitor Upper Threshold"
|
|
hexmask.long.tbyte 0x4 0.--23. 1. "WINUT,Window Upper Threshold"
|
|
tree.end
|
|
tree "GCLK (Generic Clock Controller)"
|
|
base ad:0x44010000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "CTRLA,Control"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "GENCTRL11,Generic Clock Generator Control 11 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 12. "GENCTRL10,Generic Clock Generator Control 10 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 11. "GENCTRL9,Generic Clock Generator Control 9 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 10. "GENCTRL8,Generic Clock Generator Control 8 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 9. "GENCTRL7,Generic Clock Generator Control 7 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 8. "GENCTRL6,Generic Clock Generator Control 6 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 7. "GENCTRL5,Generic Clock Generator Control 5 Synchronization Busy bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "GENCTRL4,Generic Clock Generator Control 4 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 5. "GENCTRL3,Generic Clock Generator Control 3 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 4. "GENCTRL2,Generic Clock Generator Control 2 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 3. "GENCTRL1,Generic Clock Generator Control 1 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 2. "GENCTRL0,Generic Clock Generator Control 0 Synchronization Busy bit" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy bit" "0,1"
|
|
repeat 12. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "GENCTRL[$1],Generic Clock Generator Control"
|
|
hexmask.long.word 0x0 16.--31. 1. "DIV,Division Factor"
|
|
bitfld.long 0x0 13. "RUNSTDBY,Run in Standby" "0,1"
|
|
bitfld.long 0x0 12. "DIVSEL,Divide Selection" "0: Divide input directly by divider factor,1: Divide input by 2^(divider factor+ 1)"
|
|
bitfld.long 0x0 11. "OE,Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "OOV,Output Off Value" "0,1"
|
|
bitfld.long 0x0 9. "IDC,Improve Duty Cycle" "0,1"
|
|
bitfld.long 0x0 8. "GENEN,Generic Clock Generator Enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "SRC,Source Select"
|
|
repeat.end
|
|
repeat 48. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "PCHCTRL[$1],Peripheral Clock Control"
|
|
bitfld.long 0x0 7. "WRTLOCK,Write Lock" "0,1"
|
|
bitfld.long 0x0 6. "CHEN,Channel Enable" "0,1"
|
|
hexmask.long.byte 0x0 0.--3. 1. "GEN,Generic Clock Generator"
|
|
repeat.end
|
|
tree.end
|
|
tree "HMATRIX (High-Speed Bus Matrix)"
|
|
base ad:0x44806000
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "MCFG[$1],Master Configuration"
|
|
bitfld.long 0x0 0.--2. "ULBT,Undefined Length Burst Type" "0: Infinite Length,1: Single Access,2: Four Beat Burst,3: Eight Beat Burst,4: Sixteen Beat Burst,?,?,?"
|
|
repeat.end
|
|
repeat 13. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "SCFG[$1],Slave Configuration"
|
|
hexmask.long.byte 0x0 18.--21. 1. "FIXED_DEFMSTR,Fixed Index of Default Master"
|
|
bitfld.long 0x0 16.--17. "DEFMSTR_TYPE,Default Master Type" "0: No Default Master. At the end of current slave..,1: Last Default Master At the end of current slave..,2: Fixed Default Master At the end of current slave..,?"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "SLOT_CYCLE,Maximum Number of Allowed Cycles for a Burst"
|
|
repeat.end
|
|
repeat 13. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC)(list ad:0x44806080 ad:0x44806088 ad:0x44806090 ad:0x44806098 ad:0x448060A0 ad:0x448060A8 ad:0x448060B0 ad:0x448060B8 ad:0x448060C0 ad:0x448060C8 ad:0x448060D0 ad:0x448060D8 ad:0x448060E0)
|
|
tree "PRS[$1]"
|
|
base $2
|
|
group.long ($2)++0x7
|
|
line.long 0x0 "PRAS,Priority A for Slave"
|
|
bitfld.long 0x0 30. "LQOSEN7,Latency Quality Of Service Enable for Master 7" "0,1"
|
|
bitfld.long 0x0 28.--29. "M7PR,Master 7 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 26. "LQOSEN6,Latency Quality Of Service Enable for Master 6" "0,1"
|
|
bitfld.long 0x0 24.--25. "M6PR,Master 6 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 22. "LQOSEN5,Latency Quality Of Service Enable for Master 5" "0,1"
|
|
bitfld.long 0x0 20.--21. "M5PR,Master 5 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 18. "LQOSEN4,Latency Quality Of Service Enable for Master 4" "0,1"
|
|
bitfld.long 0x0 16.--17. "M4PR,Master 4 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 14. "LQOSEN3,Latency Quality Of Service Enable for Master 3" "0,1"
|
|
bitfld.long 0x0 12.--13. "M3PR,Master 3 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 10. "LQOSEN2,Latency Quality Of Service Enable for Master 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "M2PR,Master 2 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 6. "LQOSEN1,Latency Quality Of Service Enable for Master 1" "0,1"
|
|
bitfld.long 0x0 4.--5. "M1PR,Master 1 Priority" "0,1,2,3"
|
|
bitfld.long 0x0 2. "LQOSEN0,Latency Quality Of Service Enable for Master 0" "0,1"
|
|
bitfld.long 0x0 0.--1. "M0PR,Master 0 Priority" "0,1,2,3"
|
|
line.long 0x4 "PRBS,Priority B for Slave"
|
|
bitfld.long 0x4 30. "LQOSEN15,Latency Quality Of Service Enable for Master 15" "0,1"
|
|
bitfld.long 0x4 28.--29. "M15PR,Master 15 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 26. "LQOSEN14,Latency Quality Of Service Enable for Master 14" "0,1"
|
|
bitfld.long 0x4 24.--25. "M14PR,Master 14 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 22. "LQOSEN13,Latency Quality Of Service Enable for Master 13" "0,1"
|
|
bitfld.long 0x4 20.--21. "M13PR,Master 13 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 18. "LQOSEN12,Latency Quality Of Service Enable for Master 12" "0,1"
|
|
bitfld.long 0x4 16.--17. "M12PR,Master 12 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 14. "LQOSEN11,Latency Quality Of Service Enable for Master 11" "0,1"
|
|
bitfld.long 0x4 12.--13. "M11PR,Master 11 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 10. "LQOSEN10,Latency Quality Of Service Enable for Master 10" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8.--9. "M10PR,Master 10 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 6. "LQOSEN9,Latency Quality Of Service Enable for Master 9" "0,1"
|
|
bitfld.long 0x4 4.--5. "M9PR,Master 9 Priority" "0,1,2,3"
|
|
bitfld.long 0x4 2. "LQOSEN8,Latency Quality Of Service Enable for Master 8" "0,1"
|
|
bitfld.long 0x4 0.--1. "M8PR,Master 8 Priority" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x44806000
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "MRCR,Master Remap Control"
|
|
bitfld.long 0x0 15. "RCB15,Remap Command Bit for Master 15" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 14. "RCB14,Remap Command Bit for Master 14" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 13. "RCB13,Remap Command Bit for Master 13" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 12. "RCB12,Remap Command Bit for Master 12" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 11. "RCB11,Remap Command Bit for Master 11" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 10. "RCB10,Remap Command Bit for Master 10" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 9. "RCB9,Remap Command Bit for Master 9" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 8. "RCB8,Remap Command Bit for Master 8" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 7. "RCB7,Remap Command Bit for Master 7" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 6. "RCB6,Remap Command Bit for Master 6" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 5. "RCB5,Remap Command Bit for Master 5" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 4. "RCB4,Remap Command Bit for Master 4" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 3. "RCB3,Remap Command Bit for Master 3" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 2. "RCB2,Remap Command Bit for Master 2" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
newline
|
|
bitfld.long 0x0 1. "RCB1,Remap Command Bit for Master 1" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
bitfld.long 0x0 0. "RCB0,Remap Command Bit for Master 0" "0: Disable remapped address decoding for master,1: Enable remapped address decoding for master"
|
|
repeat 13. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x110)++0x3
|
|
line.long 0x0 "SFR[$1],Special Function"
|
|
hexmask.long 0x0 0.--31. 1. "SFR,Special Function Register"
|
|
repeat.end
|
|
wgroup.long 0x150++0x7
|
|
line.long 0x0 "MEIER,Master Error Interrupt Enable"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MEIDR,Master Error Interrupt Disable"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
rgroup.long 0x158++0x7
|
|
line.long 0x0 "MEIMR,Master Error Interrupt Mask"
|
|
bitfld.long 0x0 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x0 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x0 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x0 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x0 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x0 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x0 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x0 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x0 0. "MERR0,Master 0 Access Error" "0,1"
|
|
line.long 0x4 "MESR,Master Error Status"
|
|
bitfld.long 0x4 15. "MERR15,Master 15 Access Error" "0,1"
|
|
bitfld.long 0x4 14. "MERR14,Master 14 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "MERR13,Master 13 Access Error" "0,1"
|
|
bitfld.long 0x4 12. "MERR12,Master 12 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "MERR11,Master 11 Access Error" "0,1"
|
|
bitfld.long 0x4 10. "MERR10,Master 10 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "MERR9,Master 9 Access Error" "0,1"
|
|
bitfld.long 0x4 8. "MERR8,Master 8 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 7. "MERR7,Master 7 Access Error" "0,1"
|
|
bitfld.long 0x4 6. "MERR6,Master 6 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "MERR5,Master 5 Access Error" "0,1"
|
|
bitfld.long 0x4 4. "MERR4,Master 4 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "MERR3,Master 3 Access Error" "0,1"
|
|
bitfld.long 0x4 2. "MERR2,Master 2 Access Error" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "MERR1,Master 1 Access Error" "0,1"
|
|
bitfld.long 0x4 0. "MERR0,Master 0 Access Error" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x160)++0x3
|
|
line.long 0x0 "MEAR[$1],Master Error Address"
|
|
repeat.end
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "HSM (Hardware Security Module)"
|
|
base ad:0x48000000
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRLA,CONTROL REGISTER A"
|
|
bitfld.long 0x0 6. "RUNSTDBY,Run In Standby bit" "0,1"
|
|
bitfld.long 0x0 2. "PRIV,Privileged Access Only bit" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Clock Enable bit" "0,1"
|
|
line.long 0x4 "CTRLB,CONTROL REGISTER B"
|
|
bitfld.long 0x4 0. "CANCEL,Cancel Command" "0,1"
|
|
line.long 0x8 "INTENCLR,INTERRUPT ENABLE CLEAR REGISTER"
|
|
bitfld.long 0x8 1. "TAMPER,Tamper Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "ERROR,Error Interrupt Enable" "0,1"
|
|
line.long 0xC "INTENSET,INTERRUPT ENABLE SET"
|
|
bitfld.long 0xC 1. "TAMPER,Tamper Interrupt Enable" "0,1"
|
|
bitfld.long 0xC 0. "ERROR,Error Interrupt Enable" "0,1"
|
|
line.long 0x10 "INTFLAG,INTERRUPT FLAG"
|
|
bitfld.long 0x10 1. "TAMPER,Tamper Interrupt Flag" "0,1"
|
|
bitfld.long 0x10 0. "ERROR,Error Interrupt Flag" "0,1"
|
|
line.long 0x14 "STATUS,STATUS"
|
|
hexmask.long.byte 0x14 16.--19. 1. "ECODE,ERROR CODE"
|
|
bitfld.long 0x14 12.--14. "SBS,SECURE BOOT STATE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 8.--10. "LCS,LIFECYCLE STATE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 4.--6. "PS,PROCESSING STATE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x14 1. "LKUP,HSM CPU LOCKUP" "0,1"
|
|
bitfld.long 0x14 0. "BUSY,HSM CPU BUSY" "0,1"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "MBFIFO[$1],MAILBOX FIFO"
|
|
hexmask.long 0x0 0.--31. 1. "MBFIFO,MAILBOX FIFO"
|
|
repeat.end
|
|
group.long 0x140++0x1B
|
|
line.long 0x0 "MBTXSTATUS,MAILBOX TRANSMIT STATUS"
|
|
bitfld.long 0x0 23. "TXERR,TRANSMIT ERROR" "0,1"
|
|
bitfld.long 0x0 21. "TXFULL,TRANSMIT FIFO FULL" "0,1"
|
|
bitfld.long 0x0 20. "TXINT,TRANSMIT FIFO INTERRUPT FLAG" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "TXTYPE,TRANSMIT MESSAGE HEADER TYPE"
|
|
hexmask.long.word 0x0 0.--15. 1. "TXREMAINING,TRANSMIT BYTES REMAINING"
|
|
line.long 0x4 "MBRXSTATUS,MAILBOX RECEIVE STATUS"
|
|
bitfld.long 0x4 23. "RXERR,RECEIVE ERROR" "0,1"
|
|
bitfld.long 0x4 22. "RXHEAD,Receive Header Next Word bit" "0,1"
|
|
bitfld.long 0x4 21. "RXEMPTY,RECEIVE FIFO FULL" "0,1"
|
|
bitfld.long 0x4 20. "RXINT,RECEIVE FIFO INTERRUPT FLAG" "0,1"
|
|
hexmask.long.byte 0x4 16.--19. 1. "RXTYPE,RECEIVE MESSAGE HEADER TYPE"
|
|
hexmask.long.word 0x4 0.--15. 1. "RXREMAINING,RECEIVE BYTES REMAINING"
|
|
line.long 0x8 "MBTXPROT,MAILBOX TX PROTECTION"
|
|
hexmask.long.byte 0x8 24.--31. 1. "USER,USER SIDEBAND"
|
|
bitfld.long 0x8 23. "NSEC,MAILBOX MESSAGE NON-SECURE ACCESS" "0,1"
|
|
bitfld.long 0x8 22. "PRIV,MAILBOX MESSAGE PRIVILEDGED ACCESS" "0,1"
|
|
bitfld.long 0x8 21. "UNPROT,MAILBOX UNPROTECTED" "0,1"
|
|
line.long 0xC "MBRXPROT,MAILBOX RX PROTECTION"
|
|
hexmask.long.byte 0xC 24.--31. 1. "USER,USER SIDEBAND"
|
|
bitfld.long 0xC 23. "NSEC,MAILBOX MESSAGE NON-SECURE ACCESS" "0,1"
|
|
bitfld.long 0xC 22. "PRIV,MAILBOX MESSAGE PRIVILEDGED ACCESS" "0,1"
|
|
bitfld.long 0xC 21. "UNPROT,MAILBOX UNPROTECTED" "0,1"
|
|
line.long 0x10 "MBTXHEAD,MAILBOX TRANSMIT HEADER"
|
|
hexmask.long 0x10 0.--31. 1. "TXHEAD,MAILBOX TRANSMIT HEADER REGISTER"
|
|
line.long 0x14 "MBRXHEAD,MAILBOX RECEIVE HEADER"
|
|
hexmask.long 0x14 0.--31. 1. "RXHEAD,MAILBOX RECEIVE HEADER REGISTER"
|
|
line.long 0x18 "MBCONFIG,MAILBOX CONFIGURATION"
|
|
bitfld.long 0x18 1. "RXINT,MAILBOX RECEIVE INTERRUPT ENABLE" "0,1"
|
|
bitfld.long 0x18 0. "TXINT,MAILBOX TRANSMIT INTERRUPT ENABLE" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "ICB (Implementation Control Block)"
|
|
base ad:0xE000E000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ICTR,Interrupt Controller Type Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTLINESNUM,Interrupt line set number"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
line.long 0x4 "CPPWR,Coprocessor Power Control Register"
|
|
bitfld.long 0x4 23. "SUS11,State UNKNOWN Secure only 11" "0,1"
|
|
bitfld.long 0x4 22. "SU11,State UNKNOWN 11" "0,1"
|
|
bitfld.long 0x4 21. "SUS10,State UNKNOWN Secure only 10" "0,1"
|
|
bitfld.long 0x4 20. "SU10,State UNKNOWN 10" "0,1"
|
|
bitfld.long 0x4 15. "SUS7,State UNKNOWN Secure only 7" "0,1"
|
|
bitfld.long 0x4 14. "SU7,State UNKNOWN 7" "0,1"
|
|
bitfld.long 0x4 13. "SUS6,State UNKNOWN Secure only 6" "0,1"
|
|
bitfld.long 0x4 12. "SU6,State UNKNOWN 6" "0,1"
|
|
bitfld.long 0x4 11. "SUS5,State UNKNOWN Secure only 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SU5,State UNKNOWN 5" "0,1"
|
|
bitfld.long 0x4 9. "SUS4,State UNKNOWN Secure only 4" "0,1"
|
|
bitfld.long 0x4 8. "SU4,State UNKNOWN 4" "0,1"
|
|
bitfld.long 0x4 7. "SUS3,State UNKNOWN Secure only 3" "0,1"
|
|
bitfld.long 0x4 6. "SU3,State UNKNOWN 3" "0,1"
|
|
bitfld.long 0x4 5. "SUS2,State UNKNOWN Secure only 2" "0,1"
|
|
bitfld.long 0x4 4. "SU2,State UNKNOWN 2" "0,1"
|
|
bitfld.long 0x4 3. "SUS1,State UNKNOWN Secure only 1" "0,1"
|
|
bitfld.long 0x4 2. "SU1,State UNKNOWN 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SUS0,State UNKNOWN Secure only 0" "0,1"
|
|
bitfld.long 0x4 0. "SU0,State UNKNOWN 0" "0,1"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "ICB_NS (Implementation Control Block (Non-secure))"
|
|
base ad:0xE002E000
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "ICTR,Interrupt Controller Type Register"
|
|
hexmask.long.byte 0x0 0.--3. 1. "INTLINESNUM,Interrupt line set number"
|
|
group.long 0x8++0x7
|
|
line.long 0x0 "ACTLR,Auxiliary Control Register"
|
|
line.long 0x4 "CPPWR,Coprocessor Power Control Register"
|
|
bitfld.long 0x4 23. "SUS11,State UNKNOWN Secure only 11" "0,1"
|
|
bitfld.long 0x4 22. "SU11,State UNKNOWN 11" "0,1"
|
|
bitfld.long 0x4 21. "SUS10,State UNKNOWN Secure only 10" "0,1"
|
|
bitfld.long 0x4 20. "SU10,State UNKNOWN 10" "0,1"
|
|
bitfld.long 0x4 15. "SUS7,State UNKNOWN Secure only 7" "0,1"
|
|
bitfld.long 0x4 14. "SU7,State UNKNOWN 7" "0,1"
|
|
bitfld.long 0x4 13. "SUS6,State UNKNOWN Secure only 6" "0,1"
|
|
bitfld.long 0x4 12. "SU6,State UNKNOWN 6" "0,1"
|
|
bitfld.long 0x4 11. "SUS5,State UNKNOWN Secure only 5" "0,1"
|
|
newline
|
|
bitfld.long 0x4 10. "SU5,State UNKNOWN 5" "0,1"
|
|
bitfld.long 0x4 9. "SUS4,State UNKNOWN Secure only 4" "0,1"
|
|
bitfld.long 0x4 8. "SU4,State UNKNOWN 4" "0,1"
|
|
bitfld.long 0x4 7. "SUS3,State UNKNOWN Secure only 3" "0,1"
|
|
bitfld.long 0x4 6. "SU3,State UNKNOWN 3" "0,1"
|
|
bitfld.long 0x4 5. "SUS2,State UNKNOWN Secure only 2" "0,1"
|
|
bitfld.long 0x4 4. "SU2,State UNKNOWN 2" "0,1"
|
|
bitfld.long 0x4 3. "SUS1,State UNKNOWN Secure only 1" "0,1"
|
|
bitfld.long 0x4 2. "SU1,State UNKNOWN 1" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "SUS0,State UNKNOWN Secure only 0" "0,1"
|
|
bitfld.long 0x4 0. "SU0,State UNKNOWN 0" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "IDAU (Implementation Defined Attribution Unit)"
|
|
base ad:0x4480C000
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long.word 0x0 16.--31. 1. "CMD,Command Register"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "STATUSA,Status A"
|
|
hexmask.long.word 0x0 8.--16. 1. "NBRG,Number Of IDAU Regions"
|
|
bitfld.long 0x0 1. "WLCK,Write Lock" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,Enable" "0,1"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "STATUSB,Status B"
|
|
bitfld.long 0x0 0. "CFGERR,Configuration Error" "0,1"
|
|
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF)(list ad:0x4480D000 ad:0x4480D010 ad:0x4480D020 ad:0x4480D030 ad:0x4480D040 ad:0x4480D050 ad:0x4480D060 ad:0x4480D070 ad:0x4480D080 ad:0x4480D090 ad:0x4480D0A0 ad:0x4480D0B0 ad:0x4480D0C0 ad:0x4480D0D0 ad:0x4480D0E0 ad:0x4480D0F0)
|
|
tree "REGIONS[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "RCTRL_BLOCK_MODE,Region Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CMD,Command"
|
|
hexmask.long.byte 0x0 0.--4. 1. "ARG,Command Argument (Block ID)"
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "RCTRL_WATERMARK_MODE,Region Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CMD,Command"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "ARG,Command Argument (Watermark)"
|
|
rgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RSTATUSA,Region Status A"
|
|
hexmask.long.byte 0x0 16.--21. 1. "MAXSZ,Command Argument Maximum Size"
|
|
hexmask.long.byte 0x0 8.--13. 1. "GRAN,Region Granularity"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TYPE,IDAU Region Type"
|
|
line.long 0x4 "RSTATUSB_BLOCK_MODE,Region Status B"
|
|
hexmask.long 0x4 0.--31. 1. "NONSEC,Block Based Region Non-Secure State"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "RSTATUSB_WATERMARK_MODE,Region Status B"
|
|
hexmask.long 0x0 0.--31. 1. "SIZE,Watermark Based Region Size in Bytes"
|
|
line.long 0x4 "RSTATUSC_BLOCK_MODE,Region Status C"
|
|
hexmask.long 0x4 0.--31. 1. "CST,Constant Block Configuration"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "RSTATUSC_LINK_MODE,Region Status C"
|
|
hexmask.long.byte 0x0 8.--12. 1. "BLK,Linked IDAU Region Block ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RGN,Linked IDAU Region ID"
|
|
tree.end
|
|
repeat.end
|
|
repeat 8. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17)(list ad:0x4480D100 ad:0x4480D110 ad:0x4480D120 ad:0x4480D130 ad:0x4480D140 ad:0x4480D150 ad:0x4480D160 ad:0x4480D170)
|
|
tree "REGIONS[$1]"
|
|
base $2
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "RCTRL_BLOCK_MODE,Region Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CMD,Command"
|
|
hexmask.long.byte 0x0 0.--4. 1. "ARG,Command Argument (Block ID)"
|
|
wgroup.long ($2)++0x3
|
|
line.long 0x0 "RCTRL_WATERMARK_MODE,Region Control"
|
|
hexmask.long.byte 0x0 24.--31. 1. "CMD,Command"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "ARG,Command Argument (Watermark)"
|
|
rgroup.long ($2+0x4)++0x7
|
|
line.long 0x0 "RSTATUSA,Region Status A"
|
|
hexmask.long.byte 0x0 16.--21. 1. "MAXSZ,Command Argument Maximum Size"
|
|
hexmask.long.byte 0x0 8.--13. 1. "GRAN,Region Granularity"
|
|
hexmask.long.byte 0x0 0.--3. 1. "TYPE,IDAU Region Type"
|
|
line.long 0x4 "RSTATUSB_BLOCK_MODE,Region Status B"
|
|
hexmask.long 0x4 0.--31. 1. "NONSEC,Block Based Region Non-Secure State"
|
|
rgroup.long ($2+0x8)++0x7
|
|
line.long 0x0 "RSTATUSB_WATERMARK_MODE,Region Status B"
|
|
hexmask.long 0x0 0.--31. 1. "SIZE,Watermark Based Region Size in Bytes"
|
|
line.long 0x4 "RSTATUSC_BLOCK_MODE,Region Status C"
|
|
hexmask.long 0x4 0.--31. 1. "CST,Constant Block Configuration"
|
|
rgroup.long ($2+0xC)++0x3
|
|
line.long 0x0 "RSTATUSC_LINK_MODE,Region Status C"
|
|
hexmask.long.byte 0x0 8.--12. 1. "BLK,Linked IDAU Region Block ID"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RGN,Linked IDAU Region ID"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "ITM (Instrumentation Trace Macrocell)"
|
|
base ad:0xE0000000
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "STIM[$1],ITM Stimulus Port Register n"
|
|
bitfld.long 0x0 1. "DISABLED,Stimulus port enabled" "0,1"
|
|
bitfld.long 0x0 0. "FIFOREADY,Stimulus port can accept data" "0,1"
|
|
repeat.end
|
|
repeat 256. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "STIM_WRITE_MODE[$1],ITM Stimulus Port Register n"
|
|
hexmask.long 0x0 0.--31. 1. "STIMULUS,Stimulus data"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xE00)++0x3
|
|
line.long 0x0 "TER[$1],ITM Trace Enable Register n"
|
|
bitfld.long 0x0 31. "STIMENA31,Stimulus port 31 enabled" "0,1"
|
|
bitfld.long 0x0 30. "STIMENA30,Stimulus port 30 enabled" "0,1"
|
|
bitfld.long 0x0 29. "STIMENA29,Stimulus port 29 enabled" "0,1"
|
|
bitfld.long 0x0 28. "STIMENA28,Stimulus port 28 enabled" "0,1"
|
|
bitfld.long 0x0 27. "STIMENA27,Stimulus port 27 enabled" "0,1"
|
|
bitfld.long 0x0 26. "STIMENA26,Stimulus port 26 enabled" "0,1"
|
|
bitfld.long 0x0 25. "STIMENA25,Stimulus port 25 enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "STIMENA24,Stimulus port 24 enabled" "0,1"
|
|
bitfld.long 0x0 23. "STIMENA23,Stimulus port 23 enabled" "0,1"
|
|
bitfld.long 0x0 22. "STIMENA22,Stimulus port 22 enabled" "0,1"
|
|
bitfld.long 0x0 21. "STIMENA21,Stimulus port 21 enabled" "0,1"
|
|
bitfld.long 0x0 20. "STIMENA20,Stimulus port 20 enabled" "0,1"
|
|
bitfld.long 0x0 19. "STIMENA19,Stimulus port 19 enabled" "0,1"
|
|
bitfld.long 0x0 18. "STIMENA18,Stimulus port 18 enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "STIMENA17,Stimulus port 17 enabled" "0,1"
|
|
bitfld.long 0x0 16. "STIMENA16,Stimulus port 16 enabled" "0,1"
|
|
bitfld.long 0x0 15. "STIMENA15,Stimulus port 15 enabled" "0,1"
|
|
bitfld.long 0x0 14. "STIMENA14,Stimulus port 14 enabled" "0,1"
|
|
bitfld.long 0x0 13. "STIMENA13,Stimulus port 13 enabled" "0,1"
|
|
bitfld.long 0x0 12. "STIMENA12,Stimulus port 12 enabled" "0,1"
|
|
bitfld.long 0x0 11. "STIMENA11,Stimulus port 11 enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "STIMENA10,Stimulus port 10 enabled" "0,1"
|
|
bitfld.long 0x0 9. "STIMENA9,Stimulus port 9 enabled" "0,1"
|
|
bitfld.long 0x0 8. "STIMENA8,Stimulus port 8 enabled" "0,1"
|
|
bitfld.long 0x0 7. "STIMENA7,Stimulus port 7 enabled" "0,1"
|
|
bitfld.long 0x0 6. "STIMENA6,Stimulus port 6 enabled" "0,1"
|
|
bitfld.long 0x0 5. "STIMENA5,Stimulus port 5 enabled" "0,1"
|
|
bitfld.long 0x0 4. "STIMENA4,Stimulus port 4 enabled" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STIMENA3,Stimulus port 3 enabled" "0,1"
|
|
bitfld.long 0x0 2. "STIMENA2,Stimulus port 2 enabled" "0,1"
|
|
bitfld.long 0x0 1. "STIMENA1,Stimulus port 1 enabled" "0,1"
|
|
bitfld.long 0x0 0. "STIMENA0,Stimulus port 0 enabled" "0,1"
|
|
repeat.end
|
|
group.long 0xE40++0x3
|
|
line.long 0x0 "TPR,ITM Trace Privilege Register"
|
|
bitfld.long 0x0 31. "PRIVMASK31,Privilege mask for stimulus port byte 31" "0,1"
|
|
bitfld.long 0x0 30. "PRIVMASK30,Privilege mask for stimulus port byte 30" "0,1"
|
|
bitfld.long 0x0 29. "PRIVMASK29,Privilege mask for stimulus port byte 29" "0,1"
|
|
bitfld.long 0x0 28. "PRIVMASK28,Privilege mask for stimulus port byte 28" "0,1"
|
|
bitfld.long 0x0 27. "PRIVMASK27,Privilege mask for stimulus port byte 27" "0,1"
|
|
bitfld.long 0x0 26. "PRIVMASK26,Privilege mask for stimulus port byte 26" "0,1"
|
|
bitfld.long 0x0 25. "PRIVMASK25,Privilege mask for stimulus port byte 25" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24. "PRIVMASK24,Privilege mask for stimulus port byte 24" "0,1"
|
|
bitfld.long 0x0 23. "PRIVMASK23,Privilege mask for stimulus port byte 23" "0,1"
|
|
bitfld.long 0x0 22. "PRIVMASK22,Privilege mask for stimulus port byte 22" "0,1"
|
|
bitfld.long 0x0 21. "PRIVMASK21,Privilege mask for stimulus port byte 21" "0,1"
|
|
bitfld.long 0x0 20. "PRIVMASK20,Privilege mask for stimulus port byte 20" "0,1"
|
|
bitfld.long 0x0 19. "PRIVMASK19,Privilege mask for stimulus port byte 19" "0,1"
|
|
bitfld.long 0x0 18. "PRIVMASK18,Privilege mask for stimulus port byte 18" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PRIVMASK17,Privilege mask for stimulus port byte 17" "0,1"
|
|
bitfld.long 0x0 16. "PRIVMASK16,Privilege mask for stimulus port byte 16" "0,1"
|
|
bitfld.long 0x0 15. "PRIVMASK15,Privilege mask for stimulus port byte 15" "0,1"
|
|
bitfld.long 0x0 14. "PRIVMASK14,Privilege mask for stimulus port byte 14" "0,1"
|
|
bitfld.long 0x0 13. "PRIVMASK13,Privilege mask for stimulus port byte 13" "0,1"
|
|
bitfld.long 0x0 12. "PRIVMASK12,Privilege mask for stimulus port byte 12" "0,1"
|
|
bitfld.long 0x0 11. "PRIVMASK11,Privilege mask for stimulus port byte 11" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "PRIVMASK10,Privilege mask for stimulus port byte 10" "0,1"
|
|
bitfld.long 0x0 9. "PRIVMASK9,Privilege mask for stimulus port byte 9" "0,1"
|
|
bitfld.long 0x0 8. "PRIVMASK8,Privilege mask for stimulus port byte 8" "0,1"
|
|
bitfld.long 0x0 7. "PRIVMASK7,Privilege mask for stimulus port byte 7" "0,1"
|
|
bitfld.long 0x0 6. "PRIVMASK6,Privilege mask for stimulus port byte 6" "0,1"
|
|
bitfld.long 0x0 5. "PRIVMASK5,Privilege mask for stimulus port byte 5" "0,1"
|
|
bitfld.long 0x0 4. "PRIVMASK4,Privilege mask for stimulus port byte 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PRIVMASK3,Privilege mask for stimulus port byte 3" "0,1"
|
|
bitfld.long 0x0 2. "PRIVMASK2,Privilege mask for stimulus port byte 2" "0,1"
|
|
bitfld.long 0x0 1. "PRIVMASK1,Privilege mask for stimulus port byte 1" "0,1"
|
|
bitfld.long 0x0 0. "PRIVMASK0,Privilege mask for stimulus port byte 0" "0,1"
|
|
group.long 0xE80++0x3
|
|
line.long 0x0 "TCR,ITM Trace Control Register"
|
|
bitfld.long 0x0 23. "BUSY,ITM busy" "0,1"
|
|
hexmask.long.byte 0x0 16.--22. 1. "TraceBusID,Trace bus identity"
|
|
bitfld.long 0x0 10.--11. "GTSFREQ,Global timestamp frequency" "0,1,2,3"
|
|
bitfld.long 0x0 8.--9. "TSPrescale,Timestamp prescale" "0,1,2,3"
|
|
bitfld.long 0x0 5. "STALLENA,Stall enable" "0,1"
|
|
bitfld.long 0x0 4. "SWOENA,SWO enable" "0,1"
|
|
bitfld.long 0x0 3. "TXENA,Transmit enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "SYNCENA,Synchronization enable" "0,1"
|
|
bitfld.long 0x0 1. "TSENA,Timestamp enable" "0,1"
|
|
bitfld.long 0x0 0. "ITMENA,ITM enable" "0,1"
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "LAR,ITM Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0xFB4++0x3
|
|
line.long 0x0 "LSR,ITM Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
rgroup.long 0xFBC++0x3
|
|
line.long 0x0 "DEVARCH,ITM Device Architecture Register"
|
|
hexmask.long.word 0x0 21.--31. 1. "ARCHITECT,Architect"
|
|
bitfld.long 0x0 20. "PRESENT,DEVARCH Present" "0,1"
|
|
hexmask.long.byte 0x0 16.--19. 1. "REVISION,Revision"
|
|
hexmask.long.byte 0x0 12.--15. 1. "ARCHVER,Architecture Version"
|
|
hexmask.long.word 0x0 0.--11. 1. "ARCHPART,Architecture Part"
|
|
rgroup.long 0xFCC++0x33
|
|
line.long 0x0 "DEVTYPE,ITM Device Type Register"
|
|
hexmask.long.byte 0x0 4.--7. 1. "SUB,Sub-type"
|
|
hexmask.long.byte 0x0 0.--3. 1. "MAJOR,Major type"
|
|
line.long 0x4 "PIDR4,ITM Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x4 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0x8 "PIDR5,ITM Peripheral Identification Register 5"
|
|
line.long 0xC "PIDR6,ITM Peripheral Identification Register 6"
|
|
line.long 0x10 "PIDR7,ITM Peripheral Identification Register 7"
|
|
line.long 0x14 "PIDR0,ITM Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x18 "PIDR1,ITM Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x18 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x18 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x1C "PIDR2,ITM Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x1C 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x1C 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x20 "PIDR3,ITM Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x20 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x24 "CIDR0,ITM Component Identification Register 0"
|
|
hexmask.long.byte 0x24 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x28 "CIDR1,ITM Component Identification Register 1"
|
|
hexmask.long.byte 0x28 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x28 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x2C "CIDR2,ITM Component Identification Register 2"
|
|
hexmask.long.byte 0x2C 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x30 "CIDR3,ITM Component Identification Register 3"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
tree "MCLK (Main Clock)"
|
|
base ad:0x44012000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "CKRDY,Clock Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "CKRDY,Clock Ready Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "CKRDY,Clock Ready" "0,1"
|
|
line.long 0xC "CLKDIV,Clock Divider Control"
|
|
hexmask.long.byte 0xC 0.--7. 1. "DIV,Clock Domain Division Factor"
|
|
repeat 9. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x3C)++0x3
|
|
line.long 0x0 "CLKMSK[$1],Peripheral Clock Enable Mask"
|
|
hexmask.long 0x0 0.--31. 1. "MASK,Peripheral Clock Enable Mask"
|
|
repeat.end
|
|
tree.end
|
|
tree "MPU (Memory Protection Unit)"
|
|
base ad:0xE000ED90
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TYPE,MPU Type Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DREGION,Number of MPU data regions"
|
|
bitfld.long 0x0 0. "SEPARATE,Separate instructions and data address regions" "0,1"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "CTRL,MPU Control Register"
|
|
bitfld.long 0x0 2. "PRIVDEFENA,Privileged default enable" "0,1"
|
|
bitfld.long 0x0 1. "HFNMIENA,HardFault NMI enable" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,MPU enable" "0,1"
|
|
line.long 0x4 "RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REGION,Selected region number"
|
|
line.long 0x8 "RBAR,MPU Region Base Address Register"
|
|
hexmask.long 0x8 5.--31. 1. "BASE,Base address"
|
|
bitfld.long 0x8 3.--4. "SH,Shareability" "0: Non-shareable,?,2: Outer shareable,3: Inner shareable"
|
|
bitfld.long 0x8 1.--2. "AP,Access permissions" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
|
|
bitfld.long 0x8 0. "XN,Execute Never" "0,1"
|
|
line.long 0xC "RLAR,MPU Region Limit Address Register"
|
|
hexmask.long 0xC 5.--31. 1. "LIMIT,Limit address"
|
|
bitfld.long 0xC 1.--3. "AttrInd,Attribute Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0. "EN,Region enable" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x14)++0x3
|
|
line.long 0x0 "RBAR_A[$1],MPU Region Base Address Register Alias x"
|
|
hexmask.long 0x0 5.--31. 1. "BASE,Base address"
|
|
bitfld.long 0x0 3.--4. "SH,Shareability" "0: Non-shareable,?,2: Outer shareable,3: Inner shareable"
|
|
bitfld.long 0x0 1.--2. "AP,Access permissions" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
|
|
bitfld.long 0x0 0. "XN,Execute Never" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "RLAR_A[$1],MPU Region Limit Address Register Alias x"
|
|
hexmask.long 0x0 5.--31. 1. "LIMIT,Limit address"
|
|
bitfld.long 0x0 1.--3. "AttrInd,Attribute Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,Region enable" "0,1"
|
|
repeat.end
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "Attr3,Attribute of MPU region 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "Attr2,Attribute of MPU region 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Attr1,Attribute of MPU region 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "Attr0,Attribute of MPU region 0"
|
|
line.long 0x4 "MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "Attr7,Attribute of MPU region 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "Attr6,Attribute of MPU region 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. "Attr5,Attribute of MPU region 5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "Attr4,Attribute of MPU region 4"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "MPU_NS (Memory Protection Unit (Non-Secure))"
|
|
base ad:0xE002ED90
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "TYPE,MPU Type Register"
|
|
hexmask.long.byte 0x0 8.--15. 1. "DREGION,Number of MPU data regions"
|
|
bitfld.long 0x0 0. "SEPARATE,Separate instructions and data address regions" "0,1"
|
|
group.long 0x4++0xF
|
|
line.long 0x0 "CTRL,MPU Control Register"
|
|
bitfld.long 0x0 2. "PRIVDEFENA,Privileged default enable" "0,1"
|
|
bitfld.long 0x0 1. "HFNMIENA,HardFault NMI enable" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,MPU enable" "0,1"
|
|
line.long 0x4 "RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "REGION,Selected region number"
|
|
line.long 0x8 "RBAR,MPU Region Base Address Register"
|
|
hexmask.long 0x8 5.--31. 1. "BASE,Base address"
|
|
bitfld.long 0x8 3.--4. "SH,Shareability" "0: Non-shareable,?,2: Outer shareable,3: Inner shareable"
|
|
bitfld.long 0x8 1.--2. "AP,Access permissions" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
|
|
bitfld.long 0x8 0. "XN,Execute Never" "0,1"
|
|
line.long 0xC "RLAR,MPU Region Limit Address Register"
|
|
hexmask.long 0xC 5.--31. 1. "LIMIT,Limit address"
|
|
bitfld.long 0xC 1.--3. "AttrInd,Attribute Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0xC 0. "EN,Region enable" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x14)++0x3
|
|
line.long 0x0 "RBAR_A[$1],MPU Region Base Address Register Alias x"
|
|
hexmask.long 0x0 5.--31. 1. "BASE,Base address"
|
|
bitfld.long 0x0 3.--4. "SH,Shareability" "0: Non-shareable,?,2: Outer shareable,3: Inner shareable"
|
|
bitfld.long 0x0 1.--2. "AP,Access permissions" "0: Read/write by privileged code only,1: Read/write by any privilege level,2: Read-only by privileged code only,3: Read-only by any privilege level"
|
|
bitfld.long 0x0 0. "XN,Execute Never" "0,1"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x18)++0x3
|
|
line.long 0x0 "RLAR_A[$1],MPU Region Limit Address Register Alias x"
|
|
hexmask.long 0x0 5.--31. 1. "LIMIT,Limit address"
|
|
bitfld.long 0x0 1.--3. "AttrInd,Attribute Index" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "EN,Region enable" "0,1"
|
|
repeat.end
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x0 24.--31. 1. "Attr3,Attribute of MPU region 3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "Attr2,Attribute of MPU region 2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "Attr1,Attribute of MPU region 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "Attr0,Attribute of MPU region 0"
|
|
line.long 0x4 "MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x4 24.--31. 1. "Attr7,Attribute of MPU region 7"
|
|
hexmask.long.byte 0x4 16.--23. 1. "Attr6,Attribute of MPU region 6"
|
|
hexmask.long.byte 0x4 8.--15. 1. "Attr5,Attribute of MPU region 5"
|
|
hexmask.long.byte 0x4 0.--7. 1. "Attr4,Attribute of MPU region 4"
|
|
tree.end
|
|
endif
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "ISER[$1],Interrupt Set Enable Register n"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Set enable"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "ICER[$1],Interrupt Clear Enable Register n"
|
|
hexmask.long 0x0 0.--31. 1. "CLRENA,Clear enable"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "ISPR[$1],Interrupt Set Pending Register n"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Set pending"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x180)++0x3
|
|
line.long 0x0 "ICPR[$1],Interrupt Clear Pending Register n"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear pending"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x200)++0x3
|
|
line.long 0x0 "IABR[$1],Interrupt Active Bit Register n"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Active state"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "ITNS[$1],Interrupt Target Non-secure Register n"
|
|
hexmask.long 0x0 0.--31. 1. "ITNS,Interrupt Targets Non-secure"
|
|
repeat.end
|
|
repeat 40. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "IPR[$1],Interrupt Priority Register n"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PRI_N3,Priority of interrupt number 4n+3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PRI_N2,Priority of interrupt number 4n+2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRI_N1,Priority of interrupt number 4n+1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PRI_N0,Priority of interrupt number 4n+0"
|
|
repeat.end
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "NVIC_NS (Nested Vectored Interrupt Controller (Non-Secure))"
|
|
base ad:0xE002E100
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "ISER[$1],Interrupt Set Enable Register n"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Set enable"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x80)++0x3
|
|
line.long 0x0 "ICER[$1],Interrupt Clear Enable Register n"
|
|
hexmask.long 0x0 0.--31. 1. "CLRENA,Clear enable"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "ISPR[$1],Interrupt Set Pending Register n"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Set pending"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x180)++0x3
|
|
line.long 0x0 "ICPR[$1],Interrupt Clear Pending Register n"
|
|
hexmask.long 0x0 0.--31. 1. "CLRPEND,Clear pending"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x200)++0x3
|
|
line.long 0x0 "IABR[$1],Interrupt Active Bit Register n"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Active state"
|
|
repeat.end
|
|
repeat 5. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x280)++0x3
|
|
line.long 0x0 "ITNS[$1],Interrupt Target Non-secure Register n"
|
|
hexmask.long 0x0 0.--31. 1. "ITNS,Interrupt Targets Non-secure"
|
|
repeat.end
|
|
repeat 40. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "IPR[$1],Interrupt Priority Register n"
|
|
hexmask.long.byte 0x0 24.--31. 1. "PRI_N3,Priority of interrupt number 4n+3"
|
|
hexmask.long.byte 0x0 16.--23. 1. "PRI_N2,Priority of interrupt number 4n+2"
|
|
hexmask.long.byte 0x0 8.--15. 1. "PRI_N1,Priority of interrupt number 4n+1"
|
|
hexmask.long.byte 0x0 0.--7. 1. "PRI_N0,Priority of interrupt number 4n+0"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "OSC32KCTRL (32kHz Oscillators Controller)"
|
|
base ad:0x4400E000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 2. "XOSC32KFAIL,XOSC32K Clock Failure Detector Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "XOSC32KRDY,XOSC32K Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 2. "XOSC32KFAIL,XOSC32K Clock Failure Detector Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "XOSC32KRDY,XOSC32K Ready Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 2. "XOSC32KFAIL,XOSC32K Clock Failure Detector" "0,1"
|
|
bitfld.long 0x8 0. "XOSC32KRDY,XOSC32K Ready" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "STATUS,Power and Clocks Status"
|
|
bitfld.long 0x0 3. "XOSC32KSW,XOSC32K Clock switch" "0,1"
|
|
bitfld.long 0x0 2. "XOSC32KFAIL,XOSC32K Clock Failure Detector" "0,1"
|
|
bitfld.long 0x0 0. "XOSC32KRDY,XOSC32K Ready" "0,1"
|
|
group.long 0x10++0xF
|
|
line.long 0x0 "CLKSELCTRL,Clock Selection Control"
|
|
bitfld.long 0x0 4.--5. "HSMSEL,HSM Clock Selection" "0: 32.768kHz from 32kHz internal ULP oscillator,?,2: 32.768kHz from 32.768kHz external crystal..,?"
|
|
bitfld.long 0x0 0.--1. "RTCSEL,RTC Clock Selection" "0: 32.768kHz from 32kHz internal ULP oscillator,1: 1.024kHz from 32kHz internal ULP oscillator,2: 32.768kHz from 32.768kHz external crystal..,3: 1.024kHz from 32.768kHz internal oscillator"
|
|
line.long 0x4 "CFDCTRL,Clock Failure Detector Control"
|
|
bitfld.long 0x4 2. "CFDPRESC,Clock Failure Detector Prescaler" "0,1"
|
|
bitfld.long 0x4 1. "SWBACK,Clock Switch Back" "0,1"
|
|
bitfld.long 0x4 0. "CFDEN,Clock Failure Detector Enable" "0,1"
|
|
line.long 0x8 "EVCTRL,Event Control"
|
|
bitfld.long 0x8 0. "CFDEO,Clock Failure Detector Event Output Enable" "0,1"
|
|
line.long 0xC "XOSC32K,32kHz External Crystal Oscillator (XOSC32K) Control"
|
|
hexmask.long.byte 0xC 24.--27. 1. "CTRLX,Extended Control"
|
|
hexmask.long.byte 0xC 18.--21. 1. "CGM,Control Gain Mode"
|
|
bitfld.long 0xC 17. "BOOST,Gain Boost" "0,1"
|
|
newline
|
|
bitfld.long 0xC 16. "ENSL,Enable Servo Loop" "0,1"
|
|
hexmask.long.byte 0xC 8.--11. 1. "STARTUP,Startup Mode"
|
|
bitfld.long 0xC 7. "ONDEMAND,On Demand Mode" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "XTALEN,Crystal Oscillator Enable" "0,1"
|
|
bitfld.long 0xC 1. "ENABLE,Oscillator Enable" "0,1"
|
|
tree.end
|
|
tree "OSCCTRL (Oscillators Controller)"
|
|
base ad:0x4400C000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 0. "CFDEO,Clock Failure Detector Event Output Enable" "0,1"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 25. "PLL0LOCKF,PLL 0 Lock Fall Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 24. "PLL0LOCKR,PLL 0 Lock Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 13. "DFLLFAIL,DFLL Startup Failure Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 12. "DFLLRCS,DFLL Reference Clock Stopped Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 11. "DFLLUNF,DFLL Tuner Underflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "DFLLOVF,DFLL Tuner Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "DFLLLOCK,DFLL Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 8. "DFLLRDY,DFLL Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CLKFAIL,XOSC Clock Failure Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "XOSCFAIL,XOSC Startup Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "XOSCRDY,XOSC Ready Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 25. "PLL0LOCKF,PLL 0 Lock Fall Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 24. "PLL0LOCKR,PLL 0 Lock Rise Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 13. "DFLLFAIL,DFLL Startup Failure Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 12. "DFLLRCS,DFLL Reference Clock Stopped Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 11. "DFLLUNF,DFLL Tuner Underflow Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "DFLLOVF,DFLL Tuner Overflow Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DFLLLOCK,DFLL Lock Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 8. "DFLLRDY,DFLL Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CLKFAIL,XOSC Clock Failure Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "XOSCFAIL,XOSC Startup Failure Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "XOSCRDY,XOSC Ready Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 25. "PLL0LOCKF,PLL 0 Lock Fall" "0,1"
|
|
bitfld.long 0xC 24. "PLL0LOCKR,PLL 0 Lock Rise" "0,1"
|
|
bitfld.long 0xC 13. "DFLLFAIL,DFLL Startup Failure" "0,1"
|
|
newline
|
|
bitfld.long 0xC 12. "DFLLRCS,DFLL Reference Clock Stopped" "0,1"
|
|
bitfld.long 0xC 11. "DFLLUNF,DFLL Tuner Underflow" "0,1"
|
|
bitfld.long 0xC 10. "DFLLOVF,DFLL Tuner Overflow" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "DFLLLOCK,DFLL Lock" "0,1"
|
|
bitfld.long 0xC 8. "DFLLRDY,DFLL Ready" "0,1"
|
|
bitfld.long 0xC 2. "CLKFAIL,XOSC Clock Failure" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "XOSCFAIL,XOSC Startup Failure" "0,1"
|
|
bitfld.long 0xC 0. "XOSCRDY,XOSC Ready" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 24. "PLL0LOCK,PLL 0 Lock" "0,1"
|
|
bitfld.long 0x0 13. "DFLLFAIL,DFLL Startup Failure" "0,1"
|
|
bitfld.long 0x0 12. "DFLLRCS,DFLL Reference Clock Stopped" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "DFLLUNF,DFLL Tuner Underflow" "0,1"
|
|
bitfld.long 0x0 10. "DFLLOVF,DFLL Tuner Overflow" "0,1"
|
|
bitfld.long 0x0 9. "DFLLLOCK,DFLL Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "DFLLRDY,DFLL Ready" "0,1"
|
|
bitfld.long 0x0 3. "XOSCCKSW,XOSC Clock Switch" "0,1"
|
|
bitfld.long 0x0 2. "CLKFAIL,XOSC Clock Failure" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "XOSCFAIL,XOSC Startup Failure" "0,1"
|
|
bitfld.long 0x0 0. "XOSCRDY,XOSC Ready" "0,1"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "XOSCCTRLA,External Multipurpose Crystal Oscillator Control A"
|
|
bitfld.long 0x0 31. "WRTLOCK,Write Lock for CTRLA register" "0,1"
|
|
bitfld.long 0x0 24.--25. "USBHSDIV,USBHS Referrence Clock Division" "0: USBHS PLL reference XOSC clock is disabled,1: USBHS PLL reference XOSC clock is divided by 1,2: USBHS PLL reference XOSC clock is divided by 2,3: USBHS PLL reference XOSC clock is divided by 4"
|
|
hexmask.long.byte 0x0 16.--19. 1. "CFDPRESC,Clock Failure Detector Prescaler"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--11. 1. "STARTUP,Start-Up Time"
|
|
bitfld.long 0x0 7. "ONDEMAND,On Demand Control" "0,1"
|
|
bitfld.long 0x0 5. "SWBEN,Xosc Clock Switch Back Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "CFDEN,Clock Failure Detector Enable" "0,1"
|
|
bitfld.long 0x0 3. "XTALEN,Crystal Oscillator Enable" "0,1"
|
|
bitfld.long 0x0 2. "AGC,Auto Gain Control Loop Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Oscillator Enable" "0,1"
|
|
line.long 0x4 "XOSCCTRLB,External Multipurpose Crystal Oscillator Control B"
|
|
bitfld.long 0x4 31. "WRTLOCK,Write Lock for CTRLB register" "0,1"
|
|
hexmask.long.byte 0x4 0.--7. 1. "USRCFG,User Configuration Control Bits"
|
|
group.long 0x2C++0xB
|
|
line.long 0x0 "DFLLCTRLA,DFLL48M Control A"
|
|
bitfld.long 0x0 7. "ONDEMAND,On Demand Control" "0,1"
|
|
bitfld.long 0x0 3. "LOWFREQ,Low Frequency Mode" "0,1"
|
|
bitfld.long 0x0 2. "WRTLOCK,Write Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,DFLL Enable" "0,1"
|
|
line.long 0x4 "DFLLCTRLB,DFLL48M Control B"
|
|
bitfld.long 0x4 7. "WAITLOCK,Wait Lock" "0,1"
|
|
bitfld.long 0x4 5. "QLDIS,Quick Lock Disable" "0,1"
|
|
bitfld.long 0x4 4. "CCDIS,Chill Cycle Disable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "USBCRM,USB Clock Recovery Mode" "0,1"
|
|
bitfld.long 0x4 2. "LLAW,Lose Lock After Wake" "0,1"
|
|
bitfld.long 0x4 1. "STABLE,Stable DFLL Frequency" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LOOPEN,Operating Mode Selection" "0,1"
|
|
line.long 0x8 "DFLLTUNE,DFLL48M Tune"
|
|
hexmask.long.byte 0x8 0.--6. 1. "TUNE,Tune Value"
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x0 "DFLLDIFF,DFLL48M Diff"
|
|
hexmask.long.word 0x0 0.--15. 1. "DIFF,Multiplication Ratio Difference"
|
|
group.long 0x3C++0x17
|
|
line.long 0x0 "DFLLMUL,DFLL48M Multiplier"
|
|
hexmask.long.byte 0x0 16.--22. 1. "STEP,Tune Maximum Step"
|
|
hexmask.long.word 0x0 0.--15. 1. "MUL,DFLL Multiply Factor"
|
|
line.long 0x4 "PLL0CTRL,PLL Control"
|
|
bitfld.long 0x4 11.--13. "BWSEL,Bandwidth selection" "0: TBD,1: TBD,2: TBD,3: TBD,4: TBD,5: TBD,6: TBD,7: TBD"
|
|
bitfld.long 0x4 8.--10. "REFSEL,Reference selection" "0: Dedicated GCLK clock reference,1: XOSC clock reference,2: DFLL48M clock reference,?,?,?,?,?"
|
|
bitfld.long 0x4 7. "ONDEMAND,On Demand Control" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "WRTLOCK,Write Lock" "0,1"
|
|
bitfld.long 0x4 1. "ENABLE,PLL Enable" "0,1"
|
|
line.long 0x8 "PLL0FBDIV,PLL Feed-Back Divider"
|
|
hexmask.long.word 0x8 0.--9. 1. "FBDIV,PLL Feed-Back Divider Factor"
|
|
line.long 0xC "PLL0REFDIV,PLL reference divider"
|
|
hexmask.long.byte 0xC 0.--5. 1. "REFDIV,PLL reference division factor"
|
|
line.long 0x10 "PLL0POSTDIVA,PLL output clock divider A"
|
|
bitfld.long 0x10 31. "OUTEN3,PLL output 0 enable" "0,1"
|
|
hexmask.long.byte 0x10 24.--29. 1. "POSTDIV3,PLL output 0 clock division factor"
|
|
bitfld.long 0x10 23. "OUTEN2,PLL output 0 enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x10 16.--21. 1. "POSTDIV2,PLL output 0 clock division factor"
|
|
bitfld.long 0x10 15. "OUTEN1,PLL output 0 enable" "0,1"
|
|
hexmask.long.byte 0x10 8.--13. 1. "POSTDIV1,PLL output 0 clock division factor"
|
|
newline
|
|
bitfld.long 0x10 7. "OUTEN0,PLL output 0 enable" "0,1"
|
|
hexmask.long.byte 0x10 0.--5. 1. "POSTDIV0,PLL output 0 clock division factor"
|
|
line.long 0x14 "PLL0POSTDIVB,PLL output clock divider B"
|
|
bitfld.long 0x14 15. "OUTEN5,PLL output 4 enable" "0,1"
|
|
hexmask.long.byte 0x14 8.--13. 1. "POSTDIV5,PLL output 4 clock division factor"
|
|
bitfld.long 0x14 7. "OUTEN4,PLL output 4 enable" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x14 0.--5. 1. "POSTDIV4,PLL output 4 clock division factor"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "FRACDIV0,Fractional Divider"
|
|
hexmask.long.word 0x0 16.--30. 1. "INTDIV,Frequency division factor integer part"
|
|
hexmask.long.word 0x0 7.--15. 1. "REMDIV,Frequency division factor reminder part"
|
|
rgroup.long 0x78++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 7. "FRACDIV1,FRACDIV1 Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 6. "FRACDIV0,FRACDIV0 Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 5. "DFLLMUL,DFLLMUL Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "DFLLDIFF,DFLLDIFF Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "DFLLTUNE,DFLLTUNE Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "DFLLCTRLB,DFLLCTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "DFLLENABLE,DFLL48M ENABLE Synchronization Busy" "0,1"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "XOSCCAL,XOSC Calibration Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CAL,XOSC Calibration"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "XOSCCAL_FUSES_OSC_XTAL_HF_AGC_V2_MODE,XOSC Calibration Register"
|
|
hexmask.long.byte 0x0 10.--15. 1. "SPARES,Spare bits"
|
|
bitfld.long 0x0 9. "REDOSC,reduce oscillation debug counter" "0,1"
|
|
bitfld.long 0x0 8. "REDGAIN,reduce gain control timer" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "FLIPPOL,flip output clock polarity" "0,1"
|
|
bitfld.long 0x0 5. "CMSEL,clock buffer common mode selection" "0,1"
|
|
bitfld.long 0x0 4. "HYST,loop hysteresis control" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "ENVAMP,envelope amplitude at osci" "0,1"
|
|
bitfld.long 0x0 2. "KICKEREN,Kicker enable" "0,1"
|
|
bitfld.long 0x0 0.--1. "FTRANS,Fine Transconductance programmability for Oscillator" "0,1,2,3"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "RC48MCAL0,RC48M Calibration 0"
|
|
hexmask.long 0x0 0.--31. 1. "CAL,RC48M Calibration"
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "RC48MCAL0_FUSES_OSC_RC48MHZ_V1_MODE,RC48M Calibration 0"
|
|
bitfld.long 0x0 20.--22. "cmp_pwr_ctrl,Comparator power control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 19. "cmp_8m_lp,Comparator 8MHz low-power" "0,1"
|
|
bitfld.long 0x0 18. "ldo_vout_boost,LDO VOUT boost" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "out_buf_sel,Output buffer select" "0,1"
|
|
bitfld.long 0x0 16. "iosc_boost,IOSC boost" "0,1"
|
|
hexmask.long.byte 0x0 6.--13. 1. "proc_trim_mv,Proc trim value"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "temp_trim_mv,Temp trim value"
|
|
tree.end
|
|
tree "PAC (Peripheral Access Controller)"
|
|
base ad:0x4401C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "WRCTRL,Write control"
|
|
hexmask.long.byte 0x0 16.--23. 1. "KEY,Peripheral access control key"
|
|
hexmask.long.word 0x0 0.--15. 1. "PERID,Peripheral identifier"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "EVCTRL,Event control"
|
|
bitfld.byte 0x0 0. "ERREO,Peripheral acess error event output" "0,1"
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "INTENCLR,Interrupt enable clear"
|
|
bitfld.byte 0x0 0. "ERR,Peripheral access error interrupt disable" "0,1"
|
|
line.byte 0x1 "INTENSET,Interrupt enable set"
|
|
bitfld.byte 0x1 0. "ERR,Peripheral access error interrupt enable" "0,1"
|
|
group.long 0x10++0x13
|
|
line.long 0x0 "INTFLAGAHB,Bridge interrupt flag status"
|
|
line.long 0x4 "INTFLAGA,Peripheral interrupt flag status - Bridge A"
|
|
line.long 0x8 "INTFLAGB,Peripheral interrupt flag status - Bridge B"
|
|
line.long 0xC "INTFLAGC,Peripheral interrupt flag status - Bridge C"
|
|
line.long 0x10 "INTFLAGD,Peripheral interrupt flag status - Bridge D"
|
|
rgroup.long 0x34++0xF
|
|
line.long 0x0 "STATUSA,Peripheral write protection status - Bridge A"
|
|
line.long 0x4 "STATUSB,Peripheral write protection status - Bridge B"
|
|
line.long 0x8 "STATUSC,Peripheral write protection status - Bridge C"
|
|
line.long 0xC "STATUSD,Peripheral write protection status - Bridge D"
|
|
rgroup.long 0x54++0xF
|
|
line.long 0x0 "NONSECA,Peripheral Non-Secure Status - Bridge A"
|
|
line.long 0x4 "NONSECB,Peripheral Non-Secure Status - Bridge B"
|
|
line.long 0x8 "NONSECC,Peripheral Non-Secure Status - Bridge C"
|
|
line.long 0xC "NONSECD,Peripheral Non-Secure Status - Bridge D"
|
|
rgroup.long 0x74++0xF
|
|
line.long 0x0 "SECLOCKA,Peripheral Security Lock Status - Bridge A"
|
|
line.long 0x4 "SECLOCKB,Peripheral Security Lock Status - Bridge B"
|
|
line.long 0x8 "SECLOCKC,Peripheral Security Lock Status - Bridge C"
|
|
line.long 0xC "SECLOCKD,Peripheral Security Lock Status - Bridge D"
|
|
tree.end
|
|
tree "PCC (Parallel Capture Controller)"
|
|
base ad:0x45018000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "MR,Mode Register"
|
|
bitfld.long 0x0 30.--31. "CID,Clear If Disabled" "0,1,2,3"
|
|
bitfld.long 0x0 16.--18. "ISIZE,Input Data Size" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 11. "FRSTS,First sample" "0,1"
|
|
bitfld.long 0x0 10. "HALFS,Half Sampling" "0,1"
|
|
bitfld.long 0x0 9. "ALWYS,Always Sampling" "0,1"
|
|
bitfld.long 0x0 8. "SCALE,Scale data" "0,1"
|
|
bitfld.long 0x0 4.--5. "DSIZE,Data size" "0,1,2,3"
|
|
bitfld.long 0x0 0. "PCEN,Parallel Capture Enable" "0,1"
|
|
wgroup.long 0x4++0x7
|
|
line.long 0x0 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 0. "DRDY,Data Ready Interrupt Enable" "0,1"
|
|
line.long 0x4 "IDR,Interrupt Disable Register"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Disable" "0,1"
|
|
bitfld.long 0x4 0. "DRDY,Data Ready Interrupt Disable" "0,1"
|
|
rgroup.long 0xC++0xB
|
|
line.long 0x0 "IMR,Interrupt Mask Register"
|
|
bitfld.long 0x0 1. "OVRE,Overrun Error Interrupt Mask" "0,1"
|
|
bitfld.long 0x0 0. "DRDY,Data Ready Interrupt Mask" "0,1"
|
|
line.long 0x4 "ISR,Interrupt Status Register"
|
|
bitfld.long 0x4 1. "OVRE,Overrun Error Interrupt Status" "0,1"
|
|
bitfld.long 0x4 0. "DRDY,Data Ready Interrupt Status" "0,1"
|
|
line.long 0x8 "RHR,Reception Holding Register"
|
|
hexmask.long 0x8 0.--31. 1. "RDATA,Reception Data"
|
|
group.long 0xE0++0x3
|
|
line.long 0x0 "WPMR,Write Protection Mode Register"
|
|
hexmask.long.tbyte 0x0 8.--31. 1. "WPKEY,Write Protection Key"
|
|
bitfld.long 0x0 0. "WPEN,Write Protection Enable" "0,1"
|
|
rgroup.long 0xE4++0x3
|
|
line.long 0x0 "WPSR,Write Protection Status Register"
|
|
hexmask.long.word 0x0 8.--23. 1. "WPVSRC,Write Protection Violation Status"
|
|
bitfld.long 0x0 0. "WPVS,Write Protection Violation Source" "0,1"
|
|
tree.end
|
|
tree "PDEC (Position Decoder)"
|
|
base ad:0x4501C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
hexmask.long.byte 0x0 28.--31. 1. "MAXCMP,Maximum Consecutive Missing Pulses"
|
|
bitfld.long 0x0 24.--26. "ANGULAR,Angular Counter Length" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 22. "PINVEN2,IO Pin 2 Invert Enable" "0,1"
|
|
bitfld.long 0x0 21. "PINVEN1,IO Pin 1 Invert Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20. "PINVEN0,IO Pin 0 Invert Enable" "0,1"
|
|
bitfld.long 0x0 18. "PINEN2,PDEC Input From Pin 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "PINEN1,PDEC Input From Pin 1 Enable" "0,1"
|
|
bitfld.long 0x0 16. "PINEN0,PDEC Input From Pin 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "PEREN,Period Enable" "0,1"
|
|
bitfld.long 0x0 14. "SWAP,PDEC Phase A and B Swap" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "ALOCK,Auto Lock" "0,1"
|
|
bitfld.long 0x0 8.--10. "CONF,PDEC Configuration" "0: Quadrature decoder direction,1: Secure Quadrature decoder direction,2: Decoder direction,3: Secure decoder direction,4: Auto correction mode,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 6. "RUNSTDBY,Run in Standby" "0,1"
|
|
bitfld.long 0x0 2.--3. "MODE,Operation Mode" "0: QDEC operating mode,1: HALL operating mode,2: COUNTER operating mode,?"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,Command" "0: No action,1: Force a counter restart or retrigger,2: Force update of double buffered registers,3: Force a read synchronization of COUNT,4: Start QDEC/HALL,5: Stop QDEC/HALL,?,?"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,Command" "0: No action,1: Force a counter restart or retrigger,2: Force update of double buffered registers,3: Force a read synchronization of COUNT,4: Start QDEC/HALL,5: Stop QDEC/HALL,?,?"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "EVCTRL,Event Control"
|
|
bitfld.word 0x0 13. "MCEO1,Match Channel 1 Event Output Enable" "0,1"
|
|
bitfld.word 0x0 12. "MCEO0,Match Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "VLCEO,Velocity Output Event Enable" "0,1"
|
|
bitfld.word 0x0 10. "DIREO,Direction Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "ERREO,Error Output Event Enable" "0,1"
|
|
bitfld.word 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5.--7. "EVEI,Event Input Enable" "0,1,2,3,4,5,6,7"
|
|
bitfld.word 0x0 2.--4. "EVINV,Inverted Event Input Enable" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.word 0x0 0.--1. "EVACT,Event Action" "0: Event action disabled,1: Start restart or retrigger on event,2: Count on event,?"
|
|
group.byte 0x8++0x2
|
|
line.byte 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.byte 0x0 5. "MC1,Channel 1 Compare Match Disable" "0,1"
|
|
bitfld.byte 0x0 4. "MC0,Channel 0 Compare Match Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "VLC,Velocity Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DIR,Direction Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "ERR,Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "OVF,Overflow/Underflow Interrupt Disable" "0,1"
|
|
line.byte 0x1 "INTENSET,Interrupt Enable Set"
|
|
bitfld.byte 0x1 5. "MC1,Channel 1 Compare Match Enable" "0,1"
|
|
bitfld.byte 0x1 4. "MC0,Channel 0 Compare Match Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "VLC,Velocity Interrupt Enable" "0,1"
|
|
bitfld.byte 0x1 2. "DIR,Direction Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x1 0. "OVF,Overflow/Underflow Interrupt Enable" "0,1"
|
|
line.byte 0x2 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x2 5. "MC1,Channel 1 Compare Match" "0,1"
|
|
bitfld.byte 0x2 4. "MC0,Channel 0 Compare Match" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 3. "VLC,Velocity" "0,1"
|
|
bitfld.byte 0x2 2. "DIR,Direction Change" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "ERR,Error" "0,1"
|
|
bitfld.byte 0x2 0. "OVF,Overflow/Underflow" "0,1"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "STATUS,Status"
|
|
bitfld.word 0x0 13. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.word 0x0 12. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "FILTERBUFV,Filter Buffer Valid" "0,1"
|
|
bitfld.word 0x0 8. "PRESCBUFV,Prescaler Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "DIR,Direction Status Flag" "0,1"
|
|
bitfld.word 0x0 6. "STOP,Stop" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "HERR,Hall Error Flag" "0,1"
|
|
bitfld.word 0x0 4. "WINERR,Window Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "MPERR,Missing Pulse Error flag" "0,1"
|
|
bitfld.word 0x0 1. "IDXERR,Index Error Flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "QERR,Quadrature Error Flag" "0,1"
|
|
group.byte 0xF++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Run Mode" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Status"
|
|
bitfld.long 0x0 8. "CC1,Compare Channel 1 Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 7. "CC0,Compare Channel 0 Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "COUNT,Count Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 5. "FILTER,Filter Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "PRESC,Prescaler Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "STATUS,Status Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,Control B Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.byte 0x14++0x1
|
|
line.byte 0x0 "PRESC,Prescaler Value"
|
|
hexmask.byte 0x0 0.--3. 1. "PRESC,Prescaler Value"
|
|
line.byte 0x1 "FILTER,Filter Value"
|
|
hexmask.byte 0x1 0.--7. 1. "FILTER,Filter Value"
|
|
group.byte 0x18++0x1
|
|
line.byte 0x0 "PRESCBUF,Prescaler Buffer Value"
|
|
hexmask.byte 0x0 0.--3. 1. "PRESCBUF,Prescaler Buffer Value"
|
|
line.byte 0x1 "FILTERBUF,Filter Buffer Value"
|
|
hexmask.byte 0x1 0.--7. 1. "FILTERBUF,Filter Buffer Value"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "COUNT,Counter Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT,Counter Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "CC[$1],Channel n Compare Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "CC,Channel Compare Value"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x30)++0x3
|
|
line.long 0x0 "CCBUF[$1],Channel n Compare Buffer Value"
|
|
hexmask.long.word 0x0 0.--15. 1. "CCBUF,Channel Compare Buffer Value"
|
|
repeat.end
|
|
tree.end
|
|
tree "PM (Power Manager)"
|
|
base ad:0x44006000
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "CTRLA,Control A"
|
|
bitfld.byte 0x0 2. "IORET,I/O Retention" "0: When the device exits the HIBERNATE or BACKUP..,1: When the device exits the HIBERNATE or BACKUP.."
|
|
line.byte 0x1 "SLEEPCFG,Sleep Configuration"
|
|
bitfld.byte 0x1 0.--2. "SLEEPMODE,Sleep Mode" "?,?,2: CPU AHB and APB clocks are OFF,?,4: All Clocks are OFF,5: Backup domain is ON as well as some PDRAMs,6: Only Backup domain is powered ON,7: All power domains are powered OFF"
|
|
group.byte 0x4++0x2
|
|
line.byte 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.byte 0x0 0. "SLEEPRDY,Backup Sleep Mode Entry Ready Enable" "0,1"
|
|
line.byte 0x1 "INTENSET,Interrupt Enable Set"
|
|
bitfld.byte 0x1 0. "SLEEPRDY,Backup Sleep Mode Entry Ready Enable" "0,1"
|
|
line.byte 0x2 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x2 0. "SLEEPRDY,Backup Sleep Mode Entry Ready" "0,1"
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "STDBYCFG,Standby Configuration"
|
|
bitfld.byte 0x0 2. "LPRAM,Low Power RAM Enable" "0,1"
|
|
bitfld.byte 0x0 0. "RAMCFG,Ram Configuration" "0: All the RAMs are retained,1: Only the first 32K bytes are retained"
|
|
line.byte 0x1 "HIBCFG,Hibernate Configuration"
|
|
bitfld.byte 0x1 2. "LPRAM,Low Power RAM Enable" "0,1"
|
|
bitfld.byte 0x1 0. "RAMCFG,Ram Configuration" "0: All the RAMs are retained,1: Only the first 32K bytes are retained"
|
|
tree.end
|
|
tree "PORT (I/O Pin Controller)"
|
|
base ad:0x44800000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x44800000
|
|
sif (cpuis("PIC32CK0512SG00064*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG00100*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01064*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK0512SG01100*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00064*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG00100*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01064*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK1025SG01100*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00064*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00100*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG00144*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01064*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01100*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif (cpuis("PIC32CK2051SG01144*"))
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44800000 ad:0x44800080 ad:0x44800100 ad:0x44800180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "PORT_SEC (I/O Pin Controller (Secure))"
|
|
base ad:0x44801000
|
|
repeat 4. (list 0x0 0x1 0x2 0x3)(list ad:0x44801000 ad:0x44801080 ad:0x44801100 ad:0x44801180)
|
|
tree "GROUP[$1]"
|
|
base $2
|
|
group.long ($2)++0x1F
|
|
line.long 0x0 "DIR,Data Direction"
|
|
hexmask.long 0x0 0.--31. 1. "DIR,Port Data Direction"
|
|
line.long 0x4 "DIRCLR,Data Direction Clear"
|
|
hexmask.long 0x4 0.--31. 1. "DIRCLR,Port Data Direction Clear"
|
|
line.long 0x8 "DIRSET,Data Direction Set"
|
|
hexmask.long 0x8 0.--31. 1. "DIRSET,Port Data Direction Set"
|
|
line.long 0xC "DIRTGL,Data Direction Toggle"
|
|
hexmask.long 0xC 0.--31. 1. "DIRTGL,Port Data Direction Toggle"
|
|
line.long 0x10 "OUT,Data Output Value"
|
|
hexmask.long 0x10 0.--31. 1. "OUT,PORT Data Output Value"
|
|
line.long 0x14 "OUTCLR,Data Output Value Clear"
|
|
hexmask.long 0x14 0.--31. 1. "OUTCLR,PORT Data Output Value Clear"
|
|
line.long 0x18 "OUTSET,Data Output Value Set"
|
|
hexmask.long 0x18 0.--31. 1. "OUTSET,PORT Data Output Value Set"
|
|
line.long 0x1C "OUTTGL,Data Output Value Toggle"
|
|
hexmask.long 0x1C 0.--31. 1. "OUTTGL,PORT Data Output Value Toggle"
|
|
rgroup.long ($2+0x20)++0x3
|
|
line.long 0x0 "IN,Data Input Value"
|
|
hexmask.long 0x0 0.--31. 1. "IN,PORT Data Input Value"
|
|
group.long ($2+0x24)++0x3
|
|
line.long 0x0 "CTRL,Control"
|
|
hexmask.long 0x0 0.--31. 1. "SAMPLING,Input Sampling Mode"
|
|
wgroup.long ($2+0x28)++0x3
|
|
line.long 0x0 "WRCONFIG,Write Configuration"
|
|
bitfld.long 0x0 31. "HWSEL,Half-Word Select" "0,1"
|
|
bitfld.long 0x0 30. "WRPINCFG,Write PINCFG" "0,1"
|
|
bitfld.long 0x0 28. "WRPMUX,Write PMUX" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--27. 1. "PMUX,Peripheral Multiplexing"
|
|
bitfld.long 0x0 20.--21. "SLEWLIM,Output Driver Slew Rate Selection" "0,1,2,3"
|
|
bitfld.long 0x0 19. "ODRAIN,Open Drain Output" "0,1"
|
|
newline
|
|
bitfld.long 0x0 18. "PULLEN,Pull Enable" "0,1"
|
|
bitfld.long 0x0 17. "INEN,Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "PINMASK,Pin Mask for Multiple Pin Configuration"
|
|
group.long ($2+0x2C)++0x3
|
|
line.long 0x0 "EVCTRL,Event Input Control"
|
|
bitfld.long 0x0 31. "PORTEI3,PORT Event Input Enable 3" "0,1"
|
|
bitfld.long 0x0 29.--30. "EVACT3,PORT Event Action 3" "0,1,2,3"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PID3,PORT Event Pin Identifier 3"
|
|
newline
|
|
bitfld.long 0x0 23. "PORTEI2,PORT Event Input Enable 2" "0,1"
|
|
bitfld.long 0x0 21.--22. "EVACT2,PORT Event Action 2" "0,1,2,3"
|
|
hexmask.long.byte 0x0 16.--20. 1. "PID2,PORT Event Pin Identifier 2"
|
|
newline
|
|
bitfld.long 0x0 15. "PORTEI1,PORT Event Input Enable 1" "0,1"
|
|
bitfld.long 0x0 13.--14. "EVACT1,PORT Event Action 1" "0,1,2,3"
|
|
hexmask.long.byte 0x0 8.--12. 1. "PID1,PORT Event Pin Identifier 1"
|
|
newline
|
|
bitfld.long 0x0 7. "PORTEI0,PORT Event Input Enable 0" "0,1"
|
|
bitfld.long 0x0 5.--6. "EVACT0,PORT Event Action 0" "0: Event output to pin,1: Set output register of pin on event,2: Clear output register of pin on event,3: Toggle output register of pin on event"
|
|
hexmask.long.byte 0x0 0.--4. 1. "PID0,PORT Event Pin Identifier 0"
|
|
repeat 16. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x30)++0x0
|
|
line.byte 0x0 "PMUX[$1],Peripheral Multiplexing"
|
|
hexmask.byte 0x0 4.--7. 1. "PMUXO,Peripheral Multiplexing for Odd-Numbered Pin"
|
|
hexmask.byte 0x0 0.--3. 1. "PMUXE,Peripheral Multiplexing for Even-Numbered Pin"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0x40)++0x0
|
|
line.byte 0x0 "PINCFG[$1],Pin Configuration"
|
|
bitfld.byte 0x0 4.--5. "SLEWLIM,Output Driver Slew Rate Selection" "0: Slew rate control disabled (fast rise/fall time..,1: Slew rate control enabled (4x slower),2: Slew rate control enabled (8x slower),3: Slew rate control enabled (12x slower)"
|
|
bitfld.byte 0x0 3. "ODRAIN,Open Drain Output" "0,1"
|
|
bitfld.byte 0x0 2. "PULLEN,Pull Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "INEN,Input Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PMUXEN,Peripheral Multiplexer Enable" "0,1"
|
|
repeat.end
|
|
group.long ($2+0x60)++0x13
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 0. "NSCHK,Non-Secure Check Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 0. "NSCHK,Non-Secure Check" "0,1"
|
|
line.long 0xC "NONSEC,Security Attribution"
|
|
hexmask.long 0xC 0.--31. 1. "NONSEC,Port Security Attribution"
|
|
line.long 0x10 "NSCHK,Security Attribution Check"
|
|
hexmask.long 0x10 0.--31. 1. "NSCHK,Port Security Attribution Check"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "PRM (Boot ROM Controller)"
|
|
base ad:0x4480A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,CONTROL A REGISTER"
|
|
bitfld.long 0x0 8.--10. "PRMWS,ROM ACCESS TIME WAIT STATE" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 1. "ENABLE,ENABLE BIT" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,SOFTWARE RESET BIT" "0,1"
|
|
tree.end
|
|
tree "RSTC (Reset Controller)"
|
|
base ad:0x4400A000
|
|
rgroup.word 0x0++0x1
|
|
line.word 0x0 "RCAUSE,Reset Cause"
|
|
bitfld.word 0x0 9. "LOCKUP,Lockup Reset" "0,1"
|
|
bitfld.word 0x0 8. "BACKUP,Backup Reset" "0,1"
|
|
bitfld.word 0x0 7. "SYST,System Reset Request" "0,1"
|
|
bitfld.word 0x0 6. "WDT,Watchdog Reset" "0,1"
|
|
bitfld.word 0x0 5. "EXT,External Reset" "0,1"
|
|
bitfld.word 0x0 4. "BORVDDIO,Brown Out VDDIO Detector Reset" "0,1"
|
|
bitfld.word 0x0 3. "BORVDDA,Brown Out VDDA Detector Reset" "0,1"
|
|
bitfld.word 0x0 2. "BORVDDREG,Brown Out VDDREG Detector Reset" "0,1"
|
|
bitfld.word 0x0 1. "PORCORE,Brown Out CORE Detector Reset" "0,1"
|
|
bitfld.word 0x0 0. "POR,Power On Reset" "0,1"
|
|
rgroup.byte 0x2++0x0
|
|
line.byte 0x0 "BKUPEXIT,Backup Exit Source. Implemented only if RSTC_BACKUP_IMPLEMENTED=1"
|
|
bitfld.byte 0x0 7. "HIB0,Hibernate" "0,1"
|
|
bitfld.byte 0x0 2. "BBPS0,Battery Backup Power Switch" "0,1"
|
|
bitfld.byte 0x0 1. "RTC,Real Timer Counter Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "VBAT0,VBAT failure in backup mode" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.long 0x0 0. "LCKUPDIS,Lockup Disable" "0,1"
|
|
tree.end
|
|
tree "RTC (Real-Time Counter)"
|
|
base ad:0x44018000
|
|
tree "MODE0 (32-bit Counter with Single 32-bit Compare)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "CTRLA,MODE0 Control A"
|
|
bitfld.word 0x0 15. "COUNTSYNC,Count Read Synchronization Enable" "0,1"
|
|
bitfld.word 0x0 14. "GPTRST,GP Registers Reset On Tamper Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x0 8.--11. 1. "PRESCALER,Prescaler"
|
|
bitfld.word 0x0 7. "MATCHCLR,Clear on Match" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "MODE,Operating Mode" "0: Mode 0: 32-bit Counter,1: Mode 1: 16-bit Counter,2: Mode 2: Clock/Calendar,?"
|
|
bitfld.word 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.word 0x2 "CTRLB,MODE0 Control B"
|
|
bitfld.word 0x2 15. "SEPTO,Separate Tamper Outputs" "0,1"
|
|
bitfld.word 0x2 12.--14. "ACTF,Active Layer Frequency" "0: CLK_RTC_OUT = CLK_RTC/2,1: CLK_RTC_OUT = CLK_RTC/4,2: CLK_RTC_OUT = CLK_RTC/8,3: CLK_RTC_OUT = CLK_RTC/16,4: CLK_RTC_OUT = CLK_RTC/32,5: CLK_RTC_OUT = CLK_RTC/64,6: CLK_RTC_OUT = CLK_RTC/128,7: CLK_RTC_OUT = CLK_RTC/256"
|
|
newline
|
|
bitfld.word 0x2 8.--10. "DEBF,Debounce Frequency" "0: CLK_RTC_DEB = CLK_RTC/2,1: CLK_RTC_DEB = CLK_RTC/4,2: CLK_RTC_DEB = CLK_RTC/8,3: CLK_RTC_DEB = CLK_RTC/16,4: CLK_RTC_DEB = CLK_RTC/32,5: CLK_RTC_DEB = CLK_RTC/64,6: CLK_RTC_DEB = CLK_RTC/128,7: CLK_RTC_DEB = CLK_RTC/256"
|
|
bitfld.word 0x2 7. "DMAEN,DMA Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "RTCOUT,RTC Output Enable" "0,1"
|
|
bitfld.word 0x2 5. "DEBASYNC,Debouncer Asynchronous Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DEBMAJ,Debouncer Majority Enable" "0,1"
|
|
bitfld.word 0x2 1. "GP2EN,General Purpose 2 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "GP0EN,General Purpose 0 Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "EVCTRL,MODE0 Event Control"
|
|
bitfld.long 0x0 24. "PERDEO,Periodic Interval Daily Event Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "TAMPEVEI,Tamper Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVFEO,Overflow Event Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "TAMPEREO,Tamper Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPEO1,Compare 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "CMPEO0,Compare 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PEREO7,Periodic Interval 7 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "PEREO6,Periodic Interval 6 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PEREO5,Periodic Interval 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "PEREO4,Periodic Interval 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PEREO3,Periodic Interval 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "PEREO2,Periodic Interval 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PEREO1,Periodic Interval 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "PEREO0,Periodic Interval 0 Event Output Enable" "0,1"
|
|
group.word 0x8++0x5
|
|
line.word 0x0 "INTENCLR,MODE0 Interrupt Enable Clear"
|
|
bitfld.word 0x0 15. "OVF,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 14. "TAMPER,Tamper Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CMP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PER7,Periodic Interval 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 6. "PER6,Periodic Interval 6 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PER5,Periodic Interval 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 4. "PER4,Periodic Interval 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PER3,Periodic Interval 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "PER2,Periodic Interval 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PER1,Periodic Interval 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 0. "PER0,Periodic Interval 0 Interrupt Enable" "0,1"
|
|
line.word 0x2 "INTENSET,MODE0 Interrupt Enable Set"
|
|
bitfld.word 0x2 15. "OVF,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 14. "TAMPER,Tamper Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "CMP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 8. "CMP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "PER7,Periodic Interval 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "PER6,Periodic Interval 6 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "PER5,Periodic Interval 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "PER4,Periodic Interval 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "PER3,Periodic Interval 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "PER2,Periodic Interval 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PER1,Periodic Interval 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 0. "PER0,Periodic Interval 0 Interrupt Enable" "0,1"
|
|
line.word 0x4 "INTFLAG,MODE0 Interrupt Flag Status and Clear"
|
|
bitfld.word 0x4 15. "OVF,Overflow" "0,1"
|
|
bitfld.word 0x4 14. "TAMPER,Tamper" "0,1"
|
|
newline
|
|
bitfld.word 0x4 9. "CMP1,Compare 1" "0,1"
|
|
bitfld.word 0x4 8. "CMP0,Compare 0" "0,1"
|
|
newline
|
|
bitfld.word 0x4 7. "PER7,Periodic Interval 7" "0,1"
|
|
bitfld.word 0x4 6. "PER6,Periodic Interval 6" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "PER5,Periodic Interval 5" "0,1"
|
|
bitfld.word 0x4 4. "PER4,Periodic Interval 4" "0,1"
|
|
newline
|
|
bitfld.word 0x4 3. "PER3,Periodic Interval 3" "0,1"
|
|
bitfld.word 0x4 2. "PER2,Periodic Interval 2" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PER1,Periodic Interval 1" "0,1"
|
|
bitfld.word 0x4 0. "PER0,Periodic Interval 0" "0,1"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 0. "DBGRUN,Run During Debug" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SYNCBUSY,MODE0 Synchronization Busy Status"
|
|
bitfld.long 0x0 19. "GP3,General Purpose 3 Register Busy" "0,1"
|
|
bitfld.long 0x0 18. "GP2,General Purpose 2 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GP1,General Purpose 1 Register Busy" "0,1"
|
|
bitfld.long 0x0 16. "GP0,General Purpose 0 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "COUNTSYNC,Count Synchronization Enable Bit Busy" "0,1"
|
|
bitfld.long 0x0 6. "COMP1,COMP 1 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "COMP0,COMP 0 Register Busy" "0,1"
|
|
bitfld.long 0x0 3. "COUNT,COUNT Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FREQCORR,FREQCORR Register Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Bit Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Busy" "0,1"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "FREQCORR,Frequency Correction"
|
|
bitfld.byte 0x0 7. "SIGN,Correction Sign" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "VALUE,Correction Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "COUNT,MODE0 Counter Value"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Counter Value"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x20)++0x3
|
|
line.long 0x0 "COMP[$1],MODE0 Compare n Value"
|
|
hexmask.long 0x0 0.--31. 1. "COMP,Compare Value"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "GP[$1],General Purpose"
|
|
hexmask.long 0x0 0.--31. 1. "GP,General Purpose"
|
|
repeat.end
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TAMPCTRL,Tamper Control"
|
|
bitfld.long 0x0 31. "DEBNC7,Debouncer Enable 7" "0,1"
|
|
bitfld.long 0x0 30. "DEBNC6,Debouncer Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DEBNC5,Debouncer Enable 5" "0,1"
|
|
bitfld.long 0x0 28. "DEBNC4,Debouncer Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DEBNC3,Debouncer Enable 3" "0,1"
|
|
bitfld.long 0x0 26. "DEBNC2,Debouncer Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DEBNC1,Debouncer Enable 1" "0,1"
|
|
bitfld.long 0x0 24. "DEBNC0,Debouncer Enable 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TAMLVL7,Tamper Level Select 7" "0,1"
|
|
bitfld.long 0x0 22. "TAMLVL6,Tamper Level Select 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TAMLVL5,Tamper Level Select 5" "0,1"
|
|
bitfld.long 0x0 20. "TAMLVL4,Tamper Level Select 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TAMLVL3,Tamper Level Select 3" "0,1"
|
|
bitfld.long 0x0 18. "TAMLVL2,Tamper Level Select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TAMLVL1,Tamper Level Select 1" "0,1"
|
|
bitfld.long 0x0 16. "TAMLVL0,Tamper Level Select 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "IN7ACT,Tamper Input 7 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN7 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 12.--13. "IN6ACT,Tamper Input 6 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN6 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "IN5ACT,Tamper Input 5 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN5 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 8.--9. "IN4ACT,Tamper Input 4 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN4 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IN3ACT,Tamper Input 3 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN3 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 4.--5. "IN2ACT,Tamper Input 2 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN2 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IN1ACT,Tamper Input 1 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN1 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 0.--1. "IN0ACT,Tamper Input 0 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN0 to OUT. When a mismatch occurs.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TIMESTAMP,MODE0 Timestamp"
|
|
hexmask.long 0x0 0.--31. 1. "COUNT,Count Timestamp Value"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "TAMPID,Tamper ID"
|
|
bitfld.long 0x0 31. "TAMPEVT,Tamper Event Detected" "0,1"
|
|
bitfld.long 0x0 7. "TAMPID7,Tamper Input 7 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TAMPID6,Tamper Input 6 Detected" "0,1"
|
|
bitfld.long 0x0 5. "TAMPID5,Tamper Input 5 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TAMPID4,Tamper Input 4 Detected" "0,1"
|
|
bitfld.long 0x0 3. "TAMPID3,Tamper Input 3 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMPID2,Tamper Input 2 Detected" "0,1"
|
|
bitfld.long 0x0 1. "TAMPID1,Tamper Input 1 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMPID0,Tamper Input 0 Detected" "0,1"
|
|
line.long 0x4 "TAMPCTRLB,Tamper Control B"
|
|
bitfld.long 0x4 7. "ALSI7,Active Layer Select Internal 7" "0,1"
|
|
bitfld.long 0x4 6. "ALSI6,Active Layer Select Internal 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ALSI5,Active Layer Select Internal 5" "0,1"
|
|
bitfld.long 0x4 4. "ALSI4,Active Layer Select Internal 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ALSI3,Active Layer Select Internal 3" "0,1"
|
|
bitfld.long 0x4 2. "ALSI2,Active Layer Select Internal 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALSI1,Active Layer Select Internal 1" "0,1"
|
|
bitfld.long 0x4 0. "ALSI0,Active Layer Select Internal 0" "0,1"
|
|
tree.end
|
|
tree "MODE1 (16-bit Counter with Two 16-bit Compares)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "CTRLA,MODE1 Control A"
|
|
bitfld.word 0x0 15. "COUNTSYNC,Count Read Synchronization Enable" "0,1"
|
|
bitfld.word 0x0 14. "GPTRST,GP Registers Reset On Tamper Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x0 8.--11. 1. "PRESCALER,Prescaler"
|
|
bitfld.word 0x0 2.--3. "MODE,Operating Mode" "0: Mode 0: 32-bit Counter,1: Mode 1: 16-bit Counter,2: Mode 2: Clock/Calendar,?"
|
|
newline
|
|
bitfld.word 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.word 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.word 0x2 "CTRLB,MODE1 Control B"
|
|
bitfld.word 0x2 15. "SEPTO,Separate Tamper Outputs" "0,1"
|
|
bitfld.word 0x2 12.--14. "ACTF,Active Layer Frequency" "0: CLK_RTC_OUT = CLK_RTC/2,1: CLK_RTC_OUT = CLK_RTC/4,2: CLK_RTC_OUT = CLK_RTC/8,3: CLK_RTC_OUT = CLK_RTC/16,4: CLK_RTC_OUT = CLK_RTC/32,5: CLK_RTC_OUT = CLK_RTC/64,6: CLK_RTC_OUT = CLK_RTC/128,7: CLK_RTC_OUT = CLK_RTC/256"
|
|
newline
|
|
bitfld.word 0x2 8.--10. "DEBF,Debounce Frequency" "0: CLK_RTC_DEB = CLK_RTC/2,1: CLK_RTC_DEB = CLK_RTC/4,2: CLK_RTC_DEB = CLK_RTC/8,3: CLK_RTC_DEB = CLK_RTC/16,4: CLK_RTC_DEB = CLK_RTC/32,5: CLK_RTC_DEB = CLK_RTC/64,6: CLK_RTC_DEB = CLK_RTC/128,7: CLK_RTC_DEB = CLK_RTC/256"
|
|
bitfld.word 0x2 7. "DMAEN,DMA Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "RTCOUT,RTC Output Enable" "0,1"
|
|
bitfld.word 0x2 5. "DEBASYNC,Debouncer Asynchronous Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DEBMAJ,Debouncer Majority Enable" "0,1"
|
|
bitfld.word 0x2 1. "GP2EN,General Purpose 2 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "GP0EN,General Purpose 0 Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "EVCTRL,MODE1 Event Control"
|
|
bitfld.long 0x0 24. "PERDEO,Periodic Interval Daily Event Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "TAMPEVEI,Tamper Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVFEO,Overflow Event Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "TAMPEREO,Tamper Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CMPEO3,Compare 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 10. "CMPEO2,Compare 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CMPEO1,Compare 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "CMPEO0,Compare 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PEREO7,Periodic Interval 7 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "PEREO6,Periodic Interval 6 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PEREO5,Periodic Interval 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "PEREO4,Periodic Interval 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PEREO3,Periodic Interval 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "PEREO2,Periodic Interval 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PEREO1,Periodic Interval 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "PEREO0,Periodic Interval 0 Event Output Enable" "0,1"
|
|
group.word 0x8++0x5
|
|
line.word 0x0 "INTENCLR,MODE1 Interrupt Enable Clear"
|
|
bitfld.word 0x0 15. "OVF,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 14. "TAMPER,Tamper Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "CMP3,Compare 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 10. "CMP2,Compare 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "CMP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 8. "CMP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PER7,Periodic Interval 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 6. "PER6,Periodic Interval 6 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PER5,Periodic Interval 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 4. "PER4,Periodic Interval 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PER3,Periodic Interval 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "PER2,Periodic Interval 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PER1,Periodic Interval 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 0. "PER0,Periodic Interval 0 Interrupt Enable" "0,1"
|
|
line.word 0x2 "INTENSET,MODE1 Interrupt Enable Set"
|
|
bitfld.word 0x2 15. "OVF,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 14. "TAMPER,Tamper Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 11. "CMP3,Compare 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 10. "CMP2,Compare 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "CMP1,Compare 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 8. "CMP0,Compare 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "PER7,Periodic Interval 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 6. "PER6,Periodic Interval 6 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "PER5,Periodic Interval 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 4. "PER4,Periodic Interval 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "PER3,Periodic Interval 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 2. "PER2,Periodic Interval 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PER1,Periodic Interval 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 0. "PER0,Periodic Interval 0 Interrupt Enable" "0,1"
|
|
line.word 0x4 "INTFLAG,MODE1 Interrupt Flag Status and Clear"
|
|
bitfld.word 0x4 15. "OVF,Overflow" "0,1"
|
|
bitfld.word 0x4 14. "TAMPER,Tamper" "0,1"
|
|
newline
|
|
bitfld.word 0x4 11. "CMP3,Compare 3" "0,1"
|
|
bitfld.word 0x4 10. "CMP2,Compare 2" "0,1"
|
|
newline
|
|
bitfld.word 0x4 9. "CMP1,Compare 1" "0,1"
|
|
bitfld.word 0x4 8. "CMP0,Compare 0" "0,1"
|
|
newline
|
|
bitfld.word 0x4 7. "PER7,Periodic Interval 7" "0,1"
|
|
bitfld.word 0x4 6. "PER6,Periodic Interval 6" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "PER5,Periodic Interval 5" "0,1"
|
|
bitfld.word 0x4 4. "PER4,Periodic Interval 4" "0,1"
|
|
newline
|
|
bitfld.word 0x4 3. "PER3,Periodic Interval 3" "0,1"
|
|
bitfld.word 0x4 2. "PER2,Periodic Interval 2" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PER1,Periodic Interval 1" "0,1"
|
|
bitfld.word 0x4 0. "PER0,Periodic Interval 0" "0,1"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 0. "DBGRUN,Run During Debug" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SYNCBUSY,MODE1 Synchronization Busy Status"
|
|
bitfld.long 0x0 19. "GP3,General Purpose 3 Register Busy" "0,1"
|
|
bitfld.long 0x0 18. "GP2,General Purpose 2 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GP1,General Purpose 1 Register Busy" "0,1"
|
|
bitfld.long 0x0 16. "GP0,General Purpose 0 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "COUNTSYNC,Count Synchronization Enable Bit Busy" "0,1"
|
|
bitfld.long 0x0 8. "COMP3,COMP 3 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "COMP2,COMP 2 Register Busy" "0,1"
|
|
bitfld.long 0x0 6. "COMP1,COMP 1 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "COMP0,COMP 0 Register Busy" "0,1"
|
|
bitfld.long 0x0 4. "PER,PER Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "COUNT,COUNT Register Busy" "0,1"
|
|
bitfld.long 0x0 2. "FREQCORR,FREQCORR Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Bit Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Bit Busy" "0,1"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "FREQCORR,Frequency Correction"
|
|
bitfld.byte 0x0 7. "SIGN,Correction Sign" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "VALUE,Correction Value"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "COUNT,MODE1 Counter Value"
|
|
hexmask.word 0x0 0.--15. 1. "COUNT,Counter Value"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "PER,MODE1 Counter Period"
|
|
hexmask.word 0x0 0.--15. 1. "PER,Counter Period"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x20)++0x1
|
|
line.word 0x0 "COMP[$1],MODE1 Compare n Value"
|
|
hexmask.word 0x0 0.--15. 1. "COMP,Compare Value"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "GP[$1],General Purpose"
|
|
hexmask.long 0x0 0.--31. 1. "GP,General Purpose"
|
|
repeat.end
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TAMPCTRL,Tamper Control"
|
|
bitfld.long 0x0 31. "DEBNC7,Debouncer Enable 7" "0,1"
|
|
bitfld.long 0x0 30. "DEBNC6,Debouncer Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DEBNC5,Debouncer Enable 5" "0,1"
|
|
bitfld.long 0x0 28. "DEBNC4,Debouncer Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DEBNC3,Debouncer Enable 3" "0,1"
|
|
bitfld.long 0x0 26. "DEBNC2,Debouncer Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DEBNC1,Debouncer Enable 1" "0,1"
|
|
bitfld.long 0x0 24. "DEBNC0,Debouncer Enable 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TAMLVL7,Tamper Level Select 7" "0,1"
|
|
bitfld.long 0x0 22. "TAMLVL6,Tamper Level Select 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TAMLVL5,Tamper Level Select 5" "0,1"
|
|
bitfld.long 0x0 20. "TAMLVL4,Tamper Level Select 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TAMLVL3,Tamper Level Select 3" "0,1"
|
|
bitfld.long 0x0 18. "TAMLVL2,Tamper Level Select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TAMLVL1,Tamper Level Select 1" "0,1"
|
|
bitfld.long 0x0 16. "TAMLVL0,Tamper Level Select 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "IN7ACT,Tamper Input 7 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN7 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 12.--13. "IN6ACT,Tamper Input 6 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN6 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "IN5ACT,Tamper Input 5 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN5 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 8.--9. "IN4ACT,Tamper Input 4 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN4 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IN3ACT,Tamper Input 3 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN3 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 4.--5. "IN2ACT,Tamper Input 2 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN2 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IN1ACT,Tamper Input 1 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN1 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 0.--1. "IN0ACT,Tamper Input 0 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN0 to OUT. When a mismatch occurs.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TIMESTAMP,MODE1 Timestamp"
|
|
hexmask.long.word 0x0 0.--15. 1. "COUNT,Count Timestamp Value"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "TAMPID,Tamper ID"
|
|
bitfld.long 0x0 31. "TAMPEVT,Tamper Event Detected" "0,1"
|
|
bitfld.long 0x0 7. "TAMPID7,Tamper Input 7 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TAMPID6,Tamper Input 6 Detected" "0,1"
|
|
bitfld.long 0x0 5. "TAMPID5,Tamper Input 5 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TAMPID4,Tamper Input 4 Detected" "0,1"
|
|
bitfld.long 0x0 3. "TAMPID3,Tamper Input 3 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMPID2,Tamper Input 2 Detected" "0,1"
|
|
bitfld.long 0x0 1. "TAMPID1,Tamper Input 1 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMPID0,Tamper Input 0 Detected" "0,1"
|
|
line.long 0x4 "TAMPCTRLB,Tamper Control B"
|
|
bitfld.long 0x4 7. "ALSI7,Active Layer Select Internal 7" "0,1"
|
|
bitfld.long 0x4 6. "ALSI6,Active Layer Select Internal 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ALSI5,Active Layer Select Internal 5" "0,1"
|
|
bitfld.long 0x4 4. "ALSI4,Active Layer Select Internal 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ALSI3,Active Layer Select Internal 3" "0,1"
|
|
bitfld.long 0x4 2. "ALSI2,Active Layer Select Internal 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALSI1,Active Layer Select Internal 1" "0,1"
|
|
bitfld.long 0x4 0. "ALSI0,Active Layer Select Internal 0" "0,1"
|
|
tree.end
|
|
tree "MODE2 (Clock/Calendar with Alarm)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "CTRLA,MODE2 Control A"
|
|
bitfld.word 0x0 15. "CLOCKSYNC,Clock Read Synchronization Enable" "0,1"
|
|
bitfld.word 0x0 14. "GPTRST,GP Registers Reset On Tamper Enable" "0,1"
|
|
newline
|
|
hexmask.word.byte 0x0 8.--11. 1. "PRESCALER,Prescaler"
|
|
bitfld.word 0x0 7. "MATCHCLR,Clear on Match" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "CLKREP,Clock Representation" "0,1"
|
|
bitfld.word 0x0 2.--3. "MODE,Operating Mode" "0: Mode 0: 32-bit Counter,1: Mode 1: 16-bit Counter,2: Mode 2: Clock/Calendar,?"
|
|
newline
|
|
bitfld.word 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.word 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.word 0x2 "CTRLB,MODE2 Control B"
|
|
bitfld.word 0x2 15. "SEPTO,Separate Tamper Outputs" "0,1"
|
|
bitfld.word 0x2 12.--14. "ACTF,Active Layer Frequency" "0: CLK_RTC_OUT = CLK_RTC/2,1: CLK_RTC_OUT = CLK_RTC/4,2: CLK_RTC_OUT = CLK_RTC/8,3: CLK_RTC_OUT = CLK_RTC/16,4: CLK_RTC_OUT = CLK_RTC/32,5: CLK_RTC_OUT = CLK_RTC/64,6: CLK_RTC_OUT = CLK_RTC/128,7: CLK_RTC_OUT = CLK_RTC/256"
|
|
newline
|
|
bitfld.word 0x2 8.--10. "DEBF,Debounce Frequency" "0: CLK_RTC_DEB = CLK_RTC/2,1: CLK_RTC_DEB = CLK_RTC/4,2: CLK_RTC_DEB = CLK_RTC/8,3: CLK_RTC_DEB = CLK_RTC/16,4: CLK_RTC_DEB = CLK_RTC/32,5: CLK_RTC_DEB = CLK_RTC/64,6: CLK_RTC_DEB = CLK_RTC/128,7: CLK_RTC_DEB = CLK_RTC/256"
|
|
bitfld.word 0x2 7. "DMAEN,DMA Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "RTCOUT,RTC Output Enable" "0,1"
|
|
bitfld.word 0x2 5. "DEBASYNC,Debouncer Asynchronous Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "DEBMAJ,Debouncer Majority Enable" "0,1"
|
|
bitfld.word 0x2 1. "GP2EN,General Purpose 2 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 0. "GP0EN,General Purpose 0 Enable" "0,1"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "EVCTRL,MODE2 Event Control"
|
|
bitfld.long 0x0 24. "PERDEO,Periodic Interval Daily Event Output Enable" "0,1"
|
|
bitfld.long 0x0 16. "TAMPEVEI,Tamper Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "OVFEO,Overflow Event Output Enable" "0,1"
|
|
bitfld.long 0x0 14. "TAMPEREO,Tamper Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "ALARMEO1,Alarm 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 8. "ALARMEO0,Alarm 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PEREO7,Periodic Interval 7 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 6. "PEREO6,Periodic Interval 6 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PEREO5,Periodic Interval 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 4. "PEREO4,Periodic Interval 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "PEREO3,Periodic Interval 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 2. "PEREO2,Periodic Interval 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PEREO1,Periodic Interval 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 0. "PEREO0,Periodic Interval 0 Event Output Enable" "0,1"
|
|
group.word 0x8++0x5
|
|
line.word 0x0 "INTENCLR,MODE2 Interrupt Enable Clear"
|
|
bitfld.word 0x0 15. "OVF,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 14. "TAMPER,Tamper Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "ALARM1,Alarm 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 8. "ALARM0,Alarm 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PER7,Periodic Interval 7 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 6. "PER6,Periodic Interval 6 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PER5,Periodic Interval 5 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 4. "PER4,Periodic Interval 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PER3,Periodic Interval 3 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "PER2,Periodic Interval 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PER1,Periodic Interval 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 0. "PER0,Periodic Interval 0 Interrupt Enable" "0,1"
|
|
line.word 0x2 "INTENSET,MODE2 Interrupt Enable Set"
|
|
bitfld.word 0x2 15. "OVF,Overflow Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 14. "TAMPER,Tamper Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 9. "ALARM1,Alarm 1 Interrupt Enable" "0,1"
|
|
bitfld.word 0x2 8. "ALARM0,Alarm 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 7. "PER7,Periodic Interval 7 Enable" "0,1"
|
|
bitfld.word 0x2 6. "PER6,Periodic Interval 6 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "PER5,Periodic Interval 5 Enable" "0,1"
|
|
bitfld.word 0x2 4. "PER4,Periodic Interval 4 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "PER3,Periodic Interval 3 Enable" "0,1"
|
|
bitfld.word 0x2 2. "PER2,Periodic Interval 2 Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "PER1,Periodic Interval 1 Enable" "0,1"
|
|
bitfld.word 0x2 0. "PER0,Periodic Interval 0 Enable" "0,1"
|
|
line.word 0x4 "INTFLAG,MODE2 Interrupt Flag Status and Clear"
|
|
bitfld.word 0x4 15. "OVF,Overflow" "0,1"
|
|
bitfld.word 0x4 14. "TAMPER,Tamper" "0,1"
|
|
newline
|
|
bitfld.word 0x4 9. "ALARM1,Alarm 1" "0,1"
|
|
bitfld.word 0x4 8. "ALARM0,Alarm 0" "0,1"
|
|
newline
|
|
bitfld.word 0x4 7. "PER7,Periodic Interval 7" "0,1"
|
|
bitfld.word 0x4 6. "PER6,Periodic Interval 6" "0,1"
|
|
newline
|
|
bitfld.word 0x4 5. "PER5,Periodic Interval 5" "0,1"
|
|
bitfld.word 0x4 4. "PER4,Periodic Interval 4" "0,1"
|
|
newline
|
|
bitfld.word 0x4 3. "PER3,Periodic Interval 3" "0,1"
|
|
bitfld.word 0x4 2. "PER2,Periodic Interval 2" "0,1"
|
|
newline
|
|
bitfld.word 0x4 1. "PER1,Periodic Interval 1" "0,1"
|
|
bitfld.word 0x4 0. "PER0,Periodic Interval 0" "0,1"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 0. "DBGRUN,Run During Debug" "0,1"
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x0 "SYNCBUSY,MODE2 Synchronization Busy Status"
|
|
bitfld.long 0x0 19. "GP3,General Purpose 3 Register Busy" "0,1"
|
|
bitfld.long 0x0 18. "GP2,General Purpose 2 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "GP1,General Purpose 1 Register Busy" "0,1"
|
|
bitfld.long 0x0 16. "GP0,General Purpose 0 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "CLOCKSYNC,Clock Synchronization Enable Bit Busy" "0,1"
|
|
bitfld.long 0x0 12. "MASK1,MASK 1 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "MASK0,MASK 0 Register Busy" "0,1"
|
|
bitfld.long 0x0 6. "ALARM1,ALARM 1 Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "ALARM0,ALARM 0 Register Busy" "0,1"
|
|
bitfld.long 0x0 3. "CLOCK,CLOCK Register Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "FREQCORR,FREQCORR Register Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Bit Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Bit Busy" "0,1"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "FREQCORR,Frequency Correction"
|
|
bitfld.byte 0x0 7. "SIGN,Correction Sign" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "VALUE,Correction Value"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CLOCK,MODE2 Clock Value"
|
|
hexmask.long.byte 0x0 26.--31. 1. "YEAR,Year"
|
|
hexmask.long.byte 0x0 22.--25. 1. "MONTH,Month"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--21. 1. "DAY,Day"
|
|
hexmask.long.byte 0x0 12.--16. 1. "HOUR,Hour"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--11. 1. "MINUTE,Minute"
|
|
hexmask.long.byte 0x0 0.--5. 1. "SECOND,Second"
|
|
repeat 2. (list 0x0 0x1)(list ad:0x44018020 ad:0x44018028)
|
|
tree "MODE2_ALARM[$1]"
|
|
base $2
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "ALARM,MODE2_ALARM Alarm n Value"
|
|
hexmask.long.byte 0x0 26.--31. 1. "YEAR,Year"
|
|
hexmask.long.byte 0x0 22.--25. 1. "MONTH,Month"
|
|
hexmask.long.byte 0x0 17.--21. 1. "DAY,Day"
|
|
hexmask.long.byte 0x0 12.--16. 1. "HOUR,Hour"
|
|
hexmask.long.byte 0x0 6.--11. 1. "MINUTE,Minute"
|
|
hexmask.long.byte 0x0 0.--5. 1. "SECOND,Second"
|
|
group.byte ($2+0x4)++0x0
|
|
line.byte 0x0 "MASK,MODE2_ALARM Alarm n Mask"
|
|
bitfld.byte 0x0 0.--2. "SEL,Alarm Mask Selection" "0: Alarm Disabled,1: Match seconds only,2: Match seconds and minutes only,3: Match seconds minutes and hours only,4: Match seconds minutes hours and days only,5: Match seconds minutes hours days and months only,6: Match seconds minutes hours days months and years,?"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x44018000
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "GP[$1],General Purpose"
|
|
hexmask.long 0x0 0.--31. 1. "GP,General Purpose"
|
|
repeat.end
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "TAMPCTRL,Tamper Control"
|
|
bitfld.long 0x0 31. "DEBNC7,Debouncer Enable 7" "0,1"
|
|
bitfld.long 0x0 30. "DEBNC6,Debouncer Enable 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 29. "DEBNC5,Debouncer Enable 5" "0,1"
|
|
bitfld.long 0x0 28. "DEBNC4,Debouncer Enable 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "DEBNC3,Debouncer Enable 3" "0,1"
|
|
bitfld.long 0x0 26. "DEBNC2,Debouncer Enable 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "DEBNC1,Debouncer Enable 1" "0,1"
|
|
bitfld.long 0x0 24. "DEBNC0,Debouncer Enable 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "TAMLVL7,Tamper Level Select 7" "0,1"
|
|
bitfld.long 0x0 22. "TAMLVL6,Tamper Level Select 6" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "TAMLVL5,Tamper Level Select 5" "0,1"
|
|
bitfld.long 0x0 20. "TAMLVL4,Tamper Level Select 4" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "TAMLVL3,Tamper Level Select 3" "0,1"
|
|
bitfld.long 0x0 18. "TAMLVL2,Tamper Level Select 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "TAMLVL1,Tamper Level Select 1" "0,1"
|
|
bitfld.long 0x0 16. "TAMLVL0,Tamper Level Select 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14.--15. "IN7ACT,Tamper Input 7 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN7 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 12.--13. "IN6ACT,Tamper Input 6 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN6 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 10.--11. "IN5ACT,Tamper Input 5 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN5 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 8.--9. "IN4ACT,Tamper Input 4 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN4 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 6.--7. "IN3ACT,Tamper Input 3 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN3 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 4.--5. "IN2ACT,Tamper Input 2 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN2 to OUT. When a mismatch occurs.."
|
|
newline
|
|
bitfld.long 0x0 2.--3. "IN1ACT,Tamper Input 1 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN1 to OUT. When a mismatch occurs.."
|
|
bitfld.long 0x0 0.--1. "IN0ACT,Tamper Input 0 Action" "0: Off (Disabled),1: Wake and set Tamper flag,2: Capture timestamp and set Tamper flag,3: Compare IN0 to OUT. When a mismatch occurs.."
|
|
rgroup.long 0x64++0x3
|
|
line.long 0x0 "TIMESTAMP,MODE2 Timestamp"
|
|
hexmask.long.byte 0x0 26.--31. 1. "YEAR,Year Timestamp Value"
|
|
hexmask.long.byte 0x0 22.--25. 1. "MONTH,Month Timestamp Value"
|
|
newline
|
|
hexmask.long.byte 0x0 17.--21. 1. "DAY,Day Timestamp Value"
|
|
hexmask.long.byte 0x0 12.--16. 1. "HOUR,Hour Timestamp Value"
|
|
newline
|
|
hexmask.long.byte 0x0 6.--11. 1. "MINUTE,Minute Timestamp Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "SECOND,Second Timestamp Value"
|
|
group.long 0x68++0x7
|
|
line.long 0x0 "TAMPID,Tamper ID"
|
|
bitfld.long 0x0 31. "TAMPEVT,Tamper Event Detected" "0,1"
|
|
bitfld.long 0x0 7. "TAMPID7,Tamper Input 7 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 6. "TAMPID6,Tamper Input 6 Detected" "0,1"
|
|
bitfld.long 0x0 5. "TAMPID5,Tamper Input 5 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "TAMPID4,Tamper Input 4 Detected" "0,1"
|
|
bitfld.long 0x0 3. "TAMPID3,Tamper Input 3 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "TAMPID2,Tamper Input 2 Detected" "0,1"
|
|
bitfld.long 0x0 1. "TAMPID1,Tamper Input 1 Detected" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "TAMPID0,Tamper Input 0 Detected" "0,1"
|
|
line.long 0x4 "TAMPCTRLB,Tamper Control B"
|
|
bitfld.long 0x4 7. "ALSI7,Active Layer Select Internal 7" "0,1"
|
|
bitfld.long 0x4 6. "ALSI6,Active Layer Select Internal 6" "0,1"
|
|
newline
|
|
bitfld.long 0x4 5. "ALSI5,Active Layer Select Internal 5" "0,1"
|
|
bitfld.long 0x4 4. "ALSI4,Active Layer Select Internal 4" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ALSI3,Active Layer Select Internal 3" "0,1"
|
|
bitfld.long 0x4 2. "ALSI2,Active Layer Select Internal 2" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ALSI1,Active Layer Select Internal 1" "0,1"
|
|
bitfld.long 0x4 0. "ALSI0,Active Layer Select Internal 0" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "SCB (System Control Block)"
|
|
base ad:0xE000ED00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CPUID,CPUID base register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "Implementer,Implementer code ARM=0x41"
|
|
hexmask.long.byte 0x0 20.--23. 1. "Variant,Variant number"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "Architecture,Architecture version 0xC=ARMv8-M Base Line 0xF=ARMv8-M Main Line"
|
|
hexmask.long.word 0x0 4.--15. 1. "PartNo,Part number 0xD20=Cortex-M23"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "Revision,Revision number"
|
|
group.long 0x4++0x27
|
|
line.long 0x0 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x0 31. "PENDNMISET,Pend NMI set" "0: Write: no effect; read: NMI exception is not..,1: Write: changes NMI exception state to pending;.."
|
|
bitfld.long 0x0 30. "PENDNMICLR,Pend NMI clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "PENDSVSET,Pend PendSV set" "0: Write: no effect; read: PendSV exception is not..,1: Write: changes PendSV exception state to.."
|
|
bitfld.long 0x0 27. "PENDSVCLR,Pend PendSV clear" "0: No effect,1: Removes the pending state from the PendSV.."
|
|
newline
|
|
bitfld.long 0x0 26. "PENDSTSET,Pend SysTick set" "0: Write: no effect; read: SysTick exception is not..,1: Write: changes SysTick exception state to.."
|
|
bitfld.long 0x0 25. "PENDSTCLR,Pend SysTick clear" "0: No effect,1: Removes the pending state from the SysTick.."
|
|
newline
|
|
bitfld.long 0x0 23. "ISRPREEMPT,Interrupt preempt" "0,1"
|
|
bitfld.long 0x0 22. "ISRPENDING,Interrupt pending" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Vector pending"
|
|
bitfld.long 0x0 11. "RETTOBASE,Return to base" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Vector active"
|
|
line.long 0x4 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x4 7.--31. 1. "TBLOFF,Vector table base offset"
|
|
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "VECTKEY,Register Key (0x05FA)"
|
|
bitfld.long 0x8 15. "ENDIANNESS,Data Endianness 0=little 1=big" "0: little,1: big"
|
|
newline
|
|
bitfld.long 0x8 14. "PRIS,Prioritize Secure Exceptions" "0: Priority ranges of Secure and Non-secure..,1: Non-secure exceptions are de-prioritized"
|
|
bitfld.long 0x8 13. "BFHFNMINS,BusFault HardFault and NMI Non-secure enable" "0: BusFault HardFault and NMI are Secure,1: BusFault and NMI are Non-secure and exceptions.."
|
|
newline
|
|
bitfld.long 0x8 3. "SYSRESETREQS,System Reset Request Secure only" "0: SYSRESETREQ functionality is available to both..,1: SYSRESETREQ functionality is only available to.."
|
|
bitfld.long 0x8 2. "SYSRESETREQ,System Reset Request" "0: Do not request a system reset,1: Request a system reset"
|
|
newline
|
|
bitfld.long 0x8 1. "VECTCLRACTIVE,Debug: Clear Active State" "0: Do not clear active state,1: Clear active state"
|
|
line.long 0xC "SCR,System Control Register"
|
|
bitfld.long 0xC 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup the..,1: Enabled events and all interrupts including.."
|
|
bitfld.long 0xC 3. "SLEEPDEEPS,Sleep deep secure" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "SLEEPDEEP,Sleep deep" "0: Sleep,1: Deep sleep"
|
|
bitfld.long 0xC 1. "SLEEPONEXIT,Sleep on exit" "0: O not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. "BP,Branch prediction enable" "0,1"
|
|
bitfld.long 0x10 17. "IC,Instruction cache enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "DC,Data cache enable" "0,1"
|
|
bitfld.long 0x10 10. "STKOFHFNMIGN,Stack overflow in HardFault and NMI ignore" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "BFHFNMIGN,BusFault in HardFault or NMI ignore" "0,1"
|
|
bitfld.long 0x10 4. "DIV_0_TRP,Divide by zero trap" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "UNALIGN_TRP,Unaligned trap" "0: Do not trap unaligned halfword and word accesses,1: Trap unaligned halfword and word accesses"
|
|
bitfld.long 0x10 1. "USERSETMPEND,User set main pending" "0,1"
|
|
line.long 0x14 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. "PRI_7,Priority of system handler 7 SecureFault"
|
|
hexmask.long.byte 0x14 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRI_12,Priority of system handler 12 DebugMonitor"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 21. "HARDFAULTPENDED,HardFault exception pended state" "0,1"
|
|
bitfld.long 0x20 15. "SVCALLPENDED,SVCall exception pended state" "0,1"
|
|
newline
|
|
bitfld.long 0x20 11. "SYSTICKACT,SysTick exception active state" "0,1"
|
|
bitfld.long 0x20 10. "PENDSVACT,PendSV exception active state" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "SVCALLACT,SVCall exception active state" "0,1"
|
|
bitfld.long 0x20 5. "NMIACT,NMI exception active state" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "HARDFAULTACT,HardFault exception active state" "0,1"
|
|
line.long 0x24 "CFSR,Configurable Fault Status Register"
|
|
bitfld.long 0x24 25. "DIVBYZERO,Divide by zero flag" "0,1"
|
|
bitfld.long 0x24 24. "UNALIGNED,Unaligned access flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 20. "STKOF,Stack overflow flag" "0,1"
|
|
bitfld.long 0x24 19. "NOCP,No coprocessor flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 18. "INVPC,Invalid PC flag" "0,1"
|
|
bitfld.long 0x24 17. "INVSTATE,Invalid state flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 16. "UNDEFINSTR,Undefined instruction flag" "0,1"
|
|
bitfld.long 0x24 15. "BFARVALID,BFAR valid" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "LSPERR,Lazy state preservation error" "0,1"
|
|
bitfld.long 0x24 12. "STKERR,Stack error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 11. "UNSTKERR,Unstack error" "0,1"
|
|
bitfld.long 0x24 10. "IMPRECISERR,Imprecise error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 9. "PRECISERR,Precise error" "0,1"
|
|
bitfld.long 0x24 8. "IBUSERR,Instruction bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "MMFARVALID,MMFAR valid flag" "0,1"
|
|
bitfld.long 0x24 5. "MLSPERR,MemManage lazy state preservation error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "MSTKERR,MemManage stacking error flag" "0,1"
|
|
bitfld.long 0x24 3. "MUNSTKERR,MemManage unstacking error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "DACCVIOL,Data access violation flag" "0,1"
|
|
bitfld.long 0x24 0. "IACCVIOL,Instruction access violation flag" "0,1"
|
|
group.byte 0x28++0x1
|
|
line.byte 0x0 "MMFSR,MemManage Fault Status Register"
|
|
bitfld.byte 0x0 7. "MMFARVALID,MMFAR valid flag" "0,1"
|
|
bitfld.byte 0x0 5. "MLSPERR,MemManage lazy state preservation error flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "MSTKERR,MemManage stacking error flag" "0,1"
|
|
bitfld.byte 0x0 3. "MUNSTKERR,MemManage unstacking error flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DACCVIOL,Data access violation flag" "0,1"
|
|
bitfld.byte 0x0 0. "IACCVIOL,Instruction access violation flag" "0,1"
|
|
line.byte 0x1 "BFSR,BusFault Status Register"
|
|
bitfld.byte 0x1 7. "BFARVALID,BFAR valid" "0,1"
|
|
bitfld.byte 0x1 5. "LSPERR,Lazy state preservation error" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "STKERR,Stack error" "0,1"
|
|
bitfld.byte 0x1 3. "UNSTKERR,Unstack error" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "IMPRECISERR,Imprecise error" "0,1"
|
|
bitfld.byte 0x1 1. "PRECISERR,Precise error" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "IBUSERR,Instruction bus error" "0,1"
|
|
group.word 0x2A++0x1
|
|
line.word 0x0 "UFSR,UsageFault Status Register"
|
|
bitfld.word 0x0 9. "DIVBYZERO,Divide by zero flag" "0,1"
|
|
bitfld.word 0x0 8. "UNALIGNED,Unaligned access flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "STKOF,Stack overflow flag" "0,1"
|
|
bitfld.word 0x0 3. "NOCP,No coprocessor flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INVPC,Invalid PC flag" "0,1"
|
|
bitfld.word 0x0 1. "INVSTATE,Invalid state flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "UNDEFINSTR,Undefined instruction flag" "0,1"
|
|
group.long 0x2C++0x13
|
|
line.long 0x0 "HFSR,HardFault Status Register"
|
|
bitfld.long 0x0 31. "DEBUGEVT,Debug event" "0,1"
|
|
bitfld.long 0x0 30. "FORCED,Forced configurable-priority exception escalated to HardFault" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VECTTBL,Vector table read error" "0,1"
|
|
line.long 0x4 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x4 4. "EXTERNAL,External event" "0,1"
|
|
bitfld.long 0x4 3. "VCATCH,Vector Catch event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DWTTRAP,Watchpoint event" "0,1"
|
|
bitfld.long 0x4 1. "BKPT,Breakpoint event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HALTED,Halt or step event" "0,1"
|
|
line.long 0x8 "MMFAR,MemManage Fault Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDRESS,Data address for a MemManage fault"
|
|
line.long 0xC "BFAR,BusFault Address Register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRESS,Data address for a precise BusFault"
|
|
line.long 0x10 "AFSR,Auxiliary Fault Status Register"
|
|
rgroup.long 0x40++0x43
|
|
line.long 0x0 "ID_PFR0,Processor Feature Register 0"
|
|
hexmask.long.byte 0x0 4.--7. 1. "State1,State one T32 instruction set support"
|
|
hexmask.long.byte 0x0 0.--3. 1. "State0,State two A32 instruction set support"
|
|
line.long 0x4 "ID_PFR1,Processor Feature Register 1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MProgMod,M programmer's model"
|
|
hexmask.long.byte 0x4 4.--7. 1. "Security,Security Extension implemented"
|
|
line.long 0x8 "ID_DFR0,Debug Feature Register 0"
|
|
hexmask.long.byte 0x8 20.--23. 1. "MProgDbg,M-profile debug"
|
|
line.long 0xC "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long.byte 0xC 12.--15. 1. "IMPDEF3,Implementation defined feature 3"
|
|
hexmask.long.byte 0xC 8.--11. 1. "IMPDEF2,Implementation defined feature 2"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "IMPDEF1,Implementation defined feature 1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "IMPDEF0,Implementation defined feature 0"
|
|
line.long 0x10 "ID_MMFR0,Memory Model Feature Register 0"
|
|
hexmask.long.byte 0x10 20.--23. 1. "AuxReg,Auxiliary Registers"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TCM,Tightly Coupled Memories"
|
|
newline
|
|
hexmask.long.byte 0x10 12.--15. 1. "ShareLvl,Shareability Levels"
|
|
hexmask.long.byte 0x10 8.--11. 1. "OuterShr,Outermost Shareability"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "PMSA,Protected Memory System Architecture"
|
|
line.long 0x14 "ID_MMFR1,Memory Model Feature Register 1"
|
|
line.long 0x18 "ID_MMFR2,Memory Model Feature Register 2"
|
|
hexmask.long.byte 0x18 24.--27. 1. "WFIStall,Wait For Interrupt stalling"
|
|
line.long 0x1C "ID_MMFR3,Memory Model Feature Register 3"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "BPMaint,Branch predictor maintenance"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "CMaintSW,Cache maintenance set/way"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "CMaintVA,Cache maintenance by address"
|
|
line.long 0x20 "ID_ISAR0,Instruction Set Attribute Register 0"
|
|
hexmask.long.byte 0x20 24.--27. 1. "Divide,Divide instructions"
|
|
hexmask.long.byte 0x20 20.--23. 1. "Debug,Debug instructions"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--19. 1. "Coproc,Coprocessor instructions"
|
|
hexmask.long.byte 0x20 12.--15. 1. "CmpBranch,Compare and Branch instructions"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--11. 1. "BitField,Bit field instructions"
|
|
hexmask.long.byte 0x20 4.--7. 1. "BitCount,Bit count instructions"
|
|
line.long 0x24 "ID_ISAR1,Instruction Set Attribute Register 1"
|
|
hexmask.long.byte 0x24 24.--27. 1. "Interwork,Interworking instructions"
|
|
hexmask.long.byte 0x24 20.--23. 1. "Immediate,Data-processing instructions with long immediates"
|
|
newline
|
|
hexmask.long.byte 0x24 16.--19. 1. "IfThen,If-Then instructions"
|
|
hexmask.long.byte 0x24 12.--15. 1. "Extend,Extend instructions"
|
|
line.long 0x28 "ID_ISAR2,Instruction Set Attribute Register 2"
|
|
hexmask.long.byte 0x28 28.--31. 1. "Reversal,Reversal instructions"
|
|
hexmask.long.byte 0x28 20.--23. 1. "MultU,Advanced unsigned Multiply instructions"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "MultS,Advanced signed Multiply instructions"
|
|
hexmask.long.byte 0x28 12.--15. 1. "Mult,Additional Multiply instructions"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--11. 1. "MultiAccessInt,Interruptible multi-access instructions"
|
|
hexmask.long.byte 0x28 4.--7. 1. "MemHint,Memory hint instructions"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--3. 1. "LoadStore,Additional load/store instructions"
|
|
line.long 0x2C "ID_ISAR3,Instruction Set Attribute Register 3"
|
|
hexmask.long.byte 0x2C 24.--27. 1. "TrueNOP,True NOP instructions"
|
|
hexmask.long.byte 0x2C 20.--23. 1. "T32Copy,T32 non flag-setting MOV instructions"
|
|
newline
|
|
hexmask.long.byte 0x2C 16.--19. 1. "TabBranch,Table Branch instructions"
|
|
hexmask.long.byte 0x2C 12.--15. 1. "SynchPrim,Synchronization primitive instructions"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--11. 1. "SVC,Supervisor Call instructions"
|
|
hexmask.long.byte 0x2C 4.--7. 1. "SIMD,Single-instruction multiple-data instructions"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--3. 1. "Saturate,Saturating instructions"
|
|
line.long 0x30 "ID_ISAR4,Instruction Set Attribute Register 4"
|
|
hexmask.long.byte 0x30 24.--27. 1. "PSR_M,M profile instructions to modify the Program Status Registers"
|
|
hexmask.long.byte 0x30 20.--23. 1. "SyncPrim_frac,Synchronization primitives fractional instructions"
|
|
newline
|
|
hexmask.long.byte 0x30 16.--19. 1. "Barrier,Barrier instructions"
|
|
hexmask.long.byte 0x30 8.--11. 1. "Writeback,Writeback addressing modes"
|
|
newline
|
|
hexmask.long.byte 0x30 4.--7. 1. "WithShifts,Constant shifts instructions"
|
|
hexmask.long.byte 0x30 0.--3. 1. "Unpriv,Unprivileged instructions"
|
|
line.long 0x34 "ID_ISAR5,Instruction Set Attribute Register 5"
|
|
line.long 0x38 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x38 30.--31. "ICB,Inner cache boundary" "0: Not disclosed in this mechanism,1: L1 cache is the highest inner level,2: L2 cache is the highest inner level,3: L3 cache is the highest inner level"
|
|
bitfld.long 0x38 27.--29. "LoUU,Level of Unification Uniprocessor" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 24.--26. "LoC,Level of Coherence" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 21.--23. "LoUIS,Level of Unification Inner Shareable" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 18.--20. "Ctype7,Cache type at level 7" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
bitfld.long 0x38 15.--17. "Ctype6,Cache type at level 6" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
newline
|
|
bitfld.long 0x38 12.--14. "Ctype5,Cache type at level 5" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
bitfld.long 0x38 9.--11. "Ctype4,Cache type at level 4" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
newline
|
|
bitfld.long 0x38 6.--8. "Ctype3,Cache type at level 3" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
bitfld.long 0x38 3.--5. "Ctype2,Cache type at level 2" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
newline
|
|
bitfld.long 0x38 0.--2. "Ctype1,Cache type at level 1" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
line.long 0x3C "CTR,Cache Type Register"
|
|
bitfld.long 0x3C 29.--31. "Format,Cache Type Register format" "0: No cache type information provided,?,?,?,4: Cache type information is provided,?,?,?"
|
|
hexmask.long.byte 0x3C 24.--27. 1. "CWG,Cache Write-back Granule"
|
|
newline
|
|
hexmask.long.byte 0x3C 20.--23. 1. "ERG,Exclusives Reservation Granule"
|
|
hexmask.long.byte 0x3C 16.--19. 1. "DminLine,Data cache minimum line length"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--3. 1. "IminLine,Instruction cache minimum line length"
|
|
line.long 0x40 "CCSIDR,Current Cache Size ID register"
|
|
bitfld.long 0x40 31. "WT,Write-Through" "0,1"
|
|
bitfld.long 0x40 30. "WB,Write-Back" "0,1"
|
|
newline
|
|
bitfld.long 0x40 29. "RA,Read-Allocate" "0,1"
|
|
bitfld.long 0x40 28. "WA,Write-Allocate" "0,1"
|
|
newline
|
|
hexmask.long.word 0x40 13.--27. 1. "NumSets,Number of sets - 1"
|
|
hexmask.long.word 0x40 3.--12. 1. "Associativity,Associativity - 1"
|
|
newline
|
|
bitfld.long 0x40 0.--2. "LineSize,log2(number of words per line) - 2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x84++0xB
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x0 1.--3. "Level,Cache level - 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "InD,Instruction not Data" "0,1"
|
|
line.long 0x4 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x4 22.--23. "CP11,CP11 Privilege" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "CP10,Floating-point Extension access rights" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "CP7,Coprocessor 7 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "CP6,Coprocessor 6 privilege" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CP5,Coprocessor 5 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "CP4,Coprocessor 4 privilege" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "CP3,Coprocessor 3 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "CP2,Coprocessor 2 privilege" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "CP1,Coprocessor 1 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CP0,Coprocessor 0 privilege" "0,1,2,3"
|
|
line.long 0x8 "NSACR,Non-secure Access Control Register"
|
|
bitfld.long 0x8 11. "CP11,CP11 Non-secure" "0,1"
|
|
bitfld.long 0x8 10. "CP10,Floating-point Extension Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "CP7,Coprocessor 7 Non-secure" "0,1"
|
|
bitfld.long 0x8 6. "CP6,Coprocessor 6 Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CP5,Coprocessor 5 Non-secure" "0,1"
|
|
bitfld.long 0x8 4. "CP4,Coprocessor 4 Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CP3,Coprocessor 3 Non-secure" "0,1"
|
|
bitfld.long 0x8 2. "CP2,Coprocessor 2 Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CP1,Coprocessor 1 Non-secure" "0,1"
|
|
bitfld.long 0x8 0. "CP0,Coprocessor 0 Non-secure" "0,1"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "SCB_NS (System Control Block (Non-Secure))"
|
|
base ad:0xE002ED00
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "CPUID,CPUID base register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "Implementer,Implementer code ARM=0x41"
|
|
hexmask.long.byte 0x0 20.--23. 1. "Variant,Variant number"
|
|
newline
|
|
hexmask.long.byte 0x0 16.--19. 1. "Architecture,Architecture version 0xC=ARMv8-M Base Line 0xF=ARMv8-M Main Line"
|
|
hexmask.long.word 0x0 4.--15. 1. "PartNo,Part number 0xD20=Cortex-M23"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "Revision,Revision number"
|
|
group.long 0x4++0x27
|
|
line.long 0x0 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x0 31. "PENDNMISET,Pend NMI set" "0: Write: no effect; read: NMI exception is not..,1: Write: changes NMI exception state to pending;.."
|
|
bitfld.long 0x0 30. "PENDNMICLR,Pend NMI clear" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "PENDSVSET,Pend PendSV set" "0: Write: no effect; read: PendSV exception is not..,1: Write: changes PendSV exception state to.."
|
|
bitfld.long 0x0 27. "PENDSVCLR,Pend PendSV clear" "0: No effect,1: Removes the pending state from the PendSV.."
|
|
newline
|
|
bitfld.long 0x0 26. "PENDSTSET,Pend SysTick set" "0: Write: no effect; read: SysTick exception is not..,1: Write: changes SysTick exception state to.."
|
|
bitfld.long 0x0 25. "PENDSTCLR,Pend SysTick clear" "0: No effect,1: Removes the pending state from the SysTick.."
|
|
newline
|
|
bitfld.long 0x0 23. "ISRPREEMPT,Interrupt preempt" "0,1"
|
|
bitfld.long 0x0 22. "ISRPENDING,Interrupt pending" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 12.--20. 1. "VECTPENDING,Vector pending"
|
|
bitfld.long 0x0 11. "RETTOBASE,Return to base" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--8. 1. "VECTACTIVE,Vector active"
|
|
line.long 0x4 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x4 7.--31. 1. "TBLOFF,Vector table base offset"
|
|
line.long 0x8 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x8 16.--31. 1. "VECTKEY,Register Key (0x05FA)"
|
|
bitfld.long 0x8 15. "ENDIANNESS,Data Endianness 0=little 1=big" "0: little,1: big"
|
|
newline
|
|
bitfld.long 0x8 14. "PRIS,Prioritize Secure Exceptions" "0: Priority ranges of Secure and Non-secure..,1: Non-secure exceptions are de-prioritized"
|
|
bitfld.long 0x8 13. "BFHFNMINS,BusFault HardFault and NMI Non-secure enable" "0: BusFault HardFault and NMI are Secure,1: BusFault and NMI are Non-secure and exceptions.."
|
|
newline
|
|
bitfld.long 0x8 3. "SYSRESETREQS,System Reset Request Secure only" "0: SYSRESETREQ functionality is available to both..,1: SYSRESETREQ functionality is only available to.."
|
|
bitfld.long 0x8 2. "SYSRESETREQ,System Reset Request" "0: Do not request a system reset,1: Request a system reset"
|
|
newline
|
|
bitfld.long 0x8 1. "VECTCLRACTIVE,Debug: Clear Active State" "0: Do not clear active state,1: Clear active state"
|
|
line.long 0xC "SCR,System Control Register"
|
|
bitfld.long 0xC 4. "SEVONPEND,Send Event on Pending bit" "0: Only enabled interrupts or events can wakeup the..,1: Enabled events and all interrupts including.."
|
|
bitfld.long 0xC 3. "SLEEPDEEPS,Sleep deep secure" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "SLEEPDEEP,Sleep deep" "0: Sleep,1: Deep sleep"
|
|
bitfld.long 0xC 1. "SLEEPONEXIT,Sleep on exit" "0: O not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an ISR"
|
|
line.long 0x10 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x10 18. "BP,Branch prediction enable" "0,1"
|
|
bitfld.long 0x10 17. "IC,Instruction cache enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 16. "DC,Data cache enable" "0,1"
|
|
bitfld.long 0x10 10. "STKOFHFNMIGN,Stack overflow in HardFault and NMI ignore" "0,1"
|
|
newline
|
|
bitfld.long 0x10 8. "BFHFNMIGN,BusFault in HardFault or NMI ignore" "0,1"
|
|
bitfld.long 0x10 4. "DIV_0_TRP,Divide by zero trap" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "UNALIGN_TRP,Unaligned trap" "0: Do not trap unaligned halfword and word accesses,1: Trap unaligned halfword and word accesses"
|
|
bitfld.long 0x10 1. "USERSETMPEND,User set main pending" "0,1"
|
|
line.long 0x14 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. "PRI_7,Priority of system handler 7 SecureFault"
|
|
hexmask.long.byte 0x14 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
|
|
hexmask.long.byte 0x14 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick"
|
|
hexmask.long.byte 0x1C 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--7. 1. "PRI_12,Priority of system handler 12 DebugMonitor"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 21. "HARDFAULTPENDED,HardFault exception pended state" "0,1"
|
|
bitfld.long 0x20 15. "SVCALLPENDED,SVCall exception pended state" "0,1"
|
|
newline
|
|
bitfld.long 0x20 11. "SYSTICKACT,SysTick exception active state" "0,1"
|
|
bitfld.long 0x20 10. "PENDSVACT,PendSV exception active state" "0,1"
|
|
newline
|
|
bitfld.long 0x20 7. "SVCALLACT,SVCall exception active state" "0,1"
|
|
bitfld.long 0x20 5. "NMIACT,NMI exception active state" "0,1"
|
|
newline
|
|
bitfld.long 0x20 2. "HARDFAULTACT,HardFault exception active state" "0,1"
|
|
line.long 0x24 "CFSR,Configurable Fault Status Register"
|
|
bitfld.long 0x24 25. "DIVBYZERO,Divide by zero flag" "0,1"
|
|
bitfld.long 0x24 24. "UNALIGNED,Unaligned access flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 20. "STKOF,Stack overflow flag" "0,1"
|
|
bitfld.long 0x24 19. "NOCP,No coprocessor flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 18. "INVPC,Invalid PC flag" "0,1"
|
|
bitfld.long 0x24 17. "INVSTATE,Invalid state flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 16. "UNDEFINSTR,Undefined instruction flag" "0,1"
|
|
bitfld.long 0x24 15. "BFARVALID,BFAR valid" "0,1"
|
|
newline
|
|
bitfld.long 0x24 13. "LSPERR,Lazy state preservation error" "0,1"
|
|
bitfld.long 0x24 12. "STKERR,Stack error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 11. "UNSTKERR,Unstack error" "0,1"
|
|
bitfld.long 0x24 10. "IMPRECISERR,Imprecise error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 9. "PRECISERR,Precise error" "0,1"
|
|
bitfld.long 0x24 8. "IBUSERR,Instruction bus error" "0,1"
|
|
newline
|
|
bitfld.long 0x24 7. "MMFARVALID,MMFAR valid flag" "0,1"
|
|
bitfld.long 0x24 5. "MLSPERR,MemManage lazy state preservation error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 4. "MSTKERR,MemManage stacking error flag" "0,1"
|
|
bitfld.long 0x24 3. "MUNSTKERR,MemManage unstacking error flag" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "DACCVIOL,Data access violation flag" "0,1"
|
|
bitfld.long 0x24 0. "IACCVIOL,Instruction access violation flag" "0,1"
|
|
group.byte 0x28++0x1
|
|
line.byte 0x0 "MMFSR,MemManage Fault Status Register"
|
|
bitfld.byte 0x0 7. "MMFARVALID,MMFAR valid flag" "0,1"
|
|
bitfld.byte 0x0 5. "MLSPERR,MemManage lazy state preservation error flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "MSTKERR,MemManage stacking error flag" "0,1"
|
|
bitfld.byte 0x0 3. "MUNSTKERR,MemManage unstacking error flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "DACCVIOL,Data access violation flag" "0,1"
|
|
bitfld.byte 0x0 0. "IACCVIOL,Instruction access violation flag" "0,1"
|
|
line.byte 0x1 "BFSR,BusFault Status Register"
|
|
bitfld.byte 0x1 7. "BFARVALID,BFAR valid" "0,1"
|
|
bitfld.byte 0x1 5. "LSPERR,Lazy state preservation error" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "STKERR,Stack error" "0,1"
|
|
bitfld.byte 0x1 3. "UNSTKERR,Unstack error" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "IMPRECISERR,Imprecise error" "0,1"
|
|
bitfld.byte 0x1 1. "PRECISERR,Precise error" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "IBUSERR,Instruction bus error" "0,1"
|
|
group.word 0x2A++0x1
|
|
line.word 0x0 "UFSR,UsageFault Status Register"
|
|
bitfld.word 0x0 9. "DIVBYZERO,Divide by zero flag" "0,1"
|
|
bitfld.word 0x0 8. "UNALIGNED,Unaligned access flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "STKOF,Stack overflow flag" "0,1"
|
|
bitfld.word 0x0 3. "NOCP,No coprocessor flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "INVPC,Invalid PC flag" "0,1"
|
|
bitfld.word 0x0 1. "INVSTATE,Invalid state flag" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "UNDEFINSTR,Undefined instruction flag" "0,1"
|
|
group.long 0x2C++0x13
|
|
line.long 0x0 "HFSR,HardFault Status Register"
|
|
bitfld.long 0x0 31. "DEBUGEVT,Debug event" "0,1"
|
|
bitfld.long 0x0 30. "FORCED,Forced configurable-priority exception escalated to HardFault" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "VECTTBL,Vector table read error" "0,1"
|
|
line.long 0x4 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x4 4. "EXTERNAL,External event" "0,1"
|
|
bitfld.long 0x4 3. "VCATCH,Vector Catch event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "DWTTRAP,Watchpoint event" "0,1"
|
|
bitfld.long 0x4 1. "BKPT,Breakpoint event" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "HALTED,Halt or step event" "0,1"
|
|
line.long 0x8 "MMFAR,MemManage Fault Address Register"
|
|
hexmask.long 0x8 0.--31. 1. "ADDRESS,Data address for a MemManage fault"
|
|
line.long 0xC "BFAR,BusFault Address Register"
|
|
hexmask.long 0xC 0.--31. 1. "ADDRESS,Data address for a precise BusFault"
|
|
line.long 0x10 "AFSR,Auxiliary Fault Status Register"
|
|
rgroup.long 0x40++0x43
|
|
line.long 0x0 "ID_PFR0,Processor Feature Register 0"
|
|
hexmask.long.byte 0x0 4.--7. 1. "State1,State one T32 instruction set support"
|
|
hexmask.long.byte 0x0 0.--3. 1. "State0,State two A32 instruction set support"
|
|
line.long 0x4 "ID_PFR1,Processor Feature Register 1"
|
|
hexmask.long.byte 0x4 8.--11. 1. "MProgMod,M programmer's model"
|
|
hexmask.long.byte 0x4 4.--7. 1. "Security,Security Extension implemented"
|
|
line.long 0x8 "ID_DFR0,Debug Feature Register 0"
|
|
hexmask.long.byte 0x8 20.--23. 1. "MProgDbg,M-profile debug"
|
|
line.long 0xC "ID_AFR0,Auxiliary Feature Register 0"
|
|
hexmask.long.byte 0xC 12.--15. 1. "IMPDEF3,Implementation defined feature 3"
|
|
hexmask.long.byte 0xC 8.--11. 1. "IMPDEF2,Implementation defined feature 2"
|
|
newline
|
|
hexmask.long.byte 0xC 4.--7. 1. "IMPDEF1,Implementation defined feature 1"
|
|
hexmask.long.byte 0xC 0.--3. 1. "IMPDEF0,Implementation defined feature 0"
|
|
line.long 0x10 "ID_MMFR0,Memory Model Feature Register 0"
|
|
hexmask.long.byte 0x10 20.--23. 1. "AuxReg,Auxiliary Registers"
|
|
hexmask.long.byte 0x10 16.--19. 1. "TCM,Tightly Coupled Memories"
|
|
newline
|
|
hexmask.long.byte 0x10 12.--15. 1. "ShareLvl,Shareability Levels"
|
|
hexmask.long.byte 0x10 8.--11. 1. "OuterShr,Outermost Shareability"
|
|
newline
|
|
hexmask.long.byte 0x10 4.--7. 1. "PMSA,Protected Memory System Architecture"
|
|
line.long 0x14 "ID_MMFR1,Memory Model Feature Register 1"
|
|
line.long 0x18 "ID_MMFR2,Memory Model Feature Register 2"
|
|
hexmask.long.byte 0x18 24.--27. 1. "WFIStall,Wait For Interrupt stalling"
|
|
line.long 0x1C "ID_MMFR3,Memory Model Feature Register 3"
|
|
hexmask.long.byte 0x1C 8.--11. 1. "BPMaint,Branch predictor maintenance"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "CMaintSW,Cache maintenance set/way"
|
|
newline
|
|
hexmask.long.byte 0x1C 0.--3. 1. "CMaintVA,Cache maintenance by address"
|
|
line.long 0x20 "ID_ISAR0,Instruction Set Attribute Register 0"
|
|
hexmask.long.byte 0x20 24.--27. 1. "Divide,Divide instructions"
|
|
hexmask.long.byte 0x20 20.--23. 1. "Debug,Debug instructions"
|
|
newline
|
|
hexmask.long.byte 0x20 16.--19. 1. "Coproc,Coprocessor instructions"
|
|
hexmask.long.byte 0x20 12.--15. 1. "CmpBranch,Compare and Branch instructions"
|
|
newline
|
|
hexmask.long.byte 0x20 8.--11. 1. "BitField,Bit field instructions"
|
|
hexmask.long.byte 0x20 4.--7. 1. "BitCount,Bit count instructions"
|
|
line.long 0x24 "ID_ISAR1,Instruction Set Attribute Register 1"
|
|
hexmask.long.byte 0x24 24.--27. 1. "Interwork,Interworking instructions"
|
|
hexmask.long.byte 0x24 20.--23. 1. "Immediate,Data-processing instructions with long immediates"
|
|
newline
|
|
hexmask.long.byte 0x24 16.--19. 1. "IfThen,If-Then instructions"
|
|
hexmask.long.byte 0x24 12.--15. 1. "Extend,Extend instructions"
|
|
line.long 0x28 "ID_ISAR2,Instruction Set Attribute Register 2"
|
|
hexmask.long.byte 0x28 28.--31. 1. "Reversal,Reversal instructions"
|
|
hexmask.long.byte 0x28 20.--23. 1. "MultU,Advanced unsigned Multiply instructions"
|
|
newline
|
|
hexmask.long.byte 0x28 16.--19. 1. "MultS,Advanced signed Multiply instructions"
|
|
hexmask.long.byte 0x28 12.--15. 1. "Mult,Additional Multiply instructions"
|
|
newline
|
|
hexmask.long.byte 0x28 8.--11. 1. "MultiAccessInt,Interruptible multi-access instructions"
|
|
hexmask.long.byte 0x28 4.--7. 1. "MemHint,Memory hint instructions"
|
|
newline
|
|
hexmask.long.byte 0x28 0.--3. 1. "LoadStore,Additional load/store instructions"
|
|
line.long 0x2C "ID_ISAR3,Instruction Set Attribute Register 3"
|
|
hexmask.long.byte 0x2C 24.--27. 1. "TrueNOP,True NOP instructions"
|
|
hexmask.long.byte 0x2C 20.--23. 1. "T32Copy,T32 non flag-setting MOV instructions"
|
|
newline
|
|
hexmask.long.byte 0x2C 16.--19. 1. "TabBranch,Table Branch instructions"
|
|
hexmask.long.byte 0x2C 12.--15. 1. "SynchPrim,Synchronization primitive instructions"
|
|
newline
|
|
hexmask.long.byte 0x2C 8.--11. 1. "SVC,Supervisor Call instructions"
|
|
hexmask.long.byte 0x2C 4.--7. 1. "SIMD,Single-instruction multiple-data instructions"
|
|
newline
|
|
hexmask.long.byte 0x2C 0.--3. 1. "Saturate,Saturating instructions"
|
|
line.long 0x30 "ID_ISAR4,Instruction Set Attribute Register 4"
|
|
hexmask.long.byte 0x30 24.--27. 1. "PSR_M,M profile instructions to modify the Program Status Registers"
|
|
hexmask.long.byte 0x30 20.--23. 1. "SyncPrim_frac,Synchronization primitives fractional instructions"
|
|
newline
|
|
hexmask.long.byte 0x30 16.--19. 1. "Barrier,Barrier instructions"
|
|
hexmask.long.byte 0x30 8.--11. 1. "Writeback,Writeback addressing modes"
|
|
newline
|
|
hexmask.long.byte 0x30 4.--7. 1. "WithShifts,Constant shifts instructions"
|
|
hexmask.long.byte 0x30 0.--3. 1. "Unpriv,Unprivileged instructions"
|
|
line.long 0x34 "ID_ISAR5,Instruction Set Attribute Register 5"
|
|
line.long 0x38 "CLIDR,Cache Level ID Register"
|
|
bitfld.long 0x38 30.--31. "ICB,Inner cache boundary" "0: Not disclosed in this mechanism,1: L1 cache is the highest inner level,2: L2 cache is the highest inner level,3: L3 cache is the highest inner level"
|
|
bitfld.long 0x38 27.--29. "LoUU,Level of Unification Uniprocessor" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 24.--26. "LoC,Level of Coherence" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x38 21.--23. "LoUIS,Level of Unification Inner Shareable" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x38 18.--20. "Ctype7,Cache type at level 7" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
bitfld.long 0x38 15.--17. "Ctype6,Cache type at level 6" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
newline
|
|
bitfld.long 0x38 12.--14. "Ctype5,Cache type at level 5" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
bitfld.long 0x38 9.--11. "Ctype4,Cache type at level 4" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
newline
|
|
bitfld.long 0x38 6.--8. "Ctype3,Cache type at level 3" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
bitfld.long 0x38 3.--5. "Ctype2,Cache type at level 2" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
newline
|
|
bitfld.long 0x38 0.--2. "Ctype1,Cache type at level 1" "0: No cache,1: Instruction cache only,2: Data cache only,3: Separate instruction and data caches,4: Unified cache,?,?,?"
|
|
line.long 0x3C "CTR,Cache Type Register"
|
|
bitfld.long 0x3C 29.--31. "Format,Cache Type Register format" "0: No cache type information provided,?,?,?,4: Cache type information is provided,?,?,?"
|
|
hexmask.long.byte 0x3C 24.--27. 1. "CWG,Cache Write-back Granule"
|
|
newline
|
|
hexmask.long.byte 0x3C 20.--23. 1. "ERG,Exclusives Reservation Granule"
|
|
hexmask.long.byte 0x3C 16.--19. 1. "DminLine,Data cache minimum line length"
|
|
newline
|
|
hexmask.long.byte 0x3C 0.--3. 1. "IminLine,Instruction cache minimum line length"
|
|
line.long 0x40 "CCSIDR,Current Cache Size ID register"
|
|
bitfld.long 0x40 31. "WT,Write-Through" "0,1"
|
|
bitfld.long 0x40 30. "WB,Write-Back" "0,1"
|
|
newline
|
|
bitfld.long 0x40 29. "RA,Read-Allocate" "0,1"
|
|
bitfld.long 0x40 28. "WA,Write-Allocate" "0,1"
|
|
newline
|
|
hexmask.long.word 0x40 13.--27. 1. "NumSets,Number of sets - 1"
|
|
hexmask.long.word 0x40 3.--12. 1. "Associativity,Associativity - 1"
|
|
newline
|
|
bitfld.long 0x40 0.--2. "LineSize,log2(number of words per line) - 2" "0,1,2,3,4,5,6,7"
|
|
group.long 0x84++0xB
|
|
line.long 0x0 "CSSELR,Cache Size Selection Register"
|
|
bitfld.long 0x0 1.--3. "Level,Cache level - 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x0 0. "InD,Instruction not Data" "0,1"
|
|
line.long 0x4 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x4 22.--23. "CP11,CP11 Privilege" "0,1,2,3"
|
|
bitfld.long 0x4 20.--21. "CP10,Floating-point Extension access rights" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "CP7,Coprocessor 7 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 12.--13. "CP6,Coprocessor 6 privilege" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CP5,Coprocessor 5 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 8.--9. "CP4,Coprocessor 4 privilege" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 6.--7. "CP3,Coprocessor 3 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 4.--5. "CP2,Coprocessor 2 privilege" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x4 2.--3. "CP1,Coprocessor 1 privilege" "0,1,2,3"
|
|
bitfld.long 0x4 0.--1. "CP0,Coprocessor 0 privilege" "0,1,2,3"
|
|
line.long 0x8 "NSACR,Non-secure Access Control Register"
|
|
bitfld.long 0x8 11. "CP11,CP11 Non-secure" "0,1"
|
|
bitfld.long 0x8 10. "CP10,Floating-point Extension Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 7. "CP7,Coprocessor 7 Non-secure" "0,1"
|
|
bitfld.long 0x8 6. "CP6,Coprocessor 6 Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "CP5,Coprocessor 5 Non-secure" "0,1"
|
|
bitfld.long 0x8 4. "CP4,Coprocessor 4 Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "CP3,Coprocessor 3 Non-secure" "0,1"
|
|
bitfld.long 0x8 2. "CP2,Coprocessor 2 Non-secure" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "CP1,Coprocessor 1 Non-secure" "0,1"
|
|
bitfld.long 0x8 0. "CP0,Coprocessor 0 Non-secure" "0,1"
|
|
tree.end
|
|
endif
|
|
tree "SDMMC (SD/MMC Host Controller)"
|
|
base ad:0x0
|
|
tree "SDMMC0"
|
|
base ad:0x45026000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4k bytes,1: 8k bytes,2: 16k bytes,3: 32k bytes,4: 64k bytes,5: 128k bytes,6: 256k bytes,7: 512k bytes"
|
|
hexmask.word 0x0 0.--9. 1. "BLOCKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count"
|
|
hexmask.word 0x2 0.--15. 1. "BCNT,Blocks Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARG,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0: Single Block,1: Multiple Block"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Write (Host to Card),1: Read (Card to Host)"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enable,2: Auto CMD23 Enable,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: No data transfer or Non DMA data transfer,1: DMA data transfer"
|
|
line.word 0x2 "CR,Command"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 for writing Bus Suspend in CCCR,2: CMD52 for writing Function Select in CCCR,3: CMD12 CMD52 for writing I/O Abort in CCCR"
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|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0: No Data Present,1: Data Present"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: Disable,1: Enable"
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No response,1: 136-bit response,2: 48-bit response,3: 48-bit response check busy after response"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0: Write protected (SDWP#=0),1: Write enabled (SDWP#=1)"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0: No card present (SDCD#=1),1: Card present (SDCD#=0)"
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0: Reset or Debouncing,1: No Card or Insered"
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0: Reset or Debouncing or No Card,1: Card inserted"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0: Read disable,1: Read enable"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0: Write disable,1: Write enable"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0: No valid data,1: Transferring data"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0: No valid data,1: Transferring data"
|
|
newline
|
|
bitfld.long 0x0 3. "RTREQ,Re-Tuning Request" "0: Fixed or well-tuned sampling clock,1: Sampling clock needs re-tuning"
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0: DAT Line Inactive,1: DAT Line Active"
|
|
newline
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0: Can issue command which uses the DAT line,1: Cannot issue command which uses the DAT line"
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R,Host Control 1"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0: SDCD# is selected (for normal use),1: The Card Select Test Level is selected (for test.."
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0: No Card,1: Card Inserted"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode,1: High Speed mode"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode,1: 4-bit mode"
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off,1: LED on"
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_EMMC_MODE,Host Control 1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode,1: High Speed mode"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode,1: 4-bit mode"
|
|
line.byte 0x1 "PCR,Power Control"
|
|
bitfld.byte 0x1 1.--3. "SDBVSEL,SD Bus Voltage Select" "?,?,?,?,?,5: 1.8V (Typ.),6: 3.0V (Typ.),7: 3.3V (Typ.)"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0: Power off,1: Power on"
|
|
line.byte 0x2 "BGCR,Block Gap Control"
|
|
bitfld.byte 0x2 3. "INTBG,Interrupt at Block Gap" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x2 2. "RWCTRL,Read Wait Control" "0: Disable Read Wait Control,1: Enable Read Wait Control"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0: Not affected,1: Restart"
|
|
bitfld.byte 0x2 0. "STPBGR,Stop at Block Gap Request" "0: Transfer,1: Stop"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_EMMC_MODE,Block Gap Control"
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0: Not affected,1: Restart"
|
|
bitfld.byte 0x0 0. "STPBGR,Stop at Block Gap Request" "0: Transfer,1: Stop"
|
|
line.byte 0x1 "WCR,Wakeup Control"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Disable,1: Enable"
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Disable,1: Enable"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0: Divided Clock Mode,1: Programmable Clock Mode"
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0: Not Ready,1: Ready"
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0: Stop,1: Oscillate"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software Reset For DAT Line" "0: Work,1: Reset"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software Reset For CMD Line" "0: Work,1: Reset"
|
|
newline
|
|
bitfld.byte 0x1 0. "SWRSTALL,Software Reset For All" "0: Work,1: Reset"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "NISTR,Normal Interrupt Status"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No Error,1: Error"
|
|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0: No Card Interrupt,1: Generate Card Interrupt"
|
|
newline
|
|
bitfld.word 0x0 7. "CREM,Card Removal" "0: Card state stable or Debouncing,1: Card Removed"
|
|
bitfld.word 0x0 6. "CINS,Card Insertion" "0: Card state stable or Debouncing,1: Card inserted"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No Block Gap Event,1: Transaction stopped at block gap"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Not complete,1: Command execution is completed"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete,1: Command complete"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "NISTR_EMMC_MODE,Normal Interrupt Status"
|
|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No Error,1: Error"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No Block Gap Event,1: Transaction stopped at block gap"
|
|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Not complete,1: Command execution is completed"
|
|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete,1: Command complete"
|
|
line.word 0x2 "EISTR,Error Interrupt Status"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0: No Error,1: Error"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0: No Error,1: Error"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0: No Error,1: Power Fail"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0: No Error,1: Error"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error" "0: No Error,1: Error"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error" "0: No Error,1: Timeout"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0: No Error,1: Error"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0: No error,1: End Bit Error Generated"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0: No Error,1: CRC Error Generated"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0: No Error,1: Timeout"
|
|
group.word 0x32++0x3
|
|
line.word 0x0 "EISTR_EMMC_MODE,Error Interrupt Status"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error" "0: FIFO contains at least one byte,1: FIFO is empty"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0: No Error,1: Error"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0: No Error,1: Error"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0: No Error,1: Power Fail"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0: No Error,1: Error"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error" "0: No Error,1: Error"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error" "0: No Error,1: Timeout"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0: No Error,1: Error"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0: No error,1: End Bit Error Generated"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0: No Error,1: CRC Error Generated"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0: No Error,1: Timeout"
|
|
line.word 0x2 "NISTER,Normal Interrupt Status Enable"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 7. "CREM,Card Removal Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 6. "CINS,Card Insertion Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: Masked,1: Enabled"
|
|
group.word 0x34++0x3
|
|
line.word 0x0 "NISTER_EMMC_MODE,Normal Interrupt Status Enable"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0,1"
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: Masked,1: Enabled"
|
|
line.word 0x2 "EISTER,Error Interrupt Status Enable"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: Masked,1: Enabled"
|
|
group.word 0x36++0x3
|
|
line.word 0x0 "EISTER_EMMC_MODE,Error Interrupt Status Enable"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0,1"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: Masked,1: Enabled"
|
|
line.word 0x2 "NISIER,Normal Interrupt Signal Enable"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 7. "CREM,Card Removal Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 6. "CINS,Card Insertion Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: Masked,1: Enabled"
|
|
group.word 0x38++0x3
|
|
line.word 0x0 "NISIER_EMMC_MODE,Normal Interrupt Signal Enable"
|
|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0,1"
|
|
bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: Masked,1: Enabled"
|
|
line.word 0x2 "EISIER,Error Interrupt Signal Enable"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
|
group.word 0x3A++0x1
|
|
line.word 0x0 "EISIER_EMMC_MODE,Error Interrupt Signal Enable"
|
|
bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0,1"
|
|
bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
|
rgroup.word 0x3C++0x1
|
|
line.word 0x0 "ACESR,Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Command not Issued By Auto CMD12 Error" "0: No error,1: Not Issued"
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0: No error,1: Error"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0: No error,1: End Bit Error Generated"
|
|
bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0: No error,1: CRC Error Generated"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0: No error,1: Timeout"
|
|
bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0: Executed,1: Not executed"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R,Host Control 2"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver Strength are controlled by Host..,1: Automatic Selection by Preset Value is Enabled"
|
|
bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 7. "SLCKSEL,Sampling Clock Select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not Tuned or Tuning Completed,1: Execute Tuning"
|
|
newline
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is Selected (Default),1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0: 3.3V Signaling,1: 1.8V Signaling"
|
|
newline
|
|
bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: SDR12,1: SDR25,2: SDR50,3: SDR104,4: DDR50,?,?,?"
|
|
group.word 0x3E++0x1
|
|
line.word 0x0 "HC2R_EMMC_MODE,Host Control 2"
|
|
bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver Strength are controlled by Host..,1: Automatic Selection by Preset Value is Enabled"
|
|
bitfld.word 0x0 7. "SLCKSEL,Sampling Clock Select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
|
|
newline
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not Tuned or Tuning Completed,1: Execute Tuning"
|
|
bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is Selected (Default),1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "CA0R,Capabilities 0"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0: Asynchronous Interrupt not Supported,1: Asynchronous Interrupt supported"
|
|
newline
|
|
bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0: 32-bit Address Descriptors and System Bus,1: 64-bit Address Descriptors and System Bus"
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0: 1.8V Not Supported,1: 1.8V Supported"
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0: 3.0V Not Supported,1: 3.0V Supported"
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0: 3.3V Not Supported,1: 3.3V Supported"
|
|
newline
|
|
bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0: Suspend/Resume not Supported,1: Suspend/Resume Supported"
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0: SDMA not Supported,1: SDMA Supported"
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0: High Speed not Supported,1: High Speed Supported"
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0: ADMA2 not Supported,1: ADMA2 Supported"
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-bit Support for Embedded Device" "0: 8-bit Bus Width not Supported,1: 8-bit Bus Width Supported"
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0: KHz,1: MHz"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 13. "TSDR50,Use Tuning for SDR50" "0: SDR50 does not require tuning,1: SDR50 requires tuning"
|
|
newline
|
|
hexmask.long.byte 0x4 8.--11. 1. "TCNTRT,Timer Count for Re-Tuning"
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0: Driver Type D is Not Supported,1: Driver Type D is Supported"
|
|
newline
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0: Driver Type C is Not Supported,1: Driver Type C is Supported"
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0: Driver Type A is Not Supported,1: Driver Type A is Supported"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0: DDR50 is Not Supported,1: DDR50 is Supported"
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0: SDR104 is Not Supported,1: SDR104 is Supported"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0: SDR50 is Not Supported,1: SDR50 is Supported"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "MCCAR,Maximum Current Capabilities"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued By Auto CMD12 Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0: No Interrupt,1: Interrupt is generated"
|
|
line.word 0x2 "FEREIS,Force Event for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0: No Interrupt,1: Interrupt is generated"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0: No Error,1: Error"
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: ST_STOP (Stop DMA),1: ST_FDS (Fetch Descriptor),?,3: ST_TFR (Transfer Data)"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR,ADMA System Address n"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value n"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select Value for Initialization" "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select Value for Initialization" "0: Host Controller Ver2.00 Compatible Clock..,1: Programmable Clock Generator"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select Value for Initialization"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status"
|
|
bitfld.word 0x0 0.--1. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3"
|
|
line.word 0x2 "HCVR,Host Controller Version"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Spec Version"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0,1"
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0,1"
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: Not a MMC specific command,1: Wait IRQ Command,2: Stream Command,3: Boot Command"
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.byte 0x207++0x0
|
|
line.byte 0x0 "DEBR,Debounce Register"
|
|
bitfld.byte 0x0 0.--1. "CDDVAL,Card Detect Debounce Value" "0: 1 slow clock cycle,1: 8 slow clock cycles,2: 33 slow clock cycle,3: 328 slow clock cycle"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control"
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0,1,2,3"
|
|
line.long 0x4 "CC2R,Clock Control 2"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCK Disabled" "0: No effect,1: SDCLK can be stopped at any time after DATA.."
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key (0x46)"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)" "0,1"
|
|
line.long 0x4 "DBGR,Debug"
|
|
bitfld.long 0x4 0. "NIDBG,Non-intrusive debug enable" "0: Debugging is intrusive (reads of BDPR from..,1: Debugging is not intrusive (reads of BDPR from.."
|
|
tree.end
|
|
tree "SDMMC1"
|
|
base ad:0x45028000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR,SDMA System Address / Argument 2"
|
|
hexmask.long 0x0 0.--31. 1. "ADDR,SDMA System Address"
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "SSAR_CMD23_MODE,SDMA System Address / Argument 2"
|
|
hexmask.long 0x0 0.--31. 1. "ARG2,Argument 2"
|
|
group.word 0x4++0x3
|
|
line.word 0x0 "BSR,Block Size"
|
|
bitfld.word 0x0 12.--14. "BOUNDARY,SDMA Buffer Boundary" "0: 4k bytes,1: 8k bytes,2: 16k bytes,3: 32k bytes,4: 64k bytes,5: 128k bytes,6: 256k bytes,7: 512k bytes"
|
|
hexmask.word 0x0 0.--9. 1. "BLOCKSIZE,Transfer Block Size"
|
|
line.word 0x2 "BCR,Block Count"
|
|
hexmask.word 0x2 0.--15. 1. "BCNT,Blocks Count for Current Transfer"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "ARG1R,Argument 1"
|
|
hexmask.long 0x0 0.--31. 1. "ARG,Argument 1"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "TMR,Transfer Mode"
|
|
bitfld.word 0x0 5. "MSBSEL,Multi/Single Block Selection" "0: Single Block,1: Multiple Block"
|
|
bitfld.word 0x0 4. "DTDSEL,Data Transfer Direction Selection" "0: Write (Host to Card),1: Read (Card to Host)"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "ACMDEN,Auto Command Enable" "0: Auto Command Disabled,1: Auto CMD12 Enable,2: Auto CMD23 Enable,?"
|
|
bitfld.word 0x0 1. "BCEN,Block Count Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.word 0x0 0. "DMAEN,DMA Enable" "0: No data transfer or Non DMA data transfer,1: DMA data transfer"
|
|
line.word 0x2 "CR,Command"
|
|
hexmask.word.byte 0x2 8.--13. 1. "CMDIDX,Command Index"
|
|
bitfld.word 0x2 6.--7. "CMDTYP,Command Type" "0: Other commands,1: CMD52 for writing Bus Suspend in CCCR,2: CMD52 for writing Function Select in CCCR,3: CMD12 CMD52 for writing I/O Abort in CCCR"
|
|
newline
|
|
bitfld.word 0x2 5. "DPSEL,Data Present Select" "0: No Data Present,1: Data Present"
|
|
bitfld.word 0x2 4. "CMDICEN,Command Index Check Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.word 0x2 3. "CMDCCEN,Command CRC Check Enable" "0: Disable,1: Enable"
|
|
bitfld.word 0x2 0.--1. "RESPTYP,Response Type" "0: No response,1: 136-bit response,2: 48-bit response,3: 48-bit response check busy after response"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
rgroup.long ($2+0x10)++0x3
|
|
line.long 0x0 "RR[$1],Response"
|
|
hexmask.long 0x0 0.--31. 1. "CMDRESP,Command Response"
|
|
repeat.end
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "BDPR,Buffer Data Port"
|
|
hexmask.long 0x0 0.--31. 1. "BUFDATA,Buffer Data"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "PSR,Present State"
|
|
bitfld.long 0x0 24. "CMDLL,CMD Line Level" "0,1"
|
|
hexmask.long.byte 0x0 20.--23. 1. "DATLL,DAT[3:0] Line Level"
|
|
newline
|
|
bitfld.long 0x0 19. "WRPPL,Write Protect Pin Level" "0: Write protected (SDWP#=0),1: Write enabled (SDWP#=1)"
|
|
bitfld.long 0x0 18. "CARDDPL,Card Detect Pin Level" "0: No card present (SDCD#=1),1: Card present (SDCD#=0)"
|
|
newline
|
|
bitfld.long 0x0 17. "CARDSS,Card State Stable" "0: Reset or Debouncing,1: No Card or Insered"
|
|
bitfld.long 0x0 16. "CARDINS,Card Inserted" "0: Reset or Debouncing or No Card,1: Card inserted"
|
|
newline
|
|
bitfld.long 0x0 11. "BUFRDEN,Buffer Read Enable" "0: Read disable,1: Read enable"
|
|
bitfld.long 0x0 10. "BUFWREN,Buffer Write Enable" "0: Write disable,1: Write enable"
|
|
newline
|
|
bitfld.long 0x0 9. "RTACT,Read Transfer Active" "0: No valid data,1: Transferring data"
|
|
bitfld.long 0x0 8. "WTACT,Write Transfer Active" "0: No valid data,1: Transferring data"
|
|
newline
|
|
bitfld.long 0x0 3. "RTREQ,Re-Tuning Request" "0: Fixed or well-tuned sampling clock,1: Sampling clock needs re-tuning"
|
|
bitfld.long 0x0 2. "DLACT,DAT Line Active" "0: DAT Line Inactive,1: DAT Line Active"
|
|
newline
|
|
bitfld.long 0x0 1. "CMDINHD,Command Inhibit (DAT)" "0: Can issue command which uses the DAT line,1: Cannot issue command which uses the DAT line"
|
|
bitfld.long 0x0 0. "CMDINHC,Command Inhibit (CMD)" "0: Can issue command using only CMD line,1: Cannot issue command"
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "HC1R,Host Control 1"
|
|
bitfld.byte 0x0 7. "CARDDSEL,Card Detect Signal Selection" "0: SDCD# is selected (for normal use),1: The Card Select Test Level is selected (for test.."
|
|
bitfld.byte 0x0 6. "CARDDTL,Card Detect Test Level" "0: No Card,1: Card Inserted"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode,1: High Speed mode"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode,1: 4-bit mode"
|
|
bitfld.byte 0x0 0. "LEDCTRL,LED Control" "0: LED off,1: LED on"
|
|
group.byte 0x28++0x2
|
|
line.byte 0x0 "HC1R_EMMC_MODE,Host Control 1"
|
|
bitfld.byte 0x0 3.--4. "DMASEL,DMA Select" "0: SDMA is selected,?,2: 32-bit Address ADMA2 is selected,?"
|
|
bitfld.byte 0x0 2. "HSEN,High Speed Enable" "0: Normal Speed mode,1: High Speed mode"
|
|
newline
|
|
bitfld.byte 0x0 1. "DW,Data Width" "0: 1-bit mode,1: 4-bit mode"
|
|
line.byte 0x1 "PCR,Power Control"
|
|
bitfld.byte 0x1 1.--3. "SDBVSEL,SD Bus Voltage Select" "?,?,?,?,?,5: 1.8V (Typ.),6: 3.0V (Typ.),7: 3.3V (Typ.)"
|
|
bitfld.byte 0x1 0. "SDBPWR,SD Bus Power" "0: Power off,1: Power on"
|
|
line.byte 0x2 "BGCR,Block Gap Control"
|
|
bitfld.byte 0x2 3. "INTBG,Interrupt at Block Gap" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x2 2. "RWCTRL,Read Wait Control" "0: Disable Read Wait Control,1: Enable Read Wait Control"
|
|
newline
|
|
bitfld.byte 0x2 1. "CONTR,Continue Request" "0: Not affected,1: Restart"
|
|
bitfld.byte 0x2 0. "STPBGR,Stop at Block Gap Request" "0: Transfer,1: Stop"
|
|
group.byte 0x2A++0x1
|
|
line.byte 0x0 "BGCR_EMMC_MODE,Block Gap Control"
|
|
bitfld.byte 0x0 1. "CONTR,Continue Request" "0: Not affected,1: Restart"
|
|
bitfld.byte 0x0 0. "STPBGR,Stop at Block Gap Request" "0: Transfer,1: Stop"
|
|
line.byte 0x1 "WCR,Wakeup Control"
|
|
bitfld.byte 0x1 2. "WKENCREM,Wakeup Event Enable on Card Removal" "0: Disable,1: Enable"
|
|
bitfld.byte 0x1 1. "WKENCINS,Wakeup Event Enable on Card Insertion" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.byte 0x1 0. "WKENCINT,Wakeup Event Enable on Card Interrupt" "0: Disable,1: Enable"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "CCR,Clock Control"
|
|
hexmask.word.byte 0x0 8.--15. 1. "SDCLKFSEL,SDCLK Frequency Select"
|
|
bitfld.word 0x0 6.--7. "USDCLKFSEL,Upper Bits of SDCLK Frequency Select" "0,1,2,3"
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|
newline
|
|
bitfld.word 0x0 5. "CLKGSEL,Clock Generator Select" "0: Divided Clock Mode,1: Programmable Clock Mode"
|
|
bitfld.word 0x0 2. "SDCLKEN,SD Clock Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.word 0x0 1. "INTCLKS,Internal Clock Stable" "0: Not Ready,1: Ready"
|
|
bitfld.word 0x0 0. "INTCLKEN,Internal Clock Enable" "0: Stop,1: Oscillate"
|
|
group.byte 0x2E++0x1
|
|
line.byte 0x0 "TCR,Timeout Control"
|
|
hexmask.byte 0x0 0.--3. 1. "DTCVAL,Data Timeout Counter Value"
|
|
line.byte 0x1 "SRR,Software Reset"
|
|
bitfld.byte 0x1 2. "SWRSTDAT,Software Reset For DAT Line" "0: Work,1: Reset"
|
|
bitfld.byte 0x1 1. "SWRSTCMD,Software Reset For CMD Line" "0: Work,1: Reset"
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|
newline
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bitfld.byte 0x1 0. "SWRSTALL,Software Reset For All" "0: Work,1: Reset"
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group.word 0x30++0x1
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line.word 0x0 "NISTR,Normal Interrupt Status"
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|
bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No Error,1: Error"
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|
bitfld.word 0x0 8. "CINT,Card Interrupt" "0: No Card Interrupt,1: Generate Card Interrupt"
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|
newline
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bitfld.word 0x0 7. "CREM,Card Removal" "0: Card state stable or Debouncing,1: Card Removed"
|
|
bitfld.word 0x0 6. "CINS,Card Insertion" "0: Card state stable or Debouncing,1: Card inserted"
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|
newline
|
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer"
|
|
newline
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
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|
bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No Block Gap Event,1: Transaction stopped at block gap"
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|
newline
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Not complete,1: Command execution is completed"
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|
bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete,1: Command complete"
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group.word 0x30++0x3
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line.word 0x0 "NISTR_EMMC_MODE,Normal Interrupt Status"
|
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bitfld.word 0x0 15. "ERRINT,Error Interrupt" "0: No Error,1: Error"
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|
bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received" "0,1"
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|
newline
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready" "0: Not ready to read buffer,1: Ready to read buffer"
|
|
bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready" "0: Not ready to write buffer,1: Ready to write buffer"
|
|
newline
|
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bitfld.word 0x0 3. "DMAINT,DMA Interrupt" "0: No DMA Interrupt,1: DMA Interrupt is generated"
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bitfld.word 0x0 2. "BLKGE,Block Gap Event" "0: No Block Gap Event,1: Transaction stopped at block gap"
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newline
|
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bitfld.word 0x0 1. "TRFC,Transfer Complete" "0: Not complete,1: Command execution is completed"
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bitfld.word 0x0 0. "CMDC,Command Complete" "0: No command complete,1: Command complete"
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line.word 0x2 "EISTR,Error Interrupt Status"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error" "0: No Error,1: Error"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error" "0: No Error,1: Error"
|
|
newline
|
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bitfld.word 0x2 7. "CURLIM,Current Limit Error" "0: No Error,1: Power Fail"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error" "0: No Error,1: Error"
|
|
newline
|
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bitfld.word 0x2 5. "DATCRC,Data CRC Error" "0: No Error,1: Error"
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|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error" "0: No Error,1: Timeout"
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|
newline
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bitfld.word 0x2 3. "CMDIDX,Command Index Error" "0: No Error,1: Error"
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|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error" "0: No error,1: End Bit Error Generated"
|
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newline
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error" "0: No Error,1: CRC Error Generated"
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bitfld.word 0x2 0. "CMDTEO,Command Timeout Error" "0: No Error,1: Timeout"
|
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group.word 0x32++0x3
|
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line.word 0x0 "EISTR_EMMC_MODE,Error Interrupt Status"
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bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error" "0: FIFO contains at least one byte,1: FIFO is empty"
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|
bitfld.word 0x0 9. "ADMA,ADMA Error" "0: No Error,1: Error"
|
|
newline
|
|
bitfld.word 0x0 8. "ACMD,Auto CMD Error" "0: No Error,1: Error"
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|
bitfld.word 0x0 7. "CURLIM,Current Limit Error" "0: No Error,1: Power Fail"
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|
newline
|
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bitfld.word 0x0 6. "DATEND,Data End Bit Error" "0: No Error,1: Error"
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|
bitfld.word 0x0 5. "DATCRC,Data CRC Error" "0: No Error,1: Error"
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newline
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bitfld.word 0x0 4. "DATTEO,Data Timeout Error" "0: No Error,1: Timeout"
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bitfld.word 0x0 3. "CMDIDX,Command Index Error" "0: No Error,1: Error"
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newline
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bitfld.word 0x0 2. "CMDEND,Command End Bit Error" "0: No error,1: End Bit Error Generated"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error" "0: No Error,1: CRC Error Generated"
|
|
newline
|
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bitfld.word 0x0 0. "CMDTEO,Command Timeout Error" "0: No Error,1: Timeout"
|
|
line.word 0x2 "NISTER,Normal Interrupt Status Enable"
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|
bitfld.word 0x2 8. "CINT,Card Interrupt Status Enable" "0: Masked,1: Enabled"
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|
bitfld.word 0x2 7. "CREM,Card Removal Status Enable" "0: Masked,1: Enabled"
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|
newline
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bitfld.word 0x2 6. "CINS,Card Insertion Status Enable" "0: Masked,1: Enabled"
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|
bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Status Enable" "0: Masked,1: Enabled"
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|
newline
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bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 3. "DMAINT,DMA Interrupt Status Enable" "0: Masked,1: Enabled"
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|
newline
|
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bitfld.word 0x2 2. "BLKGE,Block Gap Event Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 1. "TRFC,Transfer Complete Status Enable" "0: Masked,1: Enabled"
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|
newline
|
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bitfld.word 0x2 0. "CMDC,Command Complete Status Enable" "0: Masked,1: Enabled"
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group.word 0x34++0x3
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line.word 0x0 "NISTER_EMMC_MODE,Normal Interrupt Status Enable"
|
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bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Status Enable" "0,1"
|
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "DMAINT,DMA Interrupt Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 2. "BLKGE,Block Gap Event Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "TRFC,Transfer Complete Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 0. "CMDC,Command Complete Status Enable" "0: Masked,1: Enabled"
|
|
line.word 0x2 "EISTER,Error Interrupt Status Enable"
|
|
bitfld.word 0x2 9. "ADMA,ADMA Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 8. "ACMD,Auto CMD Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 7. "CURLIM,Current Limit Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 5. "DATCRC,Data CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 4. "DATTEO,Data Timeout Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 3. "CMDIDX,Command Index Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 2. "CMDEND,Command End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error Status Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Status Enable" "0: Masked,1: Enabled"
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group.word 0x36++0x3
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line.word 0x0 "EISTER_EMMC_MODE,Error Interrupt Status Enable"
|
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bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Status Enable" "0,1"
|
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bitfld.word 0x0 9. "ADMA,ADMA Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 8. "ACMD,Auto CMD Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 6. "DATEND,Data End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 4. "DATTEO,Data Timeout Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 2. "CMDEND,Command End Bit Error Status Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Status Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Status Enable" "0: Masked,1: Enabled"
|
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line.word 0x2 "NISIER,Normal Interrupt Signal Enable"
|
|
bitfld.word 0x2 8. "CINT,Card Interrupt Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 7. "CREM,Card Removal Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 6. "CINS,Card Insertion Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: Masked,1: Enabled"
|
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newline
|
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bitfld.word 0x2 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 3. "DMAINT,DMA Interrupt Signal Enable" "0: Masked,1: Enabled"
|
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newline
|
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bitfld.word 0x2 2. "BLKGE,Block Gap Event Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 1. "TRFC,Transfer Complete Signal Enable" "0: Masked,1: Enabled"
|
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newline
|
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bitfld.word 0x2 0. "CMDC,Command Complete Signal Enable" "0: Masked,1: Enabled"
|
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group.word 0x38++0x3
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line.word 0x0 "NISIER_EMMC_MODE,Normal Interrupt Signal Enable"
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bitfld.word 0x0 14. "BOOTAR,Boot Acknowledge Received Signal Enable" "0,1"
|
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bitfld.word 0x0 5. "BRDRDY,Buffer Read Ready Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 4. "BWRRDY,Buffer Write Ready Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x0 3. "DMAINT,DMA Interrupt Signal Enable" "0: Masked,1: Enabled"
|
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newline
|
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bitfld.word 0x0 2. "BLKGE,Block Gap Event Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x0 1. "TRFC,Transfer Complete Signal Enable" "0: Masked,1: Enabled"
|
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newline
|
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bitfld.word 0x0 0. "CMDC,Command Complete Signal Enable" "0: Masked,1: Enabled"
|
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line.word 0x2 "EISIER,Error Interrupt Signal Enable"
|
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bitfld.word 0x2 9. "ADMA,ADMA Error Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 8. "ACMD,Auto CMD Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 7. "CURLIM,Current Limit Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x2 6. "DATEND,Data End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 5. "DATCRC,Data CRC Error Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 4. "DATTEO,Data Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
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newline
|
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bitfld.word 0x2 3. "CMDIDX,Command Index Error Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 2. "CMDEND,Command End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x2 1. "CMDCRC,Command CRC Error Signal Enable" "0: Masked,1: Enabled"
|
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bitfld.word 0x2 0. "CMDTEO,Command Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
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group.word 0x3A++0x1
|
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line.word 0x0 "EISIER_EMMC_MODE,Error Interrupt Signal Enable"
|
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bitfld.word 0x0 12. "BOOTAE,Boot Acknowledge Error Signal Enable" "0,1"
|
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bitfld.word 0x0 9. "ADMA,ADMA Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 8. "ACMD,Auto CMD Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 7. "CURLIM,Current Limit Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 6. "DATEND,Data End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 5. "DATCRC,Data CRC Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 4. "DATTEO,Data Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 3. "CMDIDX,Command Index Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 2. "CMDEND,Command End Bit Error Signal Enable" "0: Masked,1: Enabled"
|
|
bitfld.word 0x0 1. "CMDCRC,Command CRC Error Signal Enable" "0: Masked,1: Enabled"
|
|
newline
|
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bitfld.word 0x0 0. "CMDTEO,Command Timeout Error Signal Enable" "0: Masked,1: Enabled"
|
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rgroup.word 0x3C++0x1
|
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line.word 0x0 "ACESR,Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Command not Issued By Auto CMD12 Error" "0: No error,1: Not Issued"
|
|
bitfld.word 0x0 4. "ACMDIDX,Auto CMD Index Error" "0: No error,1: Error"
|
|
newline
|
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bitfld.word 0x0 3. "ACMDEND,Auto CMD End Bit Error" "0: No error,1: End Bit Error Generated"
|
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bitfld.word 0x0 2. "ACMDCRC,Auto CMD CRC Error" "0: No error,1: CRC Error Generated"
|
|
newline
|
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bitfld.word 0x0 1. "ACMDTEO,Auto CMD Timeout Error" "0: No error,1: Timeout"
|
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bitfld.word 0x0 0. "ACMD12NE,Auto CMD12 Not Executed" "0: Executed,1: Not executed"
|
|
group.word 0x3E++0x1
|
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line.word 0x0 "HC2R,Host Control 2"
|
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bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver Strength are controlled by Host..,1: Automatic Selection by Preset Value is Enabled"
|
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bitfld.word 0x0 14. "ASINTEN,Asynchronous Interrupt Enable" "0: Disabled,1: Enabled"
|
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newline
|
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bitfld.word 0x0 7. "SLCKSEL,Sampling Clock Select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
|
|
bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not Tuned or Tuning Completed,1: Execute Tuning"
|
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newline
|
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bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is Selected (Default),1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
|
|
bitfld.word 0x0 3. "VS18EN,1.8V Signaling Enable" "0: 3.3V Signaling,1: 1.8V Signaling"
|
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newline
|
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bitfld.word 0x0 0.--2. "UHSMS,UHS Mode Select" "0: SDR12,1: SDR25,2: SDR50,3: SDR104,4: DDR50,?,?,?"
|
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group.word 0x3E++0x1
|
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line.word 0x0 "HC2R_EMMC_MODE,Host Control 2"
|
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bitfld.word 0x0 15. "PVALEN,Preset Value Enable" "0: SDCLK and Driver Strength are controlled by Host..,1: Automatic Selection by Preset Value is Enabled"
|
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bitfld.word 0x0 7. "SLCKSEL,Sampling Clock Select" "0: Fixed clock is used to sample data,1: Tuned clock is used to sample data"
|
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newline
|
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bitfld.word 0x0 6. "EXTUN,Execute Tuning" "0: Not Tuned or Tuning Completed,1: Execute Tuning"
|
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bitfld.word 0x0 4.--5. "DRVSEL,Driver Strength Select" "0: Driver Type B is Selected (Default),1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
|
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newline
|
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hexmask.word.byte 0x0 0.--3. 1. "HS200EN,HS200 Mode Enable"
|
|
group.long 0x40++0x7
|
|
line.long 0x0 "CA0R,Capabilities 0"
|
|
bitfld.long 0x0 30.--31. "SLTYPE,Slot Type" "0: Removable Card Slot,1: Embedded Slot for One Device,?,?"
|
|
bitfld.long 0x0 29. "ASINTSUP,Asynchronous Interrupt Support" "0: Asynchronous Interrupt not Supported,1: Asynchronous Interrupt supported"
|
|
newline
|
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bitfld.long 0x0 28. "SB64SUP,64-Bit System Bus Support" "0: 32-bit Address Descriptors and System Bus,1: 64-bit Address Descriptors and System Bus"
|
|
bitfld.long 0x0 26. "V18VSUP,Voltage Support 1.8V" "0: 1.8V Not Supported,1: 1.8V Supported"
|
|
newline
|
|
bitfld.long 0x0 25. "V30VSUP,Voltage Support 3.0V" "0: 3.0V Not Supported,1: 3.0V Supported"
|
|
bitfld.long 0x0 24. "V33VSUP,Voltage Support 3.3V" "0: 3.3V Not Supported,1: 3.3V Supported"
|
|
newline
|
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bitfld.long 0x0 23. "SRSUP,Suspend/Resume Support" "0: Suspend/Resume not Supported,1: Suspend/Resume Supported"
|
|
bitfld.long 0x0 22. "SDMASUP,SDMA Support" "0: SDMA not Supported,1: SDMA Supported"
|
|
newline
|
|
bitfld.long 0x0 21. "HSSUP,High Speed Support" "0: High Speed not Supported,1: High Speed Supported"
|
|
bitfld.long 0x0 19. "ADMA2SUP,ADMA2 Support" "0: ADMA2 not Supported,1: ADMA2 Supported"
|
|
newline
|
|
bitfld.long 0x0 18. "ED8SUP,8-bit Support for Embedded Device" "0: 8-bit Bus Width not Supported,1: 8-bit Bus Width Supported"
|
|
bitfld.long 0x0 16.--17. "MAXBLKL,Max Block Length" "0: 512 bytes,1: 1024 bytes,2: 2048 bytes,?"
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|
newline
|
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hexmask.long.byte 0x0 8.--15. 1. "BASECLKF,Base Clock Frequency"
|
|
bitfld.long 0x0 7. "TEOCLKU,Timeout Clock Unit" "0: KHz,1: MHz"
|
|
newline
|
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hexmask.long.byte 0x0 0.--5. 1. "TEOCLKF,Timeout Clock Frequency"
|
|
line.long 0x4 "CA1R,Capabilities 1"
|
|
hexmask.long.byte 0x4 16.--23. 1. "CLKMULT,Clock Multiplier"
|
|
bitfld.long 0x4 13. "TSDR50,Use Tuning for SDR50" "0: SDR50 does not require tuning,1: SDR50 requires tuning"
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|
newline
|
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hexmask.long.byte 0x4 8.--11. 1. "TCNTRT,Timer Count for Re-Tuning"
|
|
bitfld.long 0x4 6. "DRVDSUP,Driver Type D Support" "0: Driver Type D is Not Supported,1: Driver Type D is Supported"
|
|
newline
|
|
bitfld.long 0x4 5. "DRVCSUP,Driver Type C Support" "0: Driver Type C is Not Supported,1: Driver Type C is Supported"
|
|
bitfld.long 0x4 4. "DRVASUP,Driver Type A Support" "0: Driver Type A is Not Supported,1: Driver Type A is Supported"
|
|
newline
|
|
bitfld.long 0x4 2. "DDR50SUP,DDR50 Support" "0: DDR50 is Not Supported,1: DDR50 is Supported"
|
|
bitfld.long 0x4 1. "SDR104SUP,SDR104 Support" "0: SDR104 is Not Supported,1: SDR104 is Supported"
|
|
newline
|
|
bitfld.long 0x4 0. "SDR50SUP,SDR50 Support" "0: SDR50 is Not Supported,1: SDR50 is Supported"
|
|
rgroup.long 0x48++0x3
|
|
line.long 0x0 "MCCAR,Maximum Current Capabilities"
|
|
hexmask.long.byte 0x0 16.--23. 1. "MAXCUR18V,Maximum Current for 1.8V"
|
|
hexmask.long.byte 0x0 8.--15. 1. "MAXCUR30V,Maximum Current for 3.0V"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--7. 1. "MAXCUR33V,Maximum Current for 3.3V"
|
|
wgroup.word 0x50++0x3
|
|
line.word 0x0 "FERACES,Force Event for Auto CMD Error Status"
|
|
bitfld.word 0x0 7. "CMDNI,Force Event for Command Not Issued By Auto CMD12 Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x0 4. "ACMDIDX,Force Event for Auto CMD Index Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x0 3. "ACMDEND,Force Event for Auto CMD End Bit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x0 2. "ACMDCRC,Force Event for Auto CMD CRC Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x0 1. "ACMDTEO,Force Event for Auto CMD Timeout Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x0 0. "ACMD12NE,Force Event for Auto CMD12 Not Executed" "0: No Interrupt,1: Interrupt is generated"
|
|
line.word 0x2 "FEREIS,Force Event for Error Interrupt Status"
|
|
bitfld.word 0x2 12. "BOOTAE,Force Event for Boot Acknowledge Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 9. "ADMA,Force Event for ADMA Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 8. "ACMD,Force Event for Auto CMD Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 7. "CURLIM,Force Event for Current Limit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 6. "DATEND,Force Event for Data End Bit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 5. "DATCRC,Force Event for Data CRC Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 4. "DATTEO,Force Event for Data Timeout Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 3. "CMDIDX,Force Event for Command Index Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 2. "CMDEND,Force Event for Command End Bit Error" "0: No Interrupt,1: Interrupt is generated"
|
|
bitfld.word 0x2 1. "CMDCRC,Force Event for Command CRC Error" "0: No Interrupt,1: Interrupt is generated"
|
|
newline
|
|
bitfld.word 0x2 0. "CMDTEO,Force Event for Command Timeout Error" "0: No Interrupt,1: Interrupt is generated"
|
|
rgroup.byte 0x54++0x0
|
|
line.byte 0x0 "AESR,ADMA Error Status"
|
|
bitfld.byte 0x0 2. "LMIS,ADMA Length Mismatch Error" "0: No Error,1: Error"
|
|
bitfld.byte 0x0 0.--1. "ERRST,ADMA Error State" "0: ST_STOP (Stop DMA),1: ST_FDS (Fetch Descriptor),?,3: ST_TFR (Transfer Data)"
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "ASAR,ADMA System Address n"
|
|
hexmask.long 0x0 0.--31. 1. "ADMASA,ADMA System Address"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x60)++0x1
|
|
line.word 0x0 "PVR[$1],Preset Value n"
|
|
bitfld.word 0x0 14.--15. "DRVSEL,Driver Strength Select Value for Initialization" "0: Driver Type B is Selected,1: Driver Type A is Selected,2: Driver Type C is Selected,3: Driver Type D is Selected"
|
|
bitfld.word 0x0 10. "CLKGSEL,Clock Generator Select Value for Initialization" "0: Host Controller Ver2.00 Compatible Clock..,1: Programmable Clock Generator"
|
|
newline
|
|
hexmask.word 0x0 0.--9. 1. "SDCLKFSEL,SDCLK Frequency Select Value for Initialization"
|
|
repeat.end
|
|
rgroup.word 0xFC++0x3
|
|
line.word 0x0 "SISR,Slot Interrupt Status"
|
|
bitfld.word 0x0 0.--1. "INTSSL,Interrupt Signal for Each Slot" "0,1,2,3"
|
|
line.word 0x2 "HCVR,Host Controller Version"
|
|
hexmask.word.byte 0x2 8.--15. 1. "VVER,Vendor Version"
|
|
hexmask.word.byte 0x2 0.--7. 1. "SVER,Spec Version"
|
|
group.byte 0x204++0x0
|
|
line.byte 0x0 "MC1R,e.MMC Control 1"
|
|
bitfld.byte 0x0 7. "FCD,e.MMC Force Card Detect" "0,1"
|
|
bitfld.byte 0x0 6. "RSTN,e.MMC Reset Signal" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "BOOTA,e.MMC Boot Acknowledge Enable" "0,1"
|
|
bitfld.byte 0x0 4. "OPD,e.MMC Open Drain Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DDR,e.MMC HSDDR Mode" "0,1"
|
|
bitfld.byte 0x0 0.--1. "CMDTYP,e.MMC Command Type" "0: Not a MMC specific command,1: Wait IRQ Command,2: Stream Command,3: Boot Command"
|
|
wgroup.byte 0x205++0x0
|
|
line.byte 0x0 "MC2R,e.MMC Control 2"
|
|
bitfld.byte 0x0 1. "ABOOT,e.MMC Abort Boot" "0,1"
|
|
bitfld.byte 0x0 0. "SRESP,e.MMC Abort Wait IRQ" "0,1"
|
|
group.byte 0x207++0x0
|
|
line.byte 0x0 "DEBR,Debounce Register"
|
|
bitfld.byte 0x0 0.--1. "CDDVAL,Card Detect Debounce Value" "0: 1 slow clock cycle,1: 8 slow clock cycles,2: 33 slow clock cycle,3: 328 slow clock cycle"
|
|
group.long 0x208++0x7
|
|
line.long 0x0 "ACR,AHB Control"
|
|
bitfld.long 0x0 0.--1. "BMAX,AHB Maximum Burst" "0,1,2,3"
|
|
line.long 0x4 "CC2R,Clock Control 2"
|
|
bitfld.long 0x4 0. "FSDCLKD,Force SDCK Disabled" "0: No effect,1: SDCLK can be stopped at any time after DATA.."
|
|
group.long 0x230++0x7
|
|
line.long 0x0 "CACR,Capabilities Control"
|
|
hexmask.long.byte 0x0 8.--15. 1. "KEY,Key (0x46)"
|
|
bitfld.long 0x0 0. "CAPWREN,Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers)" "0,1"
|
|
line.long 0x4 "DBGR,Debug"
|
|
bitfld.long 0x4 0. "NIDBG,Non-intrusive debug enable" "0: Debugging is intrusive (reads of BDPR from..,1: Debugging is not intrusive (reads of BDPR from.."
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM (Serial Communication Interface)"
|
|
base ad:0x0
|
|
tree "SERCOM0"
|
|
base ad:0x44810000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM1"
|
|
base ad:0x44812000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM2"
|
|
base ad:0x44814000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM3"
|
|
base ad:0x44816000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM4"
|
|
base ad:0x45000000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM5"
|
|
base ad:0x45002000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM6"
|
|
base ad:0x45004000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree "SERCOM7"
|
|
base ad:0x45006000
|
|
tree "I2CM (I2C Master Mode)"
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,I2CM Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 28.--29. "INACTOUT,Inactive Time-Out" "0: Disable,1: 5-6 SCL cycle time-out,2: 10-11 SCL cycle time-out,3: 20-21-6 SCL cycle time-out"
|
|
newline
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
newline
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.long 0x0 22. "MEXTTOEN,Master SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0: Disable,?,2: Minimum 50ns filter,3: Minimum 10ns filter"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 9. "QCEN,Quick Command Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
line.long 0xC "BAUD,I2CM Baud Rate"
|
|
hexmask.long.byte 0xC 24.--31. 1. "HSBAUDLOW,High Speed Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 16.--23. 1. "HSBAUD,High Speed Baud Rate Value"
|
|
newline
|
|
hexmask.long.byte 0xC 8.--15. 1. "BAUDLOW,Baud Rate Value Low"
|
|
hexmask.long.byte 0xC 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "SB,Slave On Bus Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "MB,Master On Bus Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CM Status"
|
|
bitfld.word 0x0 10. "LENERR,Length Error" "0,1"
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.word 0x0 8. "MEXTTOUT,Master SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4.--5. "BUSSTATE,Bus State" "0,1,2,3"
|
|
newline
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
bitfld.word 0x0 1. "ARBLOST,Arbitration Lost" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "LEN,Length"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 14. "HS,High Speed Mode" "0,1"
|
|
bitfld.long 0x0 13. "LENEN,Length Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 0.--10. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,I2CM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,I2CM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "I2CS (I2C Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,I2CS Control A"
|
|
bitfld.long 0x0 30. "LOWTOUTEN,SCL Low Timeout Enable" "0,1"
|
|
bitfld.long 0x0 27. "SCLSM,SCL Clock Stretch Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x0 24.--25. "SPEED,Transfer Speed" "0: Standard-Mode (SM) and Fast-Mode (FM),1: Fast-Mode Plus (FM+),2: High-Speed Mode,?"
|
|
bitfld.long 0x0 23. "SEXTTOEN,Slave SCL Low Extend Timeout" "0,1"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "SDAHOLD,SDA Hold Time" "0: Disable,1: 50ns - 100ns hold time,2: 300ns - 600ns hold time,3: 400ns - 800ns hold time"
|
|
bitfld.long 0x0 17. "SMBUSEN,SMBUS Input Buffer Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 16. "PINOUT,Pin Usage" "0,1"
|
|
bitfld.long 0x0 10.--11. "SLEWRATE,Slew Rate Selection" "0: Standard mode,1: Fast mode,2: Fast mode plus,3: High-speed mode"
|
|
newline
|
|
bitfld.long 0x0 8.--9. "FILTSEL,Input Filter Selection" "0,1,2,3"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,I2CS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 18. "ACKACT,Acknowledge Action" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16.--17. "CMD,Command" "0,1,2,3"
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: The slave responds to the address written in..,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
newline
|
|
bitfld.long 0x4 10. "AACKEN,Automatic Address Acknowledge" "0,1"
|
|
bitfld.long 0x4 9. "GCMD,PMBus Group Command" "0,1"
|
|
newline
|
|
bitfld.long 0x4 8. "SMEN,Smart Mode Enable" "0,1"
|
|
line.long 0x8 "CTRLC,I2CS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--3. 1. "SDASETUP,SDA Setup Time"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,I2CS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,I2CS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,I2CS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 4. "RXFF,Rx FIFO Full Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "TXFE,Tx FIFO Empty Interrupt" "0,1"
|
|
bitfld.byte 0x0 2. "DRDY,Data Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "AMATCH,Address Match Interrupt" "0,1"
|
|
bitfld.byte 0x0 0. "PREC,Stop Received Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,I2CS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 10. "HS,High Speed" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "SEXTTOUT,Slave SCL Low Extend Timeout" "0,1"
|
|
bitfld.word 0x0 7. "CLKHOLD,Clock Hold" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "LOWTOUT,SCL Low Timeout" "0,1"
|
|
bitfld.word 0x0 4. "SR,Repeated Start" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "DIR,Read/Write Direction" "0,1"
|
|
bitfld.word 0x0 2. "RXNACK,Received Not Acknowledge" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "COLL,Transmit Collision" "0,1"
|
|
bitfld.word 0x0 0. "BUSERR,Bus Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,I2CS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,Length Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "SYSOP,System Operation Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,I2CS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,I2CS Address"
|
|
hexmask.long.word 0x0 17.--26. 1. "ADDRMASK,Address Mask"
|
|
bitfld.long 0x0 15. "TENBITEN,Ten Bit Addressing Enable" "0,1"
|
|
newline
|
|
hexmask.long.word 0x0 1.--10. 1. "ADDR,Address Value"
|
|
bitfld.long 0x0 0. "GENCEN,General Call Address Enable" "0,1"
|
|
line.long 0x4 "DATA,I2CS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,I2CS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,I2CS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIM (SPI Master Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIM Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIM Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0: Hardware SS control is disabled,1: Hardware SS control is enabled"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0: SS low detector is disabled,1: SS low detector is enabled"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIM Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIM Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIM Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIM Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIM Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIM Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIM Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIM Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIM Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIM Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIM Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIM FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIM FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "SPIS (SPI Slave Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,SPIS Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first,1: LSB is transmitted first"
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0: SCK is low when idle,1: SCK is high when idle"
|
|
newline
|
|
bitfld.long 0x0 28. "CPHA,Clock Phase" "0: The data is sampled on a leading SCK edge and..,1: The data is sampled on a trailing SCK edge and.."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 20.--21. "DIPO,Data In Pinout" "0: SERCOM PAD0 is used as data input,1: SERCOM PAD1 is used as data input,2: SERCOM PAD2 is used as data input,3: SERCOM PAD3 is used as data input"
|
|
bitfld.long 0x0 16.--17. "DOPO,Data Out Pinout" "0: DO on PAD[0] SCK on PAD[1] and SS on PAD[2],?,2: DO on PAD[3] SCK on PAD[1] and SS on PAD[2],?"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,SPIS Control B"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 14.--15. "AMODE,Address Mode" "0: ADDRMASK is used as a mask to the AADR register,1: The slave responds to the two unique addresses..,2: The slave responds to the range of addresses..,?"
|
|
bitfld.long 0x4 13. "MSSEN,Master Slave Select Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 9. "SSDE,Slave Select Low Detect Enable" "0,1"
|
|
bitfld.long 0x4 6. "PLOADEN,Data Preload Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,?,?,?"
|
|
line.long 0x8 "CTRLC,SPIS Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated as long..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24. "DATA32B,Data 32 Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "FMODE,Frame mode" "0: Frame Master,1: Frame Slave"
|
|
bitfld.long 0x8 16. "FRMEN,Frame mode enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "IGNTUR,Ignore Transmit Underrun" "0,1"
|
|
bitfld.long 0x8 10. "FSPOL,Frame Synch Polarity" "0: VCC-level valid polarity,1: GND-level valid polarity"
|
|
newline
|
|
bitfld.long 0x8 9. "FSLEN,Frame Synch Length" "0: One SCK pulse,1: One frame duration"
|
|
bitfld.long 0x8 8. "FSES,Frame Synch Edge Select" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x8 0.--5. 1. "ICSPACE,Inter-Character Spacing"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "BAUD,SPIS Baud Rate"
|
|
hexmask.byte 0x0 0.--7. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,SPIS Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,SPIS Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,SPIS Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "SSL,Slave Select Low Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,SPIS Status"
|
|
bitfld.word 0x0 11. "LENERR,Transaction Length Error" "0,1"
|
|
bitfld.word 0x0 3. "TUR,Frame Transmit Underrun" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,SPIS Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,SPIS Length"
|
|
bitfld.word 0x0 8. "LENEN,Data Length Enable" "0,1"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x24++0x7
|
|
line.long 0x0 "ADDR,SPIS Address"
|
|
hexmask.long.byte 0x0 16.--23. 1. "ADDRMASK,Address Mask"
|
|
hexmask.long.byte 0x0 0.--7. 1. "ADDR,Address Value"
|
|
line.long 0x4 "DATA,SPIS Data"
|
|
hexmask.long 0x4 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,SPIS Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,SPIS FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,SPIS FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree "USART_INT (USART INTERNAL CLOCK Mode)"
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CTRLA,USART Control A"
|
|
bitfld.long 0x0 30. "DORD,Data Order" "0: MSB is transmitted first.,1: LSB is transmitted first."
|
|
bitfld.long 0x0 29. "CPOL,Clock Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 28. "CMODE,Communication Mode" "0: Asynchronous communication.,1: Synchronous communication."
|
|
hexmask.long.byte 0x0 24.--27. 1. "FORM,Frame Format"
|
|
newline
|
|
bitfld.long 0x0 22.--23. "SAMPA,Sample Adjustment" "0,1,2,3"
|
|
bitfld.long 0x0 20.--21. "RXPO,Receive Data Pinout" "0: SERCOM PAD0 is used for data reception,1: SERCOM PAD1 is used for data reception,2: SERCOM PAD2 is used for data reception,3: SERCOM PAD3 is used for data reception"
|
|
newline
|
|
bitfld.long 0x0 16.--17. "TXPO,Transmit Data Pinout" "0: PAD[0] = TxD; PAD[1] = XCK,?,2: PAD[0] = TxD; PAD[2] = RTS; PAD[3] = CTS,3: PAD[0] = TxD; PAD[1] = XCK; PAD[2] = TE"
|
|
bitfld.long 0x0 13.--15. "SAMPR,Sample" "0: 16x oversampling using arithmetic baud rate..,1: 16x oversampling using fractional baud rate..,2: 8x oversampling using arithmetic baud rate..,3: 8x oversampling using fractional baud rate..,4: 3x oversampling using arithmetic baud rate..,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 10. "RXINV,Receive Data Invert" "0: RxD is not inverted,1: RxD is inverted"
|
|
bitfld.long 0x0 9. "TXINV,Transmit Data Invert" "0: TxD is not inverted,1: TxD is inverted"
|
|
newline
|
|
bitfld.long 0x0 8. "IBON,Immediate Buffer Overflow Notification" "0,1"
|
|
bitfld.long 0x0 7. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2.--4. "MODE,Operating Mode" "0: USART with external clock,1: USART with internal clock,2: SPI in slave operation,3: SPI in master operation,4: I2C slave operation,5: I2C master operation,?,?"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USART Control B"
|
|
bitfld.long 0x4 24.--25. "LINCMD,LIN Command" "0: Normal USART transmission,1: Break field is transmitted when DATA is written,2: Break synch and identifier are automaticcaly..,?"
|
|
bitfld.long 0x4 22.--23. "FIFOCLR,FIFO Clear" "0: No action,1: Clear TX FIFO,2: Clear RX FIFO,3: Clear both TX and RF FIFOs"
|
|
newline
|
|
bitfld.long 0x4 17. "RXEN,Receiver Enable" "0,1"
|
|
bitfld.long 0x4 16. "TXEN,Transmitter Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "PMODE,Parity Mode" "0: Even parity,1: Odd parity"
|
|
bitfld.long 0x4 10. "ENC,Encoding Format" "0: Data is not encoded,1: Data is IrDA encoded"
|
|
newline
|
|
bitfld.long 0x4 9. "SFDE,Start of Frame Detection Enable" "0,1"
|
|
bitfld.long 0x4 8. "COLDEN,Collision Detection Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 6. "SBMODE,Stop Bit Mode" "0: One stop bit,1: Two stop bits"
|
|
bitfld.long 0x4 0.--2. "CHSIZE,Character Size" "0: 8-bits character,1: 9-bits character,?,?,?,5: 5-bits character,6: 6-bits character,7: 7-bits character"
|
|
line.long 0x8 "CTRLC,USART Control C"
|
|
bitfld.long 0x8 30.--31. "TXTRHOLD,Transmit FIFO Threshold" "0: Interrupt and DMA triggers are generated as long..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
bitfld.long 0x8 28.--29. "RXTRHOLD,Receive FIFO Threshold" "0: Interrupt and DMA triggers are generated when..,1: Interrupt and DMA triggers are generated when..,2: Interrupt and DMA triggers are generated when..,?"
|
|
newline
|
|
bitfld.long 0x8 27. "FIFOEN,FIFO Enable" "0,1"
|
|
bitfld.long 0x8 24.--25. "DATA32B,Data 32 Bit" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 20.--22. "MAXITER,Maximum Iterations" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x8 17. "DSNACK,Disable Successive NACK" "0,1"
|
|
newline
|
|
bitfld.long 0x8 16. "INACK,Inhibit Not Acknowledge" "0,1"
|
|
bitfld.long 0x8 10.--11. "HDRDLY,LIN Master Header Delay" "0: Delay between break and sync transmission is..,1: Delay between break and sync transmission is..,2: Delay between break and sync transmission is..,3: Delay between break and sync transmission is.."
|
|
newline
|
|
bitfld.long 0x8 8.--9. "BRKLEN,LIN Master Break Length" "0: Break field transmission is 13 bit times,1: Break field transmission is 17 bit times,2: Break field transmission is 21 bit times,3: Break field transmission is 26 bit times"
|
|
bitfld.long 0x8 0.--2. "GTIME,Guard Time" "0,1,2,3,4,5,6,7"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRAC_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_FRACFP_MODE,USART Baud Rate"
|
|
bitfld.word 0x0 13.--15. "FP,Fractional Part" "0,1,2,3,4,5,6,7"
|
|
hexmask.word 0x0 0.--12. 1. "BAUD,Baud Rate Value"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "BAUD_USARTFP_MODE,USART Baud Rate"
|
|
hexmask.word 0x0 0.--15. 1. "BAUD,Baud Rate Value"
|
|
group.byte 0xE++0x0
|
|
line.byte 0x0 "RXPL,USART Receive Pulse Length"
|
|
hexmask.byte 0x0 0.--7. 1. "RXPL,Receive Pulse Length"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "INTENCLR,USART Interrupt Enable Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Disable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Disable" "0,1"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "INTENSET,USART Interrupt Enable Set"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt Enable" "0,1"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "INTFLAG,USART Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x0 7. "ERROR,Combined Error Interrupt" "0,1"
|
|
bitfld.byte 0x0 5. "RXBRK,Break Received Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CTSIC,Clear To Send Input Change Interrupt" "0,1"
|
|
bitfld.byte 0x0 3. "RXS,Receive Start Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXC,Receive Complete Interrupt" "0,1"
|
|
bitfld.byte 0x0 1. "TXC,Transmit Complete Interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DRE,Data Register Empty Interrupt" "0,1"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "STATUS,USART Status"
|
|
bitfld.word 0x0 7. "ITER,Maximum Number of Repetitions Reached" "0,1"
|
|
bitfld.word 0x0 6. "TXE,Transmitter Empty" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "COLL,Collision Detected" "0,1"
|
|
bitfld.word 0x0 4. "ISF,Inconsistent Sync Field" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "CTS,Clear To Send" "0,1"
|
|
bitfld.word 0x0 2. "BUFOVF,Buffer Overflow" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "FERR,Frame Error" "0,1"
|
|
bitfld.word 0x0 0. "PERR,Parity Error" "0,1"
|
|
rgroup.long 0x1C++0x3
|
|
line.long 0x0 "SYNCBUSY,USART Synchronization Busy"
|
|
bitfld.long 0x0 4. "LENGTH,LENGTH Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RXERRCNT,RXERRCNT Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "CTRLB,CTRLB Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SERCOM Enable Synchronization Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
rgroup.byte 0x20++0x0
|
|
line.byte 0x0 "RXERRCNT,USART Receive Error Count"
|
|
group.word 0x22++0x1
|
|
line.word 0x0 "LENGTH,USART Length"
|
|
bitfld.word 0x0 8.--9. "LENEN,Data Length Enable" "0: Length counter is disabled,1: Length counter is enabled for transmit,2: Length counter is enabled for receive,?"
|
|
hexmask.word.byte 0x0 0.--7. 1. "LEN,Data Length"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "DATA,USART Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Value"
|
|
group.byte 0x30++0x0
|
|
line.byte 0x0 "DBGCTRL,USART Debug Control"
|
|
bitfld.byte 0x0 0. "DBGSTOP,Debug Mode" "0,1"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "FIFOSPACE,USART FIFO Space"
|
|
hexmask.word.byte 0x0 8.--12. 1. "RXSPACE,Rx FIFO Filled Space"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TXSPACE,Tx FIFO Empty Space"
|
|
group.word 0x36++0x1
|
|
line.word 0x0 "FIFOPTR,USART FIFO CPU Pointers"
|
|
hexmask.word.byte 0x0 8.--11. 1. "CPURDPTR,CPU FIFO Read Pointer"
|
|
hexmask.word.byte 0x0 0.--3. 1. "CPUWRPTR,CPU FIFO Write Pointer"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "SIG (Software Interrupt Generation)"
|
|
base ad:0xE000EF00
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "STIR,Software Triggered Interrupt Register"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID to be pended"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "SIG_NS (Software Interrupt Generation (Non-Secure))"
|
|
base ad:0xE002EF00
|
|
wgroup.long 0x0++0x3
|
|
line.long 0x0 "STIR,Software Triggered Interrupt Register"
|
|
hexmask.long.word 0x0 0.--8. 1. "INTID,Interrupt ID to be pended"
|
|
tree.end
|
|
endif
|
|
tree "SPI_IXS (Inter-IC Sound Interface)"
|
|
base ad:0x45016000
|
|
group.long 0x0++0x23
|
|
line.long 0x0 "CTRLA,SPI Control Enable Register"
|
|
bitfld.long 0x0 6. "RUNSTDBY,RUN STANDBY Mode Enable bit" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,SPI Enable (ON) bit" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,SPI Software Reset" "0,1"
|
|
line.long 0x4 "SELCTRL,SPI Control Options Select Register"
|
|
bitfld.long 0x4 30.--31. "MODEEN,MACRO MODE ENABLED" "0: Default Mode,1: Audio Mode,2: Framed Mode,3: Broadcast Mode"
|
|
bitfld.long 0x4 24. "DATFILL,DATFILL undefined bits 1 or 0" "0,1"
|
|
bitfld.long 0x4 23. "TURSAMP,Transmit Under-run last sample sent" "0,1"
|
|
newline
|
|
bitfld.long 0x4 16. "DATFMTLR,Packed data format -- left or right justified" "0,1"
|
|
bitfld.long 0x4 14. "IGNTUR,Ignore Transmit Underrun (for Audio Data Transmissions)" "0,1"
|
|
bitfld.long 0x4 12.--13. "STXISEL,SPI Transmit Service Request Interrupt Select" "0: TXB And SR Empty,1: TXB Empty,2: TXB Half Empty,3: TXB Not Full"
|
|
newline
|
|
bitfld.long 0x4 11. "CPOL,Clock Polarity Select bit" "0,1"
|
|
bitfld.long 0x4 10. "CPHA,SPI Clock Edge Select bit" "0,1"
|
|
bitfld.long 0x4 6. "IGNROV,Ignore Receive Overflow (for Audio Data Transmissions)" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4.--5. "SRXISEL,SPI Receive Service Request Interrupt Select" "0: RXB Empty,1: RXB Not Empty,2: RXB Half Full,3: RXB Full"
|
|
bitfld.long 0x4 0.--1. "CLKINDLY,Serial Clock Input Delay for SDI sampling" "0: 0 Tap Delays,1: 1 Tap Delay,2: 2 Tap Delay,3: 3 Tap Delay"
|
|
line.long 0x8 "SPICTRL,SPI Control Register"
|
|
bitfld.long 0x8 10. "SMP,SPI Data Input Sample Phase bit" "0,1"
|
|
bitfld.long 0x8 9. "SPISGNEXT,Sign Extend Read Data from the RX FIFO" "0,1"
|
|
bitfld.long 0x8 6. "MSSEN,Master/Slave Mode Select Enable bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 5. "MSTEN,Master Mode Enable bit" "0,1"
|
|
bitfld.long 0x8 4. "DISSDO,Disable SDO bit" "0,1"
|
|
bitfld.long 0x8 3. "DISSDI,Disable SDI bit" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "MODE,Serial Word Length bits for AUDEN=0 not used when AUDEN=1" "0: 8 Bits Mode,1: 16 Bits Mode,2: 32 Bits Mode,?"
|
|
line.long 0xC "FRAMECTRL,SPI Control Frame Register"
|
|
bitfld.long 0xC 29.--31. "TDMWSZ,TDM Number of Bits in a Word Size" "0: Word Size 8,1: Word Size 12,2: Word Size 16,3: Word Size 20,4: Word Size 24,5: Word Size 28,6: Word Size 32,?"
|
|
bitfld.long 0xC 24.--26. "TDMSSZ,TDM Number of Bits in a Slot Size" "0: Slot Size 8,1: Slot Size 12,2: Slot Size 16,3: Slot Size 20,4: Slot Size 24,5: Slot Size 28,6: Slot Size 32,?"
|
|
hexmask.long.byte 0xC 16.--20. 1. "FRMCNT,Frame sync pulse counter"
|
|
newline
|
|
bitfld.long 0xC 14. "FRMSLV,Frame Sync Pulse Direction Control bit" "0,1"
|
|
bitfld.long 0xC 13. "FRMPOL,Frame Sync / Slave Select Polarity bit" "0,1"
|
|
bitfld.long 0xC 8. "FRMCOINC,Frame Sync Pulse Edge Select bit" "0,1"
|
|
newline
|
|
hexmask.long.byte 0xC 0.--3. 1. "FRMSYPW,Frame sync pulse width in serial words"
|
|
line.long 0x10 "AUDCTRL,SPI Control Audio Register"
|
|
bitfld.long 0x10 8.--9. "AUDWDMODE,Serial Word Length bits (Ignored when AUDEN=0)" "0,1,2,3"
|
|
bitfld.long 0x10 4.--6. "AUDFMT,Audio Protocol Format" "0: Legacy I2S Mode,1: I2S Raw Audio Format,2: I2S Other AM824 Format,?,4: I8S Other Format,5: I8S Raw Audio Format,6: I8S Other AM824 Format,?"
|
|
bitfld.long 0x10 3. "AUDMONO,Transmit audio data format" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0.--1. "AUDMOD,Audio Protocol Mode" "0: I2S/I8S Standard Mode,1: I2S/I8S Left Or Right Justified,?,3: PCM/DSP Mode"
|
|
line.long 0x14 "TPDCTRL,SPI Control Tpd Register"
|
|
bitfld.long 0x14 8.--10. "SLVNUM,Number of the Slave designated: to be used with the PKFMT to determine the slave." "0: SLAVE 0,1: SLAVE 1,2: SLAVE 2,3: SLAVE 3,4: SLAVE 4,?,?,?"
|
|
bitfld.long 0x14 0.--2. "PKFMT,Master Slave TPD mode." "0: 32 bit data in 4x32 packed format,1: 32 bit data in 3x32 packed format,2: 24 bit data in 4x24 packed format,3: 24 bit data in 3x24 packed format,4: 16 bit data in 6x16 packed format,5: 16 bit data in 4x16 packed format,6: 16 bit data in 2x16 packed format,?"
|
|
line.long 0x18 "INTENSET,SPI Interrupt Enable Set Register"
|
|
bitfld.long 0x18 30. "SPIROVEN,Enable Interrupt Events via SPIROV" "0,1"
|
|
bitfld.long 0x18 27. "SPITUREN,Enable Interrupt Events via SPITUR" "0,1"
|
|
bitfld.long 0x18 15. "FRMERREN,Enable Interrupt Events via FRMERR" "0,1"
|
|
newline
|
|
bitfld.long 0x18 4. "SPITXBEEN,Enablie Interrupt Events via SPITXBE" "0,1"
|
|
bitfld.long 0x18 0. "SPIRXBFEN,Enablie Interrupt Events via SPIRXBF" "0,1"
|
|
line.long 0x1C "INTENCLR,SPI Interrupt Enable Clear Register"
|
|
bitfld.long 0x1C 30. "SPIROVEN,Enable Interrupt Events via SPIROV" "0,1"
|
|
bitfld.long 0x1C 27. "SPITUREN,Enable Interrupt Events via SPITUR" "0,1"
|
|
bitfld.long 0x1C 15. "FRMERREN,Enable Interrupt Events via FRMERR" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 4. "SPITXBEEN,Enablie Interrupt Events via SPITXBE" "0,1"
|
|
bitfld.long 0x1C 0. "SPIRXBFEN,Enablie Interrupt Events via SPIRXBF" "0,1"
|
|
line.long 0x20 "INTFLAG,SPI Interrupt Flag Register"
|
|
bitfld.long 0x20 30. "SPIROV,Receive Overflow Status bit" "0,1"
|
|
bitfld.long 0x20 27. "SPITUR,Transmit Underrun Status bit" "0,1"
|
|
bitfld.long 0x20 15. "FRMERR,SPI Frame Error Status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x20 4. "SPITXBE,SPI Transmit Buffer Empty Status Bit" "0,1"
|
|
bitfld.long 0x20 0. "SPIRXBF,SPI Receive Buffer Full Status Bit" "0,1"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "STATUS,SPI Status Register"
|
|
bitfld.long 0x0 31. "SPIRBE,RX Buffer Empty bit" "0,1"
|
|
bitfld.long 0x0 29. "SPIRBF,SPI Receive Buffer Full status bit" "0,1"
|
|
bitfld.long 0x0 28. "SPITBE,SPI Transmit Buffer Empty status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 26. "SPITBF,SPI Transmit Buffer Full Status bit" "0,1"
|
|
hexmask.long.word 0x0 16.--24. 1. "TXBUFELM,Transmit Buffer Element Count bits"
|
|
bitfld.long 0x0 14. "SPIBUSY,SPI activity status bit" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "SRMT,Register (SR) Empty bit" "0,1"
|
|
hexmask.long.word 0x0 0.--8. 1. "RXBUFELM,Receive Buffer Element Count bits"
|
|
group.long 0x28++0xB
|
|
line.long 0x0 "BUF,SPI Buffer Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,FIFO Data bits"
|
|
line.long 0x4 "BRG,SPI Baud Rate Register"
|
|
hexmask.long.word 0x4 0.--12. 1. "BRG,Baud Rate Divisor bits"
|
|
line.long 0x8 "DBGCTRL,SPI Debug Control Register"
|
|
bitfld.long 0x8 0. "DBGRUN,Debug Running State" "0,1"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "SYNCBUSY,SPI Sync Busy Register"
|
|
bitfld.long 0x0 0. "SWRSTBSY,Software reset busy bit --- Synchronizing Busy bit for swrst" "0,1"
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "EVCTRL,SPI Event Control Register"
|
|
bitfld.long 0x0 0. "FPSEEN,Frame Pulse Event Enable Bit" "0,1"
|
|
tree.end
|
|
tree "SQI (Serial Quad Interface)"
|
|
base ad:0xFFFF000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A register"
|
|
bitfld.long 0x0 6. "RUNSTDBY,Run in Standby" "0: Module is disabled in Standby Sleep mode,1: Module continues to run in Standby Sleep mode"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0: No reset in progress,1: Reseting the registers and EIP"
|
|
group.long 0x10++0xB
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear Register"
|
|
bitfld.long 0x0 0. "SQI,SQI Interrupt Enable Clear" "0: Interrupt Enabled,1: Interrupt Disabled"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set Register"
|
|
bitfld.long 0x4 0. "SQI,SQI Interrupt Enable Set" "0: Interrupt disabled,1: Interrupt enabled"
|
|
line.long 0x8 "INTFLAG,Interrupt Status and Clear Register"
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bitfld.long 0x8 0. "SQI,Read value reflects the state of the interrupt flag. Do not use the interrupt flag and associated mask registers if the EIP already provides similar controls for its interrupts. This feature is design for interrupts created in the SIB or EIP which do.." "0,1"
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rgroup.long 0x20++0x3
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line.long 0x0 "SYNCBUSY,Syncbusy Register"
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bitfld.long 0x0 0. "SWRST,Software Reset Synchronization Busy" "0: SWRST synchronization is not busy,1: SWRST synchronization is busy"
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group.long 0x100++0x27
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line.long 0x0 "XCON1,SPI XIP Control1 register"
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bitfld.long 0x0 29. "SDRCMD,SPI TYPE CMD SDR2DDR: This bit is used by the controller only when XIP_SPI_TYPE_CMD_DDR is 1?b1 i.e. when command sent in DDR mode. 0 - The command (XIP_SPI_READ_OPCODE) will take 4 clock cycles. Data will go in both the edges. Used when Flash.." "?,1: Say opcode = 'h ac"
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bitfld.long 0x0 28. "DDRDATA,XIP SPI TYPE DATA DDR 0 - SDR mode 1 - DDR mode. Based on this field the boot controller will send the data in SDR/DDR mode." "0,1"
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bitfld.long 0x0 27. "DDRDUMMY,XIP SPI TYPE DUMMY DDR. 0 - SDR mode 1 - DDR mode. Based on this field the boot controller will send the dummy bytes in SDR/DDR mode." "0,1"
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bitfld.long 0x0 26. "DDRMODE,XIP SPI TYPE MODE DDR 0 - SDR mode 1 - DDR mode. Based on this field the boot controller will send the mode bytes in SDR/DDR mode." "0,1"
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bitfld.long 0x0 25. "DDRADDR,XIP SPI TYPE ADDR DDR 0 - SDR mode 1 - DDR mode. Based on this field the boot controller will send the address bytes in SDR/DDR mode." "0,1"
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bitfld.long 0x0 24. "DDRCMD,XIP SPI TYPE CMD DDR 0 - SDR mode 1 - DDR mode. Based on this field the boot controller will send the command in SDR/DDR mode." "0,1"
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bitfld.long 0x0 21.--23. "DUMMYBYTES,000 - Zero Dummy bytes 001 - Transmit one dummy byte (8?h ff) 010 - Transmit two dummy bytes (16?h ffff) 011 - Transmit three dummy bytes (24?h ffffff) 111 - Transmit Seven dummy bytes" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 18.--20. "ADDRBYTES,000 - Zero Address Bytes 001 - 1 Address Byte 010 - 2 Address Bytes 011 - 3 Address Bytes 100 - 4 Address Bytes 101 - 111- Reserved for Future Use" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x0 10.--17. 1. "READOPCODE,8bit opcode value for Read operation"
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bitfld.long 0x0 8.--9. "TYPEDATA,SPI TYPE DATA: 00 - Single lane mode 01 - Dual lane mode 10 - Quad lane mode 11 - Reserved for Future use Based on this field the boot controller will receive the data in 1/2/4 lane." "0,1,2,3"
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bitfld.long 0x0 6.--7. "TYPEDUMMY,SPI TYPE DUMMY: 00 - Single lane mode 01 - Dual lane mode 10 - Quad lane mode 11 - Reserved for Future use. Based on this field the boot controller will send the Dummy in 1/2/4 lane." "0,1,2,3"
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bitfld.long 0x0 4.--5. "TYPEMODE,SPI TYPE Mode: 00 - Single lane mode 01 - Dual lane mode 10 - Quad lane mode 11 - Reserved for Future use. Based on this field the boot controller will send the Mode in 1/2/4 lane." "0,1,2,3"
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bitfld.long 0x0 2.--3. "TYPEADDR,SPI TYPE Address 00 - Single lane mode 01 - Dual lane mode 10 - Quad lane mode 11 - Reserved for Future use Based on this field the boot controller will send the Address in 1/2/4 lane." "0,1,2,3"
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bitfld.long 0x0 0.--1. "TYPECMD,SPI TYPE Command - Single lane mode - Dual lane mode - Quad lane mode - Reserved for Future use Based on this field the boot controller will send the command in 1/2/4 lane." "0,1,2,3"
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line.long 0x4 "XCON2,SPI XIP Control2 register"
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bitfld.long 0x4 10.--12. "DEVSEL,XIP SPI Device Select: This field is used to select a particular SPI device 000 - Select Device0 001 - Select Device1 010 - Select Device2 011 - Select Device3 100 - Select Device4 101 - Select Device5 110 - Select Device6 111 -.." "0,1,2,3,4,5,6,7"
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bitfld.long 0x4 8.--9. "MODEBYTES,Mode Bytes 00 - 0 Mode Bytes 01 - 1 Mode Byte 10 - 2 Mode Bytes 11 - 3 Mode Bytes" "0,1,2,3"
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hexmask.long.byte 0x4 0.--7. 1. "MODECODE,8bit value for Mode byte"
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line.long 0x8 "CFG,SPI Configuration Register"
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hexmask.long.byte 0x8 24.--31. 1. "CSEN,1 - Chip Select is used 0 - Chip Select is not used SPI_CS[7] for CS7 SPI_CS[6] for CS6 SPI_CS[5] for CS5 SPI_CS[4] for CS4 SPI_CS[3] for CS3 SPI_CS[2] for CS2 SPI_CS[1] for CS1 SPI_CS[0] for CS0. SPI_CS_PIN_EN[7:0/3:0] output pins.."
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bitfld.long 0x8 23. "SQIEN,1 - Enabled 0 - Disabled SPI_ON output pin is controlled by writing to this bit." "0,1"
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bitfld.long 0x8 20.--21. "DATAEN,Max Data Lanes 11 - Reserved 10 - 4 01 - 2 00 - 1 SPI_OUT_PIN_EN[3:0] output pins are controlled by writing to these bits." "0,1,2,3"
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bitfld.long 0x8 19. "CONBUFRST,Control FIFO Reset A reset pulse is generated when writing 1 to this bit. This bit is Auto clear and SPI Controller will clear this bit. Control fifo pointers will get reset by this reset pulse. Note: Control FIFO reset can be done only after a.." "0,1"
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bitfld.long 0x8 18. "RXBUFRST,Receive FIFO Reset A reset pulse is generated when writing 1 to this bit. This bit is Auto clear and SPI Controller will clear this bit. Receive fifo pointers will get reset by this reset pulse. Note: Receive FIFO reset can be done only after a.." "0,1"
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bitfld.long 0x8 17. "TXBUFRST,Transmit FIFO Reset A reset pulse is generated when writing 1 to this bit. This bit is Auto clear and SPI Controller will clear this bit. Transmit FIFO pointers will get reset by this reset pulse. Note: Transmit FIFO reset can be done only after.." "0,1"
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bitfld.long 0x8 14. "AHB_BURST_INCR16_EN,This field is used to configure the AHB Master Burst capability. 1 - AHB INCR16 is enabled. 0 - AHB INCR16 is disabled" "0,1"
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bitfld.long 0x8 13. "AHB_BURST_INCR8_EN,This field is used to configure the AHB Master Burst capability. 1 - AHB INCR8 is enabled. 0 - AHB INCR8 is disabled" "0,1"
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bitfld.long 0x8 12. "AHB_BURST_INCR4_EN,This field is used to configure the AHB Master Burst capability. 1 - AHB INCR4 is enabled. 0 - AHB INCR4 is disabled" "0,1"
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bitfld.long 0x8 11. "BURSTEN,This field is used to configure the AHB Master Burst capability. 1 - AHB INCR is enabled 0 - AHB INCR is disabled" "0,1"
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bitfld.long 0x8 10. "HOLD,Hold: In Single or Dual lane mode this bit is used to drive the spiout3 signal. Whenever this bit is high the controller drives 0 on spiout3 line and sets spimoe3 high (active only during transfer)." "0,1"
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bitfld.long 0x8 9. "WP,Write Protect: In single or Dual lane mode this bit is used to drive the spiout2 signal. Whenever this bit is high the controller drives 0 on spiout2 line and sets spimoe2 high (active only during transfer)." "0,1"
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bitfld.long 0x8 5. "LSBF,Data format on SPI interface 0 = MSBit sent/received first. 1 = LSBit sent/received first. This setting is supeceded by LSBF control bit in Buffer Descriptor during DMA operations." "0: MSBit sent/received first,1: LSBit sent/received first"
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bitfld.long 0x8 4. "CPOL,Clock polarity 0 = active-high SPICLK (SPICLK low is the idle state) 1 = active-low SPICLK (SPICLK high is the idle state)" "0: active-high SPICLK,1: active-low SPICLK"
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bitfld.long 0x8 3. "CPHA,Clock phase (selects the transfer format) 0 = SPICLK starts toggling at the middle of 1st data bit. 1 = SPICLK starts toggling at the start of 1st data bit." "0: SPICLK starts toggling at the middle of 1st data..,1: SPICLK starts toggling at the start of 1st data.."
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bitfld.long 0x8 0.--2. "MODE,Mode Select The default value of this field is 0. After power on reset the controller enters boot mode. 000 - Boot mode. The CSR registers are loaded with boot strap values. 001 - PIO mode. The controller is controlled by the CPU in PIO mode. 010 -.." "0,1,2,3,4,5,6,7"
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line.long 0xC "CON,SPI Control register"
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bitfld.long 0xC 25. "DEV_SEL_2,SPI Device Select[2]: This field along with SPI DEVICE SELECT [1:0] (bits 21:20) together is used to select a particular SPI device. Bit25 Bit21 Bit20 0 0 0 - SPI Device 0 0 0 1 - SPI Device 1 0 1 0 - SPI Device 2 0 1 1 - SPI Device 3 1 0.." "?,?"
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bitfld.long 0xC 24. "SCHECK,Status Check This bit is mainly used for Programming or Erase operations. 0 - do not check status 1 - check status. If this bit is set to 1 the hardware will issue the status command automatically after the current operation and wait for busy.." "0,1"
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bitfld.long 0xC 23. "DDRMODE,SDR_DDR: 0 - SDR mode 1 - DDR mode. Note: For Michigan Ax versions this bit is Reserved and should be kept 0." "0,1"
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bitfld.long 0xC 22. "DASSERT,Chip Select Assert 0 - CS is not de-asserted after transmission/reception of specified number of bytes in the control register 1 - CS is de-asserted after transmission/reception of specified number of bytes in the control register" "0,1"
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bitfld.long 0xC 20.--21. "DEVSEL,SPI Device Select: This field along with bit25 is used to select a particular SPI device. Note: For Michigan Ax versions extension by bit25 is NOT used (only 4 devices are selectable by bits 21:20 here)." "?,?,?,?"
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bitfld.long 0xC 18.--19. "LANEMODE,SPI Lane mode 00 - Single lane mode 01 - Dual lane mode 10 - Quad lane mode 11 - Reserved for Future use" "0,1,2,3"
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bitfld.long 0xC 16.--17. "CMDINIT,This signal indicates the command initiation mode. If it is Transmit Commands are initiated based on writes to transmit register or the contents of TX FIFO. If the CMD_INIT is Receive commands are initiated based on reads to Read register or RX.." "0: Reserved,1: Initiate Transmit,?,?"
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hexmask.long.word 0xC 0.--15. 1. "TXRXCOUNT,This bit specifies the total number of bytes to transmit or receive (based on CMD_INIT field). 16?d 0 - Reserved 16?d 1 - 1byte to transmit/receive 16?d 2 - 2bytes to transmit/receive NOTE: Count must be programmed to non-zero value prior to.."
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line.long 0x10 "CLKCON,SPI Clock Control register"
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hexmask.long.word 0x10 8.--18. 1. "CLKDIV,SPI Clock Frequency Select 400h - base clock divided by 2048 200h - base clock divided by 1024 100h - base clock divided by 512 080h - base clock divided by 256 040h - base clock divided by 128 020h - base clock divided by 64 010h - base.."
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bitfld.long 0x10 1. "STABLE,After Reset this bit is set to 1 when SPI Clock is stable after writing Internal Clock Enable in this register to 1. The Clock Stable indication will continue unless the Clock Divisor Value is changed in which case it.." "0,1"
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bitfld.long 0x10 0. "EN,This bit is set to 0 when the SPI Driver is not using the SPI Controller. The SPI Controller should stop its internal clock to go very low power state. Still registers will be able to be read and written. Clock starts to oscillate when this bit is.." "0,1"
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line.long 0x14 "CMDTHR,SPI command threshold register"
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hexmask.long.byte 0x14 8.--15. 1. "TXCMDTHR,In TX Initiation Mode SPI Performs a transmit Operation when TX_CMD_THRES bytes are present in the TX FIFO. This should usually be set to 1 for normal flash commands and is desired to be set to a higher value for page programming. NOTE: Value.."
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hexmask.long.byte 0x14 0.--7. 1. "RXCMDTHR,In RX initiation mode SPI attempts to perform receive fetch operations until RX_CMD_THRES bytes of space remain in the receive buffer. If space for RX_CMD_THRES bytes is not present in the FIFO then SPI would not initiate any transfer."
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line.long 0x18 "INTTHR,SPI Interrupt Threshold register"
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hexmask.long.byte 0x18 8.--15. 1. "TXINTTHR,Transmit Interrupt is set when Transmit FIFO has equal or more space than TX_INT_THRES bytes."
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hexmask.long.byte 0x18 0.--7. 1. "RXINTTHR,Receive Interrupt is set when Receive FIFO CNT is larger than or equal to RX_INT_THRES Value."
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line.long 0x1C "INTEN,SPI Interrupt Enable Register"
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bitfld.long 0x1C 11. "DMAEIE,Master Error Interrupt Enable" "0,1"
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bitfld.long 0x1C 10. "PKTCOMPIE,Packet completion Interrupt" "0,1"
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bitfld.long 0x1C 9. "BDDONEIE,Current Buffer Descriptor Interrupt Enable" "0,1"
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bitfld.long 0x1C 8. "CONTHRIE,Control Buffer Threshold Interrupt Enable" "0,1"
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bitfld.long 0x1C 7. "CONEMPTYIE,Control Buffer Empty Interrupt Enable" "0,1"
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bitfld.long 0x1C 6. "CONFULLIE,Control Buffer Full Interrupt Enable" "0,1"
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bitfld.long 0x1C 5. "RXTHRIE,Enable Interrupt to be generated when the RX FIFO has data more than or equal to RX_INT_THRES words. In case of Boot/XIP mode the power on reset value of RX buffer threshold is zero. So this bit will be set to 1 immediately after power on.." "0,1"
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bitfld.long 0x1C 4. "RXFULLIE,RX FIFO Full Interrupt Enable." "0,1"
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bitfld.long 0x1C 3. "RXEMPTYIE,RX FIFO Empty Interrupt Enable." "0,1"
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bitfld.long 0x1C 2. "TXTHRIE,Enable Interrupt to be generated when the TX FIFO has space equal to or more than TX_INT_THRES words." "0,1"
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bitfld.long 0x1C 1. "TXFULLIE,TX FIFO Full Interrupt Enable." "0,1"
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bitfld.long 0x1C 0. "TXEMPTYIE,TX FIFO Empty Interrupt Enable." "0,1"
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line.long 0x20 "INTSTAT,SPI Interrupt Status Register"
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bitfld.long 0x20 11. "DMAEIF,Master Error Interrupt" "0,1"
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bitfld.long 0x20 10. "PKTCOMPIF,Packet completion Interrupt" "0,1"
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bitfld.long 0x20 9. "BDDONEIF,BDP sets this bit to '1' after current buffer descriptor is processed" "0,1"
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bitfld.long 0x20 8. "CONTHRIF,Control Buffer Threshold Interrupt" "0,1"
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bitfld.long 0x20 7. "CONEMPTYIF,Control Buffer Empty Interrupt" "0,1"
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bitfld.long 0x20 6. "CONFULLIF,Control Buffer Full Interrupt" "0,1"
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bitfld.long 0x20 5. "RXTHRIF,Interrupt to be generated when the RX FIFO has data more than or equal to RX_INT_THRES words. In case of Boot/XIP mode the power on reset value of RX buffer threshold is zero. So this bit will be set to 1 immediately after power on reset till.." "0,1"
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bitfld.long 0x20 4. "RXFULLIF,RX FIFO Full Interrupt." "0,1"
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bitfld.long 0x20 3. "RXEMPTYIF,RX FIFO Empty Interrupt." "0,1"
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bitfld.long 0x20 2. "TXTHRIF,Interrupt to be generated when the TX FIFO has space equal to or more than TX_INT_THRES words." "0,1"
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bitfld.long 0x20 1. "TXFULLIF,TX FIFO Full Interrupt." "0,1"
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bitfld.long 0x20 0. "TXEMPTYIF,TX FIFO Empty Interrupt." "0,1"
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line.long 0x24 "TXDATA,SPI Transmit Data Register"
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hexmask.long 0x24 0.--31. 1. "TXDATA,Data is loaded into this register before being transmitted. Just prior to the beginning of a data transfer the data in TX_DATA is loaded into the shift register. This register is used as a window to write data into Transmit buffer."
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rgroup.long 0x128++0xB
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line.long 0x0 "RXDATA,SPI Receive Data Register"
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hexmask.long 0x0 0.--31. 1. "RXDATA,At the end of a data transfer the data in the shift register is loaded into RX_DATA register. This register is used as a window to read data from Receive buffer."
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line.long 0x4 "STAT1,SPI Status1 Register"
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hexmask.long.word 0x4 16.--31. 1. "TXBUFFREE,Number of Words of Space available in the TX FIFO. Max value equals value of MEM_SIZE_BYTES parameter. Default value is Max"
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hexmask.long.word 0x4 0.--15. 1. "RXBUFCNT,Number of Words of Read Data in the FIFO."
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line.long 0x8 "STAT2,SPI status 2 register"
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bitfld.long 0x8 16.--17. "CMDSTAT,Reflect the (internal state machine) CMD_INIT value. Indicates whether the controller is in Transmit/Receive/IDLE state. 2?b00 - IDLE 2?b01 - Transmit 2?b10 - Receive 2?b11 - Reserved" "0,1,2,3"
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bitfld.long 0x8 7.--9. "CONAVAIL,Indicates the number of entries in Control Buffer remaining. NOTE: This field not present in Michigan Ax versions. Treat as Reserved." "0,1,2,3,4,5,6,7"
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bitfld.long 0x8 6. "SQID3,SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 Bit4 - SPI_IO1 Bit5 - SPI_IO2 Bit6 - SPI_IO3" "0,1"
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bitfld.long 0x8 5. "SQID2,SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 Bit4 - SPI_IO1 Bit5 - SPI_IO2 Bit6 - SPI_IO3" "0,1"
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bitfld.long 0x8 4. "SQID1,SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 Bit4 - SPI_IO1 Bit5 - SPI_IO2 Bit6 - SPI_IO3" "0,1"
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bitfld.long 0x8 3. "SQID0,SPI Data bus: This status is used to check the SPI DATA line level for Debugging. Bit3 - SPI_IO0 Bit4 - SPI_IO1 Bit5 - SPI_IO2 Bit6 - SPI_IO3" "0,1"
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bitfld.long 0x8 1. "RXUN,This bit would get set when RX FIFO UNDERFLOW happens. S/W needs to monitor RX_FIFO_CNT when emptying RX_FIFO to make sure RX FIFO doesn?t under flow or in case UNDERFLOW bit gets set then RX_FIFO_RST (bit 18 of SPI Configuration register) must be.." "0,1"
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bitfld.long 0x8 0. "TXOV,This bit would get set when TX FIFO OVERFLOW happens. S/W needs to monitor TX_FIFO_FREE when filling TX_FIFO to make sure TX FIFO doesn?t over flow or in case OVERFLOW bit gets set then TX_FIFO_RST (bit 17 of SPI Configuration register) should be.." "0,1"
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group.long 0x134++0x3
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line.long 0x0 "BDCON,BD_CTRL Register"
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bitfld.long 0x0 2. "START,Setting this bit to '1' would start BDP (Buffer Descriptor Processor) to fetch a descriptor and hence this bit should be enabled only after all the DMA descriptor programming is done. Hardware clears this bit automatically after one clock cycle." "0,1"
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bitfld.long 0x0 1. "POLLEN,Setting this bit would cause Buffer Descriptor processor (BDP) to poll for descriptor valid till descriptor valid bit is set or till poll counter expires based on value programmed in BD_POLL_CTRL register." "0,1"
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bitfld.long 0x0 0. "DMAEN,DMA Enable Bit 1 - Enabled 0 - Disabled" "0,1"
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rgroup.long 0x138++0x3
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line.long 0x0 "BDCURADD,BD_CURR_ADDR Register"
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hexmask.long 0x0 0.--31. 1. "BDCURRADDR,This register field contains the current descriptor address being processed by Buffer Descriptor Processor (BDP)"
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group.long 0x140++0x3
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line.long 0x0 "BDBASEADD,BD_BASE_ADDR register"
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hexmask.long 0x0 0.--31. 1. "BDADDR,This register field contains the base address of the DMA. This register must be updated only when the DMA is IDLE."
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rgroup.long 0x144++0x3
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line.long 0x0 "BDSTAT,BD_STATUS Register"
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hexmask.long.byte 0x0 18.--21. 1. "BDSTATE,This register field contains current BDP state : 0 IDLE 1 Descriptor fetch Request Pending 2 BD loading 3 Data phase 4 Descriptor Done 5 Fetched BD is disabled 6 Wait for Control Buffer Available 7 Wait for AHB Error.."
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bitfld.long 0x0 17. "DMASTART,This register field would indicate whether DMA has started or not if bit it set '1' then it indicates DMA start has happened. Value of '0' would indicate that DMA hasn't started." "0,1"
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bitfld.long 0x0 16. "DMAACTV,A value of '1' would indicate that Buffer Descriptor Processor (BDP) is not Idle. Value of '0' would indicate that BDP is in IDLE state" "0,1"
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hexmask.long.word 0x0 0.--15. 1. "BDCON,This register field contains the current Descriptor control information. Bits [31:16] of BD_CTRL field of current descriptor are indicated in this register field."
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group.long 0x148++0x7
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line.long 0x0 "BDPOLLCON,BD_POLL_CTRL Register"
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hexmask.long.word 0x0 0.--15. 1. "POLLCON,Number of cycles that BDP block would wait before re-fetching the Descriptor control word if the previous descriptor fetched was disabled"
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line.long 0x4 "BDTXDSTAT,BD_TX_DMA_STATUS Register"
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hexmask.long.byte 0x4 16.--23. 1. "TXBUFCNT,This register field gives the information about the internal transmit FIFO space."
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hexmask.long.word 0x4 0.--15. 1. "TXCURBUFLEN,This register field gives the length of the current buffer transmit length"
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rgroup.long 0x150++0x3
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line.long 0x0 "BDRXDSTAT,BD_RX_DMA_STATUS Register"
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bitfld.long 0x0 16. "RXBUFCNT,This register field gives the information about the internal receive FIFO space." "0,1"
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hexmask.long.word 0x0 0.--15. 1. "RXCURBUFLEN,This register field gives the length of the current buffer receive length"
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group.long 0x154++0x17
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line.long 0x0 "THR,SPI Control threshold register"
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bitfld.long 0x0 0.--2. "THRES,SPI Control Threshold Value. SPI Control Threshold Interrupt is asserted whenever larger than SPI Control Threshold amount of space available in SPI Control Buffer." "0,1,2,3,4,5,6,7"
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line.long 0x4 "INTSIGEN,SPI Interrupt Signal Enable Register"
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bitfld.long 0x4 11. "DMAEISE,Master Error Interrupt Signal Enable" "0,1"
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bitfld.long 0x4 10. "PKTCOMPISE,Packet completion Interrupt Signal Enable" "0,1"
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bitfld.long 0x4 9. "BDDONEISE,Current Buffer Descriptor Interrupt Signal Enable" "0,1"
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bitfld.long 0x4 8. "CONTHRISE,Control Buffer Threshold Interrupt Signal Enable" "0,1"
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bitfld.long 0x4 7. "CONEMPTYISE,Control Buffer Empty Interrupt Signal Enable" "0,1"
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bitfld.long 0x4 6. "CONFULLISE,Control Buffer Full Interrupt Signal Enable" "0,1"
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bitfld.long 0x4 5. "RXTHRISE,Signal Enable Interrupt to be generated when the RX FIFO has data more than or equal to RX_INT_THRES words. In case of Boot/XIP mode the power on reset value of RX buffer threshold is zero. So this bit will be set to 1 immediately after power.." "0,1"
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bitfld.long 0x4 4. "RXFULLISE,RX FIFO Full Interrupt Signal Enable." "0,1"
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bitfld.long 0x4 3. "RXEMPTYISE,RX FIFO Empty Interrupt Signal Enable." "0,1"
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bitfld.long 0x4 2. "TXTHRISE,Signal Enable Interrupt to be generated when the TX FIFO has space equal to or more than TX_INT_THRES words." "0,1"
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bitfld.long 0x4 1. "TXFULLISE,TX FIFO Full Interrupt Signal Enable." "0,1"
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bitfld.long 0x4 0. "TXEMPTYISE,TX FIFO Empty Interrupt Signal Enable." "0,1"
|
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line.long 0x8 "TAPCON,Tap Control Register"
|
|
hexmask.long.byte 0x8 24.--29. 1. "DDRCLKINDLY,Used only in DDR mode. This field is used to add tap delay cells on the spi clock input. Based on the mode of operation (SDR Vs DDR) the controller dynamically picks the appropriate delay values (CLK_IN_DLY_CNT Vs CLK_IN_ALT_DLY_CNT)."
|
|
hexmask.long.byte 0x8 20.--23. 1. "SDRDATINDLY,Used only in SDR mode. This field is used to add tap delay cells on the Data input. Based on the mode of operation (SDR Vs DDR) the controller dynamically picks the appropriate delay values (DATA_IN_ALT_DLY_CNT Vs DATA_IN_DLY_CNT)."
|
|
newline
|
|
hexmask.long.byte 0x8 16.--19. 1. "DDRDATINDLY,Used only in DDR mode. This field is used to add tap delay cells on the data input. Based on the mode of operation (SDR Vs DDR) the controller dynamically picks the appropriate delay values (DATA_IN_ALT_DLY_CNT Vs DATA_IN_DLY_CNT)."
|
|
hexmask.long.byte 0x8 8.--13. 1. "SDRCLKINDLY,Used only in SDR mode. This field is used to add tap delay cells on the spi clock input. Based on the mode of operation (SDR Vs DDR) the controller dynamically picks the appropriate delay values (CLK_IN_DLY_CNT Vs CLK_IN_ALT_DLY_CNT)."
|
|
newline
|
|
hexmask.long.byte 0x8 4.--7. 1. "DATAOUTDLY,Used to add delay on spi data outputs (1/2/4lanes). 16 taps available."
|
|
hexmask.long.byte 0x8 0.--3. 1. "CLKOUTDLY,Used to add delay on spi clock output.16 taps available."
|
|
line.long 0xC "MEMSTAT,SPI Status Control Register"
|
|
bitfld.long 0xC 20. "STATPOS,Indicates whether the BUSY bit position in Status Register of flash is 0 or 7. 1?b0 - 0th bit position (bit 0 is valid for busy status) 1?b1 - 7th bit position (bit7 is valid for busy status) The Controller continuously reads the Status register.." "0,1"
|
|
bitfld.long 0xC 18.--19. "TYPESTAT,Status Lane: Indicates the number of lanes (single/dual/quad) in which the Status command/ Read Status Register value is transmitted to /received from flash. 2?b00 - single lane 2?b01 - dual lane 2?b10 - quad lane" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0xC 16.--17. "STATBYTES,No. of bytes to send: 00 - Reserved 01 - 1 byte 10 - 2 bytes 11 - Reserved" "0,1,2,3"
|
|
hexmask.long.word 0xC 0.--15. 1. "STATCMD,Status Data: The first byte to be sent must be in LSB. For example if the user wants to send 0F first and 0C second then we should program 16?h0C0F."
|
|
line.long 0x10 "XCON3,SPI XIP Control 3 Register"
|
|
bitfld.long 0x10 28. "INIT1SCHECK,SPI Init1 Status Check: 0 - do not check status 1 - check status. If this bit is set to 1 the hardware will issue the status command automatically after the current operation and wait for busy bit to clear. The hardware will issue the next.." "0,1"
|
|
bitfld.long 0x10 26.--27. "INIT1COUNT,2bit SPI INIT1 Count. Indicates whether 1 2 or 3 bytes of INIT1 Code value are being sent." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x10 24.--25. "INIT1TYPE,SPI TYPE INIT1: 00 - Single lane mode 01 - Dual lane mode 10 - Quad lane mode 11 - Reserved for Future use. Based on this field the boot controller will send the INIT1 Code in 1/2/4 lane." "0,1,2,3"
|
|
hexmask.long.byte 0x10 16.--23. 1. "INIT1CMD3,8bit SPI Init1 Code3 value."
|
|
newline
|
|
hexmask.long.byte 0x10 8.--15. 1. "INIT1CMD2,8bit SPI Init1 Code2 value."
|
|
hexmask.long.byte 0x10 0.--7. 1. "INIT1CMD1,8bit SPI Init1 Code1 value."
|
|
line.long 0x14 "XCON4,SPI XIP Control4 Register"
|
|
bitfld.long 0x14 28. "INIT2SCHECK,SPI Init2 Status Check: 0 - do not check status 1 - check status If this bit is set to 1 the hardware will issue the status command automatically after thecurrent operation and wait for busy bit to clear. The hardware will issue the next.." "0,1"
|
|
bitfld.long 0x14 26.--27. "INIT2COUNT,2bit SPI INIT2 Count. Indicates whether 1 2 or 3 bytes of INIT2 Code value are being sent." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 24.--25. "INIT2TYPE,SPI TYPE INIT2: 00 - Single lane mode. 01 - Dual lane mode. 10 - Quad lane mode. 11 - Reserved for Future use. Based on this field the boot controller will send the INIT2 Code in 1/2/4 lane." "0,1,2,3"
|
|
hexmask.long.byte 0x14 16.--23. 1. "INIT2CMD3,8bit SPI Init2 Code3 value"
|
|
newline
|
|
hexmask.long.byte 0x14 8.--15. 1. "INIT2CMD2,8bit SPI Init2 Code2 value"
|
|
hexmask.long.byte 0x14 0.--7. 1. "INIT2CMD1,8bit SPI Init2 Code1 value."
|
|
tree.end
|
|
tree "SUPC (Supply Controller)"
|
|
base ad:0x44008000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x0 8. "ADDVREGRDY0,Additional Regulator ready 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 5. "BORVDDUSB,BORVDDUSB Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "BORVDDIOB,BORVDDIOB Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 3. "ULDOOVHEAT,User LDO Regulator OverHeat Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ULDORDY,User LDO Regulator Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x0 1. "LVDRDY,Low Voltage Detector Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LVDET,Low Voltage Detector Interrupt Enable" "0,1"
|
|
line.long 0x4 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x4 8. "ADDVREGRDY0,Additional Regulator ready 0 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 5. "BORVDDUSB,BORVDDUSB Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 4. "BORVDDIOB,BORVDDIOB Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 3. "ULDOOVHEAT,User LDO Regulator OverHeat Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 2. "ULDORDY,User LDO Regulator Ready Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 1. "LVDRDY,Low Voltage Detector Ready Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "LVDET,Low Voltage Detector Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0x8 8. "ADDVREGRDY0,Additional Regulator ready 0 Interrupt. Set to one if additionnal regulator is ready meaning that output voltage is correct." "0,1"
|
|
bitfld.long 0x8 5. "BORVDDUSB,BORVDDUSB Interrupt. Set to one if VDDUSB issue is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "BORVDDIOB,BORVDDIOB Interrupt. Set to one if VDDIOB issue is detected." "0,1"
|
|
bitfld.long 0x8 3. "ULDOOVHEAT,User LDO Regulator OverHeat Interrupt. Is set to one if overheat condition is detected." "0,1"
|
|
newline
|
|
bitfld.long 0x8 2. "ULDORDY,User LDO Regulator Ready Interrupt. Set to one if ULDO is ready meaning that output voltage is correct." "0,1"
|
|
bitfld.long 0x8 1. "LVDRDY,Low Voltage Detector Ready Interrupt. Set to one if LVD is ready to operate." "0,1"
|
|
newline
|
|
bitfld.long 0x8 0. "LVDET,Low Voltage Detector Interrupt. Set to one if VDDIO crosses the treshold voltage in the good direction according to LVD.DIR." "0,1"
|
|
rgroup.long 0xC++0x7
|
|
line.long 0x0 "STATUS,Flag status"
|
|
bitfld.long 0x0 8. "ADDVREGRDY0,Additional Regulator ready 0 Status. One if voltage is OK. It corresponds to vreg_ready_mv signal of additional regulator." "0,1"
|
|
bitfld.long 0x0 5. "BORVDDUSB,BORVDDUSB Status. One if VDDUSB is OK. It corresponds to bor_vddusb_n_mv signal of SMOR." "0,1"
|
|
newline
|
|
bitfld.long 0x0 4. "BORVDDIOB,BORVDDIOB Status. One if VDDIOB is OK. It corresponds to bor_vddiob_mv signal of SMOR." "0,1"
|
|
bitfld.long 0x0 3. "ULDOOVHEAT,User LDO Regulator OverHeat Status. It corresponds to vreg_overheat_event_mv signal from ULDO." "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "ULDORDY,User LDO regulator Status. It corresponds to vreg_ready_mv signal from ULDO." "0,1"
|
|
bitfld.long 0x0 1. "LVDRDY,Low Voltage Detector Ready Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "LVDET,Low Voltage Detector Status." "0,1"
|
|
line.long 0x4 "SYNCBUSY,Synchronisation Busy"
|
|
bitfld.long 0x4 0. "BOR,BOR Synchronization Busy" "0,1"
|
|
group.long 0x14++0x17
|
|
line.long 0x0 "BOR,BOR Control"
|
|
bitfld.long 0x0 8.--9. "BORFILT,BOR filtering" "0: No digital filtering,1: 32us filtering,2: 125us filtering,3: 250us filtering"
|
|
bitfld.long 0x0 4.--6. "DCBORPSEL,Duty Cycle BOR Prescaler Select" "0: Not Divided,1: Divide clock by 2,2: Divide clock by 4,3: Divide clock by 8,4: Divide clock by 16,5: Divide clock by 32,6: Divide clock by 64,7: Divide clock by 128"
|
|
newline
|
|
bitfld.long 0x0 0. "ACTION,Action when Threshold Crossed" "0: The BOR generates a reset,1: The BOR puts the device in battery backup sleep.."
|
|
line.long 0x4 "LVD,LVD Control"
|
|
hexmask.long.byte 0x4 16.--19. 1. "LEVEL,Threshold Level. See 'pwr_smor_[nn]_v1 DOS' - level section to get details."
|
|
bitfld.long 0x4 4. "RUNSTDBY,Run during Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "OEVEN,Output Event Enable" "0,1"
|
|
bitfld.long 0x4 2. "DIR,Direction" "0: Rising detection,1: Falling detection"
|
|
newline
|
|
bitfld.long 0x4 1. "ENABLE,Enable" "0,1"
|
|
line.long 0x8 "VREGCTRL,VREG Control"
|
|
bitfld.long 0x8 24. "AVREGSTDBY,Additional Voltage Regulator Configuration" "0: Regulator is OFF while in sleep mode equal or..,1: Regulator is ON in Standby mode if AVREGEN bit.."
|
|
bitfld.long 0x8 16. "AVREGEN,Additional Voltage Regulator Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 14.--15. "ULDOLEVEL,User LDO Voltage Level Selection" "0: Vout = 1.2v,1: Vout = 1.5v,2: Vout = 1.8v,3: Vout = 2.5v"
|
|
bitfld.long 0x8 13. "ULDOSTDBY,User LDO Voltage Regulator Configuration" "0: Regulator is OFF while in sleep mode equal or..,1: Regulator is ON in Standby mode. is OFF from.."
|
|
newline
|
|
bitfld.long 0x8 12. "ULDOEN,User LDO Voltage Regulator Enable" "0,1"
|
|
bitfld.long 0x8 8.--9. "CPEN,Charge Pump Enable and Auto-enable." "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 7. "SCAPEN,Super Capacitor Charging Enable" "0,1"
|
|
bitfld.long 0x8 5. "LVHIB,Low Voltage Hibernate Enable" "0: In Hibernate mode VDDCORE_BU and VDDCORE_RAM are..,1: In Hibernate mode VDDCORE_BU and VDDCORE_RAM are.."
|
|
newline
|
|
bitfld.long 0x8 4. "LVSTDBY,Low Voltage Standby Enable" "0: In standby mode VDDCORE_BU VDDCORE_RAM..,1: In standby mode VDDCORE_BU VDDCORE_RAM.."
|
|
bitfld.long 0x8 2. "OFFSTDBY,Off in Standby Control for VREGSW[N-1]. Useful for Riverside only." "0: In standby mode VREGSW1 2 3 are OFF,1: In standby mode VREGSW1 2 3 are ON"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "VREGOUT,VREG Output Control in RUN mode only. Enable by production fuse by CALSUPC.VREGOUTEN" "0: In Active mode VDDCORE_RAM VDDCORE_BU VDDCORE_SW..,1: In Active mode VDDCORE_RAM VDDCORE_BU VDDCORE_SW..,2: In Active mode VDDCORE_RAM VDDCORE_BU VDDCORE_SW..,?"
|
|
line.long 0xC "VREFCTRL,VREF Control"
|
|
bitfld.long 0xC 4. "TSEN,Temperature Sensor Output Enable" "0,1"
|
|
bitfld.long 0xC 1. "LPHIB,Bandgap and Regulators Low Power Hibernate Enable" "0: In hibernate mode bandgap is set to nominal..,1: In hibernate mode bandgap is set to low power.."
|
|
newline
|
|
bitfld.long 0xC 0. "LPSTDBY,Bandgap and Regulators Low Power Standby Enable" "0: In standby mode bandgap and enabled regulator(s)..,1: In standby mode bandgap and enabled regulator(s).."
|
|
line.long 0x10 "BBPS,Battery Backup Power Switch. This register is implemented only if SUPC_VBAT_IMPLEMENTED==1"
|
|
bitfld.long 0x10 5. "SELVBATMON,Select VBATMON supply voltage. 0 for VDDA and 1 for VDDBAT." "0,1"
|
|
bitfld.long 0x10 4. "ENVBATMON,Enables battery monitor" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "WAKEEN,Wake Enable" "0: When exiting battery backup mode the device goes..,1: When exiting battery backup mode the device is.."
|
|
bitfld.long 0x10 1. "WKONVBATEN,Wake on VBAT Enable from Backup mode" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "CONF,Battery Backup Power Switch Configuration" "0: The power switch is automatically handled by the..,1: In Backup mode the power-switch is forced to VBAT."
|
|
line.long 0x14 "BKOUT,Backup Output Control"
|
|
bitfld.long 0x14 26.--27. "TGLOM1,Toggle Output Mode" "0: The output does not toggle.,1: The output toggles on RTC event.,2: The output is set when the device enters backup..,?"
|
|
bitfld.long 0x14 24.--25. "TGLOM0,Toggle Output Mode" "0: The output does not toggle.,1: The output toggles on RTC event.,2: The output is set when the device enters backup..,?"
|
|
newline
|
|
bitfld.long 0x14 18. "SET1,Set Output" "0,1"
|
|
bitfld.long 0x14 16. "SET0,Set Output" "0,1"
|
|
newline
|
|
bitfld.long 0x14 10. "CLR1,Clear Output" "0,1"
|
|
bitfld.long 0x14 8. "CLR0,Clear Output" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "EN1,Enable Output" "0,1"
|
|
bitfld.long 0x14 0. "EN0,Enable Output" "0,1"
|
|
rgroup.long 0x2C++0x3
|
|
line.long 0x0 "BKIN,Backup Input Control"
|
|
bitfld.long 0x0 0.--1. "BKIN,Backup Input Value" "0,1,2,3"
|
|
tree.end
|
|
tree "SYSTICK (System Timer)"
|
|
base ad:0xE000E010
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,Count flag" "0,1"
|
|
bitfld.long 0x0 2. "CLKSOURCE,Clock source" "0,1"
|
|
bitfld.long 0x0 1. "TICKINT,Tick interrupt" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,SysTick enable" "0,1"
|
|
line.long 0x4 "RVR,SysTick Reload Value Register"
|
|
bitfld.long 0x4 24. "RELOAD,Counter reload value" "0,1"
|
|
line.long 0x8 "CVR,SysTick Current Value Register"
|
|
bitfld.long 0x8 24. "CURRENT,Current counter value" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x0 31. "NOREF,No reference" "0,1"
|
|
bitfld.long 0x0 30. "SKEW,Skew" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Ten milliseconds"
|
|
tree.end
|
|
sif (cpuis("PIC32CK0512SG00064*")||cpuis("PIC32CK0512SG00100*")||cpuis("PIC32CK0512SG01064*")||cpuis("PIC32CK0512SG01100*")||cpuis("PIC32CK1025SG00064*")||cpuis("PIC32CK1025SG00100*")||cpuis("PIC32CK1025SG01064*")||cpuis("PIC32CK1025SG01100*")||cpuis("PIC32CK2051SG00064*")||cpuis("PIC32CK2051SG00100*")||cpuis("PIC32CK2051SG00144*")||cpuis("PIC32CK2051SG01064*")||cpuis("PIC32CK2051SG01100*")||cpuis("PIC32CK2051SG01144*"))
|
|
tree "SYSTICK_NS (System Timer (Non-Secure))"
|
|
base ad:0xE002E010
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x0 16. "COUNTFLAG,Count flag" "0,1"
|
|
bitfld.long 0x0 2. "CLKSOURCE,Clock source" "0,1"
|
|
bitfld.long 0x0 1. "TICKINT,Tick interrupt" "0,1"
|
|
bitfld.long 0x0 0. "ENABLE,SysTick enable" "0,1"
|
|
line.long 0x4 "RVR,SysTick Reload Value Register"
|
|
bitfld.long 0x4 24. "RELOAD,Counter reload value" "0,1"
|
|
line.long 0x8 "CVR,SysTick Current Value Register"
|
|
bitfld.long 0x8 24. "CURRENT,Current counter value" "0,1"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x0 31. "NOREF,No reference" "0,1"
|
|
bitfld.long 0x0 30. "SKEW,Skew" "0,1"
|
|
hexmask.long.tbyte 0x0 0.--23. 1. "TENMS,Ten milliseconds"
|
|
tree.end
|
|
endif
|
|
tree "TCC (Timer/Counter Controller)"
|
|
base ad:0x0
|
|
tree "TCC0"
|
|
base ad:0x44818000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
|
|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC1"
|
|
base ad:0x4481A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
|
|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC2"
|
|
base ad:0x4481C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
|
|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC3"
|
|
base ad:0x4481E000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
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bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
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|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
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|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
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|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
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|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
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bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
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bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
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|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
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|
newline
|
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bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
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|
newline
|
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bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
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bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
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|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
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|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
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|
newline
|
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bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
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|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
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|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC4"
|
|
base ad:0x45008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
|
|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC5"
|
|
base ad:0x4500A000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
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|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
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|
newline
|
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bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
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|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
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newline
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bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
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bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
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newline
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bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
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line.byte 0x1 "CTRLBSET,Control B Set"
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|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
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|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
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newline
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bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
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bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
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newline
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bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
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rgroup.long 0x8++0x3
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line.long 0x0 "SYNCBUSY,Synchronization Busy"
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|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
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bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
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newline
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bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
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|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
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newline
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bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
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bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
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newline
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bitfld.long 0x0 7. "PER,Period Busy" "0,1"
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bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
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newline
|
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bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
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bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
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newline
|
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bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
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bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
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bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
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group.long 0xC++0xF
|
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line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
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hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
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hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
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newline
|
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bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
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bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
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newline
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bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
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bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
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|
newline
|
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bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
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bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
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newline
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bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
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bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
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newline
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bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
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line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
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hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
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hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
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newline
|
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bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
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bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
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newline
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bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
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bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
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newline
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bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
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bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
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newline
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bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
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|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
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newline
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bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
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line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
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hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
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newline
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bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
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|
newline
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bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
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hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
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|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
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newline
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bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
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bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
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newline
|
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bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
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bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
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newline
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bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
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bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
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newline
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bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
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bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
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newline
|
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bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
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bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
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newline
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bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
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bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
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newline
|
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bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
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bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
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newline
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bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
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bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
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newline
|
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bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
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bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
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newline
|
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bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
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bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
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|
newline
|
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bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
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bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
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newline
|
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bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
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bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
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group.byte 0x1E++0x0
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line.byte 0x0 "DBGCTRL,Debug Control"
|
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bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
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bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
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group.long 0x20++0x17
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line.long 0x0 "EVCTRL,Event Control"
|
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bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
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bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
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bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
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bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
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bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
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bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
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|
newline
|
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bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
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bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
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bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC6"
|
|
base ad:0x4500C000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
|
|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree "TCC7"
|
|
base ad:0x4500E000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTRLA,Control A"
|
|
bitfld.long 0x0 29. "CPTEN5,Capture Channel 5 Enable" "0,1"
|
|
bitfld.long 0x0 28. "CPTEN4,Capture Channel 4 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "CPTEN3,Capture Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 26. "CPTEN2,Capture Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "CPTEN1,Capture Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 24. "CPTEN0,Capture Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 23. "DMAOS,DMA One-shot Trigger Mode" "0,1"
|
|
bitfld.long 0x0 16. "FCYCLE,Full Cycle" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "MSYNC,Master Synchronization (only for TCC Slave Instance)" "0,1"
|
|
bitfld.long 0x0 14. "ALOCK,Auto Lock" "0,1"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "PRESCSYNC,Prescaler and Counter Synchronization Selection" "0: Reload or reset counter on next GCLK,1: Reload or reset counter on next prescaler clock,2: Reload or reset counter on next GCLK and reset..,?"
|
|
bitfld.long 0x0 11. "RUNSTDBY,Run in Standby" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8.--10. "PRESCALER,Prescaler" "0: No division,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 64,6: Divide by 256,7: Divide by 1024"
|
|
bitfld.long 0x0 5.--6. "RESOLUTION,Enhanced Resolution" "0: Dithering is disabled,1: Dithering is done every 16 PWM frames,2: Dithering is done every 32 PWM frames,3: Dithering is done every 64 PWM frames"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTRLBCLR,Control B Clear"
|
|
bitfld.byte 0x0 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x0 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x0 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x0 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "DIR,Counter Direction" "0,1"
|
|
line.byte 0x1 "CTRLBSET,Control B Set"
|
|
bitfld.byte 0x1 5.--7. "CMD,TCC Command" "0: No action,1: Clear start restart or retrigger,2: Force stop,3: Force update or double buffered registers,4: Force COUNT read synchronization,5: One-shot DMA trigger,?,?"
|
|
bitfld.byte 0x1 3.--4. "IDXCMD,Ramp Index Command" "0: Command disabled: Index toggles between cycles A..,1: Set index: cycle B will be forced in the next..,2: Clear index: cycle A will be forced in the next..,3: Hold index: the next cycle will be the same as.."
|
|
newline
|
|
bitfld.byte 0x1 2. "ONESHOT,One-Shot" "0,1"
|
|
bitfld.byte 0x1 1. "LUPD,Lock Update" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DIR,Counter Direction" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 13. "CC5,Compare Channel 5 Busy" "0,1"
|
|
bitfld.long 0x0 12. "CC4,Compare Channel 4 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CC3,Compare Channel 3 Busy" "0,1"
|
|
bitfld.long 0x0 10. "CC2,Compare Channel 2 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CC1,Compare Channel 1 Busy" "0,1"
|
|
bitfld.long 0x0 8. "CC0,Compare Channel 0 Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "PER,Period Busy" "0,1"
|
|
bitfld.long 0x0 6. "WAVE,Wave Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 5. "PATT,Pattern Busy" "0,1"
|
|
bitfld.long 0x0 4. "COUNT,Count Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 3. "STATUS,Status Busy" "0,1"
|
|
bitfld.long 0x0 2. "CTRLB,Ctrlb Busy" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Swrst Busy" "0,1"
|
|
group.long 0xC++0xF
|
|
line.long 0x0 "FCTRLA,Recoverable Fault A Configuration"
|
|
hexmask.long.byte 0x0 24.--27. 1. "FILTERVAL,Fault A Filter Value"
|
|
hexmask.long.byte 0x0 16.--23. 1. "BLANKVAL,Fault A Blanking Time"
|
|
newline
|
|
bitfld.long 0x0 15. "BLANKPRESC,Fault A Blanking Prescaler" "0,1"
|
|
bitfld.long 0x0 12.--14. "CAPTURE,Fault A Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "CHSEL,Fault A Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x0 8.--9. "HALT,Fault A Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x0 7. "RESTART,Fault A Restart" "0,1"
|
|
bitfld.long 0x0 5.--6. "BLANK,Fault A Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x0 4. "QUAL,Fault A Qualification" "0,1"
|
|
bitfld.long 0x0 3. "KEEP,Fault A Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0.--1. "SRC,Fault A Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x4 "FCTRLB,Recoverable Fault B Configuration"
|
|
hexmask.long.byte 0x4 24.--27. 1. "FILTERVAL,Fault B Filter Value"
|
|
hexmask.long.byte 0x4 16.--23. 1. "BLANKVAL,Fault B Blanking Time"
|
|
newline
|
|
bitfld.long 0x4 15. "BLANKPRESC,Fault B Blanking Prescaler" "0,1"
|
|
bitfld.long 0x4 12.--14. "CAPTURE,Fault B Capture Action" "0: No capture,1: Capture on fault,2: Minimum capture,3: Maximum capture,4: Minimum local detection,5: Maximum local detection,6: Minimum and maximum local detection,7: Capture with ramp index as MSB value"
|
|
newline
|
|
bitfld.long 0x4 10.--11. "CHSEL,Fault B Capture Channel" "0: Capture value stored in channel 0,1: Capture value stored in channel 1,2: Capture value stored in channel 2,3: Capture value stored in channel 3"
|
|
bitfld.long 0x4 8.--9. "HALT,Fault B Halt Mode" "0: Halt action disabled,1: Hardware halt action,2: Software halt action,3: Non-recoverable fault"
|
|
newline
|
|
bitfld.long 0x4 7. "RESTART,Fault B Restart" "0,1"
|
|
bitfld.long 0x4 5.--6. "BLANK,Fault B Blanking Mode" "0: Blanking applied from start of the ramp,1: Blanking applied from rising edge of the output..,2: Blanking applied from falling edge of the output..,3: Blanking applied from each toggle of the output.."
|
|
newline
|
|
bitfld.long 0x4 4. "QUAL,Fault B Qualification" "0,1"
|
|
bitfld.long 0x4 3. "KEEP,Fault B Keeper" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "SRC,Fault B Source" "0: Fault input disabled,1: MCEx (x=0 1) event input,2: Inverted MCEx (x=0 1) event input,3: Alternate fault (A or B) state at the end of the.."
|
|
line.long 0x8 "WEXCTRL,Waveform Extension Configuration"
|
|
hexmask.long.byte 0x8 24.--31. 1. "DTHS,Dead-time High Side Outputs Value"
|
|
hexmask.long.byte 0x8 16.--23. 1. "DTLS,Dead-time Low Side Outputs Value"
|
|
newline
|
|
bitfld.long 0x8 11. "DTIEN3,Dead-time Insertion Generator 3 Enable" "0,1"
|
|
bitfld.long 0x8 10. "DTIEN2,Dead-time Insertion Generator 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 9. "DTIEN1,Dead-time Insertion Generator 1 Enable" "0,1"
|
|
bitfld.long 0x8 8. "DTIEN0,Dead-time Insertion Generator 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 0.--1. "OTMX,Output Matrix" "0,1,2,3"
|
|
line.long 0xC "DRVCTRL,Driver Control"
|
|
hexmask.long.byte 0xC 28.--31. 1. "FILTERVAL1,Non-Recoverable Fault Input 1 Filter Value"
|
|
hexmask.long.byte 0xC 24.--27. 1. "FILTERVAL0,Non-Recoverable Fault Input 0 Filter Value"
|
|
newline
|
|
bitfld.long 0xC 23. "INVEN7,Output Waveform 7 Inversion" "0,1"
|
|
bitfld.long 0xC 22. "INVEN6,Output Waveform 6 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 21. "INVEN5,Output Waveform 5 Inversion" "0,1"
|
|
bitfld.long 0xC 20. "INVEN4,Output Waveform 4 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "INVEN3,Output Waveform 3 Inversion" "0,1"
|
|
bitfld.long 0xC 18. "INVEN2,Output Waveform 2 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "INVEN1,Output Waveform 1 Inversion" "0,1"
|
|
bitfld.long 0xC 16. "INVEN0,Output Waveform 0 Inversion" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "NRV7,Non-Recoverable State 7 Output Value" "0,1"
|
|
bitfld.long 0xC 14. "NRV6,Non-Recoverable State 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "NRV5,Non-Recoverable State 5 Output Value" "0,1"
|
|
bitfld.long 0xC 12. "NRV4,Non-Recoverable State 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "NRV3,Non-Recoverable State 3 Output Value" "0,1"
|
|
bitfld.long 0xC 10. "NRV2,Non-Recoverable State 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 9. "NRV1,Non-Recoverable State 1 Output Value" "0,1"
|
|
bitfld.long 0xC 8. "NRV0,Non-Recoverable State 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.long 0xC 7. "NRE7,Non-Recoverable State 7 Output Enable" "0,1"
|
|
bitfld.long 0xC 6. "NRE6,Non-Recoverable State 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 5. "NRE5,Non-Recoverable State 5 Output Enable" "0,1"
|
|
bitfld.long 0xC 4. "NRE4,Non-Recoverable State 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "NRE3,Non-Recoverable State 3 Output Enable" "0,1"
|
|
bitfld.long 0xC 2. "NRE2,Non-Recoverable State 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "NRE1,Non-Recoverable State 1 Output Enable" "0,1"
|
|
bitfld.long 0xC 0. "NRE0,Non-Recoverable State 0 Output Enable" "0,1"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "DBGCTRL,Debug Control"
|
|
bitfld.byte 0x0 2. "FDDBD,Fault Detection on Debug Break Detection" "0,1"
|
|
bitfld.byte 0x0 0. "DBGRUN,Debug Running Mode" "0,1"
|
|
group.long 0x20++0x17
|
|
line.long 0x0 "EVCTRL,Event Control"
|
|
bitfld.long 0x0 29. "MCEO5,Match or Capture Channel 5 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 28. "MCEO4,Match or Capture Channel 4 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 27. "MCEO3,Match or Capture Channel 3 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 26. "MCEO2,Match or Capture Channel 2 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "MCEO1,Match or Capture Channel 1 Event Output Enable" "0,1"
|
|
bitfld.long 0x0 24. "MCEO0,Match or Capture Channel 0 Event Output Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "MCEI5,Match or Capture Channel 5 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 20. "MCEI4,Match or Capture Channel 4 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "MCEI3,Match or Capture Channel 3 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 18. "MCEI2,Match or Capture Channel 2 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "MCEI1,Match or Capture Channel 1 Event Input Enable" "0,1"
|
|
bitfld.long 0x0 16. "MCEI0,Match or Capture Channel 0 Event Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 15. "TCEI1,Timer/counter Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 14. "TCEI0,Timer/counter Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 13. "TCINV1,Inverted Event 1 Input Enable" "0,1"
|
|
bitfld.long 0x0 12. "TCINV0,Inverted Event 0 Input Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 10. "CNTEO,Timer/counter Output Event Enable" "0,1"
|
|
bitfld.long 0x0 9. "TRGEO,Retrigger Output Event Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "OVFEO,Overflow/Underflow Output Event Enable" "0,1"
|
|
bitfld.long 0x0 6.--7. "CNTSEL,Timer/counter Output Event Mode" "0: An interrupt/event is generated when a new..,1: An interrupt/event is generated when a counter..,?,3: An interrupt/event is generated when a new.."
|
|
newline
|
|
bitfld.long 0x0 3.--5. "EVACT1,Timer/counter Input Event1 Action" "0: Event action disabled,1: Re-trigger counter on event,2: Direction control,3: Stop counter on event,4: Decrement counter on event,?,6: Period capture value in CC1 register pulse width..,7: Non-recoverable fault"
|
|
bitfld.long 0x0 0.--2. "EVACT0,Timer/counter Input Event0 Action" "0: Event action disabled,1: Start restart or re-trigger counter on event,2: Count on event,3: Start counter on event,4: Increment counter on event,5: Count on active state of asynchronous event,6: Stamp capture,7: Non-recoverable fault"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 21. "MC5,Match or Capture Channel 5 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 20. "MC4,Match or Capture Channel 4 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 19. "MC3,Match or Capture Channel 3 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 18. "MC2,Match or Capture Channel 2 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 17. "MC1,Match or Capture Channel 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 16. "MC0,Match or Capture Channel 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 15. "FAULT1,Non-Recoverable Fault 1 Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 14. "FAULT0,Non-Recoverable Fault 0 Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 13. "FAULTB,Recoverable Fault B Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 12. "FAULTA,Recoverable Fault A Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 11. "DFS,Non-Recoverable Debug Fault Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 10. "UFS,Non-Recoverable Update Fault Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 3. "ERR,Error Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 2. "CNT,Counter Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x8 1. "TRG,Retrigger Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "OVF,Overflow Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 21. "MC5,Match or Capture 5" "0,1"
|
|
bitfld.long 0xC 20. "MC4,Match or Capture 4" "0,1"
|
|
newline
|
|
bitfld.long 0xC 19. "MC3,Match or Capture 3" "0,1"
|
|
bitfld.long 0xC 18. "MC2,Match or Capture 2" "0,1"
|
|
newline
|
|
bitfld.long 0xC 17. "MC1,Match or Capture 1" "0,1"
|
|
bitfld.long 0xC 16. "MC0,Match or Capture 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 15. "FAULT1,Non-Recoverable Fault 1" "0,1"
|
|
bitfld.long 0xC 14. "FAULT0,Non-Recoverable Fault 0" "0,1"
|
|
newline
|
|
bitfld.long 0xC 13. "FAULTB,Recoverable Fault B" "0,1"
|
|
bitfld.long 0xC 12. "FAULTA,Recoverable Fault A" "0,1"
|
|
newline
|
|
bitfld.long 0xC 11. "DFS,Non-Recoverable Debug Fault" "0,1"
|
|
bitfld.long 0xC 10. "UFS,Non-Recoverable Update Fault" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "ERR,Error" "0,1"
|
|
bitfld.long 0xC 2. "CNT,Counter" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "TRG,Retrigger" "0,1"
|
|
bitfld.long 0xC 0. "OVF,Overflow" "0,1"
|
|
line.long 0x10 "STATUS,Status"
|
|
bitfld.long 0x10 29. "CMP5,Compare Channel 5 Value" "0,1"
|
|
bitfld.long 0x10 28. "CMP4,Compare Channel 4 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 27. "CMP3,Compare Channel 3 Value" "0,1"
|
|
bitfld.long 0x10 26. "CMP2,Compare Channel 2 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 25. "CMP1,Compare Channel 1 Value" "0,1"
|
|
bitfld.long 0x10 24. "CMP0,Compare Channel 0 Value" "0,1"
|
|
newline
|
|
bitfld.long 0x10 21. "CCBUFV5,Compare Channel 5 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 20. "CCBUFV4,Compare Channel 4 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 19. "CCBUFV3,Compare Channel 3 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 18. "CCBUFV2,Compare Channel 2 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 17. "CCBUFV1,Compare Channel 1 Buffer Valid" "0,1"
|
|
bitfld.long 0x10 16. "CCBUFV0,Compare Channel 0 Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 15. "FAULT1,Non-Recoverable Fault 1 State" "0,1"
|
|
bitfld.long 0x10 14. "FAULT0,Non-Recoverable Fault 0 State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 13. "FAULTB,Recoverable Fault B State" "0,1"
|
|
bitfld.long 0x10 12. "FAULTA,Recoverable Fault A State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 11. "FAULT1IN,Non-Recoverable Fault1 Input" "0,1"
|
|
bitfld.long 0x10 10. "FAULT0IN,Non-Recoverable Fault0 Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 9. "FAULTBIN,Recoverable Fault B Input" "0,1"
|
|
bitfld.long 0x10 8. "FAULTAIN,Recoverable Fault A Input" "0,1"
|
|
newline
|
|
bitfld.long 0x10 7. "PERBUFV,Period Buffer Valid" "0,1"
|
|
bitfld.long 0x10 5. "PATTBUFV,Pattern Buffer Valid" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "SLAVE,Slave" "0,1"
|
|
bitfld.long 0x10 3. "DFS,Non-Recoverable Debug Fault State" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "UFS,Non-recoverable Update Fault State" "0,1"
|
|
bitfld.long 0x10 1. "IDX,Ramp" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "STOP,Stop" "0,1"
|
|
line.long 0x14 "COUNT,Count"
|
|
hexmask.long 0x14 0.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH4_MODE,Count"
|
|
hexmask.long 0x0 4.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH5_MODE,Count"
|
|
hexmask.long 0x0 5.--31. 1. "COUNT,Counter Value"
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "COUNT_DITH6_MODE,Count"
|
|
hexmask.long 0x0 6.--31. 1. "COUNT,Counter Value"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "PATT,Pattern"
|
|
bitfld.word 0x0 15. "PGV7,Pattern Generator 7 Output Value" "0,1"
|
|
bitfld.word 0x0 14. "PGV6,Pattern Generator 6 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGV5,Pattern Generator 5 Output Value" "0,1"
|
|
bitfld.word 0x0 12. "PGV4,Pattern Generator 4 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGV3,Pattern Generator 3 Output Value" "0,1"
|
|
bitfld.word 0x0 10. "PGV2,Pattern Generator 2 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGV1,Pattern Generator 1 Output Value" "0,1"
|
|
bitfld.word 0x0 8. "PGV0,Pattern Generator 0 Output Value" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGE7,Pattern Generator 7 Output Enable" "0,1"
|
|
bitfld.word 0x0 6. "PGE6,Pattern Generator 6 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGE5,Pattern Generator 5 Output Enable" "0,1"
|
|
bitfld.word 0x0 4. "PGE4,Pattern Generator 4 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGE3,Pattern Generator 3 Output Enable" "0,1"
|
|
bitfld.word 0x0 2. "PGE2,Pattern Generator 2 Output Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGE1,Pattern Generator 1 Output Enable" "0,1"
|
|
bitfld.word 0x0 0. "PGE0,Pattern Generator 0 Output Enable" "0,1"
|
|
group.long 0x3C++0x7
|
|
line.long 0x0 "WAVE,Waveform Control"
|
|
bitfld.long 0x0 27. "SWAP3,Swap DTI Output Pair 3" "0,1"
|
|
bitfld.long 0x0 26. "SWAP2,Swap DTI Output Pair 2" "0,1"
|
|
newline
|
|
bitfld.long 0x0 25. "SWAP1,Swap DTI Output Pair 1" "0,1"
|
|
bitfld.long 0x0 24. "SWAP0,Swap DTI Output Pair 0" "0,1"
|
|
newline
|
|
bitfld.long 0x0 21. "POL5,Channel 5 Polarity" "0,1"
|
|
bitfld.long 0x0 20. "POL4,Channel 4 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 19. "POL3,Channel 3 Polarity" "0,1"
|
|
bitfld.long 0x0 18. "POL2,Channel 2 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 17. "POL1,Channel 1 Polarity" "0,1"
|
|
bitfld.long 0x0 16. "POL0,Channel 0 Polarity" "0,1"
|
|
newline
|
|
bitfld.long 0x0 11. "CICCEN3,Circular Channel 3 Enable" "0,1"
|
|
bitfld.long 0x0 10. "CICCEN2,Circular Channel 2 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "CICCEN1,Circular Channel 1 Enable" "0,1"
|
|
bitfld.long 0x0 8. "CICCEN0,Circular Channel 0 Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 7. "CIPEREN,Circular period Enable" "0,1"
|
|
bitfld.long 0x0 4.--5. "RAMP,Ramp Mode" "0: RAMP1 operation,1: Alternative RAMP2 operation,2: RAMP2 operation,3: Critical RAMP2 operation"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "WAVEGEN,Waveform Generation" "0: Normal frequency,1: Match frequency,2: Normal PWM,3: Dual compare PWM,4: Dual-slope critical,5: Dual-slope with interrupt/event condition when..,6: Dual-slope with interrupt/event condition when..,7: Dual-slope with interrupt/event condition when.."
|
|
line.long 0x4 "PER,Period"
|
|
hexmask.long 0x4 0.--31. 1. "PER,Period Value"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH4_MODE,Period"
|
|
hexmask.long 0x0 4.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH5_MODE,Period"
|
|
hexmask.long 0x0 5.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PER_DITH6_MODE,Period"
|
|
hexmask.long 0x0 6.--31. 1. "PER,Period Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC[$1],Compare and Capture"
|
|
hexmask.long 0x0 0.--31. 1. "CC,Channel Compare/Capture Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH4_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 4.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH5_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 5.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x44)++0x3
|
|
line.long 0x0 "CC_DITH6_MODE[$1],Compare and Capture"
|
|
hexmask.long 0x0 6.--31. 1. "CC,Channel Compare/Capture Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHER,Dithering Cycle Number"
|
|
repeat.end
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "PATTBUF,Pattern Buffer"
|
|
bitfld.word 0x0 15. "PGVB7,Pattern Generation 7 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 14. "PGVB6,Pattern Generation 6 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 13. "PGVB5,Pattern Generation 5 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 12. "PGVB4,Pattern Generation 4 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 11. "PGVB3,Pattern Generation 3 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 10. "PGVB2,Pattern Generation 2 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 9. "PGVB1,Pattern Generation 1 Output Value Buffer" "0,1"
|
|
bitfld.word 0x0 8. "PGVB0,Pattern Generation 0 Output Value Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "PGEB7,Pattern Generation 7 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 6. "PGEB6,Pattern Generation 6 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "PGEB5,Pattern Generation 5 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 4. "PGEB4,Pattern Generation 4 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "PGEB3,Pattern Generation 3 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 2. "PGEB2,Pattern Generation 2 Output Enable Buffer" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "PGEB1,Pattern Generation 1 Output Enable Buffer" "0,1"
|
|
bitfld.word 0x0 0. "PGEB0,Pattern Generation 0 Output Enable Buffer" "0,1"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF,Period Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "PERBUF,Period Buffer Value"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH4_MODE,Period Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH5_MODE,Period Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PERBUF_DITH6_MODE,Period Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "PERBUF,Period Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 0.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH4_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 4.--31. 1. "CCBUF,Dithering Buffer Cycle Number"
|
|
hexmask.long.byte 0x0 0.--3. 1. "DITHERBUF,Channel Compare/Capture Buffer Value"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH5_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 5.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--4. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x70)++0x3
|
|
line.long 0x0 "CCBUF_DITH6_MODE[$1],Compare and Capture Buffer"
|
|
hexmask.long 0x0 6.--31. 1. "CCBUF,Channel Compare/Capture Buffer Value"
|
|
hexmask.long.byte 0x0 0.--5. 1. "DITHERBUF,Dithering Buffer Cycle Number"
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "TPIU (Trace Port Interface Unit)"
|
|
base ad:0xE0040000
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "SSPSR,TPIU Supported Parallel Port Sizes Register"
|
|
hexmask.long 0x0 0.--31. 1. "SWIDTH,Supported widths - 1"
|
|
line.long 0x4 "CSPSR,TPIU Current Parallel Port Sizes Register"
|
|
hexmask.long 0x4 0.--31. 1. "CWIDTH,Current parallel trace port widthi - 1"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "ACPR,TPIU Asynchronous Clock Prescaler Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "SWOSCALER,SWO baud rate prescaler"
|
|
group.long 0xF0++0x3
|
|
line.long 0x0 "SPPR,TPIU Selected Pin Protocol Register"
|
|
bitfld.long 0x0 0.--1. "TXMODE," "0: Parallel trace port mode,1: Asynchronous SWO using Manchester encoding,2: Asynchronous SWO using NRZ encoding,?"
|
|
rgroup.long 0x300++0x3
|
|
line.long 0x0 "FFSR,TPIU Formatter and Flush Status Register"
|
|
bitfld.long 0x0 3. "FtNonStop,Non-stop formatter" "0,1"
|
|
bitfld.long 0x0 2. "TCPresent,TRACECTL pin is present" "0,1"
|
|
bitfld.long 0x0 1. "FtStopped,Formatter stopped" "0,1"
|
|
bitfld.long 0x0 0. "FInProg,Flush in progress" "0,1"
|
|
group.long 0x304++0x7
|
|
line.long 0x0 "FFCR,TPIU Formatter and Flush Control Register"
|
|
bitfld.long 0x0 8. "TrigIn,Trigger input asserted" "0,1"
|
|
bitfld.long 0x0 6. "FOnMan,Flush On Manual" "0,1"
|
|
bitfld.long 0x0 0.--1. "EnFmt,Output formatting mode" "0: Disable formatting,?,2: Continuous formatting and embed triggers and..,?"
|
|
line.long 0x4 "PSCR,TPIU Periodic Synchronization Control Register"
|
|
hexmask.long.byte 0x4 0.--4. 1. "PSCount,Periodic Synchronization Count"
|
|
wgroup.long 0xFB0++0x3
|
|
line.long 0x0 "LAR,TPIU Software Lock Access Register"
|
|
hexmask.long 0x0 0.--31. 1. "KEY,Lock access control"
|
|
rgroup.long 0xFB4++0x3
|
|
line.long 0x0 "LSR,TPIU Software Lock Status Register"
|
|
bitfld.long 0x0 2. "nTT,Not thirty-two bit" "0,1"
|
|
bitfld.long 0x0 1. "SLK,Software Lock status" "0,1"
|
|
bitfld.long 0x0 0. "SLI,Software Lock implemented" "0,1"
|
|
rgroup.long 0xFC8++0x37
|
|
line.long 0x0 "DEVID,TPIU Device Identifier Register"
|
|
bitfld.long 0x0 24. "DWTENA," "0,1"
|
|
line.long 0x4 "DEVTYPE,TPIU Device Type Register"
|
|
hexmask.long.byte 0x4 4.--7. 1. "SUB,Sub-type"
|
|
hexmask.long.byte 0x4 0.--3. 1. "MAJOR,Major type"
|
|
line.long 0x8 "PIDR4,TPIU Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x8 4.--7. 1. "SIZE,4KB count"
|
|
hexmask.long.byte 0x8 0.--3. 1. "DES_2,JEP106 continuation code"
|
|
line.long 0xC "PIDR5,TPIU Peripheral Identification Register 5"
|
|
line.long 0x10 "PIDR6,TPIU Peripheral Identification Register 6"
|
|
line.long 0x14 "PIDR7,TPIU Peripheral Identification Register 7"
|
|
line.long 0x18 "PIDR0,TPIU Peripheral Identification Register 0"
|
|
hexmask.long.byte 0x18 0.--7. 1. "PART_0,Part number bits[7:0]"
|
|
line.long 0x1C "PIDR1,TPIU Peripheral Identification Register 1"
|
|
hexmask.long.byte 0x1C 4.--7. 1. "DES_0,JEP106 identification code bits [3:0]"
|
|
hexmask.long.byte 0x1C 0.--3. 1. "PART_1,Part number bits[11:8]"
|
|
line.long 0x20 "PIDR2,TPIU Peripheral Identification Register 2"
|
|
hexmask.long.byte 0x20 4.--7. 1. "REVISION,Component revision"
|
|
bitfld.long 0x20 3. "JEDEC,JEDEC assignee value is used" "0,1"
|
|
bitfld.long 0x20 0.--2. "DES_1,JEP106 identification code bits[6:4]" "0,1,2,3,4,5,6,7"
|
|
line.long 0x24 "PIDR3,TPIU Peripheral Identification Register 3"
|
|
hexmask.long.byte 0x24 4.--7. 1. "REVAND,RevAnd"
|
|
hexmask.long.byte 0x24 0.--3. 1. "CMOD,Customer Modified"
|
|
line.long 0x28 "CIDR0,TPIU Component Identification Register 0"
|
|
hexmask.long.byte 0x28 0.--7. 1. "PRMBL_0,CoreSight component identification preamble"
|
|
line.long 0x2C "CIDR1,TPIU Component Identification Register 1"
|
|
hexmask.long.byte 0x2C 4.--7. 1. "CLASS,CoreSight component class"
|
|
hexmask.long.byte 0x2C 0.--3. 1. "PRMBL_1,CoreSight component identification preamble"
|
|
line.long 0x30 "CIDR2,TPIU Component Identification Register 2"
|
|
hexmask.long.byte 0x30 0.--7. 1. "PRMBL_2,CoreSight component identification preamble"
|
|
line.long 0x34 "CIDR3,TPIU Component Identification Register 3"
|
|
hexmask.long.byte 0x34 0.--7. 1. "PRMBL_3,CoreSight component identification preamble"
|
|
tree.end
|
|
tree "TRAM (TrustRAM)"
|
|
base ad:0x4401E000
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "CTRLA,Control"
|
|
bitfld.long 0x0 7. "SILACC,Silent Access" "0,1"
|
|
bitfld.long 0x0 6. "DRP,Data Remanence Prevention" "0,1"
|
|
bitfld.long 0x0 4. "TAMPERS,Tamper Erase" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.long 0x0 0. "SWRST,Software Reset" "0,1"
|
|
line.long 0x4 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.long 0x4 1. "DRP,Data Remanence Prevention Ended Interrupt Enable" "0,1"
|
|
bitfld.long 0x4 0. "ERR,TrustRAM Readout Error Interrupt Enable" "0,1"
|
|
line.long 0x8 "INTENSET,Interrupt Enable Set"
|
|
bitfld.long 0x8 1. "DRP,Data Remanence Prevention Ended Interrupt Enable" "0,1"
|
|
bitfld.long 0x8 0. "ERR,TrustRAM Readout Error Interrupt Enable" "0,1"
|
|
line.long 0xC "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.long 0xC 1. "DRP,Data Remanence Prevention Ended" "0,1"
|
|
bitfld.long 0xC 0. "ERR,TrustRAM Readout Error" "0,1"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x0 "STATUS,Status"
|
|
bitfld.long 0x0 1. "DRP,Data Remanence Prevention Ongoing" "0,1"
|
|
bitfld.long 0x0 0. "RAMINV,RAM Inversion Bit" "0,1"
|
|
line.long 0x4 "SYNCBUSY,Synchronization Busy Status"
|
|
bitfld.long 0x4 1. "ENABLE,Enable Busy" "0,1"
|
|
bitfld.long 0x4 0. "SWRST,Software Reset Busy" "0,1"
|
|
wgroup.long 0x18++0x7
|
|
line.long 0x0 "DSCC,Data Scramble Control"
|
|
bitfld.long 0x0 31. "DSCEN,Data Scramble Enable" "0,1"
|
|
hexmask.long 0x0 0.--29. 1. "DSCKEY,Data Scramble Key"
|
|
line.long 0x4 "PERMW,Permutation Write"
|
|
bitfld.long 0x4 0.--2. "DATA,Permutation Scrambler Data Input" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "PERMR,Permutation Read"
|
|
bitfld.long 0x0 0.--2. "DATA,Permutation Scrambler Data Output" "0,1,2,3,4,5,6,7"
|
|
repeat 2048. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1000)++0x3
|
|
line.long 0x0 "RAM[$1],TrustRAM"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Trust RAM Data"
|
|
repeat.end
|
|
tree.end
|
|
tree "TRNG (True Random Number Generator)"
|
|
base ad:0x45024000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "CTRLA,Control A"
|
|
bitfld.byte 0x0 6. "RUNSTDBY,Run in Standby" "0,1"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "EVCTRL,Event Control"
|
|
bitfld.byte 0x0 0. "DATARDYEO,Data Ready Event Output" "0,1"
|
|
group.byte 0x8++0x2
|
|
line.byte 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.byte 0x0 0. "DATARDY,Data Ready Interrupt Enable" "0,1"
|
|
line.byte 0x1 "INTENSET,Interrupt Enable Set"
|
|
bitfld.byte 0x1 0. "DATARDY,Data Ready Interrupt Enable" "0,1"
|
|
line.byte 0x2 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x2 0. "DATARDY,Data Ready Interrupt Flag" "0,1"
|
|
rgroup.long 0x20++0x3
|
|
line.long 0x0 "DATA,Output Data"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Output Data"
|
|
tree.end
|
|
tree "USB (Full-Speed Universal Serial Bus)"
|
|
base ad:0x4502A000
|
|
tree "DEVICE (USB is Device)"
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "CTRLA,Control A"
|
|
bitfld.byte 0x0 7. "MODE,Operating Mode" "0: Device Mode,1: Host Mode"
|
|
bitfld.byte 0x0 2. "RUNSTDBY,Run in Standby Mode" "0,1"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
rgroup.byte 0x2++0x0
|
|
line.byte 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable Synchronization Busy" "0,1"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.byte 0x3++0x0
|
|
line.byte 0x0 "QOSCTRL,USB Quality Of Service"
|
|
bitfld.byte 0x0 2.--3. "DQOS,Data Quality of Service" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CQOS,Configuration Quality of Service" "0,1,2,3"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "CTRLB,DEVICE Control B"
|
|
bitfld.word 0x0 10.--11. "LPMHDSK,Link Power Management Handshake" "0: No handshake. LPM is not supported,1: ACK,2: NYET,3: STALL"
|
|
bitfld.word 0x0 9. "GNAK,Global NAK" "0,1"
|
|
bitfld.word 0x0 8. "OPMODE2,Specific Operational Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 7. "TSTPCKT,Test packet mode" "0,1"
|
|
bitfld.word 0x0 6. "TSTK,Test mode K" "0,1"
|
|
bitfld.word 0x0 5. "TSTJ,Test mode J" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "NREPLY,No Reply" "0,1"
|
|
bitfld.word 0x0 2.--3. "SPDCONF,Speed Configuration" "0: FS : Full Speed,1: LS : Low Speed,2: HS : High Speed capable,3: HSTM: High Speed Test Mode (force high-speed.."
|
|
bitfld.word 0x0 1. "UPRSM,Upstream Resume" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "DETACH,Detach" "0,1"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "DADD,DEVICE Device Address"
|
|
bitfld.byte 0x0 7. "ADDEN,Device Address Enable" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "DADD,Device Address"
|
|
rgroup.byte 0xC++0x1
|
|
line.byte 0x0 "STATUS,DEVICE Status"
|
|
bitfld.byte 0x0 6.--7. "LINESTATE,USB Line State Status" "0: SE0/RESET,1: FS-J or LS-K State,2: FS-K or LS-J State,?"
|
|
bitfld.byte 0x0 2.--3. "SPEED,Speed Status" "0: Full-speed mode,1: Low-speed mode,2: High-speed mode,?"
|
|
line.byte 0x1 "FSMSTATUS,Finite State Machine Status"
|
|
hexmask.byte 0x1 0.--6. 1. "FSMSTATE,Fine State Machine Status"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "FNUM,DEVICE Device Frame Number"
|
|
bitfld.word 0x0 15. "FNCERR,Frame Number CRC Error" "0,1"
|
|
hexmask.word 0x0 3.--13. 1. "FNUM,Frame Number"
|
|
bitfld.word 0x0 0.--2. "MFNUM,Micro Frame Number" "0,1,2,3,4,5,6,7"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "INTENCLR,DEVICE Device Interrupt Enable Clear"
|
|
bitfld.word 0x0 9. "LPMSUSP,Link Power Management Suspend Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 8. "LPMNYET,Link Power Management Not Yet Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 7. "RAMACER,Ram Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "UPRSM,Upstream Resume Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 5. "EORSM,End Of Resume Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 4. "WAKEUP,Wake Up Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EORST,End of Reset Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "SOF,Start Of Frame Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 1. "MSOF,Micro Start of Frame Interrupt Enable in High Speed Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SUSPEND,Suspend Interrupt Enable" "0,1"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "INTENSET,DEVICE Device Interrupt Enable Set"
|
|
bitfld.word 0x0 9. "LPMSUSP,Link Power Management Suspend Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 8. "LPMNYET,Link Power Management Not Yet Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 7. "RAMACER,Ram Access Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "UPRSM,Upstream Resume Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 5. "EORSM,End Of Resume Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 4. "WAKEUP,Wake Up Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EORST,End of Reset Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "SOF,Start Of Frame Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 1. "MSOF,Micro Start of Frame Interrupt Enable in High Speed Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SUSPEND,Suspend Interrupt Enable" "0,1"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "INTFLAG,DEVICE Device Interrupt Flag"
|
|
bitfld.word 0x0 9. "LPMSUSP,Link Power Management Suspend" "0,1"
|
|
bitfld.word 0x0 8. "LPMNYET,Link Power Management Not Yet" "0,1"
|
|
bitfld.word 0x0 7. "RAMACER,Ram Access" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "UPRSM,Upstream Resume" "0,1"
|
|
bitfld.word 0x0 5. "EORSM,End Of Resume" "0,1"
|
|
bitfld.word 0x0 4. "WAKEUP,Wake Up" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EORST,End of Reset" "0,1"
|
|
bitfld.word 0x0 2. "SOF,Start Of Frame" "0,1"
|
|
bitfld.word 0x0 1. "MSOF,Micro Start of Frame in High Speed Mode" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "SUSPEND,Suspend" "0,1"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "EPINTSMRY,DEVICE End Point Interrupt Summary"
|
|
bitfld.word 0x0 7. "EPINT7,End Point 7 Interrupt" "0,1"
|
|
bitfld.word 0x0 6. "EPINT6,End Point 6 Interrupt" "0,1"
|
|
bitfld.word 0x0 5. "EPINT5,End Point 5 Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "EPINT4,End Point 4 Interrupt" "0,1"
|
|
bitfld.word 0x0 3. "EPINT3,End Point 3 Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "EPINT2,End Point 2 Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "EPINT1,End Point 1 Interrupt" "0,1"
|
|
bitfld.word 0x0 0. "EPINT0,End Point 0 Interrupt" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DESCADD,Descriptor Address"
|
|
hexmask.long 0x0 0.--31. 1. "DESCADD,Descriptor Address Value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "PADCAL,USB PAD Calibration"
|
|
bitfld.word 0x0 12.--14. "TRIM,USB Pad Trim calibration" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 6.--10. 1. "TRANSN,USB Pad Transn calibration"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TRANSP,USB Pad Transp calibration"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4502A100 ad:0x4502A120 ad:0x4502A140 ad:0x4502A160 ad:0x4502A180 ad:0x4502A1A0 ad:0x4502A1C0 ad:0x4502A1E0)
|
|
tree "DEVICE_ENDPOINT[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "EPCFG,DEVICE_ENDPOINT End Point Configuration"
|
|
bitfld.byte 0x0 7. "NYETDIS,NYET Token Disable" "0,1"
|
|
bitfld.byte 0x0 4.--6. "EPTYPE1,End Point Type1" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 0.--2. "EPTYPE0,End Point Type0" "0,1,2,3,4,5,6,7"
|
|
wgroup.byte ($2+0x4)++0x1
|
|
line.byte 0x0 "EPSTATUSCLR,DEVICE_ENDPOINT End Point Pipe Status Clear"
|
|
bitfld.byte 0x0 7. "BK1RDY,Bank 1 Ready Clear" "0,1"
|
|
bitfld.byte 0x0 6. "BK0RDY,Bank 0 Ready Clear" "0,1"
|
|
bitfld.byte 0x0 5. "STALLRQ1,Stall 1 Request Clear" "0,1"
|
|
bitfld.byte 0x0 4. "STALLRQ0,Stall 0 Request Clear" "0,1"
|
|
bitfld.byte 0x0 2. "CURBK,Current Bank Clear" "0,1"
|
|
bitfld.byte 0x0 1. "DTGLIN,Data Toggle IN Clear" "0,1"
|
|
bitfld.byte 0x0 0. "DTGLOUT,Data Toggle OUT Clear" "0,1"
|
|
line.byte 0x1 "EPSTATUSSET,DEVICE_ENDPOINT End Point Pipe Status Set"
|
|
bitfld.byte 0x1 7. "BK1RDY,Bank 1 Ready Set" "0,1"
|
|
bitfld.byte 0x1 6. "BK0RDY,Bank 0 Ready Set" "0,1"
|
|
bitfld.byte 0x1 5. "STALLRQ1,Stall 1 Request Set" "0,1"
|
|
bitfld.byte 0x1 4. "STALLRQ0,Stall 0 Request Set" "0,1"
|
|
bitfld.byte 0x1 2. "CURBK,Current Bank Set" "0,1"
|
|
bitfld.byte 0x1 1. "DTGLIN,Data Toggle IN Set" "0,1"
|
|
bitfld.byte 0x1 0. "DTGLOUT,Data Toggle OUT Set" "0,1"
|
|
rgroup.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "EPSTATUS,DEVICE_ENDPOINT End Point Pipe Status"
|
|
bitfld.byte 0x0 7. "BK1RDY,Bank 1 ready" "0,1"
|
|
bitfld.byte 0x0 6. "BK0RDY,Bank 0 ready" "0,1"
|
|
bitfld.byte 0x0 5. "STALLRQ1,Stall 1 Request" "0,1"
|
|
bitfld.byte 0x0 4. "STALLRQ0,Stall 0 Request" "0,1"
|
|
bitfld.byte 0x0 2. "CURBK,Current Bank" "0,1"
|
|
bitfld.byte 0x0 1. "DTGLIN,Data Toggle In" "0,1"
|
|
bitfld.byte 0x0 0. "DTGLOUT,Data Toggle Out" "0,1"
|
|
group.byte ($2+0x7)++0x2
|
|
line.byte 0x0 "EPINTFLAG,DEVICE_ENDPOINT End Point Interrupt Flag"
|
|
bitfld.byte 0x0 6. "STALL1,Stall 1 In/out" "0,1"
|
|
bitfld.byte 0x0 5. "STALL0,Stall 0 In/out" "0,1"
|
|
bitfld.byte 0x0 4. "RXSTP,Received Setup" "0,1"
|
|
bitfld.byte 0x0 3. "TRFAIL1,Error Flow 1" "0,1"
|
|
bitfld.byte 0x0 2. "TRFAIL0,Error Flow 0" "0,1"
|
|
bitfld.byte 0x0 1. "TRCPT1,Transfer Complete 1" "0,1"
|
|
bitfld.byte 0x0 0. "TRCPT0,Transfer Complete 0" "0,1"
|
|
line.byte 0x1 "EPINTENCLR,DEVICE_ENDPOINT End Point Interrupt Clear Flag"
|
|
bitfld.byte 0x1 6. "STALL1,Stall 1 In/Out Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 5. "STALL0,Stall 0 In/Out Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 4. "RXSTP,Received Setup Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 3. "TRFAIL1,Error Flow 1 Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 2. "TRFAIL0,Error Flow 0 Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 1. "TRCPT1,Transfer Complete 1 Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 0. "TRCPT0,Transfer Complete 0 Interrupt Disable" "0,1"
|
|
line.byte 0x2 "EPINTENSET,DEVICE_ENDPOINT End Point Interrupt Set Flag"
|
|
bitfld.byte 0x2 6. "STALL1,Stall 1 In/out Interrupt enable" "0,1"
|
|
bitfld.byte 0x2 5. "STALL0,Stall 0 In/out Interrupt enable" "0,1"
|
|
bitfld.byte 0x2 4. "RXSTP,Received Setup Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 3. "TRFAIL1,Error Flow 1 Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 2. "TRFAIL0,Error Flow 0 Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 1. "TRCPT1,Transfer Complete 1 Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 0. "TRCPT0,Transfer Complete 0 Interrupt Enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "HOST (USB is Host)"
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "CTRLA,Control A"
|
|
bitfld.byte 0x0 7. "MODE,Operating Mode" "0: Device Mode,1: Host Mode"
|
|
bitfld.byte 0x0 2. "RUNSTDBY,Run in Standby Mode" "0,1"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset" "0,1"
|
|
rgroup.byte 0x2++0x0
|
|
line.byte 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable Synchronization Busy" "0,1"
|
|
bitfld.byte 0x0 0. "SWRST,Software Reset Synchronization Busy" "0,1"
|
|
group.byte 0x3++0x0
|
|
line.byte 0x0 "QOSCTRL,USB Quality Of Service"
|
|
bitfld.byte 0x0 2.--3. "DQOS,Data Quality of Service" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CQOS,Configuration Quality of Service" "0,1,2,3"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "CTRLB,HOST Control B"
|
|
bitfld.word 0x0 11. "L1RESUME,Send L1 Resume" "0,1"
|
|
bitfld.word 0x0 10. "VBUSOK,VBUS is OK" "0,1"
|
|
bitfld.word 0x0 9. "BUSRESET,Send USB Reset" "0,1"
|
|
bitfld.word 0x0 8. "SOFE,Start of Frame Generation Enable" "0,1"
|
|
bitfld.word 0x0 6. "TSTK,Test mode K" "0,1"
|
|
bitfld.word 0x0 5. "TSTJ,Test mode J" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "AUTORESUME,Auto Resume Enable" "0,1"
|
|
bitfld.word 0x0 2.--3. "SPDCONF,Speed Configuration for Host" "0: Normal mode: the host starts in full-speed mode..,?,?,3: Full-speed: the host remains in full-speed mode.."
|
|
bitfld.word 0x0 1. "RESUME,Send USB Resume" "0,1"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "HSOFC,HOST Host Start Of Frame Control"
|
|
bitfld.byte 0x0 7. "FLENCE,Frame Length Control Enable" "0,1"
|
|
hexmask.byte 0x0 0.--3. 1. "FLENC,Frame Length Control"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "STATUS,HOST Status"
|
|
bitfld.byte 0x0 6.--7. "LINESTATE,USB Line State Status" "0,1,2,3"
|
|
bitfld.byte 0x0 2.--3. "SPEED,Speed Status" "0,1,2,3"
|
|
rgroup.byte 0xD++0x0
|
|
line.byte 0x0 "FSMSTATUS,Finite State Machine Status"
|
|
hexmask.byte 0x0 0.--6. 1. "FSMSTATE,Fine State Machine Status"
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "FNUM,HOST Host Frame Number"
|
|
hexmask.word 0x0 3.--13. 1. "FNUM,Frame Number"
|
|
bitfld.word 0x0 0.--2. "MFNUM,Micro Frame Number" "0,1,2,3,4,5,6,7"
|
|
rgroup.byte 0x12++0x0
|
|
line.byte 0x0 "FLENHIGH,HOST Host Frame Length"
|
|
hexmask.byte 0x0 0.--7. 1. "FLENHIGH,Frame Length"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "INTENCLR,HOST Host Interrupt Enable Clear"
|
|
bitfld.word 0x0 9. "DDISC,Device Disconnection Interrupt Disable" "0,1"
|
|
bitfld.word 0x0 8. "DCONN,Device Connection Interrupt Disable" "0,1"
|
|
bitfld.word 0x0 7. "RAMACER,Ram Access Interrupt Disable" "0,1"
|
|
bitfld.word 0x0 6. "UPRSM,Upstream Resume from Device Interrupt Disable" "0,1"
|
|
bitfld.word 0x0 5. "DNRSM,DownStream to Device Interrupt Disable" "0,1"
|
|
bitfld.word 0x0 4. "WAKEUP,Wake Up Interrupt Disable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "RST,BUS Reset Interrupt Disable" "0,1"
|
|
bitfld.word 0x0 2. "HSOF,Host Start Of Frame Interrupt Disable" "0,1"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "INTENSET,HOST Host Interrupt Enable Set"
|
|
bitfld.word 0x0 9. "DDISC,Device Disconnection Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 8. "DCONN,Link Power Management Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 7. "RAMACER,Ram Access Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 6. "UPRSM,Upstream Resume fromthe device Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 5. "DNRSM,DownStream to the Device Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 4. "WAKEUP,Wake Up Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "RST,Bus Reset Interrupt Enable" "0,1"
|
|
bitfld.word 0x0 2. "HSOF,Host Start Of Frame Interrupt Enable" "0,1"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "INTFLAG,HOST Host Interrupt Flag"
|
|
bitfld.word 0x0 9. "DDISC,Device Disconnection" "0,1"
|
|
bitfld.word 0x0 8. "DCONN,Device Connection" "0,1"
|
|
bitfld.word 0x0 7. "RAMACER,Ram Access" "0,1"
|
|
bitfld.word 0x0 6. "UPRSM,Upstream Resume from the Device" "0,1"
|
|
bitfld.word 0x0 5. "DNRSM,Downstream" "0,1"
|
|
bitfld.word 0x0 4. "WAKEUP,Wake Up" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "RST,Bus Reset" "0,1"
|
|
bitfld.word 0x0 2. "HSOF,Host Start Of Frame" "0,1"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x0 "PINTSMRY,HOST Pipe Interrupt Summary"
|
|
bitfld.word 0x0 7. "EPINT7,Pipe 7 Interrupt" "0,1"
|
|
bitfld.word 0x0 6. "EPINT6,Pipe 6 Interrupt" "0,1"
|
|
bitfld.word 0x0 5. "EPINT5,Pipe 5 Interrupt" "0,1"
|
|
bitfld.word 0x0 4. "EPINT4,Pipe 4 Interrupt" "0,1"
|
|
bitfld.word 0x0 3. "EPINT3,Pipe 3 Interrupt" "0,1"
|
|
bitfld.word 0x0 2. "EPINT2,Pipe 2 Interrupt" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "EPINT1,Pipe 1 Interrupt" "0,1"
|
|
bitfld.word 0x0 0. "EPINT0,Pipe 0 Interrupt" "0,1"
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "DESCADD,Descriptor Address"
|
|
hexmask.long 0x0 0.--31. 1. "DESCADD,Descriptor Address Value"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "PADCAL,USB PAD Calibration"
|
|
bitfld.word 0x0 12.--14. "TRIM,USB Pad Trim calibration" "0,1,2,3,4,5,6,7"
|
|
hexmask.word.byte 0x0 6.--10. 1. "TRANSN,USB Pad Transn calibration"
|
|
hexmask.word.byte 0x0 0.--4. 1. "TRANSP,USB Pad Transp calibration"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x4502A100 ad:0x4502A120 ad:0x4502A140 ad:0x4502A160 ad:0x4502A180 ad:0x4502A1A0 ad:0x4502A1C0 ad:0x4502A1E0)
|
|
tree "HOST_PIPE[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "PCFG,HOST_PIPE End Point Configuration"
|
|
bitfld.byte 0x0 3.--5. "PTYPE,Pipe Type" "0,1,2,3,4,5,6,7"
|
|
bitfld.byte 0x0 2. "BK,Pipe Bank" "0,1"
|
|
bitfld.byte 0x0 0.--1. "PTOKEN,Pipe Token" "0,1,2,3"
|
|
group.byte ($2+0x3)++0x0
|
|
line.byte 0x0 "BINTERVAL,HOST_PIPE Bus Access Period of Pipe"
|
|
hexmask.byte 0x0 0.--7. 1. "BITINTERVAL,Bit Interval"
|
|
wgroup.byte ($2+0x4)++0x1
|
|
line.byte 0x0 "PSTATUSCLR,HOST_PIPE End Point Pipe Status Clear"
|
|
bitfld.byte 0x0 7. "BK1RDY,Bank 1 Ready Clear" "0,1"
|
|
bitfld.byte 0x0 6. "BK0RDY,Bank 0 Ready Clear" "0,1"
|
|
bitfld.byte 0x0 4. "PFREEZE,Pipe Freeze Clear" "0,1"
|
|
bitfld.byte 0x0 2. "CURBK,Curren Bank clear" "0,1"
|
|
bitfld.byte 0x0 0. "DTGL,Data Toggle clear" "0,1"
|
|
line.byte 0x1 "PSTATUSSET,HOST_PIPE End Point Pipe Status Set"
|
|
bitfld.byte 0x1 7. "BK1RDY,Bank 1 Ready Set" "0,1"
|
|
bitfld.byte 0x1 6. "BK0RDY,Bank 0 Ready Set" "0,1"
|
|
bitfld.byte 0x1 4. "PFREEZE,Pipe Freeze Set" "0,1"
|
|
bitfld.byte 0x1 2. "CURBK,Current Bank Set" "0,1"
|
|
bitfld.byte 0x1 0. "DTGL,Data Toggle Set" "0,1"
|
|
rgroup.byte ($2+0x6)++0x0
|
|
line.byte 0x0 "PSTATUS,HOST_PIPE End Point Pipe Status"
|
|
bitfld.byte 0x0 7. "BK1RDY,Bank 1 ready" "0,1"
|
|
bitfld.byte 0x0 6. "BK0RDY,Bank 0 ready" "0,1"
|
|
bitfld.byte 0x0 4. "PFREEZE,Pipe Freeze" "0,1"
|
|
bitfld.byte 0x0 2. "CURBK,Current Bank" "0,1"
|
|
bitfld.byte 0x0 0. "DTGL,Data Toggle" "0,1"
|
|
group.byte ($2+0x7)++0x2
|
|
line.byte 0x0 "PINTFLAG,HOST_PIPE Pipe Interrupt Flag"
|
|
bitfld.byte 0x0 5. "STALL,Stall Interrupt Flag" "0,1"
|
|
bitfld.byte 0x0 4. "TXSTP,Transmit Setup Interrupt Flag" "0,1"
|
|
bitfld.byte 0x0 3. "PERR,Pipe Error Interrupt Flag" "0,1"
|
|
bitfld.byte 0x0 2. "TRFAIL,Error Flow Interrupt Flag" "0,1"
|
|
bitfld.byte 0x0 1. "TRCPT1,Transfer Complete 1 Interrupt Flag" "0,1"
|
|
bitfld.byte 0x0 0. "TRCPT0,Transfer Complete 0 Interrupt Flag" "0,1"
|
|
line.byte 0x1 "PINTENCLR,HOST_PIPE Pipe Interrupt Flag Clear"
|
|
bitfld.byte 0x1 5. "STALL,Stall Inetrrupt Disable" "0,1"
|
|
bitfld.byte 0x1 4. "TXSTP,Transmit Setup Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 3. "PERR,Pipe Error Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 2. "TRFAIL,Error Flow Interrupt Disable" "0,1"
|
|
bitfld.byte 0x1 1. "TRCPT1,Transfer Complete 1 Disable" "0,1"
|
|
bitfld.byte 0x1 0. "TRCPT0,Transfer Complete 0 Disable" "0,1"
|
|
line.byte 0x2 "PINTENSET,HOST_PIPE Pipe Interrupt Flag Set"
|
|
bitfld.byte 0x2 5. "STALL,Stall Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 4. "TXSTP,Transmit Setup Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 3. "PERR,Pipe Error Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 2. "TRFAIL,Error Flow Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 1. "TRCPT1,Transfer Complete 1 Interrupt Enable" "0,1"
|
|
bitfld.byte 0x2 0. "TRCPT0,Transfer Complete 0 Interrupt Enable" "0,1"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree.end
|
|
tree "USBHS (Universal Serial Bus High-Speed)"
|
|
base ad:0x46000000
|
|
tree "ENDPOINT0 (Endpont 0 is selected)"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRLA,USBHS Control Register A. (All bits except ENABLE and SWRST are Enable protected)"
|
|
bitfld.long 0x0 10. "REFCLKSEL,Select USB PLL Reference Clock Speed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "IDOVEN,ID Source Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IDVAL,Override Valud of ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,USBHS Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,USBHS Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USBHS Control Register B"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "BLANK,Blank the wakeup monitoring for a specific real time"
|
|
line.long 0x8 "CTRLC,USBHS Control Register C"
|
|
bitfld.long 0x8 4. "T1MSEN,REFCLK and SUSPENDM override" "0,1"
|
|
line.long 0xC "INTENCLR,USBHS Interrupt Enable Clear Register"
|
|
bitfld.long 0xC 5. "PHYRDY,Clear PHYRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "T1MS,Clear T1MS Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "DMA,Clear DMA Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "USB,Clear USBCORE General Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "RESUME,Clear Resume Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "WAKEUP,Clear USCORE Detaction Interrupt Enable" "0,1"
|
|
line.long 0x10 "INTENSET,USBHS Interrupt Enable Clear Register"
|
|
bitfld.long 0x10 5. "PHYRDY,PHYRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "T1MS,T1MS Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "DMA,DMA Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "USB,USBCORE General Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "RESUME,Resume Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "WAKEUP,USCORE Detaction Interrupt Enable" "0,1"
|
|
line.long 0x14 "INTFLAG,USBHS Interrupt Flag Register"
|
|
bitfld.long 0x14 5. "PHYRDY,PHY Ready Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "T1MS,Timer 1ms Tick Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "DMA,DMA Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "USB,USBCORE General Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RESUME,Resume Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "WAKEUP,USB Activity Detection Interrupt" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "STATUS,USBHS Status Register"
|
|
bitfld.long 0x0 2. "VREGRDY,USB Voltage Regulator Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PHYON,Power On of PHY Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PHYRDY,PHY Is Ready for USBCORE Activity" "0,1"
|
|
line.long 0x4 "SYNCBUSY,USBHS Syncbusy Register"
|
|
bitfld.long 0x4 2. "T1MSEN,T1MS enable busy bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENABLE,Enable busy bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SWRST,Software reset busy bit" "0,1"
|
|
group.byte 0x1000++0x1
|
|
line.byte 0x0 "FADDR,Function Address Register"
|
|
hexmask.byte 0x0 0.--6. 1. "FUNCADDR,Function address"
|
|
line.byte 0x1 "POWER,Used For Controlling Suspend And Resume Signaling And Some Basic Operation Of USBCORE"
|
|
bitfld.byte 0x1 7. "ISOUPDATE,when set by cpu the usbcore will wait for an sof token" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 6. "SOFTCONN,if enabled the D+ D- lines are enabled when this bit is set by the cpu" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "HSENABLE,when set by cpu the usbcore will negotiate the high speed mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "HSMODE,when set this read only bit indicates high speed mode successfully negotiated during usb reset" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "RESET,this bit is set when reset signaling is present on the bus" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "RESUME,set by cpu to generate resume signaling when te device is in suspend" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "SUSPENDMODE,set by cpu to enter suspend mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "ENABLESUSPENDM,set by the cpu to enable suspendm output" "0,1"
|
|
rgroup.word 0x1002++0x3
|
|
line.word 0x0 "INTRTX,Read Only Register Which Indicates Which Interrupts Are Currently Active For EP0 And TX EP1-15"
|
|
bitfld.word 0x0 7. "EP7TX,Interrupts Active For TX7 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EP6TX,Interrupts Active For TX6 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "EP5TX,Interrupts Active For TX5 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "EP4TX,Interrupts Active For TX4 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EP3TX,Interrupts Active For TX3 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EP2TX,Interrupts Active For TX2 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "EP1TX,Interrupts Active For TX1 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "EP0TX,Interrupts Active For TX0 Endpoint" "0,1"
|
|
line.word 0x2 "INTRRX,Read Only Register Which Indicates Which Interrupts Are Currently Active For RX EP1-15"
|
|
bitfld.word 0x2 7. "EP7RX,Interrupts Active For Which RX7 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "EP6RX,Interrupts Active For Which RX6 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "EP5RX,Interrupts Active For Which RX5 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "EP4RX,Interrupts Active For Which RX4 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "EP3RX,Interrupts Active For Which RX3 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "EP2RX,Interrupts Active For Which RX2 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "EP1RX,Interrupts Active For Which RX1 Endpoint" "0,1"
|
|
group.word 0x1006++0x3
|
|
line.word 0x0 "INTRTXE,Interrupt Enable Bits for INTRTX"
|
|
bitfld.word 0x0 7. "EP7TXEN,Interrupt Enabled for TX EP7" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EP6TXEN,Interrupt Enabled for TX EP6" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "EP5TXEN,Interrupt Enabled for TX EP5" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "EP4TXEN,Interrupt Enabled for TX EP4" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EP3TXEN,Interrupt Enabled for TX EP3" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EP2TXEN,Interrupt Enabled for TX EP2" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "EP1TXEN,Interrupt Enabled for TX EP1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "EP0TXEN,Interrupt Enabled for TX EP0" "0,1"
|
|
line.word 0x2 "INTRRXE,Interrupt Enable Bits for INTRRX"
|
|
bitfld.word 0x2 7. "EP7RXE,Interrupt Enabled for RX EP7" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "EP6RXE,Interrupt Enabled for RX EP6" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "EP5RXE,Interrupt Enabled for RX EP5" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "EP4RXE,Interrupt Enabled for RX EP4" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "EP3RXE,Interrupt Enabled for RX EP3" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "EP2RXE,Interrupt Enabled for RX EP2" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "EP1RXE,Interrupt Enabled for RX EP1" "0,1"
|
|
rgroup.byte 0x100A++0x0
|
|
line.byte 0x0 "INTRUSB,Read Only Register Which Indicates Which USB Interrupts Are Currently Active."
|
|
bitfld.byte 0x0 7. "VBUSERR,Set When VBus Drops Below The VBus Valid Threshold During A Session." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "SESSREQ,Set When Session Request Signaling Has Been Detected." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "DISCON,Set In Host Mode When A Device Disconnect Is Detected.Set In Peripheral Mode When A Session Ends" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CONN,Set When A Device Connection Is Detected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "SOF,Set When A New Frame Starts" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RESET,Set In Peripheral Mode when Reset Is Detected On The Bus. In HostMode When Babble Is Detected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "RESUME,Set When Resume Signal Is Detected On The Bus" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SUSPEND,Set When Suspend Signal Is Detected On The Bus" "0,1"
|
|
group.byte 0x100B++0x0
|
|
line.byte 0x0 "INTRUSBE,Interrupt Enable Bits for USB Interrupts"
|
|
bitfld.byte 0x0 7. "VBUSERREN,VBus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "SESSREQEN,SESSREQ Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "DISCONEN,DISCONN Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CONNEN,CONN Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "SOFEN,SOF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RESETEN,RESET/BABBLE Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "RESUMEEN,RESUME Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SUSPENDEN,SUSEPND Interrupt Enable" "0,1"
|
|
rgroup.word 0x100C++0x1
|
|
line.word 0x0 "FRAME,Holds The Last Received Frame Number"
|
|
hexmask.word 0x0 0.--10. 1. "FRMNUM,Frame Number"
|
|
group.byte 0x100E++0x1
|
|
line.byte 0x0 "INDEX,Index Is A 4-Bit Register That Determines Which Endpoint Control/Status Registers Are Accessed"
|
|
hexmask.byte 0x0 0.--3. 1. "SELEP,The Selected Endpoint"
|
|
line.byte 0x1 "TESTMODE,Not Used In Normal Operation. Configuration To Put the USBCORE Into One Of The Four Test Modes For HighSpeed Operation"
|
|
bitfld.byte 0x1 7. "FORCEHOST,The CPU Sets This Bit To Instruct The Core To Enter Host Mode When The Session Bit Is Set" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 6. "FIFOACCESS,The CPU Sets This Bit To Transfer The Packet In The Endpoint 0 TX FIFO To The Endpoint 0 Rx FIFO. It Is Cleared Automatically." "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "FORCEFS,Depending On Bit 7 Force Controller Into FS Speed Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "FORCEHS,Depending On Bit 7 Force Controller Into High Speed Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "TESTPACKET,Set To Enter The Test_Packet mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "TESTK,Set To Enter The Test_K mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "TESTJ,Set To Enter The Test_J mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "TESTSE0NAK,Set To Enter The Test_SE0_NAK mode" "0,1"
|
|
group.byte 0x1012++0x0
|
|
line.byte 0x0 "CSR0L_HOST_EP0_MODE,ENDPOINT0 Control And Status Bits for TX Endpoint 0"
|
|
bitfld.byte 0x0 7. "NAKTIMEOUT,This Bit Will Be Set When Endpoint 0 Is Halted Following The Receipt Of NAK Responses For Longer Than The Time Set By The NAKLimit0 register." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "STATUSPKT,The CPU Sets This Bit At The Same Time As The TxPktRdy Or ReqPkt Bit Is Set To Perform A Status Stage Transaction" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "REQPKT,The CPU Sets This Bit To Request An IN Transaction" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "ERROR,This Bit Will Be Set When Three Attempts Have Been Made To Perform A Transaction With No Response From The Peripheral" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "SETUPPKT,The CPU Sets This Bit At The Same Time As The TxPktRdy Bit Is Set To Send A SETUP Token Instead Of An OUT Token For The Transaction" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RXSTALL,This Bit Is Set When A Stall Handshake Is Received." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "TXPKTRDY,The CPU Sets This Bit After Loading A Data Packet Into The FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "RXPKTRDY,This Bit Is Set When A Data Packet Has Been Received" "0,1"
|
|
group.byte 0x1012++0x1
|
|
line.byte 0x0 "CSR0L_PERIPHERAL_EP0_MODE,ENDPOINT0 Control And Status Bits for TX Endpoint 0"
|
|
bitfld.byte 0x0 7. "SERVICEDSETUPEND,The CPU Writes A 1 To This Bit To Clear The SetupEnd Bit. It Is Cleared Automatically." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "SERVICEDRXPKTRDY,The CPU Writes A 1 To This Bit To Clear The RxPktRdy Bit. It Is Cleared Automatically" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "SENDSTALL,The CPU Writes A 1 To This Bit To Terminate The Current Transaction" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "SETUPEND,This Bit Will Be Set When A Control Transaction Ends Before The DataEnd Bit Has Been Set" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DATAEND,The CPU Sets This Bit 1. When Setting TxPktRdy For The Last Data Packet 2. When Clearing RxPktRdy After Unloading The Last Data Packet.3. When Setting TxPktRdy For A Zero Length Data Packet." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "SENTSTALL,This Bit Is Set When A Stall Handshake Is Transmitted." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "TXPKTRDY,The CPU Sets This Bit After Loading A Data Packet Into The FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "RXPKTRDY,This Bit Is Set When A Data Packet Has Been Received" "0,1"
|
|
line.byte 0x1 "CSR0H_HOST_EP0_MODE,ENDPOINT0 Additional Control And Status Bits For TX Endpoint 0"
|
|
bitfld.byte 0x1 3. "DISPING,The CPU Writes A 1 To This Bit To Instruct The Core Not To Issue PING Tokens In Data And Status Phases Of A High-Speed Control Transfer" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "DATATOGGLEWRTENABLE,The CPU Writes A 1 To This Bit To Enable The Current State Of The Endpoint 0 Data Toggle To Be Written" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "DATATOGGLE,When Read This Bit Indicates The Current State Of The Endpoint 0 Data Toggle" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "FLUSHFIFO,Flush The Next Packet To Be Transmitted/Read" "0,1"
|
|
group.byte 0x1013++0x0
|
|
line.byte 0x0 "CSR0H_PERIPHERAL_EP0_MODE,ENDPOINT0 Additional Control And Status Bits For TX Endpoint 0"
|
|
bitfld.byte 0x0 0. "FLUSHFIFO,Flush The Next Packet To Be Transmitted/Read" "0,1"
|
|
rgroup.byte 0x1018++0x0
|
|
line.byte 0x0 "COUNT0,ENDPOINT0 Number Of Received Bytes In Endpoint 0 FIFO"
|
|
hexmask.byte 0x0 0.--6. 1. "EP0RXCOUNT,Number Of Received Data Bytes In Endpoint 0 FIFO"
|
|
group.byte 0x101A++0x1
|
|
line.byte 0x0 "TYPE0,ENDPOINT0 Host Mode Only: Operating Speed Of The Targeted Device"
|
|
bitfld.byte 0x0 6.--7. "SPEED,Operating Speed Of The Target Device" "?,1: Device In High Speed,2: Device In Full Speed,3: Device In Low Speed"
|
|
line.byte 0x1 "NAKLIMIT0,ENDPOINT0 Host Mode Only: Sets The NAK Response Timeout On Endpoint 0."
|
|
hexmask.byte 0x1 0.--4. 1. "EP0NAKLIMIT,Number Of Frames/Microframes After Which Endpoint 0 Should Timeout"
|
|
rgroup.byte 0x101F++0x0
|
|
line.byte 0x0 "CONFIGDATA,ENDPOINT0 Returns Information About The Selected Core Configuration. Only Applicable when INDEX Regsiter Is 0. That Is Endpoint0 Is Selected."
|
|
bitfld.byte 0x0 7. "MPRXE,Automatic Splitting Of Bulk Amalgamation Is Selected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "MPTXE,Automatic Splitting Of Bulk Packets Is Selected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "BIGENDIAN,Indicates Little Endian Ordering" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "HBRXE,Indicates High Bandwidth RX ISO Endpoint Support Selected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "HBTXE,Indicates High Bandwidth TX ISO Endpoint Support Selected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "DYNFIFOSIZING,Dynamic FIFO Sizing Is Selected Or Not" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "SOFTCONE,Indicates Soft Connect Or Disconnect" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "UTMIDATAWIDTH,Indicates Selected UTMI+ DataWidth. Always 0 Indicates 8 Bits" "0,1"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1020)++0x3
|
|
line.long 0x0 "FIFOX[$1],Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint"
|
|
hexmask.long 0x0 0.--31. 1. "FIFOADDR,Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint"
|
|
repeat.end
|
|
group.byte 0x1060++0x3
|
|
line.byte 0x0 "DEVCTL,Selects Whether The Core Is Operating In Peripheral Or Host Mode"
|
|
bitfld.byte 0x0 7. "BDEVICE,indicates whether the core is operating as a 'A' device or 'B' device" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "FSDEV,host mode only: this bit is set when a full or high speed device has been detected being connected to the port" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "LSDEV,host mode only: this bit is set when a low speed device has been detected being connected to the port" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "VBUS,encoded value for the VBus level" "0: Below SessionEnd,1: Above SessionEnd below AValid,2: Above AValid below VBus Valid,3: Above VBusValid"
|
|
newline
|
|
bitfld.byte 0x0 2. "HOSTMODE,this read-only bit is set when the USBCORE is acting as a host" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "HOSTREQ,when set the USBCORE will initiate the host negotiation when suspend mode is entered." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SESSION,when operating as an 'A' device this bit is set or cleared by CPU to state or end a session. when operating as a 'B' device this bit is set/cleared by the USBCORE when a session starts/ends" "0,1"
|
|
line.byte 0x1 "MISC,RX/TX Early DMA Enable Bits"
|
|
bitfld.byte 0x1 1. "TXEDMA,DMA_REQ signal for all IN endpoints will be deasserted based on this bit selection" "0: Dma_req signal for all in endpoints will be..,1: Dma_req signal for all in endpoints will be.."
|
|
newline
|
|
bitfld.byte 0x1 0. "RXEDMA,DMA_REQ signal for all OUT endpoints will be deasserted based on this bit selection" "0: Dma_req signal for all out endpoints will be..,1: Dma_req signal for all out endpoints will be.."
|
|
line.byte 0x2 "TXFIFOSZ,Controls The Size Of The Selected TX Endpoint FIFO"
|
|
bitfld.byte 0x2 4. "DPB,double packet buffering supported or not" "0,1"
|
|
newline
|
|
hexmask.byte 0x2 0.--3. 1. "SZ,maximum packet size to be allowed"
|
|
line.byte 0x3 "RXFIFOSZ,Controls The Size Of The Selected RX Endpoint FIFO"
|
|
bitfld.byte 0x3 4. "DPB,double packet buffering enabled or not" "0,1"
|
|
newline
|
|
hexmask.byte 0x3 0.--3. 1. "SZ,maximum packet size to be allowed"
|
|
group.word 0x1064++0x3
|
|
line.word 0x0 "TXFIFOADD,Controls The Start Address Of the Selected TX Endpoint FIFO"
|
|
hexmask.word 0x0 0.--12. 1. "ADDR,start address of the endpoint FIFO"
|
|
line.word 0x2 "RXFIFOADD,Controls The Start Address Of the Selected RX Endpoint FIFO"
|
|
hexmask.word 0x2 0.--12. 1. "ADDR,start address of the endpoint FIFO"
|
|
rgroup.byte 0x1078++0x1
|
|
line.byte 0x0 "EPINFO,Allows Read-Back Of The Number Of TX And RX Endpoints"
|
|
hexmask.byte 0x0 4.--7. 1. "RXENDPOINTS,number of rx endpoints"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "TXENDPOINTS,number of tx endpoints"
|
|
line.byte 0x1 "RAMINFO,Details About Width Of RAM and DMA Channels"
|
|
hexmask.byte 0x1 4.--7. 1. "DMACHANS,number of dma channels implemented in the design"
|
|
newline
|
|
hexmask.byte 0x1 0.--3. 1. "RAMBITS,width of the ram address bus"
|
|
group.byte 0x107A++0x5
|
|
line.byte 0x0 "LINKINFO,Allows Some Delays To Be Specified"
|
|
hexmask.byte 0x0 4.--7. 1. "WTCON,sets the wait to be applied to allow for the user's connect/disconnect filter in units of 533.3ns"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "WTID,sets the delay to be applied from idpullup being asserted to iddig being considered valid in units of 4.369ms"
|
|
line.byte 0x1 "VPLEN,Sets The Duration Of The VBus Pulsing Charge"
|
|
hexmask.byte 0x1 0.--7. 1. "VPLEN,duration of VBus pulsing charge in units of 546.1us"
|
|
line.byte 0x2 "HSEOF1,Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For HS Transactions"
|
|
hexmask.byte 0x2 0.--7. 1. "HSEOF1,sets for high-speed transactions the time before eof to stop beginning new transactions in units of 133.3ns. (the default setting corresponds to 17.07us.)"
|
|
line.byte 0x3 "FSEOF1,Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For FS Transactions"
|
|
hexmask.byte 0x3 0.--7. 1. "FSEOF1,sets for full-speed transactions the time before eof to stop beginning new transactions in units of 533.3ns. (the default setting corresponds to 63.46us.)"
|
|
line.byte 0x4 "LSEOF1,Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For LS Transactions"
|
|
hexmask.byte 0x4 0.--7. 1. "LSEOF1,sets for low-speed transactions the time before eof to stop beginning new transactions in units of 1.067us. (the default setting corresponds to 121.6us.)"
|
|
line.byte 0x5 "SOFTRST,Assert Low The Output Reset Signals NRSTO and NRSTXO"
|
|
bitfld.byte 0x5 1. "NRSTX,when a 1 is written to this bit the output nrstxo will be asserted (low) within a minimum delay of 7 cycles of the clk input. the output nrstxo will be asynchronously asserted and synchronously de-asserted with respect to xclk." "0,1"
|
|
newline
|
|
bitfld.byte 0x5 0. "NRST,when a 1 is written to this bit the output nrsto will be asserted (low) within a minimum delay of 7 cycles of the clk input. the output nrsto will be asynchronously asserted and synchronously de-asserted with respect to clk." "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x46001080 ad:0x46001088 ad:0x46001090 ad:0x46001098 ad:0x460010A0 ad:0x460010A8 ad:0x460010B0 ad:0x460010B8)
|
|
tree "TXFUNADDR[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "TXFUNCADDREP,Relevant In Host Mode Only. Address Of The Target Function."
|
|
hexmask.byte 0x0 0.--6. 1. "TXFUNCADDR,address of the target function"
|
|
group.byte ($2+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDREP,Relevant In Host Mode Only. HUB Address"
|
|
bitfld.byte 0x0 7. "MULTRANS,hub has multiple or single translator" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "TXHUBADDR,hub address"
|
|
line.byte 0x1 "TXHUBPORT,Relevant In Host Mode Only. HUB Address"
|
|
hexmask.byte 0x1 0.--6. 1. "HUBPORT,Hub Port"
|
|
line.byte 0x2 "RXFUNCADDREP,Relevant In Host Mode Only. Address Of The Target Function."
|
|
hexmask.byte 0x2 0.--6. 1. "RXFUNCADDR,address of the target function"
|
|
group.byte ($2+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDREP,Relevant In Host Mode Only. HUB Address"
|
|
bitfld.byte 0x0 7. "MULTRANS,hub has multiple or single translator" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "RXHUBADDR,hub address"
|
|
line.byte 0x1 "RXHUBPORT,Relevant In Host Mode Only. HUB Address"
|
|
hexmask.byte 0x1 0.--6. 1. "HUBPORT,Hub Port"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x46000000
|
|
group.long 0x1200++0x3
|
|
line.long 0x0 "DMAINTR,DMA Interrupt Status for Each Channel"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAINTR,DMA Interrupt for each channel"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x46001204 ad:0x46001214 ad:0x46001224 ad:0x46001234 ad:0x46001244 ad:0x46001254 ad:0x46001264 ad:0x46001274)
|
|
tree "DMACNT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "DMACNTL,DMA Transfer Control For Each Channel"
|
|
bitfld.long 0x0 9.--10. "DMABRSTM,burst mode" "0: Burst Mode 0,1: Burst Mode 1,2: Burst Mode 2,3: Burst Mode 3"
|
|
bitfld.long 0x0 8. "DMAERR,bus error bit" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DMAEP,endpoint number this channel is assigned to"
|
|
bitfld.long 0x0 3. "DMAIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAMODE,transfer mode" "0: Mode 0 Transfer,1: Mode1 Transfer"
|
|
bitfld.long 0x0 1. "DMADIR,transfer direction" "0: DMA Write (RX Endpoint),1: DMA Read (TX Endpoint)"
|
|
bitfld.long 0x0 0. "DMAEN,dma transfer enable" "0,1"
|
|
line.long 0x4 "DMAADDR,Memory Address Of The Corresponding DMA Channel"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR312,upper 30 bits of address"
|
|
bitfld.long 0x4 0.--1. "ADDR10,Lower 2 bits of DMA memory address" "0,1,2,3"
|
|
line.long 0x8 "DMACOUNT,Current DMA Count Of The Transfer"
|
|
hexmask.long 0x8 0.--31. 1. "DMACOUNT,current dma count of the transfer"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x46000000
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1304)++0x3
|
|
line.long 0x0 "RQPKTCOUNT[$1],Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer"
|
|
hexmask.long.word 0x0 0.--15. 1. "RQPKTCOUNT,sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set."
|
|
repeat.end
|
|
group.word 0x1340++0x9
|
|
line.word 0x0 "RXDPKTBUFDIS,Indicates Which Of The RX Endpoints Have Disabled Double Packet Buffer Functionality"
|
|
hexmask.word 0x0 1.--15. 1. "EPxRXDIS,each bit indicates which of the Rx endpoint have disabled double buffer functionality"
|
|
line.word 0x2 "TXDPKTBUFDIS,Indicates Which Of The TX Endpoints Have Disabled Double Packet Buffer Functionality"
|
|
hexmask.word 0x2 1.--15. 1. "EPxTXDIS,each bit indicates which of the Tx endpoint have disabled double buffer functionality"
|
|
line.word 0x4 "CTUCH,Chirp Timeout. Number Of XCLK Cycles Before The Timeout"
|
|
hexmask.word 0x4 0.--15. 1. "CTUCH,this number when multiplied by 4 represents the number of xclk cycles before the timeout occurs"
|
|
line.word 0x6 "CTHHSRTN,Sets The Delay From The End Of High-Speed Resume Signaling (Acting As A Host) To Enable The UTM Normal Operating Mode"
|
|
hexmask.word 0x6 0.--15. 1. "CTHHSRTN,the delay from the end of high speed resume signaling to enabling utm normal operating mode."
|
|
line.word 0x8 "CTHSBT,This Register Represents The Value To Be Added To The Minimum High Speed Timeout Period Of 736 Bit Times."
|
|
hexmask.word.byte 0x8 0.--3. 1. "HSTMEOUTADD,this register represents the value to be added to the mimumum high speed timeout period of 736 bit times"
|
|
group.word 0x1360++0x1
|
|
line.word 0x0 "LPMATTR,Defines The Attributes Of An LPM Transaction And Sleep Cycle."
|
|
hexmask.word.byte 0x0 12.--15. 1. "ENDPOINT,this is the endpnt that in the token packet of the lpm transaction."
|
|
newline
|
|
bitfld.word 0x0 8. "RMTWAK,this bit is the remote wakeup enable bit." "0,1"
|
|
newline
|
|
hexmask.word.byte 0x0 4.--7. 1. "HIRD,this is the host initiated resume duration."
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "LINKSTATE,this value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a lpm transaction."
|
|
group.byte 0x1362++0x0
|
|
line.byte 0x0 "LPMCNTRL_HOST_MODE,LPM Control Register"
|
|
bitfld.byte 0x0 1. "LPMRES,this bit is used by software to initiate a resume from the l1 state" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LPMXMT,software should set this bit to transmit an lpm transaction." "0,1"
|
|
group.byte 0x1362++0x2
|
|
line.byte 0x0 "LPMCNTRL_PERIPHERAL_MODE,LPM Control Register"
|
|
bitfld.byte 0x0 4. "LPMNAK,this bit is used to place all end points in a state such that the response to all transactions other then an lpm transaction will be a nak." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "LPMEN,this register is used to enable lpm in the musbmhdrc." "0: Core supports LPM extended transactions,1: LPM is not supported but extended transactions..,2: LPM and extended transactions are not supported,3: LPM and extended transactions are not supported"
|
|
newline
|
|
bitfld.byte 0x0 1. "LPMRES,this bit is used by software to initiate resume (remote wakeup)." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LPMXMT,this bit is set by software to instruct the core to transition to the l1 state upon the receipt of the next lpm transaction." "0,1"
|
|
line.byte 0x1 "LPMINTREN,LPM Interrupts Enable Register"
|
|
bitfld.byte 0x1 5. "LPMERREN,LPMERR interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "LPMRESEN,LPMRES interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "LPMNCEN,LPMNC interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "LPMACKEN,LPMACK interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "LPMNYEN,LPMMNY interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "LPMSTEN,LPMMST interrupt" "0,1"
|
|
line.byte 0x2 "LPMINTR_HOST_MODE,Status Of The LPM Power State"
|
|
bitfld.byte 0x2 5. "LPMERR,this bit is set if a response to the lpm transaction is received with a bit stuff error or a pid error" "0,1"
|
|
newline
|
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bitfld.byte 0x2 4. "LPMRES,this bit is set when the core has been resumed for any reason." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 3. "LPMNC,this bit is set when an lpm transaction has been transmitted and has failed to complete." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 2. "LPMACK,this bit is set when an lpm transaction is transmitted and the device responds with an ack." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "LPMNY,this bit is set when an lpm transaction is transmitted and the device responds with a nyet." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 0. "LPMST,this bit is set when an lpm transaction is transmitted and the device responds with a stall." "0,1"
|
|
group.byte 0x1364++0x1
|
|
line.byte 0x0 "LPMINTR_PERIPHERAL_MODE,Status Of The LPM Power State"
|
|
bitfld.byte 0x0 5. "LPMERR,this bit is set if an lpm transaction is received that has a linkstate field that is not supported" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "LPMRES,this bit is set if the core has been resumed for any reason." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "LPMNC,this bit is set when an lpm transaction is received and the core responds with a nyet due to data pending in the rx fifos." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "LPMACK,this bit is set when an lpm transaction is received and the core responds with an ack." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "LPMNY,this bit is set when an lpm transaction is received and the core responds with a nyet" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LPMST,this bit is set when an lpm transaction is received and the core responds with a stall." "0,1"
|
|
line.byte 0x1 "LPMFADDR,Function Address In LPM Payload"
|
|
hexmask.byte 0x1 0.--6. 1. "FUNCADDR,function address that will be placed in the LPM payload"
|
|
group.long 0x1500++0x2B
|
|
line.long 0x0 "PHY00,USBHPHY Control Register."
|
|
bitfld.long 0x0 5.--7. "RXPHSSEL,RX clock phase select" "0: Earliest phase,?,?,?,?,?,?,7: Latest phase"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "SLEWRATE,adjust FS/LS slew rate" "0: Highest slew rate,1: Middle slew rate,2: Middle slew rate,3: Smallest slew rate"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PREEMP,enables pre-emphasis" "0: Enable pre-emphasis during SOF and EOP,1: Enable pre-emphasis during chirp,2: Enable pre-emphasis in non-chirp state,3: Always enable pre-emphasis,?,?,?,?"
|
|
line.long 0x4 "PHY04,USBHPHY Control Register."
|
|
bitfld.long 0x4 5.--7. "SQUELCH210,Lower 3 bits of RX squelch trigger point configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4. "HIZ,Set D+/D- to a high impedence state" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RSVD," "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "TXPHSSEL,set the Tx clock phase select" "0,1,2,3"
|
|
line.long 0x8 "PHY08,USBHPHY Control Register."
|
|
hexmask.long.byte 0x8 1.--7. 1. "RSVD,"
|
|
newline
|
|
bitfld.long 0x8 0. "SQUELCH3,MSB of Squelch configuration" "0,1"
|
|
line.long 0xC "PHY0C,USBHPHY Control Register."
|
|
hexmask.long.byte 0xC 5.--11. 1. "TUNE210,Lower 3 bits for HS amplitude tuning"
|
|
line.long 0x10 "PHY10,USBHPHY Control Register."
|
|
bitfld.long 0x10 5.--7. "DRVTUNE210,Lower 3 bits for HS/FS/LS driver strength tuning" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--4. 1. "TUNE76543,Upper 5 bits for HS amplitude tuning"
|
|
line.long 0x14 "PHY14,USBHPHY Control Register."
|
|
bitfld.long 0x14 7. "ODT0,On die termination compensation voltage reference" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "BYPSSSQUELCH,Bypass squelch trigger point configure in chirp mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "COMPBYPSS,Auto compensation bypass" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "DRVTUNE43,Upper 2 bits for HS/FS/LS driver strength tuning" "0,1,2,3"
|
|
line.long 0x18 "PHY18,USBHPHY Control Register."
|
|
hexmask.long.byte 0x18 2.--5. 1. "RSVD,"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "ODT21,Upper 3 bits for on die termination compensation voltage reference" "0,1,2,3"
|
|
line.long 0x1C "PHY1C,USBHPHY Control Register."
|
|
bitfld.long 0x1C 7. "FSLSDIFF,Turn off FS/LS differential receiver in suspend mode" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "ODTBYPASS,ODT auto-refresh bypass" "0,1"
|
|
line.long 0x20 "PHY20,USBHPHY Control Register."
|
|
bitfld.long 0x20 6.--7. "HSSLEW10,Lower 2 bits for HS slew adjust rate" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "RSVD,"
|
|
line.long 0x24 "PHY24,USBHPHY Control Register."
|
|
bitfld.long 0x24 6.--7. "HSDRIVST10,HS transmit drive strength" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x24 3.--5. "HSPREEMPST,HS transmit pre emphasis strength" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x24 2. "ENHLFBITPRE,Enable half-bit pre-emphasis for HS transmit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "VBUSDETEN,VBUS Detection Switch 0 - Closed 1 - Open" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "HSSLEW2,MSB of HS slew rate adjust" "0,1"
|
|
line.long 0x28 "PHY28,USBHPHY Control Register."
|
|
bitfld.long 0x28 5.--7. "HSDRVCOMP,HS drive current compensation voltage reference" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x28 1.--4. 1. "DISCONDET,HOST disconnects detection trigger point"
|
|
newline
|
|
bitfld.long 0x28 0. "HSDRIVST2,MSB of HS transmit driver strength" "0,1"
|
|
group.long 0x1544++0xF
|
|
line.long 0x0 "PHY44,USBHPHY Control Register."
|
|
bitfld.long 0x0 7. "FRCSESSEND,force session end" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "RSVD," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "FRCVBUSVAL,Force output vbus_valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIGDBG,Digital debug interface" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PLLDAMP,PLL damping factor" "0,1"
|
|
line.long 0x4 "PHY48,USBHPHY Control Register."
|
|
bitfld.long 0x4 5.--7. "SESSENDTUNE,Session end reference tuning" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 2. "VBUSCHRGE,VBus charging/discharging bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FRCBSESSVAL,force B_sessionvalid" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FRCASESSVAL,force A_sessionvalid" "0,1"
|
|
line.long 0x8 "PHY4C,USBHPHY Control Register."
|
|
bitfld.long 0x8 6.--7. "BSESSVALIDTUNE10,Lower 2 B_sessionvalid reference tune" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "VBUSVALTUNE,VBus_valid reference tuning" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PHY50,USBHPHY Control Register."
|
|
bitfld.long 0xC 5.--7. "COMPCURREF,Compensation current tuning reference" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 1.--3. "ASESSVALIDTUNE,A_sessionvalid reference tune" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 0. "BSESSVALIDTUNE2,MSB of B_sessionvalid reference tune" "0,1"
|
|
tree.end
|
|
tree "ENDPOINTX (Endpont 1-15 are selected. INDEX.SELEP value needs to be greater than 0)"
|
|
group.long 0x0++0x17
|
|
line.long 0x0 "CTRLA,USBHS Control Register A. (All bits except ENABLE and SWRST are Enable protected)"
|
|
bitfld.long 0x0 10. "REFCLKSEL,Select USB PLL Reference Clock Speed" "0,1"
|
|
newline
|
|
bitfld.long 0x0 9. "IDOVEN,ID Source Select" "0,1"
|
|
newline
|
|
bitfld.long 0x0 8. "IDVAL,Override Valud of ID" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "ENABLE,USBHS Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "SWRST,USBHS Software Reset" "0,1"
|
|
line.long 0x4 "CTRLB,USBHS Control Register B"
|
|
hexmask.long.tbyte 0x4 0.--19. 1. "BLANK,Blank the wakeup monitoring for a specific real time"
|
|
line.long 0x8 "CTRLC,USBHS Control Register C"
|
|
bitfld.long 0x8 4. "T1MSEN,REFCLK and SUSPENDM override" "0,1"
|
|
line.long 0xC "INTENCLR,USBHS Interrupt Enable Clear Register"
|
|
bitfld.long 0xC 5. "PHYRDY,Clear PHYRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 4. "T1MS,Clear T1MS Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 3. "DMA,Clear DMA Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 2. "USB,Clear USBCORE General Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 1. "RESUME,Clear Resume Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0xC 0. "WAKEUP,Clear USCORE Detaction Interrupt Enable" "0,1"
|
|
line.long 0x10 "INTENSET,USBHS Interrupt Enable Clear Register"
|
|
bitfld.long 0x10 5. "PHYRDY,PHYRDY Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 4. "T1MS,T1MS Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 3. "DMA,DMA Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 2. "USB,USBCORE General Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 1. "RESUME,Resume Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x10 0. "WAKEUP,USCORE Detaction Interrupt Enable" "0,1"
|
|
line.long 0x14 "INTFLAG,USBHS Interrupt Flag Register"
|
|
bitfld.long 0x14 5. "PHYRDY,PHY Ready Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "T1MS,Timer 1ms Tick Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 3. "DMA,DMA Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2. "USB,USBCORE General Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 1. "RESUME,Resume Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x14 0. "WAKEUP,USB Activity Detection Interrupt" "0,1"
|
|
rgroup.long 0x18++0x7
|
|
line.long 0x0 "STATUS,USBHS Status Register"
|
|
bitfld.long 0x0 2. "VREGRDY,USB Voltage Regulator Status" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PHYON,Power On of PHY Complete" "0,1"
|
|
newline
|
|
bitfld.long 0x0 0. "PHYRDY,PHY Is Ready for USBCORE Activity" "0,1"
|
|
line.long 0x4 "SYNCBUSY,USBHS Syncbusy Register"
|
|
bitfld.long 0x4 2. "T1MSEN,T1MS enable busy bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "ENABLE,Enable busy bit" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "SWRST,Software reset busy bit" "0,1"
|
|
group.byte 0x1000++0x1
|
|
line.byte 0x0 "FADDR,Function Address Register"
|
|
hexmask.byte 0x0 0.--6. 1. "FUNCADDR,Function address"
|
|
line.byte 0x1 "POWER,Used For Controlling Suspend And Resume Signaling And Some Basic Operation Of USBCORE"
|
|
bitfld.byte 0x1 7. "ISOUPDATE,when set by cpu the usbcore will wait for an sof token" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 6. "SOFTCONN,if enabled the D+ D- lines are enabled when this bit is set by the cpu" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "HSENABLE,when set by cpu the usbcore will negotiate the high speed mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "HSMODE,when set this read only bit indicates high speed mode successfully negotiated during usb reset" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "RESET,this bit is set when reset signaling is present on the bus" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "RESUME,set by cpu to generate resume signaling when te device is in suspend" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "SUSPENDMODE,set by cpu to enter suspend mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "ENABLESUSPENDM,set by the cpu to enable suspendm output" "0,1"
|
|
rgroup.word 0x1002++0x3
|
|
line.word 0x0 "INTRTX,Read Only Register Which Indicates Which Interrupts Are Currently Active For EP0 And TX EP1-15"
|
|
bitfld.word 0x0 7. "EP7TX,Interrupts Active For TX7 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EP6TX,Interrupts Active For TX6 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "EP5TX,Interrupts Active For TX5 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "EP4TX,Interrupts Active For TX4 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EP3TX,Interrupts Active For TX3 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EP2TX,Interrupts Active For TX2 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "EP1TX,Interrupts Active For TX1 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "EP0TX,Interrupts Active For TX0 Endpoint" "0,1"
|
|
line.word 0x2 "INTRRX,Read Only Register Which Indicates Which Interrupts Are Currently Active For RX EP1-15"
|
|
bitfld.word 0x2 7. "EP7RX,Interrupts Active For Which RX7 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "EP6RX,Interrupts Active For Which RX6 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "EP5RX,Interrupts Active For Which RX5 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "EP4RX,Interrupts Active For Which RX4 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "EP3RX,Interrupts Active For Which RX3 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "EP2RX,Interrupts Active For Which RX2 Endpoint" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "EP1RX,Interrupts Active For Which RX1 Endpoint" "0,1"
|
|
group.word 0x1006++0x3
|
|
line.word 0x0 "INTRTXE,Interrupt Enable Bits for INTRTX"
|
|
bitfld.word 0x0 7. "EP7TXEN,Interrupt Enabled for TX EP7" "0,1"
|
|
newline
|
|
bitfld.word 0x0 6. "EP6TXEN,Interrupt Enabled for TX EP6" "0,1"
|
|
newline
|
|
bitfld.word 0x0 5. "EP5TXEN,Interrupt Enabled for TX EP5" "0,1"
|
|
newline
|
|
bitfld.word 0x0 4. "EP4TXEN,Interrupt Enabled for TX EP4" "0,1"
|
|
newline
|
|
bitfld.word 0x0 3. "EP3TXEN,Interrupt Enabled for TX EP3" "0,1"
|
|
newline
|
|
bitfld.word 0x0 2. "EP2TXEN,Interrupt Enabled for TX EP2" "0,1"
|
|
newline
|
|
bitfld.word 0x0 1. "EP1TXEN,Interrupt Enabled for TX EP1" "0,1"
|
|
newline
|
|
bitfld.word 0x0 0. "EP0TXEN,Interrupt Enabled for TX EP0" "0,1"
|
|
line.word 0x2 "INTRRXE,Interrupt Enable Bits for INTRRX"
|
|
bitfld.word 0x2 7. "EP7RXE,Interrupt Enabled for RX EP7" "0,1"
|
|
newline
|
|
bitfld.word 0x2 6. "EP6RXE,Interrupt Enabled for RX EP6" "0,1"
|
|
newline
|
|
bitfld.word 0x2 5. "EP5RXE,Interrupt Enabled for RX EP5" "0,1"
|
|
newline
|
|
bitfld.word 0x2 4. "EP4RXE,Interrupt Enabled for RX EP4" "0,1"
|
|
newline
|
|
bitfld.word 0x2 3. "EP3RXE,Interrupt Enabled for RX EP3" "0,1"
|
|
newline
|
|
bitfld.word 0x2 2. "EP2RXE,Interrupt Enabled for RX EP2" "0,1"
|
|
newline
|
|
bitfld.word 0x2 1. "EP1RXE,Interrupt Enabled for RX EP1" "0,1"
|
|
rgroup.byte 0x100A++0x0
|
|
line.byte 0x0 "INTRUSB,Read Only Register Which Indicates Which USB Interrupts Are Currently Active."
|
|
bitfld.byte 0x0 7. "VBUSERR,Set When VBus Drops Below The VBus Valid Threshold During A Session." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "SESSREQ,Set When Session Request Signaling Has Been Detected." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "DISCON,Set In Host Mode When A Device Disconnect Is Detected.Set In Peripheral Mode When A Session Ends" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CONN,Set When A Device Connection Is Detected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "SOF,Set When A New Frame Starts" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RESET,Set In Peripheral Mode when Reset Is Detected On The Bus. In HostMode When Babble Is Detected" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "RESUME,Set When Resume Signal Is Detected On The Bus" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SUSPEND,Set When Suspend Signal Is Detected On The Bus" "0,1"
|
|
group.byte 0x100B++0x0
|
|
line.byte 0x0 "INTRUSBE,Interrupt Enable Bits for USB Interrupts"
|
|
bitfld.byte 0x0 7. "VBUSERREN,VBus Error Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "SESSREQEN,SESSREQ Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "DISCONEN,DISCONN Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "CONNEN,CONN Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "SOFEN,SOF Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "RESETEN,RESET/BABBLE Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "RESUMEEN,RESUME Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SUSPENDEN,SUSEPND Interrupt Enable" "0,1"
|
|
rgroup.word 0x100C++0x1
|
|
line.word 0x0 "FRAME,Holds The Last Received Frame Number"
|
|
hexmask.word 0x0 0.--10. 1. "FRMNUM,Frame Number"
|
|
group.byte 0x100E++0x1
|
|
line.byte 0x0 "INDEX,Index Is A 4-Bit Register That Determines Which Endpoint Control/Status Registers Are Accessed"
|
|
hexmask.byte 0x0 0.--3. 1. "SELEP,The Selected Endpoint"
|
|
line.byte 0x1 "TESTMODE,Not Used In Normal Operation. Configuration To Put the USBCORE Into One Of The Four Test Modes For HighSpeed Operation"
|
|
bitfld.byte 0x1 7. "FORCEHOST,The CPU Sets This Bit To Instruct The Core To Enter Host Mode When The Session Bit Is Set" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 6. "FIFOACCESS,The CPU Sets This Bit To Transfer The Packet In The Endpoint 0 TX FIFO To The Endpoint 0 Rx FIFO. It Is Cleared Automatically." "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "FORCEFS,Depending On Bit 7 Force Controller Into FS Speed Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "FORCEHS,Depending On Bit 7 Force Controller Into High Speed Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "TESTPACKET,Set To Enter The Test_Packet mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "TESTK,Set To Enter The Test_K mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "TESTJ,Set To Enter The Test_J mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "TESTSE0NAK,Set To Enter The Test_SE0_NAK mode" "0,1"
|
|
group.word 0x1010++0x1
|
|
line.word 0x0 "TXMAXP,ENDPOINTX Maximum Amount Of Data That Can Be Transferred Through The Selected TX Endpoint In A Single Operation"
|
|
hexmask.word.byte 0x0 11.--15. 1. "MULTIPLIER,Multiplier Value (m-1)"
|
|
newline
|
|
hexmask.word 0x0 0.--10. 1. "MAXPAYLOAD,Maximum Payload/Transactions"
|
|
group.byte 0x1012++0x0
|
|
line.byte 0x0 "TXCSRL_HOST_EPX_MODE,ENDPOINTX Control And Status Bits for TX Endpoints 1-15"
|
|
bitfld.byte 0x0 7. "NAKTIMEOUT,This Bit Will Be Set When Endpoint 0 Is Halted Following The Receipt Of NAK Responses For Longer Than The Time Set By The NAKLimit0 register." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "CLRDATATOG,The CPU Writes A 1 To This Bit To Reset The Endpoint Data Toggle To 0." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "RXSTALL,This Bit Is Set When A Stall Handshake Is Received." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "SETUPPKT,The CPU Sets This Bit At The Same Time As The TxPktRdy Bit Is Set To Send A SETUP Token Instead Of An OUT Token For The Transaction" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "FLUSHFIFO,The CPU Writes A 1 To This Bit To Flush The Latest Packet From The Endpoint TX FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "ERROR,This Bit Will Be Set When Three Attempts Have Been Made To Perform A Transaction With No Response From The Peripheral" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "FIFONOTEMPTY,The USB Sets This Bit When There Is At Least 1 Packet In The TX FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "TXPKTRDY,The CPU Sets This Bit After Loading A Data Packet Into The FIFO." "0,1"
|
|
group.byte 0x1012++0x1
|
|
line.byte 0x0 "TXCSRL_PERIPHERAL_EPX_MODE,ENDPOINTX Control And Status Bits for TX Endpoints 1-15"
|
|
bitfld.byte 0x0 7. "INCOMPTX,When The Endpoint Is Being Used For High-Bandwidth Isochronous This Bit Is Set To Indicate Where A Large Packet Has Been Split Into 2 Or 3 Packets For Transmission But Insufficient IN Tokens Have Been Received To Send All The Parts." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "CLRDATATOG,The CPU Writes A 1 To This Bit To Reset The Endpoint Data Toggle To 0." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "SENTSTALL,This Bit Is Set When A Stall Handshake Is Transmitted." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "SENDSTALL,The CPU Writes A 1 To This Bit To Issue A Stall Handshake To An In Token" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "FLUSHFIFO,The CPU Writes A 1 To This Bit To Flush The Latest Packet From The Endpoint TX FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "UNDERRUN,The USB Sets This Bit If An In Token Is Received When TxPktRdy Is Not Set." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "FIFONOTEMPTY,The USB Sets This Bit When There Is At Least 1 Packet In The TX FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "TXPKTRDY,The CPU Sets This Bit After Loading A Data Packet Into The FIFO." "0,1"
|
|
line.byte 0x1 "TXCSRH_HOST_EPX_MODE,ENDPOINTX Additional Control And Status Bits For TX Endpoints 1-15"
|
|
bitfld.byte 0x1 7. "AUTOSET,If The CPU Sets This Bit TxPktRdy Will Be Automatically Set When Data Of The Maximum P" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "MODE,The CPU Sets This Bit To Enable The Endpoint Direction As TX" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "DMAREQENAB,The CPU Sets This Bit To Enable The DMA Request For The RX Endpoint" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "FRCDATATOG,The CPU Sets This Bit To Force The Endpoint Data Toggle To Switch And The Data Packe" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "DMAREQMODE,The CPU Sets This Bit To Select DMA Request Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "DATATOGGLEWRENABLE,The CPU Writes A 1 To This Bit To Enable The Current State Of The Endpoint 0 Data Toggle To Be Written" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "DATATOGGLE,When Read This Bit Indicates The Current State Of The Endpoint" "0,1"
|
|
group.byte 0x1013++0x0
|
|
line.byte 0x0 "TXCSRH_PERIPHERAL_EPX_MODE,ENDPOINTX Additional Control And Status Bits For TX Endpoints 1-15"
|
|
bitfld.byte 0x0 7. "AUTOSET,If The CPU Sets This Bit TxPktRdy Will Be Automatically Set When Data Of The Maximum Packet Size Is Loaded Into The TX FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "ISO,The CPU Sets This Bit To Enable The TX Endpoint For Isochronous Transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "MODE,The CPU Sets This Bit To Enable The Endpoint Direction As TX" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "DMAREQENAB,The CPU Sets This Bit To Enable The DMA Request For The TX Endpoint" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "FRCDATATOG,The CPU Sets This Bit To Force The Endpoint Data Toggle To Switch And The Data Packet To Be Cleared From The FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "DMAREQMODE,The CPU Sets This Bit To Select DMA Request Mode 1 And Clears It To Select DMA Request Mode 0." "0,1"
|
|
group.word 0x1014++0x1
|
|
line.word 0x0 "RXMAXP,ENDPOINTX Maximum Amount Of Data That Can Be Transferred Through The Selected RX Endpoint In A Single Operation"
|
|
hexmask.word.byte 0x0 11.--15. 1. "MULTIPLIER,Multiplier Value (m-1)"
|
|
newline
|
|
hexmask.word 0x0 0.--10. 1. "MAXPAYLOAD,Maximum Payload/Transactions"
|
|
group.byte 0x1016++0x0
|
|
line.byte 0x0 "RXCSRL_HOST_EPX_MODE,ENDPOINTX Control And Status Bits for RX Endpoint 0 Or Endpoint 1-15"
|
|
bitfld.byte 0x0 7. "CLRDATATOG,The CPU Writes A 1 To This Bit To Reset The Endpoint Data Toggle To 0." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "RXSTALL,When A STALL Handshake Is Received This Bit Is Set And An Interrupt Is Generated." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "REQPKT,The CPU Writes A 1 To This Bit To Request An IN Transaction." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "FLUSHFIFO,The CPU Writes A 1 To This Bit To Flush The Next Packet To Be Read From The Endpoint Rx FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "NAKTIMEOUT,This Bit Is Set When RxPktRdy Is Set If The Data Packet Has A CRC Or Bit-stuff Error." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "ERROR,The USB Sets This Bit When 3 Attempts Have Been Made To Receive A Packet And No Data Packet Has Been Received." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "FIFOFULL,This Bit Is Set When No More Packets Can Be Loaded" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "RXPKTRDY,This Bit Is Set When A Data Packet Has Been Received." "0,1"
|
|
group.byte 0x1016++0x1
|
|
line.byte 0x0 "RXCSRL_PERIPHERAL_EPX_MODE,ENDPOINTX Control And Status Bits for RX Endpoint 0 Or Endpoint 1-15"
|
|
bitfld.byte 0x0 7. "CLRDATATOG,The CPU Writes A 1 To This Bit To Reset The Endpoint Data Toggle To 0." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "SENTSTALL,This Bit Is Set When A STALL Handshake Is Transmitted." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "SENDSTALL,The CPU Writes A 1 To This Bit To Issue A STALL Handshake." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "FLUSHFIFO,The CPU Writes A 1 To This Bit To Flush The Next Packet To Be Read From The Endpoint Rx FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DATAERROR,This Bit Is Set When RxPktRdy Is Set If The Data Packet Has A CRC Or Bit-stuff Error." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "OVERRUN,This Bit Is Set If An OUT Packet Cannot Be Loaded Into The Rx FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "FIFOFULL,This Bit Is Set When No More Packets Can Be Loaded Into The Rx FIFO." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "RXPKTRDY,This Bit Is Set When A Data Packet Has Been Received." "0,1"
|
|
line.byte 0x1 "RXCSRH_HOST_EPX_MODE,ENDPOINTX Additional Control And Status Bits for RX Endpoint 0 Or Endpoint 1-15"
|
|
bitfld.byte 0x1 7. "AUTOCLEAR,If The CPU Sets This Bit TxPktRdy Will Be Automatically Cleared When A Packet Of RxMaxP Bytes Has Been Unloaded From The RX FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 6. "AUTOREQ,If The CPU Sets This Bit The ReqPkt Bit Will Be Automatically Set When The RxPktRdy Bit Is Cleared." "0,1"
|
|
newline
|
|
bitfld.byte 0x1 5. "DMAREQENAB,The CPU Sets This Bit To Enable The DMA Request For The RX Endpoint" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "PIDERROR,Indicates A PID Error In The Received Packet" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "DMAREQMODE,The CPU Sets This Bit To Select DMA Request Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "DATATOGGLEWRTENABLE,The CPU Writes A 1 To This Bit To Enable The Current State Of The Endpoint 0 Data Toggle To Be Written" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "DATATOGGLE,When Read This Bit Indicates The Current State Of The Endpoint" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "INCOMPRX,This Bit Is Set In A High-Bandwidth Isochronous/Interrupt Transfer If The Packet In The Rx FIFO Is Incomplete" "0,1"
|
|
group.byte 0x1017++0x0
|
|
line.byte 0x0 "RXCSRH_PERIPHERAL_EPX_MODE,ENDPOINTX Additional Control And Status Bits for RX Endpoint 0 Or Endpoint 1-15"
|
|
bitfld.byte 0x0 7. "AUTOCLEAR,If The CPU Sets This Bit Then The RxPktRdy Bit Will Be Automatically Cleared Whean A Packet Of RxMaxP Bytes Has Benn Unloaded Froim The Rx FIFO" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "ISO,The CPU Sets This Bit To Enable the RX Endpoint For Isochronous Transfers" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "DMAREQENAB,The CPU Sets This Bit To Enable The DMA Request For The RX Endpoint" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "DISNYET,The CPU Sets This Bit To Disable The Sending Of NYET Handshakes" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "DMAREQMODE,The CPU Sets This Bit To Select DMA Request Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "INCOMPRX,This Bit Is Set In A High-Bandwidth Isochronous/Interrupt Transfer If The Packet In The Rx FIFO Is Incomplete Because Parts Of The Data Were Not Received." "0,1"
|
|
rgroup.word 0x1018++0x1
|
|
line.word 0x0 "RXCOUNT,ENDPOINTX Number Of Data Bytes In The Packet Currently In Line To Be Read From The RX FIFO."
|
|
hexmask.word 0x0 0.--13. 1. "ENDPOINTRXCOUNT,Number Of Data Bytes In The Packet Currently In Line To Be Read From The RX FIFO."
|
|
group.byte 0x101A++0x3
|
|
line.byte 0x0 "TXTYPE,ENDPOINTX Host Mode Only: Should Be Written With The Endpoint Number To Be Targeted By The Endpoint"
|
|
bitfld.byte 0x0 6.--7. "SPEED,operating speed of the target device when the core is configured with the multipoint option: 00: unused (note: if selected the target will be assumed to be using the same connection speed as the core.) 01: high 10: full 11: low" "0: unused,1: high,2: Device In Full Speed,3: Device In Low Speed"
|
|
newline
|
|
bitfld.byte 0x0 4.--5. "PROTOCOL,the cpu should set this to select the required protocol for the tx endpoint 00: control 01: isochronous 10: bulk 11: interrupt" "0: control,1: isochronous,?,?"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "ENDPOINTNUMBER,the cpu should set this value to the endpoint number contained in the tx endpoint descriptor"
|
|
line.byte 0x1 "TXINTERVAL,ENDPOINTX Host Mode Only: Defines The Polling Interval For The Currently Selected TX Endpoint."
|
|
hexmask.byte 0x1 0.--7. 1. "TXPOLLINGINTERVAL,polling interval"
|
|
line.byte 0x2 "RXTYPE,ENDPOINTX Host Mode Only: Should Be Written With The Endpoint Number To Be Targeted By The Endpoint"
|
|
bitfld.byte 0x2 6.--7. "SPEED,operating speed of the target device when the core is configured with the multipoint option: 00: unused (note: if selected the target will be assumed to be using the same connection speed as the core.) 01: high 10: full 11: low" "0: unused,1: high,?,?"
|
|
newline
|
|
bitfld.byte 0x2 4.--5. "PROTOCOL,the cpu should set this to select the required protocol for the rx endpoint 00: control 01: isochronous 10: bulk 11: interrupt" "0: control,1: isochronous,?,?"
|
|
newline
|
|
hexmask.byte 0x2 0.--3. 1. "ENDPOINTNUMBER,the cpu should set this value to the endpoint number contained in the rx endpoint descriptor returned to the musbmhdrc during device enumeration."
|
|
line.byte 0x3 "RXINTERVAL,ENDPOINTX Host Mode Only: Defines The Polling Interval For The Currently Selected RX Endpoint."
|
|
hexmask.byte 0x3 0.--7. 1. "RXPOLLINGINTERVAL,polling interval"
|
|
rgroup.byte 0x101F++0x0
|
|
line.byte 0x0 "FIFOSIZE,ENDPOINTX Read Only Register That Returns The Sizes Of The FIFO's Associated With The Selected Additional TX/RX Endpoints. INDEX Regsiter should be set 1-15"
|
|
hexmask.byte 0x0 4.--7. 1. "RXFIFOSIZE,Rx FIFO Size"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "TXFIFOSIZE,Tx FIFO Size"
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1020)++0x3
|
|
line.long 0x0 "FIFOX[$1],Address Range Provides 16 Addresses For CPU Access To The FIFO's For Each Endpoint"
|
|
hexmask.long 0x0 0.--31. 1. "FIFOADDR,Writing To These Addresses Loads Data Into The TXFIFO For The Corresponding Endpoint"
|
|
repeat.end
|
|
group.byte 0x1060++0x3
|
|
line.byte 0x0 "DEVCTL,Selects Whether The Core Is Operating In Peripheral Or Host Mode"
|
|
bitfld.byte 0x0 7. "BDEVICE,indicates whether the core is operating as a 'A' device or 'B' device" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 6. "FSDEV,host mode only: this bit is set when a full or high speed device has been detected being connected to the port" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 5. "LSDEV,host mode only: this bit is set when a low speed device has been detected being connected to the port" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3.--4. "VBUS,encoded value for the VBus level" "0: Below SessionEnd,1: Above SessionEnd below AValid,2: Above AValid below VBus Valid,3: Above VBusValid"
|
|
newline
|
|
bitfld.byte 0x0 2. "HOSTMODE,this read-only bit is set when the USBCORE is acting as a host" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "HOSTREQ,when set the USBCORE will initiate the host negotiation when suspend mode is entered." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "SESSION,when operating as an 'A' device this bit is set or cleared by CPU to state or end a session. when operating as a 'B' device this bit is set/cleared by the USBCORE when a session starts/ends" "0,1"
|
|
line.byte 0x1 "MISC,RX/TX Early DMA Enable Bits"
|
|
bitfld.byte 0x1 1. "TXEDMA,DMA_REQ signal for all IN endpoints will be deasserted based on this bit selection" "0: Dma_req signal for all in endpoints will be..,1: Dma_req signal for all in endpoints will be.."
|
|
newline
|
|
bitfld.byte 0x1 0. "RXEDMA,DMA_REQ signal for all OUT endpoints will be deasserted based on this bit selection" "0: Dma_req signal for all out endpoints will be..,1: Dma_req signal for all out endpoints will be.."
|
|
line.byte 0x2 "TXFIFOSZ,Controls The Size Of The Selected TX Endpoint FIFO"
|
|
bitfld.byte 0x2 4. "DPB,double packet buffering supported or not" "0,1"
|
|
newline
|
|
hexmask.byte 0x2 0.--3. 1. "SZ,maximum packet size to be allowed"
|
|
line.byte 0x3 "RXFIFOSZ,Controls The Size Of The Selected RX Endpoint FIFO"
|
|
bitfld.byte 0x3 4. "DPB,double packet buffering enabled or not" "0,1"
|
|
newline
|
|
hexmask.byte 0x3 0.--3. 1. "SZ,maximum packet size to be allowed"
|
|
group.word 0x1064++0x3
|
|
line.word 0x0 "TXFIFOADD,Controls The Start Address Of the Selected TX Endpoint FIFO"
|
|
hexmask.word 0x0 0.--12. 1. "ADDR,start address of the endpoint FIFO"
|
|
line.word 0x2 "RXFIFOADD,Controls The Start Address Of the Selected RX Endpoint FIFO"
|
|
hexmask.word 0x2 0.--12. 1. "ADDR,start address of the endpoint FIFO"
|
|
rgroup.byte 0x1078++0x1
|
|
line.byte 0x0 "EPINFO,Allows Read-Back Of The Number Of TX And RX Endpoints"
|
|
hexmask.byte 0x0 4.--7. 1. "RXENDPOINTS,number of rx endpoints"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "TXENDPOINTS,number of tx endpoints"
|
|
line.byte 0x1 "RAMINFO,Details About Width Of RAM and DMA Channels"
|
|
hexmask.byte 0x1 4.--7. 1. "DMACHANS,number of dma channels implemented in the design"
|
|
newline
|
|
hexmask.byte 0x1 0.--3. 1. "RAMBITS,width of the ram address bus"
|
|
group.byte 0x107A++0x5
|
|
line.byte 0x0 "LINKINFO,Allows Some Delays To Be Specified"
|
|
hexmask.byte 0x0 4.--7. 1. "WTCON,sets the wait to be applied to allow for the user's connect/disconnect filter in units of 533.3ns"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "WTID,sets the delay to be applied from idpullup being asserted to iddig being considered valid in units of 4.369ms"
|
|
line.byte 0x1 "VPLEN,Sets The Duration Of The VBus Pulsing Charge"
|
|
hexmask.byte 0x1 0.--7. 1. "VPLEN,duration of VBus pulsing charge in units of 546.1us"
|
|
line.byte 0x2 "HSEOF1,Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For HS Transactions"
|
|
hexmask.byte 0x2 0.--7. 1. "HSEOF1,sets for high-speed transactions the time before eof to stop beginning new transactions in units of 133.3ns. (the default setting corresponds to 17.07us.)"
|
|
line.byte 0x3 "FSEOF1,Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For FS Transactions"
|
|
hexmask.byte 0x3 0.--7. 1. "FSEOF1,sets for full-speed transactions the time before eof to stop beginning new transactions in units of 533.3ns. (the default setting corresponds to 63.46us.)"
|
|
line.byte 0x4 "LSEOF1,Sets The Minimum Time Gap That Is To Be Allowed Between The Start Of The Last Transaction And The EOF For LS Transactions"
|
|
hexmask.byte 0x4 0.--7. 1. "LSEOF1,sets for low-speed transactions the time before eof to stop beginning new transactions in units of 1.067us. (the default setting corresponds to 121.6us.)"
|
|
line.byte 0x5 "SOFTRST,Assert Low The Output Reset Signals NRSTO and NRSTXO"
|
|
bitfld.byte 0x5 1. "NRSTX,when a 1 is written to this bit the output nrstxo will be asserted (low) within a minimum delay of 7 cycles of the clk input. the output nrstxo will be asynchronously asserted and synchronously de-asserted with respect to xclk." "0,1"
|
|
newline
|
|
bitfld.byte 0x5 0. "NRST,when a 1 is written to this bit the output nrsto will be asserted (low) within a minimum delay of 7 cycles of the clk input. the output nrsto will be asynchronously asserted and synchronously de-asserted with respect to clk." "0,1"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x46001080 ad:0x46001088 ad:0x46001090 ad:0x46001098 ad:0x460010A0 ad:0x460010A8 ad:0x460010B0 ad:0x460010B8)
|
|
tree "TXFUNADDR[$1]"
|
|
base $2
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "TXFUNCADDREP,Relevant In Host Mode Only. Address Of The Target Function."
|
|
hexmask.byte 0x0 0.--6. 1. "TXFUNCADDR,address of the target function"
|
|
group.byte ($2+0x2)++0x2
|
|
line.byte 0x0 "TXHUBADDREP,Relevant In Host Mode Only. HUB Address"
|
|
bitfld.byte 0x0 7. "MULTRANS,hub has multiple or single translator" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "TXHUBADDR,hub address"
|
|
line.byte 0x1 "TXHUBPORT,Relevant In Host Mode Only. HUB Address"
|
|
hexmask.byte 0x1 0.--6. 1. "HUBPORT,Hub Port"
|
|
line.byte 0x2 "RXFUNCADDREP,Relevant In Host Mode Only. Address Of The Target Function."
|
|
hexmask.byte 0x2 0.--6. 1. "RXFUNCADDR,address of the target function"
|
|
group.byte ($2+0x6)++0x1
|
|
line.byte 0x0 "RXHUBADDREP,Relevant In Host Mode Only. HUB Address"
|
|
bitfld.byte 0x0 7. "MULTRANS,hub has multiple or single translator" "0,1"
|
|
hexmask.byte 0x0 0.--6. 1. "RXHUBADDR,hub address"
|
|
line.byte 0x1 "RXHUBPORT,Relevant In Host Mode Only. HUB Address"
|
|
hexmask.byte 0x1 0.--6. 1. "HUBPORT,Hub Port"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x46000000
|
|
group.long 0x1200++0x3
|
|
line.long 0x0 "DMAINTR,DMA Interrupt Status for Each Channel"
|
|
hexmask.long.byte 0x0 0.--7. 1. "DMAINTR,DMA Interrupt for each channel"
|
|
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7)(list ad:0x46001204 ad:0x46001214 ad:0x46001224 ad:0x46001234 ad:0x46001244 ad:0x46001254 ad:0x46001264 ad:0x46001274)
|
|
tree "DMACNT[$1]"
|
|
base $2
|
|
group.long ($2)++0xB
|
|
line.long 0x0 "DMACNTL,DMA Transfer Control For Each Channel"
|
|
bitfld.long 0x0 9.--10. "DMABRSTM,burst mode" "0: Burst Mode 0,1: Burst Mode 1,2: Burst Mode 2,3: Burst Mode 3"
|
|
bitfld.long 0x0 8. "DMAERR,bus error bit" "0,1"
|
|
hexmask.long.byte 0x0 4.--7. 1. "DMAEP,endpoint number this channel is assigned to"
|
|
bitfld.long 0x0 3. "DMAIE,interrupt enable" "0,1"
|
|
bitfld.long 0x0 2. "DMAMODE,transfer mode" "0: Mode 0 Transfer,1: Mode1 Transfer"
|
|
bitfld.long 0x0 1. "DMADIR,transfer direction" "0: DMA Write (RX Endpoint),1: DMA Read (TX Endpoint)"
|
|
bitfld.long 0x0 0. "DMAEN,dma transfer enable" "0,1"
|
|
line.long 0x4 "DMAADDR,Memory Address Of The Corresponding DMA Channel"
|
|
hexmask.long 0x4 2.--31. 1. "ADDR312,upper 30 bits of address"
|
|
bitfld.long 0x4 0.--1. "ADDR10,Lower 2 bits of DMA memory address" "0,1,2,3"
|
|
line.long 0x8 "DMACOUNT,Current DMA Count Of The Transfer"
|
|
hexmask.long 0x8 0.--31. 1. "DMACOUNT,current dma count of the transfer"
|
|
tree.end
|
|
repeat.end
|
|
base ad:0x46000000
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1304)++0x3
|
|
line.long 0x0 "RQPKTCOUNT[$1],Host Mode Only: Used To Specify Number Of Packets That Are To Be Transaferred In A Block Transfer"
|
|
hexmask.long.word 0x0 0.--15. 1. "RQPKTCOUNT,sets the number of packets of size maxp that are to be transferred in a block transfer. only used in host mode when autoreq is set. has no effect in peripheral mode or when autoreq is not set."
|
|
repeat.end
|
|
group.word 0x1340++0x9
|
|
line.word 0x0 "RXDPKTBUFDIS,Indicates Which Of The RX Endpoints Have Disabled Double Packet Buffer Functionality"
|
|
hexmask.word 0x0 1.--15. 1. "EPxRXDIS,each bit indicates which of the Rx endpoint have disabled double buffer functionality"
|
|
line.word 0x2 "TXDPKTBUFDIS,Indicates Which Of The TX Endpoints Have Disabled Double Packet Buffer Functionality"
|
|
hexmask.word 0x2 1.--15. 1. "EPxTXDIS,each bit indicates which of the Tx endpoint have disabled double buffer functionality"
|
|
line.word 0x4 "CTUCH,Chirp Timeout. Number Of XCLK Cycles Before The Timeout"
|
|
hexmask.word 0x4 0.--15. 1. "CTUCH,this number when multiplied by 4 represents the number of xclk cycles before the timeout occurs"
|
|
line.word 0x6 "CTHHSRTN,Sets The Delay From The End Of High-Speed Resume Signaling (Acting As A Host) To Enable The UTM Normal Operating Mode"
|
|
hexmask.word 0x6 0.--15. 1. "CTHHSRTN,the delay from the end of high speed resume signaling to enabling utm normal operating mode."
|
|
line.word 0x8 "CTHSBT,This Register Represents The Value To Be Added To The Minimum High Speed Timeout Period Of 736 Bit Times."
|
|
hexmask.word.byte 0x8 0.--3. 1. "HSTMEOUTADD,this register represents the value to be added to the mimumum high speed timeout period of 736 bit times"
|
|
group.word 0x1360++0x1
|
|
line.word 0x0 "LPMATTR,Defines The Attributes Of An LPM Transaction And Sleep Cycle."
|
|
hexmask.word.byte 0x0 12.--15. 1. "ENDPOINT,this is the endpnt that in the token packet of the lpm transaction."
|
|
newline
|
|
bitfld.word 0x0 8. "RMTWAK,this bit is the remote wakeup enable bit." "0,1"
|
|
newline
|
|
hexmask.word.byte 0x0 4.--7. 1. "HIRD,this is the host initiated resume duration."
|
|
newline
|
|
hexmask.word.byte 0x0 0.--3. 1. "LINKSTATE,this value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a lpm transaction."
|
|
group.byte 0x1362++0x0
|
|
line.byte 0x0 "LPMCNTRL_HOST_MODE,LPM Control Register"
|
|
bitfld.byte 0x0 1. "LPMRES,this bit is used by software to initiate a resume from the l1 state" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LPMXMT,software should set this bit to transmit an lpm transaction." "0,1"
|
|
group.byte 0x1362++0x2
|
|
line.byte 0x0 "LPMCNTRL_PERIPHERAL_MODE,LPM Control Register"
|
|
bitfld.byte 0x0 4. "LPMNAK,this bit is used to place all end points in a state such that the response to all transactions other then an lpm transaction will be a nak." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "LPMEN,this register is used to enable lpm in the musbmhdrc." "0: Core supports LPM extended transactions,1: LPM is not supported but extended transactions..,2: LPM and extended transactions are not supported,3: LPM and extended transactions are not supported"
|
|
newline
|
|
bitfld.byte 0x0 1. "LPMRES,this bit is used by software to initiate resume (remote wakeup)." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LPMXMT,this bit is set by software to instruct the core to transition to the l1 state upon the receipt of the next lpm transaction." "0,1"
|
|
line.byte 0x1 "LPMINTREN,LPM Interrupts Enable Register"
|
|
bitfld.byte 0x1 5. "LPMERREN,LPMERR interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 4. "LPMRESEN,LPMRES interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 3. "LPMNCEN,LPMNC interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 2. "LPMACKEN,LPMACK interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 1. "LPMNYEN,LPMMNY interrupt" "0,1"
|
|
newline
|
|
bitfld.byte 0x1 0. "LPMSTEN,LPMMST interrupt" "0,1"
|
|
line.byte 0x2 "LPMINTR_HOST_MODE,Status Of The LPM Power State"
|
|
bitfld.byte 0x2 5. "LPMERR,this bit is set if a response to the lpm transaction is received with a bit stuff error or a pid error" "0,1"
|
|
newline
|
|
bitfld.byte 0x2 4. "LPMRES,this bit is set when the core has been resumed for any reason." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 3. "LPMNC,this bit is set when an lpm transaction has been transmitted and has failed to complete." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 2. "LPMACK,this bit is set when an lpm transaction is transmitted and the device responds with an ack." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 1. "LPMNY,this bit is set when an lpm transaction is transmitted and the device responds with a nyet." "0,1"
|
|
newline
|
|
bitfld.byte 0x2 0. "LPMST,this bit is set when an lpm transaction is transmitted and the device responds with a stall." "0,1"
|
|
group.byte 0x1364++0x1
|
|
line.byte 0x0 "LPMINTR_PERIPHERAL_MODE,Status Of The LPM Power State"
|
|
bitfld.byte 0x0 5. "LPMERR,this bit is set if an lpm transaction is received that has a linkstate field that is not supported" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "LPMRES,this bit is set if the core has been resumed for any reason." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "LPMNC,this bit is set when an lpm transaction is received and the core responds with a nyet due to data pending in the rx fifos." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 2. "LPMACK,this bit is set when an lpm transaction is received and the core responds with an ack." "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "LPMNY,this bit is set when an lpm transaction is received and the core responds with a nyet" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "LPMST,this bit is set when an lpm transaction is received and the core responds with a stall." "0,1"
|
|
line.byte 0x1 "LPMFADDR,Function Address In LPM Payload"
|
|
hexmask.byte 0x1 0.--6. 1. "FUNCADDR,function address that will be placed in the LPM payload"
|
|
group.long 0x1500++0x2B
|
|
line.long 0x0 "PHY00,USBHPHY Control Register."
|
|
bitfld.long 0x0 5.--7. "RXPHSSEL,RX clock phase select" "0: Earliest phase,?,?,?,?,?,?,7: Latest phase"
|
|
newline
|
|
bitfld.long 0x0 3.--4. "SLEWRATE,adjust FS/LS slew rate" "0: Highest slew rate,1: Middle slew rate,2: Middle slew rate,3: Smallest slew rate"
|
|
newline
|
|
bitfld.long 0x0 0.--2. "PREEMP,enables pre-emphasis" "0: Enable pre-emphasis during SOF and EOP,1: Enable pre-emphasis during chirp,2: Enable pre-emphasis in non-chirp state,3: Always enable pre-emphasis,?,?,?,?"
|
|
line.long 0x4 "PHY04,USBHPHY Control Register."
|
|
bitfld.long 0x4 5.--7. "SQUELCH210,Lower 3 bits of RX squelch trigger point configuration" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 4. "HIZ,Set D+/D- to a high impedence state" "0,1"
|
|
newline
|
|
bitfld.long 0x4 3. "RSVD," "0,1"
|
|
newline
|
|
bitfld.long 0x4 0.--1. "TXPHSSEL,set the Tx clock phase select" "0,1,2,3"
|
|
line.long 0x8 "PHY08,USBHPHY Control Register."
|
|
hexmask.long.byte 0x8 1.--7. 1. "RSVD,"
|
|
newline
|
|
bitfld.long 0x8 0. "SQUELCH3,MSB of Squelch configuration" "0,1"
|
|
line.long 0xC "PHY0C,USBHPHY Control Register."
|
|
hexmask.long.byte 0xC 5.--11. 1. "TUNE210,Lower 3 bits for HS amplitude tuning"
|
|
line.long 0x10 "PHY10,USBHPHY Control Register."
|
|
bitfld.long 0x10 5.--7. "DRVTUNE210,Lower 3 bits for HS/FS/LS driver strength tuning" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x10 0.--4. 1. "TUNE76543,Upper 5 bits for HS amplitude tuning"
|
|
line.long 0x14 "PHY14,USBHPHY Control Register."
|
|
bitfld.long 0x14 7. "ODT0,On die termination compensation voltage reference" "0,1"
|
|
newline
|
|
bitfld.long 0x14 4. "BYPSSSQUELCH,Bypass squelch trigger point configure in chirp mode" "0,1"
|
|
newline
|
|
bitfld.long 0x14 2.--3. "COMPBYPSS,Auto compensation bypass" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x14 0.--1. "DRVTUNE43,Upper 2 bits for HS/FS/LS driver strength tuning" "0,1,2,3"
|
|
line.long 0x18 "PHY18,USBHPHY Control Register."
|
|
hexmask.long.byte 0x18 2.--5. 1. "RSVD,"
|
|
newline
|
|
bitfld.long 0x18 0.--1. "ODT21,Upper 3 bits for on die termination compensation voltage reference" "0,1,2,3"
|
|
line.long 0x1C "PHY1C,USBHPHY Control Register."
|
|
bitfld.long 0x1C 7. "FSLSDIFF,Turn off FS/LS differential receiver in suspend mode" "0,1"
|
|
newline
|
|
bitfld.long 0x1C 1. "ODTBYPASS,ODT auto-refresh bypass" "0,1"
|
|
line.long 0x20 "PHY20,USBHPHY Control Register."
|
|
bitfld.long 0x20 6.--7. "HSSLEW10,Lower 2 bits for HS slew adjust rate" "0,1,2,3"
|
|
newline
|
|
hexmask.long.byte 0x20 0.--3. 1. "RSVD,"
|
|
line.long 0x24 "PHY24,USBHPHY Control Register."
|
|
bitfld.long 0x24 6.--7. "HSDRIVST10,HS transmit drive strength" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x24 3.--5. "HSPREEMPST,HS transmit pre emphasis strength" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x24 2. "ENHLFBITPRE,Enable half-bit pre-emphasis for HS transmit" "0,1"
|
|
newline
|
|
bitfld.long 0x24 1. "VBUSDETEN,VBUS Detection Switch 0 - Closed 1 - Open" "0,1"
|
|
newline
|
|
bitfld.long 0x24 0. "HSSLEW2,MSB of HS slew rate adjust" "0,1"
|
|
line.long 0x28 "PHY28,USBHPHY Control Register."
|
|
bitfld.long 0x28 5.--7. "HSDRVCOMP,HS drive current compensation voltage reference" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.long.byte 0x28 1.--4. 1. "DISCONDET,HOST disconnects detection trigger point"
|
|
newline
|
|
bitfld.long 0x28 0. "HSDRIVST2,MSB of HS transmit driver strength" "0,1"
|
|
group.long 0x1544++0xF
|
|
line.long 0x0 "PHY44,USBHPHY Control Register."
|
|
bitfld.long 0x0 7. "FRCSESSEND,force session end" "0,1"
|
|
newline
|
|
bitfld.long 0x0 4.--6. "RSVD," "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x0 3. "FRCVBUSVAL,Force output vbus_valid" "0,1"
|
|
newline
|
|
bitfld.long 0x0 2. "DIGDBG,Digital debug interface" "0,1"
|
|
newline
|
|
bitfld.long 0x0 1. "PLLDAMP,PLL damping factor" "0,1"
|
|
line.long 0x4 "PHY48,USBHPHY Control Register."
|
|
bitfld.long 0x4 5.--7. "SESSENDTUNE,Session end reference tuning" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x4 2. "VBUSCHRGE,VBus charging/discharging bypass" "0,1"
|
|
newline
|
|
bitfld.long 0x4 1. "FRCBSESSVAL,force B_sessionvalid" "0,1"
|
|
newline
|
|
bitfld.long 0x4 0. "FRCASESSVAL,force A_sessionvalid" "0,1"
|
|
line.long 0x8 "PHY4C,USBHPHY Control Register."
|
|
bitfld.long 0x8 6.--7. "BSESSVALIDTUNE10,Lower 2 B_sessionvalid reference tune" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x8 0.--2. "VBUSVALTUNE,VBus_valid reference tuning" "0,1,2,3,4,5,6,7"
|
|
line.long 0xC "PHY50,USBHPHY Control Register."
|
|
bitfld.long 0xC 5.--7. "COMPCURREF,Compensation current tuning reference" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 1.--3. "ASESSVALIDTUNE,A_sessionvalid reference tune" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0xC 0. "BSESSVALIDTUNE2,MSB of B_sessionvalid reference tune" "0,1"
|
|
tree.end
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x44016000
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "CTRLA,Control"
|
|
bitfld.byte 0x0 7. "ALWAYSON,Always-On" "0,1"
|
|
bitfld.byte 0x0 6. "RUNSTDBY,Run During Standby" "0,1"
|
|
bitfld.byte 0x0 2. "WEN,Watchdog Timer Window Mode Enable" "0,1"
|
|
bitfld.byte 0x0 1. "ENABLE,Enable" "0,1"
|
|
line.byte 0x1 "CONFIG,Configuration"
|
|
hexmask.byte 0x1 4.--7. 1. "WINDOW,Window Mode Time-Out Period"
|
|
hexmask.byte 0x1 0.--3. 1. "PER,Time-Out Period"
|
|
line.byte 0x2 "EWCTRL,Early Warning Interrupt Control"
|
|
hexmask.byte 0x2 0.--3. 1. "EWOFFSET,Early Warning Interrupt Time Offset"
|
|
group.byte 0x4++0x2
|
|
line.byte 0x0 "INTENCLR,Interrupt Enable Clear"
|
|
bitfld.byte 0x0 0. "EW,Early Warning Interrupt Enable" "0,1"
|
|
line.byte 0x1 "INTENSET,Interrupt Enable Set"
|
|
bitfld.byte 0x1 0. "EW,Early Warning Interrupt Enable" "0,1"
|
|
line.byte 0x2 "INTFLAG,Interrupt Flag Status and Clear"
|
|
bitfld.byte 0x2 0. "EW,Early Warning" "0,1"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x0 "SYNCBUSY,Synchronization Busy"
|
|
bitfld.long 0x0 5. "CLEAR,Clear Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 4. "ALWAYSON,Always-On Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 3. "RUNSTDBY,Run During Standby Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 2. "WEN,Window Enable Synchronization Busy" "0,1"
|
|
bitfld.long 0x0 1. "ENABLE,Enable Synchronization Busy" "0,1"
|
|
wgroup.byte 0xC++0x0
|
|
line.byte 0x0 "CLEAR,Clear"
|
|
hexmask.byte 0x0 0.--7. 1. "CLEAR,Watchdog Clear"
|
|
tree.end
|
|
AUTOINDENT.OFF
|