14673 lines
1006 KiB
Plaintext
14673 lines
1006 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: OMAP5912 On-Chip Peripherals
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; @Props: Released
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; @Author: WOJ, ZUB
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; @Changelog:
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; 2006-01-07
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; 2008-03-05
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; @Manufacturer: TI - Texas Instruments
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; @Doc: 14357.0.sprs231e.pdf; omap5912.pdf; sprt303.pdf; spru652d.pdf
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; spru748a.pdf; spru749a.pdf; spru750a.pdf; spru751a.pdf; spru752a.pdf
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; spru753a.pdf; spru754a.pdf; spru755a.pdf; spru756a.pdf; spru757a.pdf
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; spru758a.pdf; spru759a.pdf; spru760a.pdf; spru761a.pdf; spru762a.pdf
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; spru763a.pdf; spru764a.pdf; spru765a.pdf; spru766a.pdf; spru767a.pdf
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; spru768a.pdf; spru769a.pdf; spru782a.pdf; sprz209b.pdf
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; @Core: ARM926EJ, DSP
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; @Chip: OMAP5912
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; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: peromap5912a.per 7592 2017-02-18 13:54:14Z askoncej $
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config 16. 8.
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base AD:0x00000000
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tree "ARM Core Registers"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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width 8.
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tree "ID Registers"
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group c15:0x0000--0x0000
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line.long 0x0 "MIDR,Identity Code"
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hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer"
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hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision"
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hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version"
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hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number"
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hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision"
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group c15:0x0100--0x0100
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line.long 0x0 "CTR,Cache Type"
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bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f"
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bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes"
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textline " "
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bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16"
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textline " "
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bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..."
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bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128"
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bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1"
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bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16"
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group c15:0x0200--0x0200
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line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register"
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bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes"
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bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes"
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tree.end
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tree "MMU Control and Configuration"
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width 8.
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group c15:0x0001--0x0001
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line.long 0x0 "CR,Control Register"
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bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable"
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bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin"
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bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000"
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textline " "
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bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable"
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bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable"
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bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable"
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bitfld.long 0x0 7. " B ,Endianism" "Little,Big"
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textline " "
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bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable"
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bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable"
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bitfld.long 0x0 0. " M ,MMU" "Disable,Enable"
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textline " "
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group c15:0x0002--0x0002
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line.long 0x0 "TTBR,Translation Table Base Register"
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hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address"
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textline " "
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group c15:0x3--0x3
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line.long 0x0 "DACR,Domain Access Control Register"
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bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager"
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textline " "
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bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager"
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bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager"
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textline " "
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group c15:0x0005--0x0005
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line.long 0x0 "DFSR,Data Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0105--0x0105
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line.long 0x0 "IFSR,Instruction Fault Status Register"
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bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page"
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group c15:0x0006--0x0006
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line.long 0x0 "DFAR,Data Fault Address Register"
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textline " "
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group c15:0x000a--0x000a
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line.long 0x0 "TLBR,TLB Lockdown Register"
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bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0 0. " P ,P bit" "0,1"
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textline " "
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group c15:0x000d--0x000d
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line.long 0x0 "FCSEPID,FCSE Process ID"
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group c15:0x010d--0x010d
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line.long 0x0 "CONTEXT,Context ID"
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tree.end
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tree "Cache Control and Configuration"
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group c15:0x0009--0x0009
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line.long 0x0 "DCACHE,Data Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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group c15:0x0109--0x0109
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line.long 0x0 "ICACHE,Instruction Cache Lockdown"
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bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1"
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bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1"
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bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1"
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bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1"
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tree.end
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tree "TCM Control and Configuration"
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group c15:0x0019--0x0019
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line.long 0x0 "DTCM,Data TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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group c15:0x0119--0x0119
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line.long 0x0 "ITCM,Instruction TCM Region Register"
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hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address"
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bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res"
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bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable"
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tree.end
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tree "Test and Debug"
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group c15:0x000f--0x000f
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line.long 0x0 "DOVRR,Debug Override Register"
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bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable"
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bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort"
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bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort"
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textline " "
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bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable"
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bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable"
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bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable"
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bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT"
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group c15:0x001f--0x001f
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line.long 0x0 "ADDRESS,Debug/Test Address"
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;wgroup c15:0x402f--0x402f
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; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry"
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;wgroup c15:0x403f--0x403f
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; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry"
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;wgroup c15:0x404f--0x404f
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; line.long 0x0 "RMTLBPA,Read PA in main TLB entry"
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;wgroup c15:0x405f--0x405f
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; line.long 0x0 "WMTLBPA,Write PA in main TLB entry"
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;wgroup c15:0x407f--0x407f
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; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM"
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;wgroup c15:0x412f--0x412f
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; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry"
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;wgroup c15:0x413f--0x413f
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; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry"
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;wgroup c15:0x414f--0x414f
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; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry"
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;wgroup c15:0x415f--0x415f
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; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry"
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;wgroup c15:0x417f--0x417f
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; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM"
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group c15:0x101f--0x101f
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line.long 0x0 "TRACE,Trace Control"
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bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall"
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bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall"
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group c15:0x700f--0x700f
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line.long 0x0 "CACHE,Cache Debug Control"
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bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through"
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bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable"
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bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable"
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group c15:0x701f--0x701f
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line.long 0x0 "MMU,MMU Debug Control"
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bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable"
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textline " "
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bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable"
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bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable"
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bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable"
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bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable"
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group c15:0x002f--0x002f
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line.long 0x0 "REMAP,Memory Region Remap"
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bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB"
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textline " "
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bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB"
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bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB"
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tree.end
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tree "ICEbreaker"
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width 8.
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group ice:0x0--0x5 "Debug Control"
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line.long 0x0 "DBGCTRL,Debug Control Register"
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bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled"
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bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled"
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textline " "
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bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled"
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bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled"
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bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x4 "DBGSTAT,Debug Status Register"
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bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res"
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bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java"
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bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb"
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bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1"
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bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled"
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bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes"
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bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes"
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line.long 0x8 "VECTOR,Vector Catch Register"
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bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena"
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bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena"
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bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena"
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bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena"
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bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena"
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bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena"
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bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena"
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line.long 0x10 "COMCTRL,Debug Communication Control Register"
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bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
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bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend"
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bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend"
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line.long 0x14 "COMDATA,Debug Communication Data Register"
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group ice:0x8--0x0d "Watchpoint 0"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
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bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
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bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
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bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
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bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
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bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
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group ice:0x10--0x15 "Watchpoint 1"
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line.long 0x0 "AV,Address Value"
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line.long 0x4 "AM,Address Mask"
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line.long 0x8 "DV,Data Value"
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line.long 0x0c "DM,Data Mask"
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line.long 0x10 "CV,Control Value"
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bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA"
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bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1"
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bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1"
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bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1"
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bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User"
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bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data"
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bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res"
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bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w"
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line.long 0x14 "CM,Control Mask"
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bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS"
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bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS"
|
|
bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS"
|
|
bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS "
|
|
bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS"
|
|
bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS"
|
|
bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS"
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "MPU Private Peripheral Registers"
|
|
base AD:0xFFFE0000
|
|
tree "MPU Level 2 Interrupt Handler Registers"
|
|
width 16.
|
|
tree "BANK 0"
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "MPU_L2_ITR,Interrupt Register"
|
|
bitfld.long 0x00 31. " IRQ_31 ,Interrupt on line number 31 is detected" "No,Yes"
|
|
bitfld.long 0x00 30. " IRQ_30 ,Interrupt on line number 30 is detected" "No,Yes"
|
|
bitfld.long 0x00 29. " IRQ_29 ,Interrupt on line number 29 is detected" "No,Yes"
|
|
bitfld.long 0x00 28. " IRQ_28 ,Interrupt on line number 28 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQ_27 ,Interrupt on line number 27 is detected" "No,Yes"
|
|
bitfld.long 0x00 26. " IRQ_26 ,Interrupt on line number 26 is detected" "No,Yes"
|
|
bitfld.long 0x00 25. " IRQ_25 ,Interrupt on line number 25 is detected" "No,Yes"
|
|
bitfld.long 0x00 24. " IRQ_24 ,Interrupt on line number 24 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQ_23 ,Interrupt on line number 23 is detected" "No,Yes"
|
|
bitfld.long 0x00 22. " IRQ_22 ,Interrupt on line number 22 is detected" "No,Yes"
|
|
bitfld.long 0x00 21. " IRQ_21 ,Interrupt on line number 21 is detected" "No,Yes"
|
|
bitfld.long 0x00 20. " IRQ_20 ,Interrupt on line number 20 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQ_19 ,Interrupt on line number 19 is detected" "No,Yes"
|
|
bitfld.long 0x00 18. " IRQ_18 ,Interrupt on line number 18 is detected" "No,Yes"
|
|
bitfld.long 0x00 17. " IRQ_17 ,Interrupt on line number 17 is detected" "No,Yes"
|
|
bitfld.long 0x00 16. " IRQ_16 ,Interrupt on line number 16 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQ_15 ,Interrupt on line number 15 is detected" "No,Yes"
|
|
bitfld.long 0x00 14. " IRQ_14 ,Interrupt on line number 14 is detected" "No,Yes"
|
|
bitfld.long 0x00 13. " IRQ_13 ,Interrupt on line number 13 is detected" "No,Yes"
|
|
bitfld.long 0x00 12. " IRQ_12 ,Interrupt on line number 12 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQ_11 ,Interrupt on line number 11 is detected" "No,Yes"
|
|
bitfld.long 0x00 10. " IRQ_10 ,Interrupt on line number 10 is detected" "No,Yes"
|
|
bitfld.long 0x00 9. " IRQ_9 ,Interrupt on line number 9 is detected" "No,Yes"
|
|
bitfld.long 0x00 8. " IRQ_8 ,Interrupt on line number 8 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_7 ,Interrupt on line number 7 is detected" "No,Yes"
|
|
bitfld.long 0x00 6. " IRQ_6 ,Interrupt on line number 6 is detected" "No,Yes"
|
|
bitfld.long 0x00 5. " IRQ_5 ,Interrupt on line number 5 is detected" "No,Yes"
|
|
bitfld.long 0x00 4. " IRQ_4 ,Interrupt on line number 4 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQ_3 ,Interrupt on line number 3 is detected" "No,Yes"
|
|
bitfld.long 0x00 2. " IRQ_2 ,Interrupt on line number 2 is detected" "No,Yes"
|
|
bitfld.long 0x00 1. " IRQ_1 ,Interrupt on line number 1 is detected" "No,Yes"
|
|
bitfld.long 0x00 0. " IRQ_0 ,Interrupt on line number 0 is detected" "No,Yes"
|
|
line.long 0x04 "MPU_L2_MIR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " MIR_31 ,Mask interrupt on line number 31" "No mask,Mask"
|
|
bitfld.long 0x04 30. " MIR_30 ,Mask interrupt on line number 30" "No mask,Mask"
|
|
bitfld.long 0x04 29. " MIR_29 ,Mask interrupt on line number 29" "No mask,Mask"
|
|
bitfld.long 0x04 28. " MIR_28 ,Mask interrupt on line number 28" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MIR_27 ,Mask interrupt on line number 27" "No mask,Mask"
|
|
bitfld.long 0x04 26. " MIR_26 ,Mask interrupt on line number 26" "No mask,Mask"
|
|
bitfld.long 0x04 25. " MIR_25 ,Mask interrupt on line number 25" "No mask,Mask"
|
|
bitfld.long 0x04 24. " MIR_24 ,Mask interrupt on line number 24" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MIR_23 ,Mask interrupt on line number 23" "No mask,Mask"
|
|
bitfld.long 0x04 22. " MIR_22 ,Mask interrupt on line number 22" "No mask,Mask"
|
|
bitfld.long 0x04 21. " MIR_21 ,Mask interrupt on line number 21" "No mask,Mask"
|
|
bitfld.long 0x04 20. " MIR_20 ,Mask interrupt on line number 20" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MIR_19 ,Mask interrupt on line number 19" "No mask,Mask"
|
|
bitfld.long 0x04 18. " MIR_18 ,Mask interrupt on line number 18" "No mask,Mask"
|
|
bitfld.long 0x04 17. " MIR_17 ,Mask interrupt on line number 17" "No mask,Mask"
|
|
bitfld.long 0x04 16. " MIR_16 ,Mask interrupt on line number 16" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MIR_15 ,Mask interrupt on line number 15" "No mask,Mask"
|
|
bitfld.long 0x04 14. " MIR_14 ,Mask interrupt on line number 14" "No mask,Mask"
|
|
bitfld.long 0x04 13. " MIR_13 ,Mask interrupt on line number 13" "No mask,Mask"
|
|
bitfld.long 0x04 12. " MIR_12 ,Mask interrupt on line number 12" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MIR_11 ,Mask interrupt on line number 11" "No mask,Mask"
|
|
bitfld.long 0x04 10. " MIR_10 ,Mask interrupt on line number 10" "No mask,Mask"
|
|
bitfld.long 0x04 9. " MIR_9 ,Mask interrupt on line number 9" "No mask,Mask"
|
|
bitfld.long 0x04 8. " MIR_8 ,Mask interrupt on line number 8" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MIR_7 ,Mask interrupt on line number 7" "No mask,Mask"
|
|
bitfld.long 0x04 6. " MIR_6 ,Mask interrupt on line number 6" "No mask,Mask"
|
|
bitfld.long 0x04 5. " MIR_5 ,Mask interrupt on line number 5" "No mask,Mask"
|
|
bitfld.long 0x04 4. " MIR_4 ,Mask interrupt on line number 4" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MIR_3 ,Mask interrupt on line number 3" "No mask,Mask"
|
|
bitfld.long 0x04 2. " MIR_2 ,Mask interrupt on line number 2" "No mask,Mask"
|
|
bitfld.long 0x04 1. " MIR_1 ,Mask interrupt on line number 1" "No mask,Mask"
|
|
bitfld.long 0x04 0. " MIR_0 ,Mask interrupt on line number 0" "No mask,Mask"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "MPU_L2_SIR_IRQ,Interrupt Encoded Source (IRQ) Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IRQ ,Active IRQ number"
|
|
line.long 0x04 "MPU_L2_SIR_FIQ,Interrupt Encoded Source (FIQ) Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FIQ ,Active FIQ number"
|
|
group.long 0x18++0x83
|
|
line.long 0x00 "MPU_L2_CONTROL,Interrupt Control Register"
|
|
bitfld.long 0x00 3. " GLOBAL_MASK " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_FIQ_AGR " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_IRQ_AGR " "Disabled,Enabled"
|
|
line.long 0x04 "MPU_L2_ILR0,Interrupt Priority Level For IRQ 0 Register"
|
|
hexmask.long.byte 0x04 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x04 1. " SENS_0EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x04 0. " FIQ_0IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x08 "MPU_L2_ILR1,Interrupt Priority Level For IRQ 1 Register"
|
|
hexmask.long.byte 0x08 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x08 1. " SENS_1EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x08 0. " FIQ_1IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x0c "MPU_L2_ILR2,Interrupt Priority Level For IRQ 2 Register"
|
|
hexmask.long.byte 0x0c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x0c 1. " SENS_2EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x0c 0. " FIQ_2IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x10 "MPU_L2_ILR3,Interrupt Priority Level For IRQ 3 Register"
|
|
hexmask.long.byte 0x10 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x10 1. " SENS_3EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x10 0. " FIQ_3IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x14 "MPU_L2_ILR4,Interrupt Priority Level For IRQ 4 Register"
|
|
hexmask.long.byte 0x14 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x14 1. " SENS_4EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x14 0. " FIQ_4IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x18 "MPU_L2_ILR5,Interrupt Priority Level For IRQ 5 Register"
|
|
hexmask.long.byte 0x18 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x18 1. " SENS_5EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x18 0. " FIQ_5IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x1c "MPU_L2_ILR6,Interrupt Priority Level For IRQ 6 Register"
|
|
hexmask.long.byte 0x1c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x1c 1. " SENS_6EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x1c 0. " FIQ_6IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x20 "MPU_L2_ILR7,Interrupt Priority Level For IRQ 7 Register"
|
|
hexmask.long.byte 0x20 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x20 1. " SENS_7EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x20 0. " FIQ_7IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x24 "MPU_L2_ILR8,Interrupt Priority Level For IRQ 8 Register"
|
|
hexmask.long.byte 0x24 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x24 1. " SENS_8EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x24 0. " FIQ_8IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x28 "MPU_L2_ILR9,Interrupt Priority Level For IRQ 9 Register"
|
|
hexmask.long.byte 0x28 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x28 1. " SENS_9EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x28 0. " FIQ_9IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x2c "MPU_L2_ILR10,Interrupt Priority Level For IRQ 10 Register"
|
|
hexmask.long.byte 0x2c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x2c 1. " SENS_10EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x2c 0. " FIQ_10IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x30 "MPU_L2_ILR11,Interrupt Priority Level For IRQ 11 Register"
|
|
hexmask.long.byte 0x30 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x30 1. " SENS_11EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x30 0. " FIQ_11IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x34 "MPU_L2_ILR12,Interrupt Priority Level For IRQ 12 Register"
|
|
hexmask.long.byte 0x34 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x34 1. " SENS_12EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x34 0. " FIQ_12IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x38 "MPU_L2_ILR13,Interrupt Priority Level For IRQ 13 Register"
|
|
hexmask.long.byte 0x38 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x38 1. " SENS_13EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x38 0. " FIQ_13IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x3c "MPU_L2_ILR14,Interrupt Priority Level For IRQ 14 Register"
|
|
hexmask.long.byte 0x3c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x3c 1. " SENS_14EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x3c 0. " FIQ_14IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x40 "MPU_L2_ILR15,Interrupt Priority Level For IRQ 15 Register"
|
|
hexmask.long.byte 0x40 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x40 1. " SENS_15EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x40 0. " FIQ_15IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x44 "MPU_L2_ILR16,Interrupt Priority Level For IRQ 16 Register"
|
|
hexmask.long.byte 0x44 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x44 1. " SENS_16EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x44 0. " FIQ_16IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x48 "MPU_L2_ILR17,Interrupt Priority Level For IRQ 17 Register"
|
|
hexmask.long.byte 0x48 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x48 1. " SENS_17EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x48 0. " FIQ_17IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x4c "MPU_L2_ILR18,Interrupt Priority Level For IRQ 18 Register"
|
|
hexmask.long.byte 0x4c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x4c 1. " SENS_18EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x4c 0. " FIQ_18IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x50 "MPU_L2_ILR19,Interrupt Priority Level For IRQ 19 Register"
|
|
hexmask.long.byte 0x50 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x50 1. " SENS_19EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x50 0. " FIQ_19IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x54 "MPU_L2_ILR20,Interrupt Priority Level For IRQ 20 Register"
|
|
hexmask.long.byte 0x54 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x54 1. " SENS_20EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x54 0. " FIQ_20IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x58 "MPU_L2_ILR21,Interrupt Priority Level For IRQ 21 Register"
|
|
hexmask.long.byte 0x58 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x58 1. " SENS_21EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x58 0. " FIQ_21IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x5c "MPU_L2_ILR22,Interrupt Priority Level For IRQ 22 Register"
|
|
hexmask.long.byte 0x5c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x5c 1. " SENS_22EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x5c 0. " FIQ_22IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x60 "MPU_L2_ILR23,Interrupt Priority Level For IRQ 23 Register"
|
|
hexmask.long.byte 0x60 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x60 1. " SENS_23EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x60 0. " FIQ_23IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x64 "MPU_L2_ILR24,Interrupt Priority Level For IRQ 24 Register"
|
|
hexmask.long.byte 0x64 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x64 1. " SENS_24EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x64 0. " FIQ_24IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x68 "MPU_L2_ILR25,Interrupt Priority Level For IRQ 25 Register"
|
|
hexmask.long.byte 0x68 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x68 1. " SENS_25EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x68 0. " FIQ_25IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x6c "MPU_L2_ILR26,Interrupt Priority Level For IRQ 26 Register"
|
|
hexmask.long.byte 0x6c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x6c 1. " SENS_26EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x6c 0. " FIQ_26IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x70 "MPU_L2_ILR27,Interrupt Priority Level For IRQ 27 Register"
|
|
hexmask.long.byte 0x70 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x70 1. " SENS_27EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x70 0. " FIQ_27IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x74 "MPU_L2_ILR28,Interrupt Priority Level For IRQ 28 Register"
|
|
hexmask.long.byte 0x74 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x74 1. " SENS_28EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x74 0. " FIQ_28IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x78 "MPU_L2_ILR29,Interrupt Priority Level For IRQ 29 Register"
|
|
hexmask.long.byte 0x78 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x78 1. " SENS_29EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x78 0. " FIQ_29IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x7c "MPU_L2_ILR30,Interrupt Priority Level For IRQ 30 Register"
|
|
hexmask.long.byte 0x7c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x7c 1. " SENS_30EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x7c 0. " FIQ_30IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x80 "MPU_L2_ILR31,Interrupt Priority Level For IRQ 31 Register"
|
|
hexmask.long.byte 0x80 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x80 1. " SENS_31EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x80 0. " FIQ_31IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
wgroup.long 0x9C++0x3
|
|
line.long 0x00 "MPU_L2_ISR,Software Interrupt Set Register"
|
|
bitfld.long 0x00 31. " SISR_31 ,Generate interrupt on line number 31" "Do not,Do"
|
|
bitfld.long 0x00 30. " SISR_30 ,Generate interrupt on line number 30" "Do not,Do"
|
|
bitfld.long 0x00 29. " SISR_29 ,Generate interrupt on line number 29" "Do not,Do"
|
|
bitfld.long 0x00 28. " SISR_28 ,Generate interrupt on line number 28" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SISR_27 ,Generate interrupt on line number 27" "Do not,Do"
|
|
bitfld.long 0x00 26. " SISR_26 ,Generate interrupt on line number 26" "Do not,Do"
|
|
bitfld.long 0x00 25. " SISR_25 ,Generate interrupt on line number 25" "Do not,Do"
|
|
bitfld.long 0x00 24. " SISR_24 ,Generate interrupt on line number 24" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SISR_23 ,Generate interrupt on line number 23" "Do not,Do"
|
|
bitfld.long 0x00 22. " SISR_22 ,Generate interrupt on line number 22" "Do not,Do"
|
|
bitfld.long 0x00 21. " SISR_21 ,Generate interrupt on line number 21" "Do not,Do"
|
|
bitfld.long 0x00 20. " SISR_20 ,Generate interrupt on line number 20" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SISR_19 ,Generate interrupt on line number 19" "Do not,Do"
|
|
bitfld.long 0x00 18. " SISR_18 ,Generate interrupt on line number 18" "Do not,Do"
|
|
bitfld.long 0x00 17. " SISR_17 ,Generate interrupt on line number 17" "Do not,Do"
|
|
bitfld.long 0x00 16. " SISR_16 ,Generate interrupt on line number 16" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SISR_15 ,Generate interrupt on line number 15" "Do not,Do"
|
|
bitfld.long 0x00 14. " SISR_14 ,Generate interrupt on line number 14" "Do not,Do"
|
|
bitfld.long 0x00 13. " SISR_13 ,Generate interrupt on line number 13" "Do not,Do"
|
|
bitfld.long 0x00 12. " SISR_12 ,Generate interrupt on line number 12" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SISR_11 ,Generate interrupt on line number 11" "Do not,Do"
|
|
bitfld.long 0x00 10. " SISR_10 ,Generate interrupt on line number 10" "Do not,Do"
|
|
bitfld.long 0x00 9. " SISR_9 ,Generate interrupt on line number 9" "Do not,Do"
|
|
bitfld.long 0x00 8. " SISR_8 ,Generate interrupt on line number 8" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SISR_7 ,Generate interrupt on line number 7" "Do not,Do"
|
|
bitfld.long 0x00 6. " SISR_6 ,Generate interrupt on line number 6" "Do not,Do"
|
|
bitfld.long 0x00 5. " SISR_5 ,Generate interrupt on line number 5" "Do not,Do"
|
|
bitfld.long 0x00 4. " SISR_4 ,Generate interrupt on line number 4" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SISR_3 ,Generate interrupt on line number 3" "Do not,Do"
|
|
bitfld.long 0x00 2. " SISR_2 ,Generate interrupt on line number 2" "Do not,Do"
|
|
bitfld.long 0x00 1. " SISR_1 ,Generate interrupt on line number 1" "Do not,Do"
|
|
bitfld.long 0x00 0. " SISR_0 ,Generate interrupt on line number 0" "Do not,Do"
|
|
rgroup.long 0xA0++0x3
|
|
line.long 0x00 "MPU_L2_STATUS,Status Register"
|
|
bitfld.long 0x00 0. " RESET_DONE ,A reset has occured" "No reset,Reset"
|
|
group.long 0xA4++0x3
|
|
line.long 0x00 "MPU_L2_OCP_CFG,OCP Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ," "Force wake-up,Reserved,Smart idle,?..."
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Generate a soft reset of the module" "Do not,Do"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internat OCP clock gating strategy" "Free running,OCP interface"
|
|
rgroup.long 0xA8++0x3
|
|
line.long 0x00 "MPU_L2_INTH_REV,Interrupt Controller Revision ID"
|
|
hexfld.byte 0x00 " REV ,Revision number"
|
|
tree.end
|
|
tree "BANK 1"
|
|
base AD:0xFFFE0100
|
|
group 0x0000++0x7
|
|
line.long 0x00 "MPU_L2_ITR,Interrupt Register"
|
|
bitfld.long 0x00 31. " IRQ_31 ,Interrupt on line number 31 is detected" "No,Yes"
|
|
bitfld.long 0x00 30. " IRQ_30 ,Interrupt on line number 30 is detected" "No,Yes"
|
|
bitfld.long 0x00 29. " IRQ_29 ,Interrupt on line number 29 is detected" "No,Yes"
|
|
bitfld.long 0x00 28. " IRQ_28 ,Interrupt on line number 28 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQ_27 ,Interrupt on line number 27 is detected" "No,Yes"
|
|
bitfld.long 0x00 26. " IRQ_26 ,Interrupt on line number 26 is detected" "No,Yes"
|
|
bitfld.long 0x00 25. " IRQ_25 ,Interrupt on line number 25 is detected" "No,Yes"
|
|
bitfld.long 0x00 24. " IRQ_24 ,Interrupt on line number 24 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQ_23 ,Interrupt on line number 23 is detected" "No,Yes"
|
|
bitfld.long 0x00 22. " IRQ_22 ,Interrupt on line number 22 is detected" "No,Yes"
|
|
bitfld.long 0x00 21. " IRQ_21 ,Interrupt on line number 21 is detected" "No,Yes"
|
|
bitfld.long 0x00 20. " IRQ_20 ,Interrupt on line number 20 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQ_19 ,Interrupt on line number 19 is detected" "No,Yes"
|
|
bitfld.long 0x00 18. " IRQ_18 ,Interrupt on line number 18 is detected" "No,Yes"
|
|
bitfld.long 0x00 17. " IRQ_17 ,Interrupt on line number 17 is detected" "No,Yes"
|
|
bitfld.long 0x00 16. " IRQ_16 ,Interrupt on line number 16 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQ_15 ,Interrupt on line number 15 is detected" "No,Yes"
|
|
bitfld.long 0x00 14. " IRQ_14 ,Interrupt on line number 14 is detected" "No,Yes"
|
|
bitfld.long 0x00 13. " IRQ_13 ,Interrupt on line number 13 is detected" "No,Yes"
|
|
bitfld.long 0x00 12. " IRQ_12 ,Interrupt on line number 12 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQ_11 ,Interrupt on line number 11 is detected" "No,Yes"
|
|
bitfld.long 0x00 10. " IRQ_10 ,Interrupt on line number 10 is detected" "No,Yes"
|
|
bitfld.long 0x00 9. " IRQ_9 ,Interrupt on line number 9 is detected" "No,Yes"
|
|
bitfld.long 0x00 8. " IRQ_8 ,Interrupt on line number 8 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_7 ,Interrupt on line number 7 is detected" "No,Yes"
|
|
bitfld.long 0x00 6. " IRQ_6 ,Interrupt on line number 6 is detected" "No,Yes"
|
|
bitfld.long 0x00 5. " IRQ_5 ,Interrupt on line number 5 is detected" "No,Yes"
|
|
bitfld.long 0x00 4. " IRQ_4 ,Interrupt on line number 4 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQ_3 ,Interrupt on line number 3 is detected" "No,Yes"
|
|
bitfld.long 0x00 2. " IRQ_2 ,Interrupt on line number 2 is detected" "No,Yes"
|
|
bitfld.long 0x00 1. " IRQ_1 ,Interrupt on line number 1 is detected" "No,Yes"
|
|
bitfld.long 0x00 0. " IRQ_0 ,Interrupt on line number 0 is detected" "No,Yes"
|
|
line.long 0x04 "MPU_L2_MIR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " MIR_31 ,Mask interrupt on line number 31" "No mask,Mask"
|
|
bitfld.long 0x04 30. " MIR_30 ,Mask interrupt on line number 30" "No mask,Mask"
|
|
bitfld.long 0x04 29. " MIR_29 ,Mask interrupt on line number 29" "No mask,Mask"
|
|
bitfld.long 0x04 28. " MIR_28 ,Mask interrupt on line number 28" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MIR_27 ,Mask interrupt on line number 27" "No mask,Mask"
|
|
bitfld.long 0x04 26. " MIR_26 ,Mask interrupt on line number 26" "No mask,Mask"
|
|
bitfld.long 0x04 25. " MIR_25 ,Mask interrupt on line number 25" "No mask,Mask"
|
|
bitfld.long 0x04 24. " MIR_24 ,Mask interrupt on line number 24" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MIR_23 ,Mask interrupt on line number 23" "No mask,Mask"
|
|
bitfld.long 0x04 22. " MIR_22 ,Mask interrupt on line number 22" "No mask,Mask"
|
|
bitfld.long 0x04 21. " MIR_21 ,Mask interrupt on line number 21" "No mask,Mask"
|
|
bitfld.long 0x04 20. " MIR_20 ,Mask interrupt on line number 20" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MIR_19 ,Mask interrupt on line number 19" "No mask,Mask"
|
|
bitfld.long 0x04 18. " MIR_18 ,Mask interrupt on line number 18" "No mask,Mask"
|
|
bitfld.long 0x04 17. " MIR_17 ,Mask interrupt on line number 17" "No mask,Mask"
|
|
bitfld.long 0x04 16. " MIR_16 ,Mask interrupt on line number 16" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MIR_15 ,Mask interrupt on line number 15" "No mask,Mask"
|
|
bitfld.long 0x04 14. " MIR_14 ,Mask interrupt on line number 14" "No mask,Mask"
|
|
bitfld.long 0x04 13. " MIR_13 ,Mask interrupt on line number 13" "No mask,Mask"
|
|
bitfld.long 0x04 12. " MIR_12 ,Mask interrupt on line number 12" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MIR_11 ,Mask interrupt on line number 11" "No mask,Mask"
|
|
bitfld.long 0x04 10. " MIR_10 ,Mask interrupt on line number 10" "No mask,Mask"
|
|
bitfld.long 0x04 9. " MIR_9 ,Mask interrupt on line number 9" "No mask,Mask"
|
|
bitfld.long 0x04 8. " MIR_8 ,Mask interrupt on line number 8" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MIR_7 ,Mask interrupt on line number 7" "No mask,Mask"
|
|
bitfld.long 0x04 6. " MIR_6 ,Mask interrupt on line number 6" "No mask,Mask"
|
|
bitfld.long 0x04 5. " MIR_5 ,Mask interrupt on line number 5" "No mask,Mask"
|
|
bitfld.long 0x04 4. " MIR_4 ,Mask interrupt on line number 4" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MIR_3 ,Mask interrupt on line number 3" "No mask,Mask"
|
|
bitfld.long 0x04 2. " MIR_2 ,Mask interrupt on line number 2" "No mask,Mask"
|
|
bitfld.long 0x04 1. " MIR_1 ,Mask interrupt on line number 1" "No mask,Mask"
|
|
bitfld.long 0x04 0. " MIR_0 ,Mask interrupt on line number 0" "No mask,Mask"
|
|
rgroup 0x0010++0x7
|
|
line.long 0x00 "MPU_L2_SIR_IRQ,Interrupt Encoded Source (IRQ) Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IRQ ,Active IRQ number"
|
|
line.long 0x04 "MPU_L2_SIR_FIQ,Interrupt Encoded Source (FIQ) Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FIQ ,Active FIQ number"
|
|
group 0x0018++0x83
|
|
line.long 0x00 "MPU_L2_CONTROL,Interrupt Control Register"
|
|
bitfld.long 0x00 3. " GLOBAL_MASK " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_FIQ_AGR " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_IRQ_AGR " "Disabled,Enabled"
|
|
line.long 0x04 "MPU_L2_ILR0,Interrupt Priority Level For IRQ 0 Register"
|
|
hexmask.long.byte 0x04 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x04 1. " SENS_0EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x04 0. " FIQ_0IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x08 "MPU_L2_ILR1,Interrupt Priority Level For IRQ 1 Register"
|
|
hexmask.long.byte 0x08 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x08 1. " SENS_1EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x08 0. " FIQ_1IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x0c "MPU_L2_ILR2,Interrupt Priority Level For IRQ 2 Register"
|
|
hexmask.long.byte 0x0c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x0c 1. " SENS_2EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x0c 0. " FIQ_2IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x10 "MPU_L2_ILR3,Interrupt Priority Level For IRQ 3 Register"
|
|
hexmask.long.byte 0x10 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x10 1. " SENS_3EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x10 0. " FIQ_3IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x14 "MPU_L2_ILR4,Interrupt Priority Level For IRQ 4 Register"
|
|
hexmask.long.byte 0x14 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x14 1. " SENS_4EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x14 0. " FIQ_4IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x18 "MPU_L2_ILR5,Interrupt Priority Level For IRQ 5 Register"
|
|
hexmask.long.byte 0x18 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x18 1. " SENS_5EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x18 0. " FIQ_5IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x1c "MPU_L2_ILR6,Interrupt Priority Level For IRQ 6 Register"
|
|
hexmask.long.byte 0x1c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x1c 1. " SENS_6EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x1c 0. " FIQ_6IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x20 "MPU_L2_ILR7,Interrupt Priority Level For IRQ 7 Register"
|
|
hexmask.long.byte 0x20 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x20 1. " SENS_7EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x20 0. " FIQ_7IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x24 "MPU_L2_ILR8,Interrupt Priority Level For IRQ 8 Register"
|
|
hexmask.long.byte 0x24 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x24 1. " SENS_8EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x24 0. " FIQ_8IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x28 "MPU_L2_ILR9,Interrupt Priority Level For IRQ 9 Register"
|
|
hexmask.long.byte 0x28 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x28 1. " SENS_9EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x28 0. " FIQ_9IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x2c "MPU_L2_ILR10,Interrupt Priority Level For IRQ 10 Register"
|
|
hexmask.long.byte 0x2c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x2c 1. " SENS_10EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x2c 0. " FIQ_10IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x30 "MPU_L2_ILR11,Interrupt Priority Level For IRQ 11 Register"
|
|
hexmask.long.byte 0x30 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x30 1. " SENS_11EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x30 0. " FIQ_11IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x34 "MPU_L2_ILR12,Interrupt Priority Level For IRQ 12 Register"
|
|
hexmask.long.byte 0x34 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x34 1. " SENS_12EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x34 0. " FIQ_12IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x38 "MPU_L2_ILR13,Interrupt Priority Level For IRQ 13 Register"
|
|
hexmask.long.byte 0x38 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x38 1. " SENS_13EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x38 0. " FIQ_13IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x3c "MPU_L2_ILR14,Interrupt Priority Level For IRQ 14 Register"
|
|
hexmask.long.byte 0x3c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x3c 1. " SENS_14EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x3c 0. " FIQ_14IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x40 "MPU_L2_ILR15,Interrupt Priority Level For IRQ 15 Register"
|
|
hexmask.long.byte 0x40 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x40 1. " SENS_15EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x40 0. " FIQ_15IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x44 "MPU_L2_ILR16,Interrupt Priority Level For IRQ 16 Register"
|
|
hexmask.long.byte 0x44 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x44 1. " SENS_16EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x44 0. " FIQ_16IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x48 "MPU_L2_ILR17,Interrupt Priority Level For IRQ 17 Register"
|
|
hexmask.long.byte 0x48 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x48 1. " SENS_17EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x48 0. " FIQ_17IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x4c "MPU_L2_ILR18,Interrupt Priority Level For IRQ 18 Register"
|
|
hexmask.long.byte 0x4c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x4c 1. " SENS_18EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x4c 0. " FIQ_18IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x50 "MPU_L2_ILR19,Interrupt Priority Level For IRQ 19 Register"
|
|
hexmask.long.byte 0x50 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x50 1. " SENS_19EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x50 0. " FIQ_19IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x54 "MPU_L2_ILR20,Interrupt Priority Level For IRQ 20 Register"
|
|
hexmask.long.byte 0x54 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x54 1. " SENS_20EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x54 0. " FIQ_20IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x58 "MPU_L2_ILR21,Interrupt Priority Level For IRQ 21 Register"
|
|
hexmask.long.byte 0x58 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x58 1. " SENS_21EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x58 0. " FIQ_21IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x5c "MPU_L2_ILR22,Interrupt Priority Level For IRQ 22 Register"
|
|
hexmask.long.byte 0x5c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x5c 1. " SENS_22EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x5c 0. " FIQ_22IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x60 "MPU_L2_ILR23,Interrupt Priority Level For IRQ 23 Register"
|
|
hexmask.long.byte 0x60 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x60 1. " SENS_23EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x60 0. " FIQ_23IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x64 "MPU_L2_ILR24,Interrupt Priority Level For IRQ 24 Register"
|
|
hexmask.long.byte 0x64 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x64 1. " SENS_24EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x64 0. " FIQ_24IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x68 "MPU_L2_ILR25,Interrupt Priority Level For IRQ 25 Register"
|
|
hexmask.long.byte 0x68 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x68 1. " SENS_25EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x68 0. " FIQ_25IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x6c "MPU_L2_ILR26,Interrupt Priority Level For IRQ 26 Register"
|
|
hexmask.long.byte 0x6c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x6c 1. " SENS_26EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x6c 0. " FIQ_26IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x70 "MPU_L2_ILR27,Interrupt Priority Level For IRQ 27 Register"
|
|
hexmask.long.byte 0x70 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x70 1. " SENS_27EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x70 0. " FIQ_27IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x74 "MPU_L2_ILR28,Interrupt Priority Level For IRQ 28 Register"
|
|
hexmask.long.byte 0x74 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x74 1. " SENS_28EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x74 0. " FIQ_28IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x78 "MPU_L2_ILR29,Interrupt Priority Level For IRQ 29 Register"
|
|
hexmask.long.byte 0x78 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x78 1. " SENS_29EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x78 0. " FIQ_29IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x7c "MPU_L2_ILR30,Interrupt Priority Level For IRQ 30 Register"
|
|
hexmask.long.byte 0x7c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x7c 1. " SENS_30EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x7c 0. " FIQ_30IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x80 "MPU_L2_ILR31,Interrupt Priority Level For IRQ 31 Register"
|
|
hexmask.long.byte 0x80 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x80 1. " SENS_31EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x80 0. " FIQ_31IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
wgroup 0x009C++0x3
|
|
line.long 0x00 "MPU_L2_ISR,Software Interrupt Set Register"
|
|
bitfld.long 0x00 31. " SISR_31 ,Generate interrupt on line number 31" "Do not,Do"
|
|
bitfld.long 0x00 30. " SISR_30 ,Generate interrupt on line number 30" "Do not,Do"
|
|
bitfld.long 0x00 29. " SISR_29 ,Generate interrupt on line number 29" "Do not,Do"
|
|
bitfld.long 0x00 28. " SISR_28 ,Generate interrupt on line number 28" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SISR_27 ,Generate interrupt on line number 27" "Do not,Do"
|
|
bitfld.long 0x00 26. " SISR_26 ,Generate interrupt on line number 26" "Do not,Do"
|
|
bitfld.long 0x00 25. " SISR_25 ,Generate interrupt on line number 25" "Do not,Do"
|
|
bitfld.long 0x00 24. " SISR_24 ,Generate interrupt on line number 24" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SISR_23 ,Generate interrupt on line number 23" "Do not,Do"
|
|
bitfld.long 0x00 22. " SISR_22 ,Generate interrupt on line number 22" "Do not,Do"
|
|
bitfld.long 0x00 21. " SISR_21 ,Generate interrupt on line number 21" "Do not,Do"
|
|
bitfld.long 0x00 20. " SISR_20 ,Generate interrupt on line number 20" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SISR_19 ,Generate interrupt on line number 19" "Do not,Do"
|
|
bitfld.long 0x00 18. " SISR_18 ,Generate interrupt on line number 18" "Do not,Do"
|
|
bitfld.long 0x00 17. " SISR_17 ,Generate interrupt on line number 17" "Do not,Do"
|
|
bitfld.long 0x00 16. " SISR_16 ,Generate interrupt on line number 16" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SISR_15 ,Generate interrupt on line number 15" "Do not,Do"
|
|
bitfld.long 0x00 14. " SISR_14 ,Generate interrupt on line number 14" "Do not,Do"
|
|
bitfld.long 0x00 13. " SISR_13 ,Generate interrupt on line number 13" "Do not,Do"
|
|
bitfld.long 0x00 12. " SISR_12 ,Generate interrupt on line number 12" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SISR_11 ,Generate interrupt on line number 11" "Do not,Do"
|
|
bitfld.long 0x00 10. " SISR_10 ,Generate interrupt on line number 10" "Do not,Do"
|
|
bitfld.long 0x00 9. " SISR_9 ,Generate interrupt on line number 9" "Do not,Do"
|
|
bitfld.long 0x00 8. " SISR_8 ,Generate interrupt on line number 8" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SISR_7 ,Generate interrupt on line number 7" "Do not,Do"
|
|
bitfld.long 0x00 6. " SISR_6 ,Generate interrupt on line number 6" "Do not,Do"
|
|
bitfld.long 0x00 5. " SISR_5 ,Generate interrupt on line number 5" "Do not,Do"
|
|
bitfld.long 0x00 4. " SISR_4 ,Generate interrupt on line number 4" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SISR_3 ,Generate interrupt on line number 3" "Do not,Do"
|
|
bitfld.long 0x00 2. " SISR_2 ,Generate interrupt on line number 2" "Do not,Do"
|
|
bitfld.long 0x00 1. " SISR_1 ,Generate interrupt on line number 1" "Do not,Do"
|
|
bitfld.long 0x00 0. " SISR_0 ,Generate interrupt on line number 0" "Do not,Do"
|
|
rgroup 0x00A0++0x3
|
|
line.long 0x00 "MPU_L2_STATUS,Status Register"
|
|
bitfld.long 0x00 0. " RESET_DONE ,A reset has occured" "No reset,Reset"
|
|
group 0x00A4++0x3
|
|
line.long 0x00 "MPU_L2_OCP_CFG,OCP Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ," "Force wake-up,Reserved,Smart idle,?..."
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Generate a soft reset of the module" "Do not,Do"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internat OCP clock gating strategy" "Free running,OCP interface"
|
|
rgroup 0x00A8++0x3
|
|
line.long 0x00 "MPU_L2_INTH_REV,Interrupt Controller Revision ID"
|
|
hexfld.byte 0x00 " REV ,Revision number"
|
|
tree.end
|
|
; --------------------------------------------------------------------------------
|
|
tree "BANK 2"
|
|
base AD:0xFFFE0200
|
|
group 0x0000++0x7
|
|
line.long 0x00 "MPU_L2_ITR,Interrupt Register"
|
|
bitfld.long 0x00 31. " IRQ_31 ,Interrupt on line number 31 is detected" "No,Yes"
|
|
bitfld.long 0x00 30. " IRQ_30 ,Interrupt on line number 30 is detected" "No,Yes"
|
|
bitfld.long 0x00 29. " IRQ_29 ,Interrupt on line number 29 is detected" "No,Yes"
|
|
bitfld.long 0x00 28. " IRQ_28 ,Interrupt on line number 28 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQ_27 ,Interrupt on line number 27 is detected" "No,Yes"
|
|
bitfld.long 0x00 26. " IRQ_26 ,Interrupt on line number 26 is detected" "No,Yes"
|
|
bitfld.long 0x00 25. " IRQ_25 ,Interrupt on line number 25 is detected" "No,Yes"
|
|
bitfld.long 0x00 24. " IRQ_24 ,Interrupt on line number 24 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQ_23 ,Interrupt on line number 23 is detected" "No,Yes"
|
|
bitfld.long 0x00 22. " IRQ_22 ,Interrupt on line number 22 is detected" "No,Yes"
|
|
bitfld.long 0x00 21. " IRQ_21 ,Interrupt on line number 21 is detected" "No,Yes"
|
|
bitfld.long 0x00 20. " IRQ_20 ,Interrupt on line number 20 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQ_19 ,Interrupt on line number 19 is detected" "No,Yes"
|
|
bitfld.long 0x00 18. " IRQ_18 ,Interrupt on line number 18 is detected" "No,Yes"
|
|
bitfld.long 0x00 17. " IRQ_17 ,Interrupt on line number 17 is detected" "No,Yes"
|
|
bitfld.long 0x00 16. " IRQ_16 ,Interrupt on line number 16 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQ_15 ,Interrupt on line number 15 is detected" "No,Yes"
|
|
bitfld.long 0x00 14. " IRQ_14 ,Interrupt on line number 14 is detected" "No,Yes"
|
|
bitfld.long 0x00 13. " IRQ_13 ,Interrupt on line number 13 is detected" "No,Yes"
|
|
bitfld.long 0x00 12. " IRQ_12 ,Interrupt on line number 12 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQ_11 ,Interrupt on line number 11 is detected" "No,Yes"
|
|
bitfld.long 0x00 10. " IRQ_10 ,Interrupt on line number 10 is detected" "No,Yes"
|
|
bitfld.long 0x00 9. " IRQ_9 ,Interrupt on line number 9 is detected" "No,Yes"
|
|
bitfld.long 0x00 8. " IRQ_8 ,Interrupt on line number 8 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_7 ,Interrupt on line number 7 is detected" "No,Yes"
|
|
bitfld.long 0x00 6. " IRQ_6 ,Interrupt on line number 6 is detected" "No,Yes"
|
|
bitfld.long 0x00 5. " IRQ_5 ,Interrupt on line number 5 is detected" "No,Yes"
|
|
bitfld.long 0x00 4. " IRQ_4 ,Interrupt on line number 4 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQ_3 ,Interrupt on line number 3 is detected" "No,Yes"
|
|
bitfld.long 0x00 2. " IRQ_2 ,Interrupt on line number 2 is detected" "No,Yes"
|
|
bitfld.long 0x00 1. " IRQ_1 ,Interrupt on line number 1 is detected" "No,Yes"
|
|
bitfld.long 0x00 0. " IRQ_0 ,Interrupt on line number 0 is detected" "No,Yes"
|
|
line.long 0x04 "MPU_L2_MIR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " MIR_31 ,Mask interrupt on line number 31" "No mask,Mask"
|
|
bitfld.long 0x04 30. " MIR_30 ,Mask interrupt on line number 30" "No mask,Mask"
|
|
bitfld.long 0x04 29. " MIR_29 ,Mask interrupt on line number 29" "No mask,Mask"
|
|
bitfld.long 0x04 28. " MIR_28 ,Mask interrupt on line number 28" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MIR_27 ,Mask interrupt on line number 27" "No mask,Mask"
|
|
bitfld.long 0x04 26. " MIR_26 ,Mask interrupt on line number 26" "No mask,Mask"
|
|
bitfld.long 0x04 25. " MIR_25 ,Mask interrupt on line number 25" "No mask,Mask"
|
|
bitfld.long 0x04 24. " MIR_24 ,Mask interrupt on line number 24" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MIR_23 ,Mask interrupt on line number 23" "No mask,Mask"
|
|
bitfld.long 0x04 22. " MIR_22 ,Mask interrupt on line number 22" "No mask,Mask"
|
|
bitfld.long 0x04 21. " MIR_21 ,Mask interrupt on line number 21" "No mask,Mask"
|
|
bitfld.long 0x04 20. " MIR_20 ,Mask interrupt on line number 20" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MIR_19 ,Mask interrupt on line number 19" "No mask,Mask"
|
|
bitfld.long 0x04 18. " MIR_18 ,Mask interrupt on line number 18" "No mask,Mask"
|
|
bitfld.long 0x04 17. " MIR_17 ,Mask interrupt on line number 17" "No mask,Mask"
|
|
bitfld.long 0x04 16. " MIR_16 ,Mask interrupt on line number 16" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MIR_15 ,Mask interrupt on line number 15" "No mask,Mask"
|
|
bitfld.long 0x04 14. " MIR_14 ,Mask interrupt on line number 14" "No mask,Mask"
|
|
bitfld.long 0x04 13. " MIR_13 ,Mask interrupt on line number 13" "No mask,Mask"
|
|
bitfld.long 0x04 12. " MIR_12 ,Mask interrupt on line number 12" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MIR_11 ,Mask interrupt on line number 11" "No mask,Mask"
|
|
bitfld.long 0x04 10. " MIR_10 ,Mask interrupt on line number 10" "No mask,Mask"
|
|
bitfld.long 0x04 9. " MIR_9 ,Mask interrupt on line number 9" "No mask,Mask"
|
|
bitfld.long 0x04 8. " MIR_8 ,Mask interrupt on line number 8" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MIR_7 ,Mask interrupt on line number 7" "No mask,Mask"
|
|
bitfld.long 0x04 6. " MIR_6 ,Mask interrupt on line number 6" "No mask,Mask"
|
|
bitfld.long 0x04 5. " MIR_5 ,Mask interrupt on line number 5" "No mask,Mask"
|
|
bitfld.long 0x04 4. " MIR_4 ,Mask interrupt on line number 4" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MIR_3 ,Mask interrupt on line number 3" "No mask,Mask"
|
|
bitfld.long 0x04 2. " MIR_2 ,Mask interrupt on line number 2" "No mask,Mask"
|
|
bitfld.long 0x04 1. " MIR_1 ,Mask interrupt on line number 1" "No mask,Mask"
|
|
bitfld.long 0x04 0. " MIR_0 ,Mask interrupt on line number 0" "No mask,Mask"
|
|
rgroup 0x0010++0x7
|
|
line.long 0x00 "MPU_L2_SIR_IRQ,Interrupt Encoded Source (IRQ) Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IRQ ,Active IRQ number"
|
|
line.long 0x04 "MPU_L2_SIR_FIQ,Interrupt Encoded Source (FIQ) Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FIQ ,Active FIQ number"
|
|
group 0x0018++0x83
|
|
line.long 0x00 "MPU_L2_CONTROL,Interrupt Control Register"
|
|
bitfld.long 0x00 3. " GLOBAL_MASK " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_FIQ_AGR " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_IRQ_AGR " "Disabled,Enabled"
|
|
line.long 0x04 "MPU_L2_ILR0,Interrupt Priority Level For IRQ 0 Register"
|
|
hexmask.long.byte 0x04 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x04 1. " SENS_0EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x04 0. " FIQ_0IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x08 "MPU_L2_ILR1,Interrupt Priority Level For IRQ 1 Register"
|
|
hexmask.long.byte 0x08 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x08 1. " SENS_1EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x08 0. " FIQ_1IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x0c "MPU_L2_ILR2,Interrupt Priority Level For IRQ 2 Register"
|
|
hexmask.long.byte 0x0c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x0c 1. " SENS_2EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x0c 0. " FIQ_2IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x10 "MPU_L2_ILR3,Interrupt Priority Level For IRQ 3 Register"
|
|
hexmask.long.byte 0x10 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x10 1. " SENS_3EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x10 0. " FIQ_3IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x14 "MPU_L2_ILR4,Interrupt Priority Level For IRQ 4 Register"
|
|
hexmask.long.byte 0x14 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x14 1. " SENS_4EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x14 0. " FIQ_4IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x18 "MPU_L2_ILR5,Interrupt Priority Level For IRQ 5 Register"
|
|
hexmask.long.byte 0x18 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x18 1. " SENS_5EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x18 0. " FIQ_5IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x1c "MPU_L2_ILR6,Interrupt Priority Level For IRQ 6 Register"
|
|
hexmask.long.byte 0x1c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x1c 1. " SENS_6EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x1c 0. " FIQ_6IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x20 "MPU_L2_ILR7,Interrupt Priority Level For IRQ 7 Register"
|
|
hexmask.long.byte 0x20 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x20 1. " SENS_7EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x20 0. " FIQ_7IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x24 "MPU_L2_ILR8,Interrupt Priority Level For IRQ 8 Register"
|
|
hexmask.long.byte 0x24 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x24 1. " SENS_8EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x24 0. " FIQ_8IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x28 "MPU_L2_ILR9,Interrupt Priority Level For IRQ 9 Register"
|
|
hexmask.long.byte 0x28 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x28 1. " SENS_9EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x28 0. " FIQ_9IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x2c "MPU_L2_ILR10,Interrupt Priority Level For IRQ 10 Register"
|
|
hexmask.long.byte 0x2c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x2c 1. " SENS_10EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x2c 0. " FIQ_10IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x30 "MPU_L2_ILR11,Interrupt Priority Level For IRQ 11 Register"
|
|
hexmask.long.byte 0x30 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x30 1. " SENS_11EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x30 0. " FIQ_11IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x34 "MPU_L2_ILR12,Interrupt Priority Level For IRQ 12 Register"
|
|
hexmask.long.byte 0x34 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x34 1. " SENS_12EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x34 0. " FIQ_12IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x38 "MPU_L2_ILR13,Interrupt Priority Level For IRQ 13 Register"
|
|
hexmask.long.byte 0x38 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x38 1. " SENS_13EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x38 0. " FIQ_13IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x3c "MPU_L2_ILR14,Interrupt Priority Level For IRQ 14 Register"
|
|
hexmask.long.byte 0x3c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x3c 1. " SENS_14EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x3c 0. " FIQ_14IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x40 "MPU_L2_ILR15,Interrupt Priority Level For IRQ 15 Register"
|
|
hexmask.long.byte 0x40 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x40 1. " SENS_15EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x40 0. " FIQ_15IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x44 "MPU_L2_ILR16,Interrupt Priority Level For IRQ 16 Register"
|
|
hexmask.long.byte 0x44 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x44 1. " SENS_16EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x44 0. " FIQ_16IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x48 "MPU_L2_ILR17,Interrupt Priority Level For IRQ 17 Register"
|
|
hexmask.long.byte 0x48 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x48 1. " SENS_17EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x48 0. " FIQ_17IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x4c "MPU_L2_ILR18,Interrupt Priority Level For IRQ 18 Register"
|
|
hexmask.long.byte 0x4c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x4c 1. " SENS_18EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x4c 0. " FIQ_18IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x50 "MPU_L2_ILR19,Interrupt Priority Level For IRQ 19 Register"
|
|
hexmask.long.byte 0x50 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x50 1. " SENS_19EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x50 0. " FIQ_19IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x54 "MPU_L2_ILR20,Interrupt Priority Level For IRQ 20 Register"
|
|
hexmask.long.byte 0x54 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x54 1. " SENS_20EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x54 0. " FIQ_20IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x58 "MPU_L2_ILR21,Interrupt Priority Level For IRQ 21 Register"
|
|
hexmask.long.byte 0x58 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x58 1. " SENS_21EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x58 0. " FIQ_21IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x5c "MPU_L2_ILR22,Interrupt Priority Level For IRQ 22 Register"
|
|
hexmask.long.byte 0x5c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x5c 1. " SENS_22EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x5c 0. " FIQ_22IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x60 "MPU_L2_ILR23,Interrupt Priority Level For IRQ 23 Register"
|
|
hexmask.long.byte 0x60 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x60 1. " SENS_23EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x60 0. " FIQ_23IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x64 "MPU_L2_ILR24,Interrupt Priority Level For IRQ 24 Register"
|
|
hexmask.long.byte 0x64 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x64 1. " SENS_24EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x64 0. " FIQ_24IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x68 "MPU_L2_ILR25,Interrupt Priority Level For IRQ 25 Register"
|
|
hexmask.long.byte 0x68 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x68 1. " SENS_25EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x68 0. " FIQ_25IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x6c "MPU_L2_ILR26,Interrupt Priority Level For IRQ 26 Register"
|
|
hexmask.long.byte 0x6c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x6c 1. " SENS_26EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x6c 0. " FIQ_26IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x70 "MPU_L2_ILR27,Interrupt Priority Level For IRQ 27 Register"
|
|
hexmask.long.byte 0x70 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x70 1. " SENS_27EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x70 0. " FIQ_27IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x74 "MPU_L2_ILR28,Interrupt Priority Level For IRQ 28 Register"
|
|
hexmask.long.byte 0x74 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x74 1. " SENS_28EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x74 0. " FIQ_28IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x78 "MPU_L2_ILR29,Interrupt Priority Level For IRQ 29 Register"
|
|
hexmask.long.byte 0x78 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x78 1. " SENS_29EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x78 0. " FIQ_29IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x7c "MPU_L2_ILR30,Interrupt Priority Level For IRQ 30 Register"
|
|
hexmask.long.byte 0x7c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x7c 1. " SENS_30EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x7c 0. " FIQ_30IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x80 "MPU_L2_ILR31,Interrupt Priority Level For IRQ 31 Register"
|
|
hexmask.long.byte 0x80 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x80 1. " SENS_31EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x80 0. " FIQ_31IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
wgroup 0x009C++0x3
|
|
line.long 0x00 "MPU_L2_ISR,Software Interrupt Set Register"
|
|
bitfld.long 0x00 31. " SISR_31 ,Generate interrupt on line number 31" "Do not,Do"
|
|
bitfld.long 0x00 30. " SISR_30 ,Generate interrupt on line number 30" "Do not,Do"
|
|
bitfld.long 0x00 29. " SISR_29 ,Generate interrupt on line number 29" "Do not,Do"
|
|
bitfld.long 0x00 28. " SISR_28 ,Generate interrupt on line number 28" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SISR_27 ,Generate interrupt on line number 27" "Do not,Do"
|
|
bitfld.long 0x00 26. " SISR_26 ,Generate interrupt on line number 26" "Do not,Do"
|
|
bitfld.long 0x00 25. " SISR_25 ,Generate interrupt on line number 25" "Do not,Do"
|
|
bitfld.long 0x00 24. " SISR_24 ,Generate interrupt on line number 24" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SISR_23 ,Generate interrupt on line number 23" "Do not,Do"
|
|
bitfld.long 0x00 22. " SISR_22 ,Generate interrupt on line number 22" "Do not,Do"
|
|
bitfld.long 0x00 21. " SISR_21 ,Generate interrupt on line number 21" "Do not,Do"
|
|
bitfld.long 0x00 20. " SISR_20 ,Generate interrupt on line number 20" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SISR_19 ,Generate interrupt on line number 19" "Do not,Do"
|
|
bitfld.long 0x00 18. " SISR_18 ,Generate interrupt on line number 18" "Do not,Do"
|
|
bitfld.long 0x00 17. " SISR_17 ,Generate interrupt on line number 17" "Do not,Do"
|
|
bitfld.long 0x00 16. " SISR_16 ,Generate interrupt on line number 16" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SISR_15 ,Generate interrupt on line number 15" "Do not,Do"
|
|
bitfld.long 0x00 14. " SISR_14 ,Generate interrupt on line number 14" "Do not,Do"
|
|
bitfld.long 0x00 13. " SISR_13 ,Generate interrupt on line number 13" "Do not,Do"
|
|
bitfld.long 0x00 12. " SISR_12 ,Generate interrupt on line number 12" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SISR_11 ,Generate interrupt on line number 11" "Do not,Do"
|
|
bitfld.long 0x00 10. " SISR_10 ,Generate interrupt on line number 10" "Do not,Do"
|
|
bitfld.long 0x00 9. " SISR_9 ,Generate interrupt on line number 9" "Do not,Do"
|
|
bitfld.long 0x00 8. " SISR_8 ,Generate interrupt on line number 8" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SISR_7 ,Generate interrupt on line number 7" "Do not,Do"
|
|
bitfld.long 0x00 6. " SISR_6 ,Generate interrupt on line number 6" "Do not,Do"
|
|
bitfld.long 0x00 5. " SISR_5 ,Generate interrupt on line number 5" "Do not,Do"
|
|
bitfld.long 0x00 4. " SISR_4 ,Generate interrupt on line number 4" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SISR_3 ,Generate interrupt on line number 3" "Do not,Do"
|
|
bitfld.long 0x00 2. " SISR_2 ,Generate interrupt on line number 2" "Do not,Do"
|
|
bitfld.long 0x00 1. " SISR_1 ,Generate interrupt on line number 1" "Do not,Do"
|
|
bitfld.long 0x00 0. " SISR_0 ,Generate interrupt on line number 0" "Do not,Do"
|
|
rgroup 0x00A0++0x3
|
|
line.long 0x00 "MPU_L2_STATUS,Status Register"
|
|
bitfld.long 0x00 0. " RESET_DONE ,A reset has occured" "No reset,Reset"
|
|
group 0x00A4++0x3
|
|
line.long 0x00 "MPU_L2_OCP_CFG,OCP Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ," "Force wake-up,Reserved,Smart idle,?..."
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Generate a soft reset of the module" "Do not,Do"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internat OCP clock gating strategy" "Free running,OCP interface"
|
|
rgroup 0x00A8++0x3
|
|
line.long 0x00 "MPU_L2_INTH_REV,Interrupt Controller Revision ID"
|
|
hexfld.byte 0x00 " REV ,Revision number"
|
|
tree.end
|
|
; --------------------------------------------------------------------------------
|
|
tree "BANK 3"
|
|
base AD:0xFFFE0300
|
|
group 0x0000++0x7
|
|
line.long 0x00 "MPU_L2_ITR,Interrupt Register"
|
|
bitfld.long 0x00 31. " IRQ_31 ,Interrupt on line number 31 is detected" "No,Yes"
|
|
bitfld.long 0x00 30. " IRQ_30 ,Interrupt on line number 30 is detected" "No,Yes"
|
|
bitfld.long 0x00 29. " IRQ_29 ,Interrupt on line number 29 is detected" "No,Yes"
|
|
bitfld.long 0x00 28. " IRQ_28 ,Interrupt on line number 28 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 27. " IRQ_27 ,Interrupt on line number 27 is detected" "No,Yes"
|
|
bitfld.long 0x00 26. " IRQ_26 ,Interrupt on line number 26 is detected" "No,Yes"
|
|
bitfld.long 0x00 25. " IRQ_25 ,Interrupt on line number 25 is detected" "No,Yes"
|
|
bitfld.long 0x00 24. " IRQ_24 ,Interrupt on line number 24 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 23. " IRQ_23 ,Interrupt on line number 23 is detected" "No,Yes"
|
|
bitfld.long 0x00 22. " IRQ_22 ,Interrupt on line number 22 is detected" "No,Yes"
|
|
bitfld.long 0x00 21. " IRQ_21 ,Interrupt on line number 21 is detected" "No,Yes"
|
|
bitfld.long 0x00 20. " IRQ_20 ,Interrupt on line number 20 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " IRQ_19 ,Interrupt on line number 19 is detected" "No,Yes"
|
|
bitfld.long 0x00 18. " IRQ_18 ,Interrupt on line number 18 is detected" "No,Yes"
|
|
bitfld.long 0x00 17. " IRQ_17 ,Interrupt on line number 17 is detected" "No,Yes"
|
|
bitfld.long 0x00 16. " IRQ_16 ,Interrupt on line number 16 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " IRQ_15 ,Interrupt on line number 15 is detected" "No,Yes"
|
|
bitfld.long 0x00 14. " IRQ_14 ,Interrupt on line number 14 is detected" "No,Yes"
|
|
bitfld.long 0x00 13. " IRQ_13 ,Interrupt on line number 13 is detected" "No,Yes"
|
|
bitfld.long 0x00 12. " IRQ_12 ,Interrupt on line number 12 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IRQ_11 ,Interrupt on line number 11 is detected" "No,Yes"
|
|
bitfld.long 0x00 10. " IRQ_10 ,Interrupt on line number 10 is detected" "No,Yes"
|
|
bitfld.long 0x00 9. " IRQ_9 ,Interrupt on line number 9 is detected" "No,Yes"
|
|
bitfld.long 0x00 8. " IRQ_8 ,Interrupt on line number 8 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQ_7 ,Interrupt on line number 7 is detected" "No,Yes"
|
|
bitfld.long 0x00 6. " IRQ_6 ,Interrupt on line number 6 is detected" "No,Yes"
|
|
bitfld.long 0x00 5. " IRQ_5 ,Interrupt on line number 5 is detected" "No,Yes"
|
|
bitfld.long 0x00 4. " IRQ_4 ,Interrupt on line number 4 is detected" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IRQ_3 ,Interrupt on line number 3 is detected" "No,Yes"
|
|
bitfld.long 0x00 2. " IRQ_2 ,Interrupt on line number 2 is detected" "No,Yes"
|
|
bitfld.long 0x00 1. " IRQ_1 ,Interrupt on line number 1 is detected" "No,Yes"
|
|
bitfld.long 0x00 0. " IRQ_0 ,Interrupt on line number 0 is detected" "No,Yes"
|
|
line.long 0x04 "MPU_L2_MIR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " MIR_31 ,Mask interrupt on line number 31" "No mask,Mask"
|
|
bitfld.long 0x04 30. " MIR_30 ,Mask interrupt on line number 30" "No mask,Mask"
|
|
bitfld.long 0x04 29. " MIR_29 ,Mask interrupt on line number 29" "No mask,Mask"
|
|
bitfld.long 0x04 28. " MIR_28 ,Mask interrupt on line number 28" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MIR_27 ,Mask interrupt on line number 27" "No mask,Mask"
|
|
bitfld.long 0x04 26. " MIR_26 ,Mask interrupt on line number 26" "No mask,Mask"
|
|
bitfld.long 0x04 25. " MIR_25 ,Mask interrupt on line number 25" "No mask,Mask"
|
|
bitfld.long 0x04 24. " MIR_24 ,Mask interrupt on line number 24" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MIR_23 ,Mask interrupt on line number 23" "No mask,Mask"
|
|
bitfld.long 0x04 22. " MIR_22 ,Mask interrupt on line number 22" "No mask,Mask"
|
|
bitfld.long 0x04 21. " MIR_21 ,Mask interrupt on line number 21" "No mask,Mask"
|
|
bitfld.long 0x04 20. " MIR_20 ,Mask interrupt on line number 20" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MIR_19 ,Mask interrupt on line number 19" "No mask,Mask"
|
|
bitfld.long 0x04 18. " MIR_18 ,Mask interrupt on line number 18" "No mask,Mask"
|
|
bitfld.long 0x04 17. " MIR_17 ,Mask interrupt on line number 17" "No mask,Mask"
|
|
bitfld.long 0x04 16. " MIR_16 ,Mask interrupt on line number 16" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MIR_15 ,Mask interrupt on line number 15" "No mask,Mask"
|
|
bitfld.long 0x04 14. " MIR_14 ,Mask interrupt on line number 14" "No mask,Mask"
|
|
bitfld.long 0x04 13. " MIR_13 ,Mask interrupt on line number 13" "No mask,Mask"
|
|
bitfld.long 0x04 12. " MIR_12 ,Mask interrupt on line number 12" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MIR_11 ,Mask interrupt on line number 11" "No mask,Mask"
|
|
bitfld.long 0x04 10. " MIR_10 ,Mask interrupt on line number 10" "No mask,Mask"
|
|
bitfld.long 0x04 9. " MIR_9 ,Mask interrupt on line number 9" "No mask,Mask"
|
|
bitfld.long 0x04 8. " MIR_8 ,Mask interrupt on line number 8" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MIR_7 ,Mask interrupt on line number 7" "No mask,Mask"
|
|
bitfld.long 0x04 6. " MIR_6 ,Mask interrupt on line number 6" "No mask,Mask"
|
|
bitfld.long 0x04 5. " MIR_5 ,Mask interrupt on line number 5" "No mask,Mask"
|
|
bitfld.long 0x04 4. " MIR_4 ,Mask interrupt on line number 4" "No mask,Mask"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MIR_3 ,Mask interrupt on line number 3" "No mask,Mask"
|
|
bitfld.long 0x04 2. " MIR_2 ,Mask interrupt on line number 2" "No mask,Mask"
|
|
bitfld.long 0x04 1. " MIR_1 ,Mask interrupt on line number 1" "No mask,Mask"
|
|
bitfld.long 0x04 0. " MIR_0 ,Mask interrupt on line number 0" "No mask,Mask"
|
|
rgroup 0x0010++0x7
|
|
line.long 0x00 "MPU_L2_SIR_IRQ,Interrupt Encoded Source (IRQ) Register"
|
|
hexmask.long.byte 0x00 0.--6. 1. " IRQ ,Active IRQ number"
|
|
line.long 0x04 "MPU_L2_SIR_FIQ,Interrupt Encoded Source (FIQ) Register"
|
|
hexmask.long.byte 0x04 0.--6. 1. " FIQ ,Active FIQ number"
|
|
group 0x0018++0x83
|
|
line.long 0x00 "MPU_L2_CONTROL,Interrupt Control Register"
|
|
bitfld.long 0x00 3. " GLOBAL_MASK " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_FIQ_AGR " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " NEW_IRQ_AGR " "Disabled,Enabled"
|
|
line.long 0x04 "MPU_L2_ILR0,Interrupt Priority Level For IRQ 0 Register"
|
|
hexmask.long.byte 0x04 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x04 1. " SENS_0EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x04 0. " FIQ_0IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x08 "MPU_L2_ILR1,Interrupt Priority Level For IRQ 1 Register"
|
|
hexmask.long.byte 0x08 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x08 1. " SENS_1EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x08 0. " FIQ_1IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x0c "MPU_L2_ILR2,Interrupt Priority Level For IRQ 2 Register"
|
|
hexmask.long.byte 0x0c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x0c 1. " SENS_2EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x0c 0. " FIQ_2IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x10 "MPU_L2_ILR3,Interrupt Priority Level For IRQ 3 Register"
|
|
hexmask.long.byte 0x10 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x10 1. " SENS_3EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x10 0. " FIQ_3IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x14 "MPU_L2_ILR4,Interrupt Priority Level For IRQ 4 Register"
|
|
hexmask.long.byte 0x14 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x14 1. " SENS_4EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x14 0. " FIQ_4IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x18 "MPU_L2_ILR5,Interrupt Priority Level For IRQ 5 Register"
|
|
hexmask.long.byte 0x18 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x18 1. " SENS_5EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x18 0. " FIQ_5IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x1c "MPU_L2_ILR6,Interrupt Priority Level For IRQ 6 Register"
|
|
hexmask.long.byte 0x1c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x1c 1. " SENS_6EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x1c 0. " FIQ_6IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x20 "MPU_L2_ILR7,Interrupt Priority Level For IRQ 7 Register"
|
|
hexmask.long.byte 0x20 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x20 1. " SENS_7EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x20 0. " FIQ_7IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x24 "MPU_L2_ILR8,Interrupt Priority Level For IRQ 8 Register"
|
|
hexmask.long.byte 0x24 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x24 1. " SENS_8EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x24 0. " FIQ_8IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x28 "MPU_L2_ILR9,Interrupt Priority Level For IRQ 9 Register"
|
|
hexmask.long.byte 0x28 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x28 1. " SENS_9EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x28 0. " FIQ_9IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x2c "MPU_L2_ILR10,Interrupt Priority Level For IRQ 10 Register"
|
|
hexmask.long.byte 0x2c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x2c 1. " SENS_10EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x2c 0. " FIQ_10IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x30 "MPU_L2_ILR11,Interrupt Priority Level For IRQ 11 Register"
|
|
hexmask.long.byte 0x30 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x30 1. " SENS_11EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x30 0. " FIQ_11IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x34 "MPU_L2_ILR12,Interrupt Priority Level For IRQ 12 Register"
|
|
hexmask.long.byte 0x34 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x34 1. " SENS_12EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x34 0. " FIQ_12IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x38 "MPU_L2_ILR13,Interrupt Priority Level For IRQ 13 Register"
|
|
hexmask.long.byte 0x38 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x38 1. " SENS_13EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x38 0. " FIQ_13IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x3c "MPU_L2_ILR14,Interrupt Priority Level For IRQ 14 Register"
|
|
hexmask.long.byte 0x3c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x3c 1. " SENS_14EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x3c 0. " FIQ_14IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x40 "MPU_L2_ILR15,Interrupt Priority Level For IRQ 15 Register"
|
|
hexmask.long.byte 0x40 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x40 1. " SENS_15EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x40 0. " FIQ_15IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x44 "MPU_L2_ILR16,Interrupt Priority Level For IRQ 16 Register"
|
|
hexmask.long.byte 0x44 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x44 1. " SENS_16EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x44 0. " FIQ_16IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x48 "MPU_L2_ILR17,Interrupt Priority Level For IRQ 17 Register"
|
|
hexmask.long.byte 0x48 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x48 1. " SENS_17EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x48 0. " FIQ_17IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x4c "MPU_L2_ILR18,Interrupt Priority Level For IRQ 18 Register"
|
|
hexmask.long.byte 0x4c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x4c 1. " SENS_18EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x4c 0. " FIQ_18IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x50 "MPU_L2_ILR19,Interrupt Priority Level For IRQ 19 Register"
|
|
hexmask.long.byte 0x50 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x50 1. " SENS_19EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x50 0. " FIQ_19IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x54 "MPU_L2_ILR20,Interrupt Priority Level For IRQ 20 Register"
|
|
hexmask.long.byte 0x54 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x54 1. " SENS_20EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x54 0. " FIQ_20IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x58 "MPU_L2_ILR21,Interrupt Priority Level For IRQ 21 Register"
|
|
hexmask.long.byte 0x58 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x58 1. " SENS_21EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x58 0. " FIQ_21IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x5c "MPU_L2_ILR22,Interrupt Priority Level For IRQ 22 Register"
|
|
hexmask.long.byte 0x5c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x5c 1. " SENS_22EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x5c 0. " FIQ_22IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x60 "MPU_L2_ILR23,Interrupt Priority Level For IRQ 23 Register"
|
|
hexmask.long.byte 0x60 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x60 1. " SENS_23EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x60 0. " FIQ_23IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x64 "MPU_L2_ILR24,Interrupt Priority Level For IRQ 24 Register"
|
|
hexmask.long.byte 0x64 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x64 1. " SENS_24EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x64 0. " FIQ_24IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x68 "MPU_L2_ILR25,Interrupt Priority Level For IRQ 25 Register"
|
|
hexmask.long.byte 0x68 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x68 1. " SENS_25EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x68 0. " FIQ_25IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x6c "MPU_L2_ILR26,Interrupt Priority Level For IRQ 26 Register"
|
|
hexmask.long.byte 0x6c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x6c 1. " SENS_26EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x6c 0. " FIQ_26IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x70 "MPU_L2_ILR27,Interrupt Priority Level For IRQ 27 Register"
|
|
hexmask.long.byte 0x70 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x70 1. " SENS_27EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x70 0. " FIQ_27IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x74 "MPU_L2_ILR28,Interrupt Priority Level For IRQ 28 Register"
|
|
hexmask.long.byte 0x74 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x74 1. " SENS_28EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x74 0. " FIQ_28IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x78 "MPU_L2_ILR29,Interrupt Priority Level For IRQ 29 Register"
|
|
hexmask.long.byte 0x78 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x78 1. " SENS_29EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x78 0. " FIQ_29IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x7c "MPU_L2_ILR30,Interrupt Priority Level For IRQ 30 Register"
|
|
hexmask.long.byte 0x7c 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x7c 1. " SENS_30EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x7c 0. " FIQ_30IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
line.long 0x80 "MPU_L2_ILR31,Interrupt Priority Level For IRQ 31 Register"
|
|
hexmask.long.byte 0x80 2.--8. 1. " PRIORITY ,Defines the priority level: 0 - highest; 7F - lowest"
|
|
bitfld.long 0x80 1. " SENS_31EDGE ,Interrupt sensitivity" "Falling-edge,Low-level"
|
|
bitfld.long 0x80 0. " FIQ_31IRQ ,Interrupt routing" "IRQ,FIQ"
|
|
wgroup 0x009C++0x3
|
|
line.long 0x00 "MPU_L2_ISR,Software Interrupt Set Register"
|
|
bitfld.long 0x00 31. " SISR_31 ,Generate interrupt on line number 31" "Do not,Do"
|
|
bitfld.long 0x00 30. " SISR_30 ,Generate interrupt on line number 30" "Do not,Do"
|
|
bitfld.long 0x00 29. " SISR_29 ,Generate interrupt on line number 29" "Do not,Do"
|
|
bitfld.long 0x00 28. " SISR_28 ,Generate interrupt on line number 28" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SISR_27 ,Generate interrupt on line number 27" "Do not,Do"
|
|
bitfld.long 0x00 26. " SISR_26 ,Generate interrupt on line number 26" "Do not,Do"
|
|
bitfld.long 0x00 25. " SISR_25 ,Generate interrupt on line number 25" "Do not,Do"
|
|
bitfld.long 0x00 24. " SISR_24 ,Generate interrupt on line number 24" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 23. " SISR_23 ,Generate interrupt on line number 23" "Do not,Do"
|
|
bitfld.long 0x00 22. " SISR_22 ,Generate interrupt on line number 22" "Do not,Do"
|
|
bitfld.long 0x00 21. " SISR_21 ,Generate interrupt on line number 21" "Do not,Do"
|
|
bitfld.long 0x00 20. " SISR_20 ,Generate interrupt on line number 20" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 19. " SISR_19 ,Generate interrupt on line number 19" "Do not,Do"
|
|
bitfld.long 0x00 18. " SISR_18 ,Generate interrupt on line number 18" "Do not,Do"
|
|
bitfld.long 0x00 17. " SISR_17 ,Generate interrupt on line number 17" "Do not,Do"
|
|
bitfld.long 0x00 16. " SISR_16 ,Generate interrupt on line number 16" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SISR_15 ,Generate interrupt on line number 15" "Do not,Do"
|
|
bitfld.long 0x00 14. " SISR_14 ,Generate interrupt on line number 14" "Do not,Do"
|
|
bitfld.long 0x00 13. " SISR_13 ,Generate interrupt on line number 13" "Do not,Do"
|
|
bitfld.long 0x00 12. " SISR_12 ,Generate interrupt on line number 12" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SISR_11 ,Generate interrupt on line number 11" "Do not,Do"
|
|
bitfld.long 0x00 10. " SISR_10 ,Generate interrupt on line number 10" "Do not,Do"
|
|
bitfld.long 0x00 9. " SISR_9 ,Generate interrupt on line number 9" "Do not,Do"
|
|
bitfld.long 0x00 8. " SISR_8 ,Generate interrupt on line number 8" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 7. " SISR_7 ,Generate interrupt on line number 7" "Do not,Do"
|
|
bitfld.long 0x00 6. " SISR_6 ,Generate interrupt on line number 6" "Do not,Do"
|
|
bitfld.long 0x00 5. " SISR_5 ,Generate interrupt on line number 5" "Do not,Do"
|
|
bitfld.long 0x00 4. " SISR_4 ,Generate interrupt on line number 4" "Do not,Do"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SISR_3 ,Generate interrupt on line number 3" "Do not,Do"
|
|
bitfld.long 0x00 2. " SISR_2 ,Generate interrupt on line number 2" "Do not,Do"
|
|
bitfld.long 0x00 1. " SISR_1 ,Generate interrupt on line number 1" "Do not,Do"
|
|
bitfld.long 0x00 0. " SISR_0 ,Generate interrupt on line number 0" "Do not,Do"
|
|
rgroup 0x00A0++0x3
|
|
line.long 0x00 "MPU_L2_STATUS,Status Register"
|
|
bitfld.long 0x00 0. " RESET_DONE ,A reset has occured" "No reset,Reset"
|
|
group 0x00A4++0x3
|
|
line.long 0x00 "MPU_L2_OCP_CFG,OCP Configuration Register"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ," "Force wake-up,Reserved,Smart idle,?..."
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Generate a soft reset of the module" "Do not,Do"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internat OCP clock gating strategy" "Free running,OCP interface"
|
|
rgroup 0x00A8++0x3
|
|
line.long 0x00 "MPU_L2_INTH_REV,Interrupt Controller Revision ID"
|
|
hexfld.byte 0x00 " REV ,Revision number"
|
|
tree.end
|
|
tree.end
|
|
base AD:0xFFFE3000
|
|
tree "LCDCONV Registers"
|
|
width 19.
|
|
group.byte 0x00--0x1f
|
|
line.byte 0x00 "LCDCONV_R_LOOK_UP,R Look-up Table Register File"
|
|
hexmask.byte 0x00 0.--5. 1. " Line0 ,R Line 0"
|
|
line.byte 0x1 ""
|
|
hexmask.byte 0x1 0.--5. 1. " Line1 ,R Line 1 "
|
|
line.byte 0x2 ""
|
|
hexmask.byte 0x2 0.--5. 1. " Line2 ,R Line 2 "
|
|
line.byte 0x3 ""
|
|
hexmask.byte 0x3 0.--5. 1. " Line3 ,R Line 3 "
|
|
line.byte 0x4 ""
|
|
hexmask.byte 0x4 0.--5. 1. " Line4 ,R Line 4 "
|
|
line.byte 0x5 ""
|
|
hexmask.byte 0x5 0.--5. 1. " Line5 ,R Line 5 "
|
|
line.byte 0x6 ""
|
|
hexmask.byte 0x6 0.--5. 1. " Line6 ,R Line 6 "
|
|
line.byte 0x7 ""
|
|
hexmask.byte 0x7 0.--5. 1. " Line7 ,R Line 7 "
|
|
line.byte 0x8 ""
|
|
hexmask.byte 0x8 0.--5. 1. " Line8 ,R Line 8 "
|
|
line.byte 0x9 ""
|
|
hexmask.byte 0x9 0.--5. 1. " Line9 ,R Line 9 "
|
|
line.byte 0xA ""
|
|
hexmask.byte 0xA 0.--5. 1. " Line10 ,R Line 10"
|
|
line.byte 0xB ""
|
|
hexmask.byte 0xB 0.--5. 1. " Line11 ,R Line 11"
|
|
line.byte 0xC ""
|
|
hexmask.byte 0xC 0.--5. 1. " Line12 ,R Line 12"
|
|
line.byte 0xD ""
|
|
hexmask.byte 0xD 0.--5. 1. " Line13 ,R Line 13"
|
|
line.byte 0xE ""
|
|
hexmask.byte 0xE 0.--5. 1. " Line14 ,R Line 14"
|
|
line.byte 0xF ""
|
|
hexmask.byte 0xF 0.--5. 1. " Line15 ,R Line 15"
|
|
line.byte 0x10 ""
|
|
hexmask.byte 0x10 0.--5. 1. " Line16 ,R Line 16"
|
|
line.byte 0x11 ""
|
|
hexmask.byte 0x11 0.--5. 1. " Line17 ,R Line 17"
|
|
line.byte 0x12 ""
|
|
hexmask.byte 0x12 0.--5. 1. " Line18 ,R Line 18"
|
|
line.byte 0x13 ""
|
|
hexmask.byte 0x13 0.--5. 1. " Line19 ,R Line 19"
|
|
line.byte 0x14 ""
|
|
hexmask.byte 0x14 0.--5. 1. " Line20 ,R Line 20"
|
|
line.byte 0x15 ""
|
|
hexmask.byte 0x15 0.--5. 1. " Line21 ,R Line 21"
|
|
line.byte 0x16 ""
|
|
hexmask.byte 0x16 0.--5. 1. " Line22 ,R Line 22"
|
|
line.byte 0x17 ""
|
|
hexmask.byte 0x17 0.--5. 1. " Line23 ,R Line 23"
|
|
line.byte 0x18 ""
|
|
hexmask.byte 0x18 0.--5. 1. " Line24 ,R Line 24"
|
|
line.byte 0x19 ""
|
|
hexmask.byte 0x19 0.--5. 1. " Line25 ,R Line 25"
|
|
line.byte 0x1A ""
|
|
hexmask.byte 0x1A 0.--5. 1. " Line26 ,R Line 26"
|
|
line.byte 0x1B ""
|
|
hexmask.byte 0x1B 0.--5. 1. " Line27 ,R Line 27"
|
|
line.byte 0x1C ""
|
|
hexmask.byte 0x1C 0.--5. 1. " Line28 ,R Line 28"
|
|
line.byte 0x1D ""
|
|
hexmask.byte 0x1D 0.--5. 1. " Line29 ,R Line 29"
|
|
line.byte 0x1E ""
|
|
hexmask.byte 0x1E 0.--5. 1. " Line30 ,R Line 30"
|
|
line.byte 0x1F ""
|
|
hexmask.byte 0x1F 0.--5. 1. " Line31 ,R Line 31"
|
|
group.byte 0x20--0x3f
|
|
line.byte 0x0 "LCDCONV_B_LOOK_UP,B Look-up Table Register File"
|
|
hexmask.byte 0x0 0.--5. 1. " Line0 ,B Line0"
|
|
line.byte 0x1 ""
|
|
hexmask.byte 0x1 0.--5. 1. " Line1 ,B Line 1 "
|
|
line.byte 0x2 ""
|
|
hexmask.byte 0x2 0.--5. 1. " Line2 ,B Line 2 "
|
|
line.byte 0x3 ""
|
|
hexmask.byte 0x3 0.--5. 1. " Line3 ,B Line 3 "
|
|
line.byte 0x4 ""
|
|
hexmask.byte 0x4 0.--5. 1. " Line4 ,B Line 4 "
|
|
line.byte 0x5 ""
|
|
hexmask.byte 0x5 0.--5. 1. " Line5 ,B Line 5 "
|
|
line.byte 0x6 ""
|
|
hexmask.byte 0x6 0.--5. 1. " Line6 ,B Line 6 "
|
|
line.byte 0x7 ""
|
|
hexmask.byte 0x7 0.--5. 1. " Line7 ,B Line 7 "
|
|
line.byte 0x8 ""
|
|
hexmask.byte 0x8 0.--5. 1. " Line8 ,B Line 8 "
|
|
line.byte 0x9 ""
|
|
hexmask.byte 0x9 0.--5. 1. " Line9 ,B Line 9 "
|
|
line.byte 0xA ""
|
|
hexmask.byte 0xA 0.--5. 1. " Line10 ,B Line 10"
|
|
line.byte 0xB ""
|
|
hexmask.byte 0xB 0.--5. 1. " Line11 ,B Line 11"
|
|
line.byte 0xC ""
|
|
hexmask.byte 0xC 0.--5. 1. " Line12 ,B Line 12"
|
|
line.byte 0xD ""
|
|
hexmask.byte 0xD 0.--5. 1. " Line13 ,B Line 13"
|
|
line.byte 0xE ""
|
|
hexmask.byte 0xE 0.--5. 1. " Line14 ,B Line 14"
|
|
line.byte 0xF ""
|
|
hexmask.byte 0xF 0.--5. 1. " Line15 ,B Line 15"
|
|
line.byte 0x10 ""
|
|
hexmask.byte 0x10 0.--5. 1. " Line16 ,B Line 16"
|
|
line.byte 0x11 ""
|
|
hexmask.byte 0x11 0.--5. 1. " Line17 ,B Line 17"
|
|
line.byte 0x12 ""
|
|
hexmask.byte 0x12 0.--5. 1. " Line18 ,B Line 18"
|
|
line.byte 0x13 ""
|
|
hexmask.byte 0x13 0.--5. 1. " Line19 ,B Line 19"
|
|
line.byte 0x14 ""
|
|
hexmask.byte 0x14 0.--5. 1. " Line20 ,B Line 20"
|
|
line.byte 0x15 ""
|
|
hexmask.byte 0x15 0.--5. 1. " Line21 ,B Line 21"
|
|
line.byte 0x16 ""
|
|
hexmask.byte 0x16 0.--5. 1. " Line22 ,B Line 22"
|
|
line.byte 0x17 ""
|
|
hexmask.byte 0x17 0.--5. 1. " Line23 ,B Line 23"
|
|
line.byte 0x18 ""
|
|
hexmask.byte 0x18 0.--5. 1. " Line24 ,B Line 24"
|
|
line.byte 0x19 ""
|
|
hexmask.byte 0x19 0.--5. 1. " Line25 ,B Line 25"
|
|
line.byte 0x1A ""
|
|
hexmask.byte 0x1A 0.--5. 1. " Line26 ,B Line 26"
|
|
line.byte 0x1B ""
|
|
hexmask.byte 0x1B 0.--5. 1. " Line27 ,B Line 27"
|
|
line.byte 0x1C ""
|
|
hexmask.byte 0x1C 0.--5. 1. " Line28 ,B Line 28"
|
|
line.byte 0x1D ""
|
|
hexmask.byte 0x1D 0.--5. 1. " Line29 ,B Line 29"
|
|
line.byte 0x1E ""
|
|
hexmask.byte 0x1E 0.--5. 1. " Line30 ,B Line 30"
|
|
line.byte 0x1F ""
|
|
hexmask.byte 0x1F 0.--5. 1. " Line31 ,B Line 31"
|
|
group.word 0x40--0x7f
|
|
line.byte 0x0 "LCDCONV_G_LOOK_UP,G Look-up Table Register File"
|
|
hexmask.byte 0x0 0.--5. 1. " Line0 ,G Line0"
|
|
line.byte 0x1 ""
|
|
hexmask.byte 0x1 0.--5. 1. " Line1 ,G Line 1 "
|
|
line.byte 0x2 ""
|
|
hexmask.byte 0x2 0.--5. 1. " Line2 ,G Line 2 "
|
|
line.byte 0x3 ""
|
|
hexmask.byte 0x3 0.--5. 1. " Line3 ,G Line 3 "
|
|
line.byte 0x4 ""
|
|
hexmask.byte 0x4 0.--5. 1. " Line4 ,G Line 4 "
|
|
line.byte 0x5 ""
|
|
hexmask.byte 0x5 0.--5. 1. " Line5 ,G Line 5 "
|
|
line.byte 0x6 ""
|
|
hexmask.byte 0x6 0.--5. 1. " Line6 ,G Line 6 "
|
|
line.byte 0x7 ""
|
|
hexmask.byte 0x7 0.--5. 1. " Line7 ,G Line 7 "
|
|
line.byte 0x8 ""
|
|
hexmask.byte 0x8 0.--5. 1. " Line8 ,G Line 8 "
|
|
line.byte 0x9 ""
|
|
hexmask.byte 0x9 0.--5. 1. " Line9 ,G Line 9 "
|
|
line.byte 0xA ""
|
|
hexmask.byte 0xA 0.--5. 1. " Line10 ,G Line 10"
|
|
line.byte 0xB ""
|
|
hexmask.byte 0xB 0.--5. 1. " Line11 ,G Line 11"
|
|
line.byte 0xC ""
|
|
hexmask.byte 0xC 0.--5. 1. " Line12 ,G Line 12"
|
|
line.byte 0xD ""
|
|
hexmask.byte 0xD 0.--5. 1. " Line13 ,G Line 13"
|
|
line.byte 0xE ""
|
|
hexmask.byte 0xE 0.--5. 1. " Line14 ,G Line 14"
|
|
line.byte 0xF ""
|
|
hexmask.byte 0xF 0.--5. 1. " Line15 ,G Line 15"
|
|
line.byte 0x10 ""
|
|
hexmask.byte 0x10 0.--5. 1. " Line16 ,G Line 16"
|
|
line.byte 0x11 ""
|
|
hexmask.byte 0x11 0.--5. 1. " Line17 ,G Line 17"
|
|
line.byte 0x12 ""
|
|
hexmask.byte 0x12 0.--5. 1. " Line18 ,G Line 18"
|
|
line.byte 0x13 ""
|
|
hexmask.byte 0x13 0.--5. 1. " Line19 ,G Line 19"
|
|
line.byte 0x14 ""
|
|
hexmask.byte 0x14 0.--5. 1. " Line20 ,G Line 20"
|
|
line.byte 0x15 ""
|
|
hexmask.byte 0x15 0.--5. 1. " Line21 ,G Line 21"
|
|
line.byte 0x16 ""
|
|
hexmask.byte 0x16 0.--5. 1. " Line22 ,G Line 22"
|
|
line.byte 0x17 ""
|
|
hexmask.byte 0x17 0.--5. 1. " Line23 ,G Line 23"
|
|
line.byte 0x18 ""
|
|
hexmask.byte 0x18 0.--5. 1. " Line24 ,G Line 24"
|
|
line.byte 0x19 ""
|
|
hexmask.byte 0x19 0.--5. 1. " Line25 ,G Line 25"
|
|
line.byte 0x1A ""
|
|
hexmask.byte 0x1A 0.--5. 1. " Line26 ,G Line 26"
|
|
line.byte 0x1B ""
|
|
hexmask.byte 0x1B 0.--5. 1. " Line27 ,G Line 27"
|
|
line.byte 0x1C ""
|
|
hexmask.byte 0x1C 0.--5. 1. " Line28 ,G Line 28"
|
|
line.byte 0x1D ""
|
|
hexmask.byte 0x1D 0.--5. 1. " Line29 ,G Line 29"
|
|
line.byte 0x1E ""
|
|
hexmask.byte 0x1E 0.--5. 1. " Line30 ,G Line 30"
|
|
line.byte 0x1F ""
|
|
hexmask.byte 0x1F 0.--5. 1. " Line31 ,G Line 31"
|
|
line.byte 0x20 ""
|
|
hexmask.byte 0x20 0.--5. 1. " Line32 ,G Line 32"
|
|
line.byte 0x21 ""
|
|
hexmask.byte 0x21 0.--5. 1. " Line33 ,G Line 33"
|
|
line.byte 0x22 ""
|
|
hexmask.byte 0x22 0.--5. 1. " Line34 ,G Line 34"
|
|
line.byte 0x23 ""
|
|
hexmask.byte 0x23 0.--5. 1. " Line35 ,G Line 35"
|
|
line.byte 0x24 ""
|
|
hexmask.byte 0x24 0.--5. 1. " Line36 ,G Line 36"
|
|
line.byte 0x25 ""
|
|
hexmask.byte 0x25 0.--5. 1. " Line37 ,G Line 37"
|
|
line.byte 0x26 ""
|
|
hexmask.byte 0x26 0.--5. 1. " Line38 ,G Line 38"
|
|
line.byte 0x27 ""
|
|
hexmask.byte 0x27 0.--5. 1. " Line39 ,G Line 39"
|
|
line.byte 0x28 ""
|
|
hexmask.byte 0x28 0.--5. 1. " Line40 ,G Line 40"
|
|
line.byte 0x29 ""
|
|
hexmask.byte 0x29 0.--5. 1. " Line41 ,G Line 41"
|
|
line.byte 0x2A ""
|
|
hexmask.byte 0x2A 0.--5. 1. " Line42 ,G Line 42"
|
|
line.byte 0x2B ""
|
|
hexmask.byte 0x2B 0.--5. 1. " Line43 ,G Line 43"
|
|
line.byte 0x2C ""
|
|
hexmask.byte 0x2C 0.--5. 1. " Line44 ,G Line 44"
|
|
line.byte 0x2D ""
|
|
hexmask.byte 0x2D 0.--5. 1. " Line45 ,G Line 45"
|
|
line.byte 0x2E ""
|
|
hexmask.byte 0x2E 0.--5. 1. " Line46 ,G Line 46"
|
|
line.byte 0x2F ""
|
|
hexmask.byte 0x2F 0.--5. 1. " Line47 ,G Line 47"
|
|
line.byte 0x30 ""
|
|
hexmask.byte 0x30 0.--5. 1. " Line48 ,G Line 48"
|
|
line.byte 0x31 ""
|
|
hexmask.byte 0x31 0.--5. 1. " Line49 ,G Line 49"
|
|
line.byte 0x32 ""
|
|
hexmask.byte 0x32 0.--5. 1. " Line50 ,G Line 50"
|
|
line.byte 0x33 ""
|
|
hexmask.byte 0x33 0.--5. 1. " Line51 ,G Line 51"
|
|
line.byte 0x34 ""
|
|
hexmask.byte 0x34 0.--5. 1. " Line52 ,G Line 52"
|
|
line.byte 0x35 ""
|
|
hexmask.byte 0x35 0.--5. 1. " Line53 ,G Line 53"
|
|
line.byte 0x36 ""
|
|
hexmask.byte 0x36 0.--5. 1. " Line54 ,G Line 54"
|
|
line.byte 0x37 ""
|
|
hexmask.byte 0x37 0.--5. 1. " Line55 ,G Line 55"
|
|
line.byte 0x38 ""
|
|
hexmask.byte 0x38 0.--5. 1. " Line56 ,G Line 56"
|
|
line.byte 0x39 ""
|
|
hexmask.byte 0x39 0.--5. 1. " Line57 ,G Line 57"
|
|
line.byte 0x3A ""
|
|
hexmask.byte 0x3A 0.--5. 1. " Line58 ,G Line 58"
|
|
line.byte 0x3B ""
|
|
hexmask.byte 0x3B 0.--5. 1. " Line59 ,G Line 59"
|
|
line.byte 0x3C ""
|
|
hexmask.byte 0x3C 0.--5. 1. " Line60 ,G Line 60"
|
|
line.byte 0x3D ""
|
|
hexmask.byte 0x3D 0.--5. 1. " Line61 ,G Line 61"
|
|
line.byte 0x3E ""
|
|
hexmask.byte 0x3E 0.--5. 1. " Line62 ,G Line 62"
|
|
line.byte 0x3F ""
|
|
hexmask.byte 0x3F 0.--5. 1. " Line63 ,G Line 63"
|
|
group.byte 0x80++0x0
|
|
line.byte 0x0 "LCDCONV_CONTROL,Control Register"
|
|
bitfld.byte 0x0 3. " LCD_AC_EDGE ,This bit represents the active edge of the LCD frame sync signal" "Positive,Negative"
|
|
bitfld.byte 0x0 2. " CLOCK_EN ,Enable the write clock to RGB look-up table RAM" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x0 1. " MODE_STATUS ,Actual mode of LCD" "16-bit,18-bit"
|
|
bitfld.byte 0x0 0. " MODE_SET ,This bit represents the software setup for the LCD mode" "16-bit,18-bit"
|
|
rgroup.byte 0x84++0x0
|
|
line.byte 0x00 "LCDCONV_DEV_REV,Device Revision File"
|
|
tree.end
|
|
base AD:0xFFFEC000
|
|
tree "LCD Controller Registers"
|
|
width 19.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "LCD_CONTROL,LCD Control Register"
|
|
bitfld.long 0x00 24. " Off ,12-BPP (565) mode" "Off,On"
|
|
bitfld.long 0x00 23. " TFTMAP ,TFT alternative signal mapping" "Right aligned,Converted"
|
|
textline " "
|
|
bitfld.long 0x00 22. " LCDCB1 ,LCD control bit 1" "0,1"
|
|
bitfld.long 0x00 20.--21. " PLM ,Palette loading module" "Palette & data,Palette,Data,Not connected"
|
|
textline " "
|
|
hexmask.long.byte 0x00 12.--19. 1. " FDD ,FIFO DMA request delay"
|
|
bitfld.long 0x00 11. " PXL_GATED ,Pixel gated (for TFT mode only)" "Always,On valid data"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LINE_INT_CLR_SEL ,Line interrupt clear select bit" "TIPB,End of line"
|
|
bitfld.long 0x00 9. " M8B ,Mono 8-bit mode" "4 pixel,8 pixel"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCDCB0 ,LCD control bit 0" "0,1"
|
|
bitfld.long 0x00 7. " LCDTFT ,LCD TFT" "Passive or STN,Active or TFT"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LINE_INT_MASK ,Line interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " LINE_INT_NIRQ_MASK ,Line interrupt mask" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LOADMASK ,Load mask" "Active,Inactive"
|
|
bitfld.long 0x00 3. " DONEMASK ,Done mask" "Active,Inactive"
|
|
textline " "
|
|
bitfld.long 0x00 2. " VSYNC_MASK ,LCD VSYNC interrupt mask" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " LCDBW ,LCD monochrome" "Color,Monochrome"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LCDEN ,LCD controller enable" "Disabled,Enabled"
|
|
line.long 0x04 "LCD_TIMING0,LCD Timing0 Register"
|
|
hexfld.byte 0x07 " HBP ,Horinzontal back porch"
|
|
hexfld.byte 0x06 " HFP ,Horinzontal front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x04 10.--15. 1. " HSW ,Horizontal synchronization pulse width"
|
|
hexmask.long.word 0x04 0.--9. 1. " PPL ,Pixels per line"
|
|
line.long 0x08 "LCD_TIMING1,LCD Timing1 Register"
|
|
hexfld.byte 0x0b " VBP ,Vertical back porch"
|
|
hexfld.byte 0x0a " VFP ,Vertical front porch"
|
|
textline " "
|
|
hexmask.long.byte 0x08 10.--15. 1. " VSW ,Vertical synchronization pulse width"
|
|
hexmask.long.word 0x05 0.--9. 1. " LPP ,Lines per panel"
|
|
line.long 0x0c "LCD_TIMING2,LCD Timing2 Register"
|
|
bitfld.long 0x0c 25. " ON_OFF ,HSYNC/VSYNC pixel clock control on/off" "Opposite edges,According to RF"
|
|
bitfld.long 0x0c 24. " RF ,Program HSYNC/VSYNC RISE OR FALL" "Falling edge,Rising edge"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " IEO ,Invert output enable" "Active high,Active low"
|
|
bitfld.long 0x0c 22. " IPC ,Invert pixel clock" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " IHS ,Invert HSYNC" "Active high,Active low"
|
|
bitfld.long 0x0c 20. " IVS ,Invert VSYNC" "Active high,Active low"
|
|
textline " "
|
|
bitfld.long 0x0c 16.--19. " ACBI ,AC-bias pin transitions per interupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexfld.byte 0x0d " ACB ,AC-BIAS pin frequency"
|
|
textline " "
|
|
hexfld.byte 0x0c " PCD ,Pixel clock divisor"
|
|
line.long 0x10 "LCD_STATUS,LCD Status Register"
|
|
bitfld.long 0x10 6. " LP ,Loaded palette" "Not loaded,Loaded"
|
|
bitfld.long 0x10 5. " FUF ,FIFO underflow status" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.long 0x10 4. " LINE_INT ,Line interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x10 3. " ABC ,AC-bias count status" "Not 0,0"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SYNC_LOST ,Synchronization lost" "No error,Error"
|
|
bitfld.long 0x10 1. " VS ,VSYNC interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 0. " DONE ,Frame done" "LCD enabled,LCD disabled"
|
|
line.long 0x14 "LCD_SUBPANEL,LCD Subpanel Display Register"
|
|
bitfld.long 0x14 31. " SPEN ,Subpanel enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 29. " HOLS ,High or low signal" "Below LPPT,Above LPPT"
|
|
textline " "
|
|
hexmask.long.word 0x14 16.--25. 1. " LPPT ,Line per panel threshold"
|
|
hexfld.word 0x14 " DPD ,Default pixel data"
|
|
line.long 0x18 "LCD_LINEINT,LCD Line Interrupt Register"
|
|
hexmask.long.word 0x18 0.--9. 1. " LINE_INT_NUMBER ,Line number at which line interrupt occurs"
|
|
line.long 0x1c "LCD_DISPLAYSTATUS,LCD Display Status Register"
|
|
hexmask.long.word 0x1c 0.--9. 1. " CURRENT_LINE_NUMBER ,Line number being displayed"
|
|
tree.end
|
|
tree "MPU Timers"
|
|
width 16.
|
|
base AD:0xFFFEC500
|
|
width 17.
|
|
group.long 0x00++0x3 "MPU Timer1 Registers"
|
|
line.long 0x00 "MPU_CNTL_TIMER1,MPU Timer1 Control Register"
|
|
bitfld.long 0x00 6. " FREE ,Specifies what action the timer takes upon receiving a suspend indication from the TIPB bridge" "Stop counting,No action"
|
|
bitfld.long 0x00 5. " CLOCK_ENABLE ,Enables input reference clock to the DSP OS timer module" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescale timer input reference clock" "2,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer value decrement" "Stop,Start"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x00 "MPU_LOAD_TIMER1,MPU Timer1 Load Register"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "MPU_READ_TIMER1,MPU Timer1 Read Register"
|
|
base AD:0xFFFEC600
|
|
width 17.
|
|
group.long 0x00++0x3 "MPU Timer2 Registers"
|
|
line.long 0x00 "MPU_CNTL_TIMER2,MPU Timer2 Control Register"
|
|
bitfld.long 0x00 6. " FREE ,Specifies what action the timer takes upon receiving a suspend indication from the TIPB bridge" "Stop counting,No action"
|
|
bitfld.long 0x00 5. " CLOCK_ENABLE ,Enables input reference clock to the DSP OS timer module" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescale timer input reference clock" "2,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer value decrement" "Stop,Start"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x00 "MPU_LOAD_TIMER2,MPU Timer2 Load Register"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "MPU_READ_TIMER2,MPU Timer2 Read Register"
|
|
base AD:0xFFFEC700
|
|
width 17.
|
|
group.long 0x00++0x3 "MPU Timer3 Registers"
|
|
line.long 0x00 "MPU_CNTL_TIMER3,MPU Timer3 Control Register"
|
|
bitfld.long 0x00 6. " FREE ,Specifies what action the timer takes upon receiving a suspend indication from the TIPB bridge" "Stop counting,No action"
|
|
bitfld.long 0x00 5. " CLOCK_ENABLE ,Enables input reference clock to the DSP OS timer module" "Disabled,Enabled"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescale timer input reference clock" "2,4,8,16,32,64,128,256"
|
|
textline " "
|
|
bitfld.long 0x00 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
bitfld.long 0x00 0. " ST ,Start/Stop timer value decrement" "Stop,Start"
|
|
wgroup.long 0x4++0x3
|
|
line.long 0x00 "MPU_LOAD_TIMER3,MPU Timer3 Load Register"
|
|
rgroup.long 0x8++0x3
|
|
line.long 0x00 "MPU_READ_TIMER3,MPU Timer3 Read Register"
|
|
tree.end
|
|
base AD:0xFFFEC800
|
|
tree "MPU Watchdog Timer Registers"
|
|
width 20.
|
|
group 0x0++0x3
|
|
line.long 0x00 "MPU_WDT_CNTL_TIMER,MPU Watchdog Timer Control Register"
|
|
wgroup 0x4++0x3
|
|
line.long 0x00 "MPU_WDT_LOAD_TIMER,MPU Watchdog Timer Load Register"
|
|
rgroup 0x4++0x3
|
|
line.long 0x00 "MPU_WDT_READ_TIMER,MPU Watchdog Timer Read Register"
|
|
group 0x8++0x3
|
|
line.long 0x00 "MPU_WDT_TIMER_MODE,MPU Watchdog Timer Mode Register"
|
|
tree.end
|
|
base AD:0xFFFECB00
|
|
tree "MPU Level 1 Interrupt Handler Registers"
|
|
width 16.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "MPU_L1_ITR,Interrupt Register"
|
|
bitfld.long 0x00 31. " ACT_IRQ31 ,Interrupt 31 is coming" "No,Yes"
|
|
bitfld.long 0x00 30. " ACT_IRQ30 ,Interrupt 30 is coming" "No,Yes"
|
|
bitfld.long 0x00 29. " ACT_IRQ29 ,Interrupt 29 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ACT_IRQ28 ,Interrupt 28 is coming" "No,Yes"
|
|
bitfld.long 0x00 27. " ACT_IRQ27 ,Interrupt 27 is coming" "No,Yes"
|
|
bitfld.long 0x00 26. " ACT_IRQ26 ,Interrupt 26 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACT_IRQ25 ,Interrupt 25 is coming" "No,Yes"
|
|
bitfld.long 0x00 24. " ACT_IRQ24 ,Interrupt 24 is coming" "No,Yes"
|
|
bitfld.long 0x00 23. " ACT_IRQ23 ,Interrupt 23 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ACT_IRQ22 ,Interrupt 22 is coming" "No,Yes"
|
|
bitfld.long 0x00 21. " ACT_IRQ21 ,Interrupt 21 is coming" "No,Yes"
|
|
bitfld.long 0x00 20. " ACT_IRQ20 ,Interrupt 20 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACT_IRQ19 ,Interrupt 19 is coming" "No,Yes"
|
|
bitfld.long 0x00 18. " ACT_IRQ18 ,Interrupt 18 is coming" "No,Yes"
|
|
bitfld.long 0x00 17. " ACT_IRQ17 ,Interrupt 17 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ACT_IRQ16 ,Interrupt 16 is coming" "No,Yes"
|
|
bitfld.long 0x00 15. " ACT_IRQ15 ,Interrupt 15 is coming" "No,Yes"
|
|
bitfld.long 0x00 14. " ACT_IRQ14 ,Interrupt 14 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACT_IRQ13 ,Interrupt 13 is coming" "No,Yes"
|
|
bitfld.long 0x00 12. " ACT_IRQ12 ,Interrupt 12 is coming" "No,Yes"
|
|
bitfld.long 0x00 11. " ACT_IRQ11 ,Interrupt 11 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ACT_IRQ10 ,Interrupt 10 is coming" "No,Yes"
|
|
bitfld.long 0x00 9. " ACT_IRQ9 ,Interrupt 9 is coming" "No,Yes"
|
|
bitfld.long 0x00 8. " ACT_IRQ8 ,Interrupt 8 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACT_IRQ7 ,Interrupt 7 is coming" "No,Yes"
|
|
bitfld.long 0x00 6. " ACT_IRQ6 ,Interrupt 6 is coming" "No,Yes"
|
|
bitfld.long 0x00 5. " ACT_IRQ5 ,Interrupt 5 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ACT_IRQ4 ,Interrupt 4 is coming" "No,Yes"
|
|
bitfld.long 0x00 3. " ACT_IRQ3 ,Interrupt 3 is coming" "No,Yes"
|
|
bitfld.long 0x00 2. " ACT_IRQ2 ,Interrupt 2 is coming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACT_IRQ1 ,Interrupt 1 is coming" "No,Yes"
|
|
bitfld.long 0x00 0. " ACT_IRQ0 ,Interrupt 0 is coming" "No,Yes"
|
|
line.long 0x04 "MPU_L1_MIR,Interrupt Mask Register"
|
|
bitfld.long 0x04 31. " IRQ_MSK31 ,Mask interrupt 31" "No,Yes"
|
|
bitfld.long 0x04 30. " IRQ_MSK30 ,Mask interrupt 30" "No,Yes"
|
|
bitfld.long 0x04 29. " IRQ_MSK29 ,Mask interrupt 29" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 28. " IRQ_MSK28 ,Mask interrupt 28" "No,Yes"
|
|
bitfld.long 0x04 27. " IRQ_MSK27 ,Mask interrupt 27" "No,Yes"
|
|
bitfld.long 0x04 26. " IRQ_MSK26 ,Mask interrupt 26" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 25. " IRQ_MSK25 ,Mask interrupt 25" "No,Yes"
|
|
bitfld.long 0x04 24. " IRQ_MSK24 ,Mask interrupt 24" "No,Yes"
|
|
bitfld.long 0x04 23. " IRQ_MSK23 ,Mask interrupt 23" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 22. " IRQ_MSK22 ,Mask interrupt 22" "No,Yes"
|
|
bitfld.long 0x04 21. " IRQ_MSK21 ,Mask interrupt 21" "No,Yes"
|
|
bitfld.long 0x04 20. " IRQ_MSK20 ,Mask interrupt 20" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 19. " IRQ_MSK19 ,Mask interrupt 19" "No,Yes"
|
|
bitfld.long 0x04 18. " IRQ_MSK18 ,Mask interrupt 18" "No,Yes"
|
|
bitfld.long 0x04 17. " IRQ_MSK17 ,Mask interrupt 17" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 16. " IRQ_MSK16 ,Mask interrupt 16" "No,Yes"
|
|
bitfld.long 0x04 15. " IRQ_MSK15 ,Mask interrupt 15" "No,Yes"
|
|
bitfld.long 0x04 14. " IRQ_MSK14 ,Mask interrupt 14" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 13. " IRQ_MSK13 ,Mask interrupt 13" "No,Yes"
|
|
bitfld.long 0x04 12. " IRQ_MSK12 ,Mask interrupt 12" "No,Yes"
|
|
bitfld.long 0x04 11. " IRQ_MSK11 ,Mask interrupt 11" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 10. " IRQ_MSK10 ,Mask interrupt 10" "No,Yes"
|
|
bitfld.long 0x04 9. " IRQ_MSK9 ,Mask interrupt 9" "No,Yes"
|
|
bitfld.long 0x04 8. " IRQ_MSK8 ,Mask interrupt 8" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 7. " IRQ_MSK7 ,Mask interrupt 7" "No,Yes"
|
|
bitfld.long 0x04 6. " IRQ_MSK6 ,Mask interrupt 6" "No,Yes"
|
|
bitfld.long 0x04 5. " IRQ_MSK5 ,Mask interrupt 5" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4. " IRQ_MSK4 ,Mask interrupt 4" "No,Yes"
|
|
bitfld.long 0x04 3. " IRQ_MSK3 ,Mask interrupt 3" "No,Yes"
|
|
bitfld.long 0x04 2. " IRQ_MSK2 ,Mask interrupt 2" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1. " IRQ_MSK1 ,Mask interrupt 1" "No,Yes"
|
|
bitfld.long 0x04 0. " IRQ_MSK0 ,Mask interrupt 0" "No,Yes"
|
|
rgroup.long 0x10++0x7
|
|
line.long 0x00 "MPU_L1_SIR_IRQ,Interrupt Encoded Source (IRQ) Register"
|
|
bitfld.long 0x00 0.--4. " IRQ_NUM ,Interrupt number that has an IRQ request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x04 "MPU_L1_SIR_FIQ,Interrupt Encoded Source (FIQ) Register"
|
|
bitfld.long 0x04 0.--4. " IRQ_NUM ,Interrupt number that has an FIQ request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x18++0x8B
|
|
line.long 0x00 "MPU_L1_CONTROL,Interrupt Control Register"
|
|
bitfld.long 0x00 1. " NEW_FIQ_AGR ,New FIQ agreement" "No,Yes"
|
|
bitfld.long 0x00 0. " NEW_IRQ_AGR ,New IRQ agreement" "No,Yes"
|
|
line.long 0x04 "MPU_L1_ILR0,Interrupt Priority Level For IRQ 0 Register"
|
|
bitfld.long 0x04 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x04 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x04 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x08 "MPU_L1_ILR1,Interrupt Priority Level For IRQ 1 Register"
|
|
bitfld.long 0x08 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x08 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x08 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x0c "MPU_L1_ILR2,Interrupt Priority Level For IRQ 2 Register"
|
|
bitfld.long 0x0c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x0c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x0c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x10 "MPU_L1_ILR3,Interrupt Priority Level For IRQ 3 Register"
|
|
bitfld.long 0x10 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x10 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x10 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x14 "MPU_L1_ILR4,Interrupt Priority Level For IRQ 4 Register"
|
|
bitfld.long 0x14 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x14 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x14 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x18 "MPU_L1_ILR5,Interrupt Priority Level For IRQ 5 Register"
|
|
bitfld.long 0x18 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x18 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x18 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x1c "MPU_L1_ILR6,Interrupt Priority Level For IRQ 6 Register"
|
|
bitfld.long 0x1c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x1c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x1c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x20 "MPU_L1_ILR7,Interrupt Priority Level For IRQ 7 Register"
|
|
bitfld.long 0x20 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x20 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x20 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x24 "MPU_L1_ILR8,Interrupt Priority Level For IRQ 8 Register"
|
|
bitfld.long 0x24 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x24 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x24 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x28 "MPU_L1_ILR9,Interrupt Priority Level For IRQ 9 Register"
|
|
bitfld.long 0x28 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x28 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x28 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x2c "MPU_L1_ILR10,Interrupt Priority Level For IRQ 10 Register"
|
|
bitfld.long 0x2c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x2c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x2c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x30 "MPU_L1_ILR11,Interrupt Priority Level For IRQ 11 Register"
|
|
bitfld.long 0x30 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x30 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x30 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x34 "MPU_L1_ILR12,Interrupt Priority Level For IRQ 12 Register"
|
|
bitfld.long 0x34 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x34 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x34 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x38 "MPU_L1_ILR13,Interrupt Priority Level For IRQ 13 Register"
|
|
bitfld.long 0x38 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x38 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x38 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x3c "MPU_L1_ILR14,Interrupt Priority Level For IRQ 14 Register"
|
|
bitfld.long 0x3c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x3c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x3c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x40 "MPU_L1_ILR15,Interrupt Priority Level For IRQ 15 Register"
|
|
bitfld.long 0x40 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x40 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x40 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x44 "MPU_L1_ILR16,Interrupt Priority Level For IRQ 16 Register"
|
|
bitfld.long 0x44 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x44 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x44 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x48 "MPU_L1_ILR17,Interrupt Priority Level For IRQ 17 Register"
|
|
bitfld.long 0x48 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x48 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x48 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x4c "MPU_L1_ILR18,Interrupt Priority Level For IRQ 18 Register"
|
|
bitfld.long 0x4c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x4c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x4c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x50 "MPU_L1_ILR19,Interrupt Priority Level For IRQ 19 Register"
|
|
bitfld.long 0x50 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x50 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x50 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x54 "MPU_L1_ILR20,Interrupt Priority Level For IRQ 20 Register"
|
|
bitfld.long 0x54 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x54 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x54 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x58 "MPU_L1_ILR21,Interrupt Priority Level For IRQ 21 Register"
|
|
bitfld.long 0x58 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x58 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x58 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x5c "MPU_L1_ILR22,Interrupt Priority Level For IRQ 22 Register"
|
|
bitfld.long 0x5c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x5c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x5c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x60 "MPU_L1_ILR23,Interrupt Priority Level For IRQ 23 Register"
|
|
bitfld.long 0x60 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x60 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x60 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x64 "MPU_L1_ILR24,Interrupt Priority Level For IRQ 24 Register"
|
|
bitfld.long 0x64 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x64 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x64 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x68 "MPU_L1_ILR25,Interrupt Priority Level For IRQ 25 Register"
|
|
bitfld.long 0x68 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x68 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x68 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x6c "MPU_L1_ILR26,Interrupt Priority Level For IRQ 26 Register"
|
|
bitfld.long 0x6c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x6c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x6c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x70 "MPU_L1_ILR27,Interrupt Priority Level For IRQ 27 Register"
|
|
bitfld.long 0x70 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x70 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x70 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x74 "MPU_L1_ILR28,Interrupt Priority Level For IRQ 28 Register"
|
|
bitfld.long 0x74 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x74 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x74 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x78 "MPU_L1_ILR29,Interrupt Priority Level For IRQ 29 Register"
|
|
bitfld.long 0x78 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x78 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x78 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x7c "MPU_L1_ILR30,Interrupt Priority Level For IRQ 30 Register"
|
|
bitfld.long 0x7c 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x7c 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x7c 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x80 "MPU_L1_ILR31,Interrupt Priority Level For IRQ 31 Register"
|
|
bitfld.long 0x80 2.--6. " PRIORITY ,Priority level" "0 - highest,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31 - lowest"
|
|
bitfld.long 0x80 1. " SENS_LEVEL ,Sensitivity level" "Falling-edge,Low-level"
|
|
bitfld.long 0x80 0. " FIQ ,Routing" "IRQ,FIQ"
|
|
line.long 0x84 "MPU_L1_SIR,Software Interrupt Set Register"
|
|
bitfld.long 0x84 31. " SIR31 ,Generate falling-edge interrupt 31" "No effect,Generate"
|
|
bitfld.long 0x84 30. " SIR30 ,Generate falling-edge interrupt 30" "No effect,Generate"
|
|
bitfld.long 0x84 29. " SIR29 ,Generate falling-edge interrupt 29" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 28. " SIR28 ,Generate falling-edge interrupt 28" "No effect,Generate"
|
|
bitfld.long 0x84 27. " SIR27 ,Generate falling-edge interrupt 27" "No effect,Generate"
|
|
bitfld.long 0x84 26. " SIR26 ,Generate falling-edge interrupt 26" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 25. " SIR25 ,Generate falling-edge interrupt 25" "No effect,Generate"
|
|
bitfld.long 0x84 24. " SIR24 ,Generate falling-edge interrupt 24" "No effect,Generate"
|
|
bitfld.long 0x84 23. " SIR23 ,Generate falling-edge interrupt 23" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 22. " SIR22 ,Generate falling-edge interrupt 22" "No effect,Generate"
|
|
bitfld.long 0x84 21. " SIR21 ,Generate falling-edge interrupt 21" "No effect,Generate"
|
|
bitfld.long 0x84 20. " SIR20 ,Generate falling-edge interrupt 20" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 19. " SIR19 ,Generate falling-edge interrupt 19" "No effect,Generate"
|
|
bitfld.long 0x84 18. " SIR18 ,Generate falling-edge interrupt 18" "No effect,Generate"
|
|
bitfld.long 0x84 17. " SIR17 ,Generate falling-edge interrupt 17" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 16. " SIR16 ,Generate falling-edge interrupt 16" "No effect,Generate"
|
|
bitfld.long 0x84 15. " SIR15 ,Generate falling-edge interrupt 15" "No effect,Generate"
|
|
bitfld.long 0x84 14. " SIR14 ,Generate falling-edge interrupt 14" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 13. " SIR13 ,Generate falling-edge interrupt 13" "No effect,Generate"
|
|
bitfld.long 0x84 12. " SIR12 ,Generate falling-edge interrupt 12" "No effect,Generate"
|
|
bitfld.long 0x84 11. " SIR11 ,Generate falling-edge interrupt 11" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 10. " SIR10 ,Generate falling-edge interrupt 10" "No effect,Generate"
|
|
bitfld.long 0x84 9. " SIR9 ,Generate falling-edge interrupt 9" "No effect,Generate"
|
|
bitfld.long 0x84 8. " SIR8 ,Generate falling-edge interrupt 8" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 7. " SIR7 ,Generate falling-edge interrupt 7" "No effect,Generate"
|
|
bitfld.long 0x84 6. " SIR6 ,Generate falling-edge interrupt 6" "No effect,Generate"
|
|
bitfld.long 0x84 5. " SIR5 ,Generate falling-edge interrupt 5" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 4. " SIR4 ,Generate falling-edge interrupt 4" "No effect,Generate"
|
|
bitfld.long 0x84 3. " SIR3 ,Generate falling-edge interrupt 3" "No effect,Generate"
|
|
bitfld.long 0x84 2. " SIR2 ,Generate falling-edge interrupt 2" "No effect,Generate"
|
|
textline " "
|
|
bitfld.long 0x84 1. " SIR1 ,Generate falling-edge interrupt 1" "No effect,Generate"
|
|
bitfld.long 0x84 0. " SIR0 ,Generate falling-edge interrupt 0" "No effect,Generate"
|
|
line.long 0x88 "MPU_L1_GMR,Global Mask Interrupt Register"
|
|
bitfld.long 0x88 0. " GLOBAL_MASK ,Global Mask Interrupt" "No,Yes"
|
|
tree.end
|
|
tree.end
|
|
tree "MPU Public Peripheral Registers"
|
|
base AD:0xFFFB0400
|
|
tree "USB On-the-Go (OTG) Registers"
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "USB_OTG_REV,USB On The Go Revision Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " OTG_REV_NB ,OTG Revision Number"
|
|
group.long 0x04++0x1F
|
|
line.long 0x00 "USB_OTG_SYSCON1,USB On The Go Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. " USB2_TRX_MODE ,USB port 2 transceiver mode" "6-pin DAT/SE0 UniDir,4-pin VP/VM BiDir,3-pin DAT/SE0 BiDir,6-pin DAT/SE0 UniDir,?..."
|
|
bitfld.long 0x00 20.--22. " USB1_TRX_MODE ,USB port 1 transceiver mode" "6-pin DAT/SE0 UniDir,4-pin VP/VM BiDir,3-pin DAT/SE0 BiDir,6-pin DAT/SE0 UniDir,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " USB0_TRX_MODE ,USB port 0 transceiver mode" "6-pin DAT/SE0 UniDir,4-pin VP/VM BiDir,3-pin DAT/SE0 BiDir,6-pin DAT/SE0 UniDir,?..."
|
|
bitfld.long 0x00 15. " OTG_IDLE_EN ,OTG controller clock-gating control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " HST_IDLE_EN ,Host power management circuity enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DEV_IDLE_EN ,Device controller clock-gating control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " RESET_DONE ,Reset status information" "Ongoing,Completed"
|
|
bitfld.long 0x00 1. " SOFT_RESET ,Soft reset for the OTG device" "Normal,Reset"
|
|
line.long 0x04 "USB_OTG_SYSCON2,USB On The Go Configuration Register 2"
|
|
bitfld.long 0x04 31. " OTG_EN ,OTG enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " USBX_SYNCHRO ,Set to allow proper signal timing on OMAP5912 USB pins" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " OTG_MST16 ,Enable compatibility with the 16-bit OTG master controller" "32-bit,16-bit"
|
|
bitfld.long 0x04 28. " SRP_GPDATA ,Session request protocol generation pulse width on D+" "6ms,9ms"
|
|
textline " "
|
|
bitfld.long 0x04 27. " SRP_GPDVBUS ,Session request protocol generation discharge VBUS enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 24.--26. " SRP_GPUVBUS ,Session request protocol generation charge VBUS duration" "Disabled,0.5ms,SRP/0.5ms,SRP/2ms,SRP/4ms,SRP/6ms,SRP/10ms,SRP/40ms"
|
|
textline " "
|
|
bitfld.long 0x04 20.--22. " A_WAIT_VRISE ,Offset for A_WAIT_VRISE timer" "200ms,287.04ms,374.08ms,548.16ms,?..."
|
|
bitfld.long 0x04 16.--18. " B_ASE0_BRST ,Offset for B_ASE0_BRST timer" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x04 14. " SRP_DPW ,Session request protocol detection - pulse width" "1ms,167ns"
|
|
bitfld.long 0x04 13. " SRP_DATA ,Session request protocol detection - data pulsing detection enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " SRP_VBUS ,Session request protocol detection - VBUS pulsing detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " OTG_PADEN ,OTG transceiver control and status information selector" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 9. " HMC_PADEN ,USB pin multiplexing control selector" "OTG_SYSCON_2,OMAP5912"
|
|
bitfld.long 0x04 8. " UHOST_EN ,Host USB controller enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " HMC_TLLSPEED ,HMC TLL SPEED configuration bit" "1.5Mbps,12Mbps"
|
|
bitfld.long 0x04 6. " HMC_TLLATTACH ,HMC TLL ATTACH" "Detached,Attached"
|
|
textline " "
|
|
bitfld.long 0x04 0.--5. " HMC_MODE ,HMC mode configuration bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,?..."
|
|
line.long 0x08 "USB_OTG_CTRL,USB On The Go Control Register"
|
|
bitfld.long 0x08 20. " ASESSVLD ,Current A-device session valid value; VBUS voltage is below/above Va_sess_vld" "Below,Above"
|
|
bitfld.long 0x08 19. " BSESSEND ,Current B-device session end value; VBUS voltage is above/below Vb_sess_end" "Above,Below"
|
|
textline " "
|
|
bitfld.long 0x08 18. " BSESSVLD ,Current B-device session valid value; VBUS voltage is below/above Vb_sess_vld" "Below,Above"
|
|
bitfld.long 0x08 17. " VBUSVLD ,Current VBUS valid value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 16. " ID ,Current ID" "Grounded,High-impedance"
|
|
bitfld.long 0x08 15. " DRIVER_SEL ,Active controller/driver software" "Host,Device"
|
|
textline " "
|
|
bitfld.long 0x08 12. " A_SETB_HNPEN ,B-device HNP indication (when acting as default-A device)" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " A_BUSREQ ,Bus request (when acting as default-A device)" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x08 9. " B_HNPEN ,B-device HNP enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " B_BUSREQ ,Bus request (when acting as default-B device)" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x08 7. " OTG_BUSDROP ,OTG bus drop request" "No request,Request"
|
|
bitfld.long 0x08 5. " OTG_PD ,D+ pulldown enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 4. " OTG_PU ,D+ pullup enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " OTG_DRV_VBUS ,VBUS drive enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " OTG_PD_VBUS ,VBUS pulldown enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " OTG_PU_VBUS ,VBUS pullup enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " OTG_PU_ID ,ID signal pullup enable" "Disabled,Enabled"
|
|
line.long 0x0c "USB_OTG_IRQ_EN,USB On The Go Interrupt Enable Register"
|
|
bitfld.long 0x0c 15. " DRIVER_SWITCH_EN ,Driver switch interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 13. " A_VBUS_ERR_EN ,A-device Vbus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " A_REQ_TMROUT_EN ,A-device request time-out interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 11. " A_SRP_DETECT_EN ,A-device request time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 10. " B_HNP_FAIL_EN ,B-device HNP failed interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 9. " B_SRP_TMROUT_EN ,B-device SRP time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " B_SRP_DONE_EN ,B-device SRP done interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x0c 7. " B_SRP_STARTED_EN ,B-device SRP started interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0c 0. " OPRT_CHG_EN ,OTG output port status change interrupt enable" "Disabled,Enabled"
|
|
line.long 0x10 "USB_OTG_IRQ_SRC,USB On The Go Interrupt Status Register"
|
|
bitfld.long 0x10 15. " DRIVER_SWITCH ,Driver switch interrupt status" "Inactive,Active"
|
|
bitfld.long 0x10 13. " A_VBUS_ERR ,A-device Vbus error interrupt status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 12. " A_REQ_TMROUT ,A-device request time-out interrupt status" "Inactive,Active"
|
|
bitfld.long 0x10 11. " A_SRP_DETECT ,A-device SRP detection interrupt status" "Inactive,Detected"
|
|
textline " "
|
|
bitfld.long 0x10 10. " B_HNP_FAIL ,B-device HNP failed interrupt status" "Inactive,Active"
|
|
bitfld.long 0x10 9. " B_SRP_TMROUT ,B-device SRP time-out interrupt status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 8. " B_SRP_DONE ,B-device SRP done interrupt status" "Inactive,Active"
|
|
bitfld.long 0x10 7. " B_SRP_STARTED ,B-device SRP started interrupt status" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x10 0. " OPRT_CHG ,OTG output port status change interrupt status" "Inactive,Active"
|
|
line.long 0x14 "USB_OTG_OUTCTRL,USB On The Go Output Pins Control Register"
|
|
bitfld.long 0x14 14. " OTGVPD ,OTG Pull down VBUS" "Disabled,Enabled"
|
|
bitfld.long 0x14 13. " OTGVPU ,OTG Pull up VBUS" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " OTGPUID ,OTG Pull up ID" "Disabled,Enabled"
|
|
bitfld.long 0x14 10. " USB2VDR ,USB2 Port Vbus drive" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 9. " USB2PDEN ,USB2 Port Pull Down enabled" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " USB2PUEN ,USB2 Port Pull Up enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " USB1VDR ,USB1 Port Vbus drive" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " USB1PDEN ,USB1 Port Pull Down enabled" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " USB1PUEN ,USB1 Port Pull Up enabled" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " USB0PDEN ,USB0 Port Vbus drive" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " USB0PDEN ,USB0 Port Pull Down enabled" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " USB0PUEN ,USB0 Port Pull Up enabled" "Disabled,Enabled"
|
|
line.long 0x1c "USB_OTG_TEST,USB On The Go Test Register"
|
|
bitfld.long 0x1c 15. " TEST_UNLOCK ,Test mode unlock" "Locked,Unlocked"
|
|
bitfld.long 0x1c 8. " IRQ_OTG ,IRQOTGON signal control" "Disabled,Enabled"
|
|
textline " "
|
|
hexfld.byte 0x1c " OTG_FSM_STATE ,OTG FSM state"
|
|
rgroup.long 0xFC++0x3
|
|
line.long 0x00 "USB_OTG_VC,USB On The Go Vendor Code Register"
|
|
hexfld.word 0x00 " VC ,Vendor code identifier"
|
|
tree.end
|
|
base AD:0xFFFBA000
|
|
tree "USB Host Controller Registers"
|
|
width 20.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "HCREVISION,OHCI revision number"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REV ,OHCI specification revision"
|
|
group.long 0x04++0x2b
|
|
line.long 0x00 "HCCONTROL,HC operating mode"
|
|
bitfld.long 0x00 10. " RWE ,Remote wake-up enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " RWC ,Remote wake-up connected" "Not connected,Connected"
|
|
bitfld.long 0x00 8. " IR ,Interrupt routing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " HCFS ,Host controller functional state" "Reset,Resume,Operational,Suspend"
|
|
bitfld.long 0x00 5. " BLE ,Bulk list enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " CLE ,Control list enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IE ,Isochronous enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PLE ,Periodic list enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--1. " CBSR ,Control/bulk service ratio" "1:1,2:1,3:1,4:1"
|
|
line.long 0x04 "HCCOMMANDSTATUS,HC command and status"
|
|
bitfld.long 0x04 16.--17. " SOC ,Scheduling overrun count" "0,1,2,3"
|
|
bitfld.long 0x04 3. " OCR ,Ownership change request" "No request,Request"
|
|
bitfld.long 0x04 2. " BLF ,Bulk list filled - start processing" "Not filled,Filled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CLF ,Control list filled - start processing" "Not filled,Filled"
|
|
bitfld.long 0x04 0. " HCR ,Host controller reset" "No effect,Reset"
|
|
line.long 0x08 "HCINTERRUPTSTATUS,HC interrupt status"
|
|
bitfld.long 0x08 30. " OC ,Ownership change" "No change,Change"
|
|
bitfld.long 0x08 6. " RHSC ,Root hub status change" "No change,Change"
|
|
bitfld.long 0x08 5. " FNO ,Frame number overflow" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x08 4. " UE ,Unrecoverable error" "No error,Error"
|
|
bitfld.long 0x08 3. " RD ,Resume detected" "No resume,Resume"
|
|
bitfld.long 0x08 2. " SF ,Start of frame" "Not issued,Issued"
|
|
textline " "
|
|
bitfld.long 0x08 1. " WDH ,Write done head" "Not updated,Updated"
|
|
bitfld.long 0x08 0. " SO ,Scheduling overrun" "No overrun,Overrun"
|
|
line.long 0xc "HCINTERRUPTENABLE,HC interrupt enable"
|
|
bitfld.long 0xc 31. " MIE ,Master interrupt enable" "Not propagate,Propagate"
|
|
bitfld.long 0xc 30. " OC ,Ownership change" "0,1"
|
|
bitfld.long 0xc 6. " RHSC ,Root hyb status change" "Not propagate,Propagate"
|
|
textline " "
|
|
bitfld.long 0xc 5. " FNO ,Frame number overflow" "Not propagate,Propagate"
|
|
bitfld.long 0xc 4. " UE ,Unrecoverable error" "Not propagate,Propagate"
|
|
bitfld.long 0xc 3. " RD ,Resume detected" "Not propagate,Propagate"
|
|
textline " "
|
|
bitfld.long 0xc 2. " SF ,Start of frame" "Not propagate,Propagate"
|
|
bitfld.long 0xc 1. " WDH ,Write done head" "Not propagate,Propagate"
|
|
bitfld.long 0xc 0. " SO ,Scheduling overrun" "Not propagate,Propagate"
|
|
line.long 0x10 "HCINTERRUPTDISABLE,HC interrupt disable"
|
|
bitfld.long 0x10 31. " MIE ,Master interrupt enable" "No effect,Disable"
|
|
bitfld.long 0x10 6. " RHSC ,Root hyb status change" "No effect,Disable"
|
|
bitfld.long 0x10 5. " FNO ,Frame number overflow" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x10 4. " UE ,Unrecoverable error" "No effect,Disable"
|
|
bitfld.long 0x10 3. " RD ,Resume detected" "No effect,Disable"
|
|
bitfld.long 0x10 2. " SF ,Start of frame" "No effect,Disable"
|
|
textline " "
|
|
bitfld.long 0x10 1. " WDH ,Write done head" "No effect,Disable"
|
|
bitfld.long 0x10 0. " SO ,Scheduling overrun" "No effect,Disable"
|
|
line.long 0x14 "HCHCCA,Physical address of HCCA"
|
|
hexmask.long.tbyte 0x14 8.--31. 1. " HCCA ,Physical address of the beginning of the HCCA"
|
|
line.long 0x18 "HCPERIODCURRENTED,Physical address of current periodic endpoint descriptor"
|
|
hexmask.long.long 0x18 4.--31. 1. " PCED ,Physical address of current ED on the periodic ED list"
|
|
line.long 0x1c "HCCONTROLHEADED,Physical address of head of control endpoint descriptor list"
|
|
hexmask.long.long 0x1c 4.--31. 1. " CHED ,Physical address of head ED on the control ED list"
|
|
line.long 0x20 "HCCONTROLCURRENTED,Physical address of current control endpoint descriptor"
|
|
hexmask.long.long 0x20 4.--31. 1. " CCED ,Physical address of current ED on the control ED list"
|
|
line.long 0x24 "HCBULKHEADED,Physical address of head of bulk endpoint descriptor list"
|
|
hexmask.long.long 0x24 4.--31. 1. " BHED ,Physical address of head ED on the bulk ED list"
|
|
line.long 0x28 "HCBULKCURRENTED,Physical of current bulk endpoint descriptor"
|
|
hexmask.long.long 0x28 4.--31. 1. " BCED ,Physical address of current ED on the bulk ED list"
|
|
rgroup.long 0x30++0x3
|
|
line.long 0x00 "HCDONEHEAD ,Physical address of head of list of retired transfer descriptors"
|
|
hexmask.long 0x00 4.--31. 1. " HC ,Physical address of the last TD that has added to the done queue"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "HCFMINTERVAL,HC frame interval"
|
|
bitfld.long 0x00 31. " FIT ,Frame interval toggle" "0,1"
|
|
hexmask.long 0x00 16.--30. 1. " FSMPS ,Largest data packet"
|
|
hexmask.long 0x00 0.--13. 1. " FI ,Frame interval"
|
|
rgroup.long 0x38++0x7
|
|
line.long 0x00 "HCFMREMAINING,HC frame remaining"
|
|
bitfld.long 0x00 31. " FRT ,Frame remaining toggle" "0,1"
|
|
hexmask.long.word 0x00 0.--13. 1. " FR ,Frame remaining"
|
|
line.long 0x04 "HCFMNUMBER,HC frame number"
|
|
hexmask.long.word 0x04 0.--15. 1. " FN ,Frame number"
|
|
rgroup.long 0x40++0xF
|
|
line.long 0x00 "HCPERIODICSTART,HC periodic start"
|
|
hexmask.long 0x00 0.--13. 1. " PS ,Periodic start"
|
|
line.long 0x04 "HCLSTHRESHOLD,HC low speed threshold"
|
|
hexmask.long 0x04 0.--13. 1. " LST ,Low-speed threshold"
|
|
line.long 0x08 "HCRHDESCRIPTORA,HC root hub A"
|
|
hexmask.long.byte 0x08 24.--31. 1. " POTPG ,Power-on to power-good time"
|
|
bitfld.long 0x08 12. " NOCP ,No overcurrent protection" "Protection,No protection"
|
|
bitfld.long 0x08 11. " OCPM ,Overcurrent protection mode" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 10. " DT ,Device type" "0,1"
|
|
bitfld.long 0x08 9. " NPS ,No power switching" "Switching,No switchinog"
|
|
bitfld.long 0x08 8. " PSM ,Power switching mode" "Simultanous,Individual"
|
|
textline " "
|
|
hexmask.long.byte 0x08 0.--7. 1. " NDP ,Number of downstream ports"
|
|
line.long 0x0c "HCRHDESCRIPTORB,HC root hub B"
|
|
bitfld.long 0x0c 19. " PPCM3 ,Port power control mask for downstream port 3" "0,1"
|
|
bitfld.long 0x0c 18. " PPCM2 ,Port power control mask for downstream port 2" "0,1"
|
|
bitfld.long 0x0c 17. " PPCM1 ,Port power control mask for downstream port 1" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " DR3 ,Device removable bit for downstream port 3" "Removable,Non-removable"
|
|
bitfld.long 0x0c 2. " DR3 ,Device removable bit for downstream port 2" "Removable,Non-removable"
|
|
bitfld.long 0x0c 1. " DR3 ,Device removable bit for downstream port 1" "Removable,Non-removable"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "HCRHSTATUS,HC root hub status"
|
|
bitfld.long 0x00 31. " CRWE ,Clear remote wake-up enable" "No effect,Clear"
|
|
eventfld.long 0x00 17. " OCIC ,Overcurrent indication change" "No effect,Clear"
|
|
bitfld.long 0x00 16. " LPSC ,Local power status change" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DRWE ,Device remote wake-up enable" "No effect,Set"
|
|
bitfld.long 0x00 1. " OCI ,Overcurrent indicator" "Not sensed,Sensed"
|
|
bitfld.long 0x00 0. " LPS ,Local power status" "No effect,Turn off"
|
|
group.long 0x54++0x0b
|
|
line.long 0x00 "HCRHPORTSTATUS1,HC port 1 control and status"
|
|
eventfld.long 0x00 20. " PRSC ,Port 1 reset status change" "Not changed,Changed"
|
|
eventfld.long 0x00 19. " OCIC ,Port 1 overcurrent indicator change" "Not changed,Changed"
|
|
eventfld.long 0x00 18. " PSSC ,Port 1 suspend status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x00 17. " PESC ,Port 1 enable status change" "Not changed,Changed"
|
|
eventfld.long 0x00 16. " CSC ,Port 1 connect status change" "Not changed,Changed"
|
|
bitfld.long 0x00 9. " LSDA ,Port 1 low-speed device attached" "Full-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PPS ,Port 1 port power status" "Not enabled,Enabled"
|
|
bitfld.long 0x00 4. " PRS ,Port 1 port reset status" "No reset,USB reset"
|
|
bitfld.long 0x00 3. " POCI ,Port 1 port overcurrent indicator" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PSS ,Port 1 port suspend status" "No suspend,Suspend"
|
|
bitfld.long 0x00 1. " PES ,Port 1 port enable status" "Not enabled,Enabled"
|
|
bitfld.long 0x00 0. " CCS ,Port 1 current connection status" "Not connected,Connected"
|
|
line.long 0x04 "HCRHPORTSTATUS2,HC port 2 control and status"
|
|
eventfld.long 0x04 20. " PRSC ,Port 2 reset status change" "Not changed,Changed"
|
|
eventfld.long 0x04 19. " OCIC ,Port 2 overcurrent indicator change" "Not changed,Changed"
|
|
eventfld.long 0x04 18. " PSSC ,Port 2 suspend status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x04 17. " PESC ,Port 2 enable status change" "Not changed,Changed"
|
|
eventfld.long 0x04 16. " CSC ,Port 2 connect status change" "Not changed,Changed"
|
|
bitfld.long 0x04 9. " LSDA ,Port 2 low-speed device attached" "Full-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x04 8. " PPS ,Port 2 port status" "Not enabled,Enabled"
|
|
bitfld.long 0x04 4. " PRS ,Port 2 port reset status" "No reset,USB reset"
|
|
bitfld.long 0x04 3. " POCI ,Port 2 port overcurrent indicator" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x04 2. " PSS ,Port 2 port suspend status" "No suspend,Suspend"
|
|
bitfld.long 0x04 1. " PES ,Port 2 port enable status" "Not enabled,Enabled"
|
|
bitfld.long 0x04 0. " CCS ,Port 2 current connection status" "Not connected,Connected"
|
|
line.long 0x08 "HCRHPORTSTATUS3,HC port 3 control and status"
|
|
eventfld.long 0x08 20. " PRSC ,Port 3 reset status change" "Not changed,Changed"
|
|
eventfld.long 0x08 19. " OCIC ,Port 3 overcurrent indicator change" "Not changed,Changed"
|
|
eventfld.long 0x08 18. " PSSC ,Port 3 suspend status change" "Not changed,Changed"
|
|
textline " "
|
|
eventfld.long 0x08 17. " PESC ,Port 3 enable status change" "Not changed,Changed"
|
|
eventfld.long 0x08 16. " CSC ,Port 3 connect status change" "Not changed,Changed"
|
|
bitfld.long 0x08 9. " LSDA ,Port 3 low-speed device attached" "Full-speed,Low-speed"
|
|
textline " "
|
|
bitfld.long 0x08 8. " PPS ,Port 3 port status" "Not enabled,Enabled"
|
|
bitfld.long 0x08 4. " PRS ,Port 3 port reset status" "No reset,USB reset"
|
|
bitfld.long 0x08 3. " POCI ,Port 3 port overcurrent indicator" "No overcurrent,Overcurrent"
|
|
textline " "
|
|
bitfld.long 0x08 2. " PSS ,Port 3 port suspend status" "No suspend,Suspend"
|
|
bitfld.long 0x08 1. " PES ,Port 3 port enable status" "Not enabled,Enabled"
|
|
bitfld.long 0x08 0. " CCS ,Port 3 current connection status" "Not connected,Connected"
|
|
rgroup.long 0xE0++0x7
|
|
line.long 0x00 "HOSTUEADDR,Host UE address"
|
|
line.long 0x04 "HOSTUESTATUS,Host UE status"
|
|
bitfld.long 0x04 0. " UEACCESS ,Access type when unrecoverable error occured" "Read,Write"
|
|
group.long 0xE8++0x3
|
|
line.long 0x00 "HOSTTIMEOUTCTRL,Host time-out control"
|
|
bitfld.long 0x00 0. " TO_DIS ,OCPI bus time-out disable" "Enabled,Disabled"
|
|
rgroup.long 0xEC++0x3
|
|
line.long 0x00 "HOSTREVISION,Host revision"
|
|
bitfld.long 0x00 4.--7. " MAJORREV ,Major Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. " MINORREV ,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
base AD:0xFFFB4000
|
|
tree "USB Device Controller Registers"
|
|
width 5.
|
|
rgroup.word 0x00++0x1
|
|
line.word 0x00 "REV,Revision"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REV_NB ,Indicates revision number of current USB device controller"
|
|
tree "Endpoint"
|
|
width 12.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "EP_NUM,Endpoint selection"
|
|
bitfld.word 0x00 6. " SETUP_SEL ,FIFO select bit" "No access,Access permitted"
|
|
bitfld.word 0x00 5. " EP_SEL ,TX/RX FIFO select bit" "No access,Access permitted"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EP_DIR ,Endpoint direction bit" "Out,In"
|
|
bitfld.word 0x00 0.--3. " EP_NUM ,Endpoint number" "EP0,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
if ((data.word(AD:0xFFFB4004)&0x10)==0x0)
|
|
hgroup.word 0x08++0x01
|
|
hide.word 0x00 "DATA,Data Receive"
|
|
in
|
|
else
|
|
wgroup.word 0x08++0x01
|
|
line.word 0x00 "DATA,Data Transmit"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "CTRL,Control"
|
|
bitfld.word 0x00 7. " CLR_HALT ,Clear halt endpoint (non-ISO) bit" "No action,Clear halt"
|
|
bitfld.word 0x00 6. " SET_HALT ,Set halt endpoint (non-ISO) bit" "No action,Halt endpoint"
|
|
textline " "
|
|
bitfld.word 0x00 2. " SET_FIFO_EN ,Set FIFO enable (non-ISO) bit" "No action,FIFO enabled"
|
|
bitfld.word 0x00 1. " CLR_EP ,Clear endpoint" "No action,Clear endpoint"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RESET_EP ,Reset endpoint" "No action,Reset endpoint"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "STAT_FLG,Status"
|
|
bitfld.word 0x00 15. " NO_RXPACKET ,Isochronous no packet received" "Received,Not received"
|
|
bitfld.word 0x00 14. " MISS_IN ,Isochronous missed IN token for the previous frame (ISO IN) bit" "Received,Not received"
|
|
textline " "
|
|
bitfld.word 0x00 13. " DATA_FLUSH ,Isochronous receive data flush (ISO OUT) bit" "Not significant,Data was flushed"
|
|
bitfld.word 0x00 12. " ISO_ERR ,Isochronous receive data error (ISO OUT)" "Not significant,Errors"
|
|
textline " "
|
|
bitfld.word 0x00 9. " ISO_FIFO_EMPTY ,ISO FIFO empty bit" "Not empty,Empty"
|
|
bitfld.word 0x00 8. " ISO_FIFO_FULL ,ISO FIFO full bit" "Not full,Full"
|
|
textline " "
|
|
bitfld.word 0x00 6. " EP_HALTED ,ENdpoint halted flag (non-ISO) bit" "Not halted,Halted"
|
|
bitfld.word 0x00 5. " STALL ,Transaction stall (non-ISO) bit" "No STALL handshake,STALL handshake"
|
|
textline " "
|
|
bitfld.word 0x00 4. " NAK ,Transaction non-acknowledge (non-ISO) bit" "No NAK handshake,NAK handshake"
|
|
bitfld.word 0x00 3. " ACK ,Transaction acknowledge (non-ISO) bit" "No ACK handshake,ACK handshake"
|
|
textline " "
|
|
bitfld.word 0x00 2. " FIFO_EN ,FIFO enable status (non-ISO) bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " NON_ISO_FIFO_EMPTY ,Non-ISO FIFO empty bit" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " NON_ISO_FIFO_FULL ,Non-ISO FIFO full bit" "Not full,Full"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "RXFSTAT,Receive FIFO status"
|
|
hexmask.word 0x00 0.--9. 1. " RXF_COUNT ,Receive FIFO byte count"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "SYSCON1,System configuration 1"
|
|
bitfld.word 0x00 8. " CFG_LOCK ,Device configuration loacked bit" "Not locked,Locked"
|
|
bitfld.word 0x00 7. " DATA_ENDIAN ,Data endian bit" "Little endian,Big endian"
|
|
textline " "
|
|
bitfld.word 0x00 6. " DMA_ENDIAN ,DMA data endian bit" "Little endian,Big endian"
|
|
bitfld.word 0x00 4. " NAK_EN ,NAK enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " AUTODEC_DIS ,Autocode process disabled" "Activated,Deactivated"
|
|
bitfld.word 0x00 2. " SELF_PWR ,Self-powered bit" "Bus powered,Self-powered"
|
|
textline " "
|
|
bitfld.word 0x00 1. " SOFF_DIS ,Shutoff disable bit" "Enabled,Disabled"
|
|
bitfld.word 0x00 0. " PULLUP_EN ,External pullup enable bit" "Disabled,Enabled"
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "SYSCON2,System configuration 2"
|
|
bitfld.word 0x00 6. " RMT_WKP ,Set-only remote wake-up bit" "No action,Initiate sequence"
|
|
bitfld.word 0x00 5. " STALL_CMD ,Set-only stall command bit" "No action,Stall"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DEV_CFG ,Device configured bit; Allow DEVSTAT.CFG to be set" "No action,Allow"
|
|
bitfld.word 0x00 2. " CLR_CFG ,Clear configured bit; Allow DEVSTAT.CFG to be cleared" "No action,Allow"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "DEVSTAT,Device status"
|
|
bitfld.word 0x00 9. " B_HNP_ENABLE ,HNP enable for B-device bit" "Not significant,Enabled"
|
|
bitfld.word 0x00 8. " A_HNP_SUPPORT ,B-device connection to HNP capable A-device" "Not significant,Connected"
|
|
textline " "
|
|
bitfld.word 0x00 7. " A_ALT_HNP_SUPPORT ,B-device connection to not HNP capable A-device" "Not significant,Connected"
|
|
bitfld.word 0x00 6. " R_WK_OK ,Remote wake-up granted bit" "Not significant,Granted"
|
|
textline " "
|
|
bitfld.word 0x00 5. " USB_RESET ,USB reset signaling is active" "No reset,Reset"
|
|
bitfld.word 0x00 4. " SUS ,Suspended state bit" "Not suspended,Suspended"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CFG ,Configured state bit" "Not configured,Configured"
|
|
bitfld.word 0x00 2. " ADD ,Addressed state bit" "Not addressed,Addressed"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DEF ,Default State bit" "Not in default,Default"
|
|
bitfld.word 0x00 0. " ATI ,Attached state bit" "Not attached,Attached"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "SOF,Start of frame"
|
|
bitfld.word 0x00 12. " FT_LOCK ,Frame timer locked bit" "Not locked,Locked"
|
|
bitfld.word 0x00 11. " TS_OK ,Timestamp OK bit" "TS invalid,TS valid"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " TS ,Timestamp number field"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "IRQ_EN,Interrupt enable"
|
|
bitfld.word 0x00 7. " SOF_IE ,Start of frame interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " EPN_RX_IE ,Receive endpoint n interrupt enable (non-ISO)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " EPN_TX_IE ,Transmit endpoint n interrupt enable (non-ISO)" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " DS_CHG_IE ,Device state chaged interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " EP0_IE ,EP0 transactions interrupt enable" "Disabled,Enabled"
|
|
group.word 0x2c++0x1
|
|
line.word 0x00 "DMA_IRQ_EN,DMA interrupt enable"
|
|
bitfld.word 0x00 10. " TX2_DONE_IE ,Tranmit DMA channel 2 done interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RX2_CNT_IE ,Receivce DMA channel 2 transactions count interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RX2_EOT_IE ,Receive DMA channel 2 end of transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TX1_DONE_IE ,Transmit DMA channel 1 done interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " RX1_CNT_IE ,Receive DMA channel 1 transactions count interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RX1_EOT_IE ,Receive DMA channel 1 end of transfer interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " TX0_DONE_IE ,Transmit DMA channel 0 done interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RX0_CNT_IE ,Receive DMA channel 0 transactions count interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RX0_EOT_IE ,Receive DMA channel 0 end of transfer interrupt enable" "Disabled,Enabled"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "IRQ_SRC,Interrupt source"
|
|
bitfld.word 0x00 10. " TXN_DONE ,Transmit DMA channel n done interrupt flag (non-ISO) bit" "No action,Done"
|
|
bitfld.word 0x00 9. " RXN_CNT ,Receive DMA channel n transactions count interrupt flag (non-ISO) bit" "No action,Reached level"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RXN_EOT ,Receive DMA channel n end of transfer interrupt flag (non-ISO) bit" "No action,Ended"
|
|
bitfld.word 0x00 7. " SOF ,Start of frame interrupt flag" "No action,SOF received"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EPN_RX ,EPn OUT transactions interrupt flag (non-ISO) bit" "No action,Detected"
|
|
bitfld.word 0x00 4. " EPN_TX ,EPn IN transactions interrupt flag (non-ISO) bit" "No action,Detected"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DS_CHG ,Device state changed interrupt flag bit" "No action,Detected"
|
|
bitfld.word 0x00 2. " SETUP ,Setup transaction interrupt flag bit" "No action,A valid one occured"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EP0_RX ,EP0 OUT transactions interrupt flag bit" "No action,Transaction"
|
|
bitfld.word 0x00 0. " EP0_TX ,EP0 IN transactions interrupt flag bit" "No action,Transaction"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x00 "EPN_STAT,Non-ISO endpoint interrupt enable"
|
|
bitfld.word 0x00 8.--11. " EPN_RX_IT_SRC ,Receive endpoint interrupt source (non-ISO)" "None is pending,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
bitfld.word 0x00 0.--3. " EPN_RX_IT_SRC ,Transmit endpoint interrupt source (non-ISO)" "None is pending,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
rgroup.word 0x38++0x1
|
|
line.word 0x00 "DMAN_STAT,Non-ISO DMA interrupt enable"
|
|
bitfld.word 0x00 12. " DMAN_RX_SB ,DMA receive single byte (non-ISO) bit" "No EOT DMA,EOT DMA"
|
|
bitfld.word 0x00 8.--11. " DMAN_RX_IT_SRC ,DMA receive interrupt source (non-ISO) bit" "None is pending,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " DMAN_TX_IT_SRC ,DMA transmit interrupt source" "None is pending,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
tree.end
|
|
tree "DMA Configuration"
|
|
width 11.
|
|
group.word 0x40++0x2b
|
|
line.word 0x00 "RXDMA_CFG,DMA receive channels configuration"
|
|
bitfld.word 0x00 12. " RX_REQ ,RX DMA request active level or pulse bit" "Level,Pulse"
|
|
bitfld.word 0x00 8.--11. " RXDMA2_EP ,Receive endpoint number from DMA channel 2" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " RXDMA1_EP ,Receive endpoint number for DMA channel 1" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
bitfld.word 0x00 0.--3. " RXDMA0_EP ,Receive endpoint number for DMA channel 0" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "TXDMA_CFG,DMA transmit channels configuration"
|
|
bitfld.word 0x00 12. " TX_REQ ,TX DMA request active level or pulse bit" "Level,Pulse"
|
|
bitfld.word 0x00 8.--11. " TXDMA2_EP ,Transmit endpoint number for DMA channel 2" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " TXDMA1_EP ,Transmit endpoint number for DMA channel 1" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
bitfld.word 0x00 0.--3. " TXDMA0_EP ,Transmit endpoint number for DMA channel 0" "Deactivated,EP1,EP2,EP3,EP4,EP5,EP6,EP7,EP8,EP9,EP10,EP11,EP12,EP13,EP14,EP15"
|
|
hgroup.word 0x48++0x1
|
|
hide.word 0x00 "DATA_DMA,DMA FIFO data"
|
|
in
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TXDMA0,Transmit DMA control 0"
|
|
bitfld.word 0x00 15. " TXN_EOT ,Transmit DMA channel n end of transfer" "Buffers,Bytes"
|
|
bitfld.word 0x00 14. " TXN_START ,Transmit DMA channel n start" "No action,Start"
|
|
textline " "
|
|
hexmask.word.word 0x00 0.--9. 1. " TXN_TSC ,Transmit DMA channel n transfer size counter"
|
|
group.word 0x54++0x1
|
|
line.word 0x00 "TXDMA1,Transmit DMA control 1"
|
|
bitfld.word 0x00 15. " TXN_EOT ,Transmit DMA channel n end of transfer" "Buffers,Bytes"
|
|
bitfld.word 0x00 14. " TXN_START ,Transmit DMA channel n start" "No action,Start"
|
|
textline " "
|
|
hexmask.word.word 0x00 0.--9. 1. " TXN_TSC ,Transmit DMA channel n transfer size counter"
|
|
group.word 0x58++0x1
|
|
line.word 0x00 "TXDMA2,Transmit DMA control 2"
|
|
bitfld.word 0x00 15. " TXN_EOT ,Transmit DMA channel n end of transfer" "Buffers,Bytes"
|
|
bitfld.word 0x00 14. " TXN_START ,Transmit DMA channel n start" "No action,Start"
|
|
textline " "
|
|
hexmask.word.word 0x00 0.--9. 1. " TXN_TSC ,Transmit DMA channel n transfer size counter"
|
|
group.word 0x60++0x1
|
|
line.word 0x00 "RXDMA0,Receive DMA control 0"
|
|
bitfld.word 0x00 15. " RXN_STOP ,Receive DMA channel n transfer stop" "No stop,Stop"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXN_TC ,Receive DMA channel n transactions count"
|
|
group.word 0x64++0x1
|
|
line.word 0x00 "RXDMA1,Receive DMA control 1"
|
|
bitfld.word 0x00 15. " RXN_STOP ,Receive DMA channel n transfer stop" "No stop,Stop"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXN_TC ,Receive DMA channel n transactions count"
|
|
group.word 0x68++0x1
|
|
line.word 0x00 "RXDMA2,Receive DMA control 2"
|
|
bitfld.word 0x00 15. " RXN_STOP ,Receive DMA channel n transfer stop" "No stop,Stop"
|
|
hexmask.word.byte 0x00 0.--7. 1. " RXN_TC ,Receive DMA channel n transactions count"
|
|
tree.end
|
|
tree "Endpoint Configuration"
|
|
width 9.
|
|
group.word 0x80++0x1
|
|
line.word 0x00 "EP0,Endpoint configuration 0"
|
|
bitfld.word 0x00 12.--13. " EP0_SIZE ,Endpoint 0 FIFO size" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
hexmask.word 0x00 0.--10. 1. " EP0_PTR "
|
|
if (d.w(ad:0xFFFB4084)&0x800)==0x800
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "EP1_RX,Receive endpoint configuration 1"
|
|
bitfld.word 0x00 15. " EP1_RX_VALID ,Receive endpoint 1 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 1 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP1_RX_SIZE ,Non-ISO receive endpoint 1 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP1_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP1_RX_PTR ,Receive endpoint 1 pointer"
|
|
else
|
|
group.word 0x84++0x1
|
|
line.word 0x00 "EP1_RX,Receive endpoint configuration 1"
|
|
bitfld.word 0x00 15. " EP1_RX_VALID ,Receive endpoint 1 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP1_RX_SIZE ,ISO receive endpoint 1 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP1_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP1_RX_PTR ,Receive endpoint 1 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB4088)&0x800)==0x800
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "EP2_RX,Receive endpoint configuration 2"
|
|
bitfld.word 0x00 15. " EP2_RX_VALID ,Receive endpoint 2 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 2 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP2_RX_SIZE ,Non-ISO receive endpoint 2 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP2_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP2_RX_PTR ,Receive endpoint 2 pointer"
|
|
else
|
|
group.word 0x88++0x1
|
|
line.word 0x00 "EP2_RX,Receive endpoint configuration 2"
|
|
bitfld.word 0x00 15. " EP2_RX_VALID ,Receive endpoint 2 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP2_RX_SIZE ,ISO receive endpoint 2 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP2_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP2_RX_PTR ,Receive endpoint 2 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB408C)&0x800)==0x800
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "EP3_RX,Receive endpoint configuration 3"
|
|
bitfld.word 0x00 15. " EP3_RX_VALID ,Receive endpoint 3 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 3 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP3_RX_SIZE ,Non-ISO receive endpoint 3 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP3_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP3_RX_PTR ,Receive endpoint 3 pointer"
|
|
else
|
|
group.word 0x8C++0x1
|
|
line.word 0x00 "EP3_RX,Receive endpoint configuration 3"
|
|
bitfld.word 0x00 15. " EP3_RX_VALID ,Receive endpoint 3 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP3_RX_SIZE ,ISO receive endpoint 3 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP3_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP3_RX_PTR ,Receive endpoint 3 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB4090)&0x800)==0x800
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "EP4_RX,Receive endpoint configuration 4"
|
|
bitfld.word 0x00 15. " EP4_RX_VALID ,Receive endpoint 4 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 4 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP4_RX_SIZE ,Non-ISO receive endpoint 4 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP4_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP4_RX_PTR ,Receive endpoint 4 pointer"
|
|
else
|
|
group.word 0x90++0x1
|
|
line.word 0x00 "EP4_RX,Receive endpoint configuration 4"
|
|
bitfld.word 0x00 15. " EP4_RX_VALID ,Receive endpoint 4 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP4_RX_SIZE ,ISO receive endpoint 4 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP4_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP4_RX_PTR ,Receive endpoint 4 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB4094)&0x800)==0x800
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "EP5_RX,Receive endpoint configuration 5"
|
|
bitfld.word 0x00 15. " EP5_RX_VALID ,Receive endpoint 5 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 5 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP5_RX_SIZE ,Non-ISO receive endpoint 5 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP5_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP5_RX_PTR ,Receive endpoint 5 pointer"
|
|
else
|
|
group.word 0x94++0x1
|
|
line.word 0x00 "EP5_RX,Receive endpoint configuration 5"
|
|
bitfld.word 0x00 15. " EP5_RX_VALID ,Receive endpoint 5 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP5_RX_SIZE ,ISO receive endpoint 5 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP5_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP5_RX_PTR ,Receive endpoint 5 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB4098)&0x800)==0x800
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "EP6_RX,Receive endpoint configuration 6"
|
|
bitfld.word 0x00 15. " EP6_RX_VALID ,Receive endpoint 6 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 6 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP6_RX_SIZE ,Non-ISO receive endpoint 6 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP6_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP6_RX_PTR ,Receive endpoint 6 pointer"
|
|
else
|
|
group.word 0x98++0x1
|
|
line.word 0x00 "EP6_RX,Receive endpoint configuration 6"
|
|
bitfld.word 0x00 15. " EP6_RX_VALID ,Receive endpoint 6 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP6_RX_SIZE ,ISO receive endpoint 6 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP6_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP6_RX_PTR ,Receive endpoint 6 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB409C)&0x800)==0x800
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "EP7_RX,Receive endpoint configuration 7"
|
|
bitfld.word 0x00 15. " EP7_RX_VALID ,Receive endpoint 7 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 7 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP7_RX_SIZE ,Non-ISO receive endpoint 7 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP7_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP7_RX_PTR ,Receive endpoint 7 pointer"
|
|
else
|
|
group.word 0x9C++0x1
|
|
line.word 0x00 "EP7_RX,Receive endpoint configuration 7"
|
|
bitfld.word 0x00 15. " EP7_RX_VALID ,Receive endpoint 7 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP7_RX_SIZE ,ISO receive endpoint 7 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP7_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP7_RX_PTR ,Receive endpoint 7 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40A0)&0x800)==0x800
|
|
group.word 0xA0++0x1
|
|
line.word 0x00 "EP8_RX,Receive endpoint configuration 8"
|
|
bitfld.word 0x00 15. " EP8_RX_VALID ,Receive endpoint 8 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 8 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP8_RX_SIZE ,Non-ISO receive endpoint 8 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP8_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP8_RX_PTR ,Receive endpoint 8 pointer"
|
|
else
|
|
group.word 0xA0++0x1
|
|
line.word 0x00 "EP8_RX,Receive endpoint configuration 8"
|
|
bitfld.word 0x00 15. " EP8_RX_VALID ,Receive endpoint 8 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP8_RX_SIZE ,ISO receive endpoint 8 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP8_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP8_RX_PTR ,Receive endpoint 8 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40A4)&0x800)==0x800
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "EP9_RX,Receive endpoint configuration 9"
|
|
bitfld.word 0x00 15. " EP9_RX_VALID ,Receive endpoint 9 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 9 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP9_RX_SIZE ,Non-ISO receive endpoint 9 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP9_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP9_RX_PTR ,Receive endpoint 9 pointer"
|
|
else
|
|
group.word 0xA4++0x1
|
|
line.word 0x00 "EP9_RX,Receive endpoint configuration 9"
|
|
bitfld.word 0x00 15. " EP9_RX_VALID ,Receive endpoint 9 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP9_RX_SIZE ,ISO receive endpoint 9 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP9_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP9_RX_PTR ,Receive endpoint 9 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40A8)&0x800)==0x800
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "EP10_RX,Receive endpoint configuration 10"
|
|
bitfld.word 0x00 15. " EP10_RX_VALID ,Receive endpoint 10 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 10 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP10_RX_SIZE ,Non-ISO receive endpoint 10 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP10_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP10_RX_PTR ,Receive endpoint 10 pointer"
|
|
else
|
|
group.word 0xA8++0x1
|
|
line.word 0x00 "EP10_RX,Receive endpoint configuration 10"
|
|
bitfld.word 0x00 15. " EP10_RX_VALID ,Receive endpoint 10 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP10_RX_SIZE ,ISO receive endpoint 10 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP10_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP10_RX_PTR ,Receive endpoint 10 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40AC)&0x800)==0x800
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "EP11_RX,Receive endpoint configuration 11"
|
|
bitfld.word 0x00 15. " EP11_RX_VALID ,Receive endpoint 11 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 11 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP11_RX_SIZE ,Non-ISO receive endpoint 11 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP11_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP11_RX_PTR ,Receive endpoint 11 pointer"
|
|
else
|
|
group.word 0xAC++0x1
|
|
line.word 0x00 "EP11_RX,Receive endpoint configuration 11"
|
|
bitfld.word 0x00 15. " EP11_RX_VALID ,Receive endpoint 11 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP11_RX_SIZE ,ISO receive endpoint 11 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP11_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP11_RX_PTR ,Receive endpoint 11 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40B0)&0x800)==0x800
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "EP12_RX,Receive endpoint configuration 12"
|
|
bitfld.word 0x00 15. " EP12_RX_VALID ,Receive endpoint 12 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 12 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP12_RX_SIZE ,Non-ISO receive endpoint 12 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP12_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP12_RX_PTR ,Receive endpoint 12 pointer"
|
|
else
|
|
group.word 0xB0++0x1
|
|
line.word 0x00 "EP12_RX,Receive endpoint configuration 12"
|
|
bitfld.word 0x00 15. " EP12_RX_VALID ,Receive endpoint 12 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP12_RX_SIZE ,ISO receive endpoint 12 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP12_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP12_RX_PTR ,Receive endpoint 12 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40B4)&0x800)==0x800
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "EP13_RX,Receive endpoint configuration 13"
|
|
bitfld.word 0x00 15. " EP13_RX_VALID ,Receive endpoint 13 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 13 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP13_RX_SIZE ,Non-ISO receive endpoint 13 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP13_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP13_RX_PTR ,Receive endpoint 13 pointer"
|
|
else
|
|
group.word 0xB4++0x1
|
|
line.word 0x00 "EP13_RX,Receive endpoint configuration 13"
|
|
bitfld.word 0x00 15. " EP13_RX_VALID ,Receive endpoint 13 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP13_RX_SIZE ,ISO receive endpoint 13 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP13_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP13_RX_PTR ,Receive endpoint 13 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40B8)&0x800)==0x800
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "EP14_RX,Receive endpoint configuration 14"
|
|
bitfld.word 0x00 15. " EP14_RX_VALID ,Receive endpoint 14 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 14 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP14_RX_SIZE ,Non-ISO receive endpoint 14 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP14_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP14_RX_PTR ,Receive endpoint 14 pointer"
|
|
else
|
|
group.word 0xB8++0x1
|
|
line.word 0x00 "EP14_RX,Receive endpoint configuration 14"
|
|
bitfld.word 0x00 15. " EP14_RX_VALID ,Receive endpoint 14 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP14_RX_SIZE ,ISO receive endpoint 14 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP14_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP14_RX_PTR ,Receive endpoint 14 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40BC)&0x800)==0x800
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "EP15_RX,Receive endpoint configuration 15"
|
|
bitfld.word 0x00 15. " EP15_RX_VALID ,Receive endpoint 15 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Receive non-ISO endpoint 15 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP15_RX_SIZE ,Non-ISO receive endpoint 15 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP15_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP15_RX_PTR ,Receive endpoint 15 pointer"
|
|
else
|
|
group.word 0xBC++0x1
|
|
line.word 0x00 "EP15_RX,Receive endpoint configuration 15"
|
|
bitfld.word 0x00 15. " EP15_RX_VALID ,Receive endpoint 15 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP15_RX_SIZE ,ISO receive endpoint 15 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP15_RX_ISO ,Receive ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP15_RX_PTR ,Receive endpoint 15 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40C4)&0x800)==0x800
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "EP1_TX,Transmit endpoint configuration 1"
|
|
bitfld.word 0x00 15. " EP1_TX_VALID ,Trasnmit endpoint 1 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 1 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP1_TX_SIZE ,Non-ISO transmit endpoint 1 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP1_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP1_TX_PTR ,Trasmit endpoint 1 pointer"
|
|
else
|
|
group.word 0xC4++0x1
|
|
line.word 0x00 "EP1_TX,Transmit endpoint configuration 1"
|
|
bitfld.word 0x00 15. " EP1_TX_VALID ,Transmit endpoint 1 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP1_TX_SIZE ,ISO transmit endpoint 1 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP1_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP1_TX_PTR ,Transmit endpoint 1 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40C8)&0x800)==0x800
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "EP2_TX,Transmit endpoint configuration 2"
|
|
bitfld.word 0x00 15. " EP2_TX_VALID ,Trasnmit endpoint 2 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 2 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP2_TX_SIZE ,Non-ISO transmit endpoint 2 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP2_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP2_TX_PTR ,Trasmit endpoint 2 pointer"
|
|
else
|
|
group.word 0xC8++0x1
|
|
line.word 0x00 "EP2_TX,Transmit endpoint configuration 2"
|
|
bitfld.word 0x00 15. " EP2_TX_VALID ,Transmit endpoint 2 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP2_TX_SIZE ,ISO transmit endpoint 2 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP2_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP2_TX_PTR ,Transmit endpoint 2 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40CC)&0x800)==0x800
|
|
group.word 0xCC++0x1
|
|
line.word 0x00 "EP3_TX,Transmit endpoint configuration 3"
|
|
bitfld.word 0x00 15. " EP3_TX_VALID ,Trasnmit endpoint 3 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 3 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP3_TX_SIZE ,Non-ISO transmit endpoint 3 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP3_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP3_TX_PTR ,Trasmit endpoint 3 pointer"
|
|
else
|
|
group.word 0xCC++0x1
|
|
line.word 0x00 "EP3_TX,Transmit endpoint configuration 3"
|
|
bitfld.word 0x00 15. " EP3_TX_VALID ,Transmit endpoint 3 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP3_TX_SIZE ,ISO transmit endpoint 3 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP3_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP3_TX_PTR ,Transmit endpoint 3 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40D0)&0x800)==0x800
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "EP4_TX,Transmit endpoint configuration 4"
|
|
bitfld.word 0x00 15. " EP4_TX_VALID ,Trasnmit endpoint 4 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 4 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP4_TX_SIZE ,Non-ISO transmit endpoint 4 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP4_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP4_TX_PTR ,Trasmit endpoint 4 pointer"
|
|
else
|
|
group.word 0xD0++0x1
|
|
line.word 0x00 "EP4_TX,Transmit endpoint configuration 4"
|
|
bitfld.word 0x00 15. " EP4_TX_VALID ,Transmit endpoint 4 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP4_TX_SIZE ,ISO transmit endpoint 4 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP4_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP4_TX_PTR ,Transmit endpoint 4 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40D4)&0x800)==0x800
|
|
group.word 0xD4++0x1
|
|
line.word 0x00 "EP5_TX,Transmit endpoint configuration 5"
|
|
bitfld.word 0x00 15. " EP5_TX_VALID ,Trasnmit endpoint 5 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 5 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP5_TX_SIZE ,Non-ISO transmit endpoint 5 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP5_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP5_TX_PTR ,Trasmit endpoint 5 pointer"
|
|
else
|
|
group.word 0xD4++0x1
|
|
line.word 0x00 "EP5_TX,Transmit endpoint configuration 5"
|
|
bitfld.word 0x00 15. " EP5_TX_VALID ,Transmit endpoint 5 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP5_TX_SIZE ,ISO transmit endpoint 5 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP5_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP5_TX_PTR ,Transmit endpoint 5 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40D8)&0x800)==0x800
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "EP6_TX,Transmit endpoint configuration 6"
|
|
bitfld.word 0x00 15. " EP6_TX_VALID ,Trasnmit endpoint 6 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 6 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP6_TX_SIZE ,Non-ISO transmit endpoint 6 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP6_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP6_TX_PTR ,Trasmit endpoint 6 pointer"
|
|
else
|
|
group.word 0xD8++0x1
|
|
line.word 0x00 "EP6_TX,Transmit endpoint configuration 6"
|
|
bitfld.word 0x00 15. " EP6_TX_VALID ,Transmit endpoint 6 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP6_TX_SIZE ,ISO transmit endpoint 6 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP6_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP6_TX_PTR ,Transmit endpoint 6 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40DC)&0x800)==0x800
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "EP7_TX,Transmit endpoint configuration 7"
|
|
bitfld.word 0x00 15. " EP7_TX_VALID ,Trasnmit endpoint 7 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 7 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP7_TX_SIZE ,Non-ISO transmit endpoint 7 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP7_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP7_TX_PTR ,Trasmit endpoint 7 pointer"
|
|
else
|
|
group.word 0xDC++0x1
|
|
line.word 0x00 "EP7_TX,Transmit endpoint configuration 7"
|
|
bitfld.word 0x00 15. " EP7_TX_VALID ,Transmit endpoint 7 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP7_TX_SIZE ,ISO transmit endpoint 7 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP7_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP7_TX_PTR ,Transmit endpoint 7 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40E0)&0x800)==0x800
|
|
group.word 0xE0++0x1
|
|
line.word 0x00 "EP8_TX,Transmit endpoint configuration 8"
|
|
bitfld.word 0x00 15. " EP8_TX_VALID ,Trasnmit endpoint 8 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 8 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP8_TX_SIZE ,Non-ISO transmit endpoint 8 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP8_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP8_TX_PTR ,Trasmit endpoint 8 pointer"
|
|
else
|
|
group.word 0xE0++0x1
|
|
line.word 0x00 "EP8_TX,Transmit endpoint configuration 8"
|
|
bitfld.word 0x00 15. " EP8_TX_VALID ,Transmit endpoint 8 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP8_TX_SIZE ,ISO transmit endpoint 8 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP8_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP8_TX_PTR ,Transmit endpoint 8 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40E4)&0x800)==0x800
|
|
group.word 0xE4++0x1
|
|
line.word 0x00 "EP9_TX,Transmit endpoint configuration 9"
|
|
bitfld.word 0x00 15. " EP9_TX_VALID ,Trasnmit endpoint 9 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 9 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP9_TX_SIZE ,Non-ISO transmit endpoint 9 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP9_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP9_TX_PTR ,Trasmit endpoint 9 pointer"
|
|
else
|
|
group.word 0xE4++0x1
|
|
line.word 0x00 "EP9_TX,Transmit endpoint configuration 9"
|
|
bitfld.word 0x00 15. " EP9_TX_VALID ,Transmit endpoint 9 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP9_TX_SIZE ,ISO transmit endpoint 9 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP9_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP9_TX_PTR ,Transmit endpoint 9 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40E8)&0x800)==0x800
|
|
group.word 0xE8++0x1
|
|
line.word 0x00 "EP10_TX,Transmit endpoint configuration 10"
|
|
bitfld.word 0x00 15. " EP10_TX_VALID ,Trasnmit endpoint 10 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 10 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP10_TX_SIZE ,Non-ISO transmit endpoint 10 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP10_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP10_TX_PTR ,Trasmit endpoint 10 pointer"
|
|
else
|
|
group.word 0xE8++0x1
|
|
line.word 0x00 "EP10_TX,Transmit endpoint configuration 10"
|
|
bitfld.word 0x00 15. " EP10_TX_VALID ,Transmit endpoint 10 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP10_TX_SIZE ,ISO transmit endpoint 10 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP10_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP10_TX_PTR ,Transmit endpoint 10 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40EC)&0x800)==0x800
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "EP11_TX,Transmit endpoint configuration 11"
|
|
bitfld.word 0x00 15. " EP11_TX_VALID ,Trasnmit endpoint 11 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 11 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP11_TX_SIZE ,Non-ISO transmit endpoint 11 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP11_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP11_TX_PTR ,Trasmit endpoint 11 pointer"
|
|
else
|
|
group.word 0xEC++0x1
|
|
line.word 0x00 "EP11_TX,Transmit endpoint configuration 11"
|
|
bitfld.word 0x00 15. " EP11_TX_VALID ,Transmit endpoint 11 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP11_TX_SIZE ,ISO transmit endpoint 11 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP11_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP11_TX_PTR ,Transmit endpoint 11 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40F0)&0x800)==0x800
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "EP12_TX,Transmit endpoint configuration 12"
|
|
bitfld.word 0x00 15. " EP12_TX_VALID ,Trasnmit endpoint 12 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 12 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP12_TX_SIZE ,Non-ISO transmit endpoint 12 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP12_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP12_TX_PTR ,Trasmit endpoint 12 pointer"
|
|
else
|
|
group.word 0xF0++0x1
|
|
line.word 0x00 "EP12_TX,Transmit endpoint configuration 12"
|
|
bitfld.word 0x00 15. " EP12_TX_VALID ,Transmit endpoint 12 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP12_TX_SIZE ,ISO transmit endpoint 12 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP12_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP12_TX_PTR ,Transmit endpoint 12 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40F4)&0x800)==0x800
|
|
group.word 0xF4++0x1
|
|
line.word 0x00 "EP13_TX,Transmit endpoint configuration 13"
|
|
bitfld.word 0x00 15. " EP13_TX_VALID ,Trasnmit endpoint 13 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 13 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP13_TX_SIZE ,Non-ISO transmit endpoint 13 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP13_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP13_TX_PTR ,Trasmit endpoint 13 pointer"
|
|
else
|
|
group.word 0xF4++0x1
|
|
line.word 0x00 "EP13_TX,Transmit endpoint configuration 13"
|
|
bitfld.word 0x00 15. " EP13_TX_VALID ,Transmit endpoint 13 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP13_TX_SIZE ,ISO transmit endpoint 13 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP13_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP13_TX_PTR ,Transmit endpoint 13 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40F8)&0x800)==0x800
|
|
group.word 0xF8++0x1
|
|
line.word 0x00 "EP14_TX,Transmit endpoint configuration 14"
|
|
bitfld.word 0x00 15. " EP14_TX_VALID ,Trasnmit endpoint 14 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 14 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP14_TX_SIZE ,Non-ISO transmit endpoint 14 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP14_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP14_TX_PTR ,Trasmit endpoint 14 pointer"
|
|
else
|
|
group.word 0xF8++0x1
|
|
line.word 0x00 "EP14_TX,Transmit endpoint configuration 14"
|
|
bitfld.word 0x00 15. " EP14_TX_VALID ,Transmit endpoint 14 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP14_TX_SIZE ,ISO transmit endpoint 14 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP14_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP14_TX_PTR ,Transmit endpoint 14 pointer"
|
|
endif
|
|
if (d.w(ad:0xFFFB40FC)&0x800)==0x800
|
|
group.word 0xFC++0x1
|
|
line.word 0x00 "EP15_TX,Transmit endpoint configuration 15"
|
|
bitfld.word 0x00 15. " EP15_TX_VALID ,Trasnmit endpoint 15 valid bit" "Not valid,Valid"
|
|
bitfld.word 0x00 14. " DB ,Transmit non-ISO endpoint 15 double-buffer (DB)" "No DB,DB used"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " EP15_TX_SIZE ,Non-ISO transmit endpoint 15 size field" "8 bytes,16 bytes,32 bytes,64 bytes"
|
|
bitfld.word 0x00 11. " EP15_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP15_TX_PTR ,Trasmit endpoint 15 pointer"
|
|
else
|
|
group.word 0xFC++0x1
|
|
line.word 0x00 "EP15_TX,Transmit endpoint configuration 15"
|
|
bitfld.word 0x00 15. " EP15_TX_VALID ,Transmit endpoint 15 valid bit" "Not valid,Valid"
|
|
textline " "
|
|
bitfld.word 0x00 12.--14. " EP15_TX_SIZE ,ISO transmit endpoint 15 size field" "8 bytes,16 bytes,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1023 bytes"
|
|
bitfld.word 0x00 11. " EP15_TX_ISO ,Transmit ISO endpoint" "Isochronous,Bulk/interrupt"
|
|
textline " "
|
|
hexmask.word 0x00 0.--10. 1. " EP15_TX_PTR ,Transmit endpoint 15 pointer"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
base AD:0xFFFB3000
|
|
tree "MICROWIRE Registers"
|
|
width 11.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "MWIRE_DR,MICROWIRE Data Register"
|
|
if (d.w(ad:0xFFFB3018)&0x4)==0x0
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "MWIRE_CSR,MICROWIRE Control And Status Register"
|
|
bitfld.word 0x00 15. " RDRB ,Receive (RDR) is full" "Not full,Full"
|
|
bitfld.word 0x00 14. " CSRB ,Control and Status (CSR) is ready to receive new data" "Not ready,Ready"
|
|
bitfld.word 0x00 13. " START ,Start a write and/or a read process" "Not start,Start"
|
|
textline " "
|
|
bitfld.word 0x00 12. " CS_CMD ,Set the chip-select of the selected device to its active level" "0,1"
|
|
bitfld.word 0x00 10.--11. " INDEX ,Index of the external device" "CS0,CS1,CS2,CS3"
|
|
bitfld.word 0x00 5.--9. " NB_BITS_WR ,Number of bits to transmit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " NB_BITS_RD ,Number of bits to receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "MWIRE_CSR,MICROWIRE Control And Status Register"
|
|
bitfld.word 0x00 15. " RDRB ,Receive (RDR) is full" "Not full,Full"
|
|
bitfld.word 0x00 14. " CSRB ,Control and Status (CSR) is ready to receive new data" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " INDEX ,Index of the external device" "CS0,CS1,CS2,CS3"
|
|
bitfld.word 0x00 5.--9. " NB_BITS_WR ,Number of bits to transmit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " NB_BITS_RD ,Number of bits to receive" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
if ((d.w(ad:0xFFFB3004)&0xC00)==0x000)&&((d.w(ad:0xFFFB3014)&0x1)==0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "MWIRE_SR1,MICROWIRE Setup Register For CS0 And CS1"
|
|
bitfld.word 0x00 5. " CS0_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 3.--4. " CS0_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 2. " CS0CS_LVL ,Defines the active level of the CS0 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CS0_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Falling,Rising"
|
|
bitfld.word 0x00 0. " CS0_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Falling,Rising"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0x000)&&((d.w(ad:0xFFFB3014)&0x1)==0x1)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "MWIRE_SR1,MICROWIRE Setup Register For CS0 And CS1"
|
|
bitfld.word 0x00 5. " CS0_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 3.--4. " CS0_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 2. " CS0CS_LVL ,Defines the active level of the CS0 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CS0_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Rising,Falling"
|
|
bitfld.word 0x00 0. " CS0_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Rising,Falling"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0x400)&&((d.w(ad:0xFFFB3014)&0x1)==0x0)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "MWIRE_SR1,MICROWIRE Setup Register For CS0 And CS1"
|
|
bitfld.word 0x00 11. " CS1_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 9.--10. " CS1_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 8. " CS1CS_LVL ,Defines the active level of the CS1 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CS1_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Falling,Rising"
|
|
bitfld.word 0x00 6. " CS1_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Falling,Rising"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0x400)&&((d.w(ad:0xFFFB3014)&0x1)==0x1)
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "MWIRE_SR1,MICROWIRE Setup Register For CS0 And CS1"
|
|
bitfld.word 0x00 11. " CS1_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 9.--10. " CS1_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 8. " CS1CS_LVL ,Defines the active level of the CS1 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CS1_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Rising,Falling"
|
|
bitfld.word 0x00 6. " CS1_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Rising,Falling"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0x800)&&((d.w(ad:0xFFFB3014)&0x1)==0x0)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "MWIRE_SR2,MICROWIRE Setup Register For CS2 And CS3"
|
|
bitfld.word 0x00 5. " CS2_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 3.--4. " CS2_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 2. " CS2CS_LVL ,Defines the active level of the CS0 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CS2_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Falling,Rising"
|
|
bitfld.word 0x00 0. " CS2_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Falling,Rising"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0x800)&&((d.w(ad:0xFFFB3014)&0x1)==0x1)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "MWIRE_SR2,MICROWIRE Setup Register For CS2 And CS3"
|
|
bitfld.word 0x00 5. " CS2_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 3.--4. " CS2_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 2. " CS2CS_LVL ,Defines the active level of the CS0 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CS2_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Rising,Falling"
|
|
bitfld.word 0x00 0. " CS2_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Rising,Falling"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0xC00)&&((d.w(ad:0xFFFB3014)&0x1)==0x0)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "MWIRE_SR2,MICROWIRE Setup Register For CS2 And CS3"
|
|
bitfld.word 0x00 11. " CS3_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 9.--10. " CS3_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 8. " CS3CS_LVL ,Defines the active level of the CS1 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CS3_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Falling,Rising"
|
|
bitfld.word 0x00 6. " CS3_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Falling,Rising"
|
|
elif ((d.w(ad:0xFFFB3004)&0xC00)==0xC00)&&((d.w(ad:0xFFFB3014)&0x1)==0x1)
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "MWIRE_SR2,MICROWIRE Setup Register For CS2 And CS3"
|
|
bitfld.word 0x00 11. " CS3_CHK ,Before activating a write process checks if external device is ready" "No check,Check"
|
|
bitfld.word 0x00 9.--10. " CS3_FRQ ,Defines the frequency of the serial clock SCLK" "F_INT/2,F_INT/4,FINT/8,Undefined"
|
|
bitfld.word 0x00 8. " CS3CS_LVL ,Defines the active level of the CS1 chip-select" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " CS3_EDGE_WR ,Defines the active edge of the serial clock SCLK used to write data to the serial output DO" "Rising,Falling"
|
|
bitfld.word 0x00 6. " CS3_EDGE_RD ,Defines the active edge of the serial clock SCLK used to read data to the serial input DI" "Rising,Falling"
|
|
endif
|
|
if (d.w(ad:0xFFFB3010)&0x1)==0x0
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MWIRE_SR3,MICROWIRE Setup Register For Internal Clock"
|
|
bitfld.word 0x00 0. " CLK_EN ,Switch off/on the clock" "Off,On"
|
|
else
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "MWIRE_SR3,MICROWIRE Setup Register For Internal Clock"
|
|
bitfld.word 0x00 1.--2. " CK_FREQ ,Defines the frequency of the internal clock F_INT" "F/2,F/4,F/7,F/10"
|
|
bitfld.word 0x00 0. " CLK_EN ,Switch off/on the clock" "Off,On"
|
|
endif
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "MWIRE_SR4,MICROWIRE Setup Register For Clock Polarity"
|
|
bitfld.word 0x00 0. " CLK_IN ,Invert the serial clock" "Not invert,Invert"
|
|
if (d.w(ad:0xFFFB3018)&0x4)==0x0
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "MWIRE_SR5,MICROWIRE Setup Register For Transmit Mode"
|
|
bitfld.word 0x00 2. " AUTO_TX_EN ,Enable autotransmit mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IT_EN ,Generate an interrupt each time a word has been transfered or received" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_TX_EN ,Enable DMA transmit mode" "Disabled,Enabled"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "MWIRE_SR5,MICROWIRE Setup Register For Transmit Mode"
|
|
bitfld.word 0x00 3. " CS_TOGGLE_TX_EN ,Enable CS_toggle" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " AUTO_TX_EN ,Enable autotransmit mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " IT_EN ,Generate an interrupt each time a word has been transfered or received" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " DMA_TX_EN ,Enable DMA transmit mode" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
base AD:0xFFFB4800
|
|
tree "Real-Time Clock (RTC) Registers"
|
|
width 20.
|
|
group.byte 0x00++0x0
|
|
line.byte 0x00 "SECONDS_REG,RTC Seconds Register"
|
|
bitfld.byte 0x00 4.--7. " SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,?..."
|
|
bitfld.byte 0x00 0.--3. " SEC0 ,1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "MINUTES_REG,RTC Minutes Register"
|
|
bitfld.byte 0x00 4.--7. " MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,?..."
|
|
bitfld.byte 0x00 0.--3. " MIN0 ,1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x08++0x0
|
|
line.byte 0x00 "HOURS_REG,RTC Hours Register"
|
|
bitfld.byte 0x00 7. " PM_/AM ,Only in PM_AM mode (otherwise 0)" "AM,PM"
|
|
textline " "
|
|
bitfld.byte 0x00 4.--6. " HOUR1 ,2nd digit of hours" "0,1,2,?..."
|
|
bitfld.byte 0x00 0.--3. " HOUR0 ,1st digit of hours" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x0c++0x0
|
|
line.byte 0x00 "DAYS_REG,RTC Days Register"
|
|
bitfld.byte 0x00 4.--7. " DAY1 ,2nd digit of days" "0,1,2,3,?..."
|
|
bitfld.byte 0x00 0.--3. " DAY0 ,1st digit of days" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x10++0x0
|
|
line.byte 0x00 "MONTHS_REG,RTC Months Register"
|
|
bitfld.byte 0x00 4.--7. " MONTH1 ,2nd digit of months" "0,1,?..."
|
|
bitfld.byte 0x00 0.--3. " MONTH0 ,1st digit of months" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x14++0x0
|
|
line.byte 0x00 "YEARS_REG,RTC Years Register"
|
|
bitfld.byte 0x00 4.--7. " YEAR1 ,2nd digit of years" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
bitfld.byte 0x00 0.--3. " YEAR0 ,1st digit of years" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "WEEKS_REG,RTC Weeks Register"
|
|
bitfld.byte 0x00 0.--3. " WEEK ,1st digit of days in week" "0,1,2,3,4,5,6,?..."
|
|
group.byte 0x20++0x0
|
|
line.byte 0x00 "ALARM_SECONDS_REG,RTC Alarm Seconds Register"
|
|
bitfld.byte 0x00 4.--7. " ALARM_SEC1 ,2nd digit of seconds" "0,1,2,3,4,5,?..."
|
|
bitfld.byte 0x00 0.--3. " ALARM_SEC0 ,1st digit of seconds" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x24++0x0
|
|
line.byte 0x00 "ALARM_MINUTES_REG,RTC Alarm Minutes Register"
|
|
bitfld.byte 0x00 4.--7. " ALARM_MIN1 ,2nd digit of minutes" "0,1,2,3,4,5,?..."
|
|
bitfld.byte 0x00 0.--3. " ALARM_MIN0 ,1st digit of minutes" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x28++0x0
|
|
line.byte 0x00 "ALARM_HOURS_REG,RTC Alarm Hours Register"
|
|
bitfld.byte 0x00 7. " ALARM_PM_/AM ,Only in PM_AM mode (otherwise 0)" "AM,PM"
|
|
textline " "
|
|
bitfld.byte 0x00 4.--6. " ALARM_HOUR1 ,2nd digit of hours" "0,1,2,?..."
|
|
bitfld.byte 0x00 0.--3. " ALARM_HOUR0 ,1st digit of hours" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x2c++0x0
|
|
line.byte 0x00 "ALARM_DAYS_REG,RTC Alarm Days Register"
|
|
bitfld.byte 0x00 4.--7. " ALARM_DAY1 ,2nd digit of days" "0,1,2,3,?..."
|
|
bitfld.byte 0x00 0.--3. " ALARM_DAY0 ,1st digit of days" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x30++0x0
|
|
line.byte 0x00 "ALARM_MONTHS_REG,RTC Alarm Months Register"
|
|
bitfld.byte 0x00 4.--7. " ALARM_MONTH1 ,2nd digit of months" "0,1,?..."
|
|
bitfld.byte 0x00 0.--3. " ALARM_MONTH0 ,1st digit of months" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x34++0x0
|
|
line.byte 0x00 "ALARM_YEARS_REG,RTC Alarm Years Register"
|
|
bitfld.byte 0x00 4.--7. " ALARM_YEAR1 ,2nd digit of years" "0,1,2,3,4,5,6,7,8,9,?..."
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|
bitfld.byte 0x00 0.--3. " ALARM_YEAR0 ,1st digit of years" "0,1,2,3,4,5,6,7,8,9,?..."
|
|
group.byte 0x40++0x0
|
|
line.byte 0x00 "RTC_CTRL_REG,RTC Control Register"
|
|
bitfld.byte 0x00 7. " /SPLIT_POWER ,Can use split power" "Cannot,Can"
|
|
bitfld.byte 0x00 6. " RTC_DISABLE ,Disable RTC" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " SET_32_COUNTER ,Set the 32-kHz counter with COMP_REG value" "No action,Set"
|
|
bitfld.byte 0x00 4. " TEST_MODE ," "Functional,Test"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MODE_12_24 ," "24-hour,12-hour (PM/AM)"
|
|
bitfld.byte 0x00 2. " AUTO_COMP ,Enable autocompensation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " ROUND_30S ,Round the time to the closest minute" "Not round,Round"
|
|
bitfld.byte 0x00 0. " STOP_RTC ,RTC is frozen/running" "Frozen,Running"
|
|
group.byte 0x44++0x0
|
|
line.byte 0x00 "RTC_STATUS_REG,RTC Status Register"
|
|
bitfld.byte 0x00 7. " POWER_UP ,A reset has occured" "No reset,Reset"
|
|
bitfld.byte 0x00 6. " ALARM ,An alarm interrupt has been generated" "No alarm,Alarm"
|
|
textline " "
|
|
bitfld.byte 0x00 5. " 1D_EVENT ,One day has occured" "Not occured,Occured"
|
|
bitfld.byte 0x00 4. " 1H_EVENT ,One hour has occured" "Not occured,Occured"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " 1M_EVENT ,One minute has occured" "Not occured,Occured"
|
|
bitfld.byte 0x00 2. " 1S_EVENT ,One second has occured" "Not occured,Occured"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " RUN ,RTC is frozen/running" "Frozen,Running"
|
|
bitfld.byte 0x00 0. " BUSY ,Updating event in more than 15us" ">15us,Now"
|
|
group.byte 0x48++0x0
|
|
line.byte 0x00 "RTC_INTERRUPTS_REG,RTC Interrupts Register"
|
|
bitfld.byte 0x00 3. " IT_ALARM ,Enable one interrupt when the alarm value is reached (time and calendar alarm registers) by the time and calendar registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " IT_TIMER ,Enable periodic interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " EVERY ,Interrupt period" "Second,Minute,Hour,Day"
|
|
group.byte 0x4c++0x0
|
|
line.byte 0x00 "RTC_COMP_LSB_REG,RTC Compensation LSB Register"
|
|
group.byte 0x50++0x0
|
|
line.byte 0x00 "RTC_COMP_MSB_REG,RTC Compensation MSB Register"
|
|
group.byte 0x54++0x0
|
|
line.byte 0x00 "RTC_OSC_REG,RTC Oscillator Register"
|
|
bitfld.byte 0x00 4. " OSC32K_PWRDN ,Control of 32-kHz oscillator power down" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--3. " SW_RES_PROG ,Value of the oscillator resistance" "0,1,2,3,4,5,6,7,?..."
|
|
tree.end
|
|
base AD:0xFFFB5000
|
|
tree "MPUIO (Keyboard Included) Registers"
|
|
width 13.
|
|
rgroup.word 0x00++0x1
|
|
line.word 0x00 "INPUT_LATCH,MPUIO General Purpose Input Register"
|
|
bitfld.word 0x00 15. " INPUT_LATCH15 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 14. " INPUT_LATCH14 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 13. " INPUT_LATCH13 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 12. " INPUT_LATCH12 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 11. " INPUT_LATCH11 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 10. " INPUT_LATCH10 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 9. " INPUT_LATCH9 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 8. " INPUT_LATCH8 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " INPUT_LATCH7 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 6. " INPUT_LATCH6 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 5. " INPUT_LATCH5 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 4. " INPUT_LATCH4 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " INPUT_LATCH3 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 2. " INPUT_LATCH2 ,General-purpose input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INPUT_LATCH1 ,General-purpose input" "Low,High"
|
|
bitfld.word 0x00 0. " INPUT_LATCH0 ,General-purpose input" "Low,High"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "OUTPUT,MPUIO General Purpose Output Register"
|
|
bitfld.word 0x00 15. " OUTPUT_REG15 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 14. " OUTPUT_REG14 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 13. " OUTPUT_REG13 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 12. " OUTPUT_REG12 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OUTPUT_REG11 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 10. " OUTPUT_REG10 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 9. " OUTPUT_REG9 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 8. " OUTPUT_REG8 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OUTPUT_REG7 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 6. " OUTPUT_REG6 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 5. " OUTPUT_REG5 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 4. " OUTPUT_REG4 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OUTPUT_REG3 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 2. " OUTPUT_REG2 ,General purpose output" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OUTPUT_REG1 ,General purpose output" "Low,High"
|
|
bitfld.word 0x00 0. " OUTPUT_REG0 ,General purpose output" "Low,High"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "IO_CNTL,MPUIO In/Out Control Register for General-Purpose I/O"
|
|
bitfld.word 0x00 15. " IO_CNTL15 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 14. " IO_CNTL14 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 13. " IO_CNTL13 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 12. " IO_CNTL12 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 11. " IO_CNTL11 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 10. " IO_CNTL10 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 9. " IO_CNTL9 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 8. " IO_CNTL8 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 7. " IO_CNTL7 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 6. " IO_CNTL6 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 5. " IO_CNTL5 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 4. " IO_CNTL4 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 3. " IO_CNTL3 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 2. " IO_CNTL2 ,In/out control for general-purpose I/O" "Output,Input"
|
|
textline " "
|
|
bitfld.word 0x00 1. " IO_CNTL1 ,In/out control for general-purpose I/O" "Output,Input"
|
|
bitfld.word 0x00 0. " IO_CNTL0 ,In/out control for general-purpose I/O" "Output,Input"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x00 "KBR_LATCH,MPUIO Keyboard Row Input Register"
|
|
bitfld.word 0x00 7. " KBR_LATCH7 ,Keyboard row input" "Low,High"
|
|
bitfld.word 0x00 6. " KBR_LATCH6 ,Keyboard row input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 5. " KBR_LATCH5 ,Keyboard row input" "Low,High"
|
|
bitfld.word 0x00 4. " KBR_LATCH4 ,Keyboard row input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " KBR_LATCH3 ,Keyboard row input" "Low,High"
|
|
bitfld.word 0x00 2. " KBR_LATCH2 ,Keyboard row input" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " KBR_LATCH1 ,Keyboard row input" "Low,High"
|
|
bitfld.word 0x00 0. " KBR_LATCH0 ,Keyboard row input" "Low,High"
|
|
group.word 0x14++0x1
|
|
line.word 0x00 "KBC,MPUIO Keyboard Column Output Register"
|
|
bitfld.word 0x00 7. " KBC_REG7 ,Keyboard column outputs" "Low,Z"
|
|
bitfld.word 0x00 6. " KBC_REG6 ,Keyboard column outputs" "Low,Z"
|
|
textline " "
|
|
bitfld.word 0x00 5. " KBC_REG5 ,Keyboard column outputs" "Low,Z"
|
|
bitfld.word 0x00 4. " KBC_REG4 ,Keyboard column outputs" "Low,Z"
|
|
textline " "
|
|
bitfld.word 0x00 3. " KBC_REG3 ,Keyboard column outputs" "Low,Z"
|
|
bitfld.word 0x00 2. " KBC_REG2 ,Keyboard column outputs" "Low,Z"
|
|
textline " "
|
|
bitfld.word 0x00 1. " KBC_REG1 ,Keyboard column outputs" "Low,Z"
|
|
bitfld.word 0x00 0. " KBC_REG0 ,Keyboard column outputs" "Low,Z"
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "GPIO_EVENT,MPUIO GPIO Event Mode Register"
|
|
bitfld.word 0x00 1.--4. " PIN_SELECT ,Select MPUIO_IN[15:0] pin to be the MPUIO_CLK event" "Pin 0,Pin 1,Pin 2,Pin 3,Pin 4,Pin 5,Pin 6,Pin 7,Pin 8,Pin 9,Pin 10,Pin 11,Pin 12,Pin 13,Pin 14,Pin 15"
|
|
bitfld.word 0x00 0. " SET_EVENT_MODE ," "Disabled,Enabled"
|
|
group.word 0x1c++0x1
|
|
line.word 0x00 "GPIO_EDGE,MPUIO GPIO Interrupt Egde Register"
|
|
bitfld.word 0x00 15. " EDGE_SELECT15 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 14. " EDGE_SELECT14 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 13. " EDGE_SELECT13 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 12. " EDGE_SELECT12 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 11. " EDGE_SELECT11 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 10. " EDGE_SELECT10 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 9. " EDGE_SELECT9 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 8. " EDGE_SELECT8 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 7. " EDGE_SELECT7 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 6. " EDGE_SELECT6 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 5. " EDGE_SELECT5 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 4. " EDGE_SELECT4 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 3. " EDGE_SELECT3 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 2. " EDGE_SELECT2 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
textline " "
|
|
bitfld.word 0x00 1. " EDGE_SELECT1 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
bitfld.word 0x00 0. " EDGE_SELECT0 ,Set interrupt on falling/rising edge" "Falling,Rising"
|
|
rgroup.word 0x20++0x1
|
|
line.word 0x00 "KBD_INT,MPUIO Keyboard Interrupt Register"
|
|
bitfld.word 0x00 0. " KBD_INT ,Keyboard interrupt" "Occured,None pending"
|
|
rgroup.word 0x24++0x1
|
|
line.word 0x00 "GPIO_INT,MPUIO GPIO Interrupt Register"
|
|
bitfld.word 0x00 15. " INT15 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 14. " INT14 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 13. " INT13 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 12. " INT12 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 11. " INT11 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 10. " INT10 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 9. " INT9 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 8. " INT8 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 7. " INT7 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 6. " INT6 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 5. " INT5 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 4. " INT4 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 3. " INT3 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 2. " INT2 ,MPUIO interrupt" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 1. " INT1 ,MPUIO interrupt" "No,Yes"
|
|
bitfld.word 0x00 0. " INT0 ,MPUIO interrupt" "No,Yes"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "KBD_MASKIT,MPUIO Keyboard Interrupt Mask Register"
|
|
bitfld.word 0x00 0. " KBD_MASKIT ," "Inactive,Active"
|
|
group.word 0x2c++0x1
|
|
line.word 0x00 "GPIO_MASKIT,MPUIO GPIO Interrupt Mask Register"
|
|
bitfld.word 0x00 15. " MASKIT15 ," "Inactive,Active"
|
|
bitfld.word 0x00 14. " MASKIT14 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 13. " MASKIT13 ," "Inactive,Active"
|
|
bitfld.word 0x00 12. " MASKIT12 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 11. " MASKIT11 ," "Inactive,Active"
|
|
bitfld.word 0x00 10. " MASKIT10 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 9. " MASKIT9 ," "Inactive,Active"
|
|
bitfld.word 0x00 8. " MASKIT8 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MASKIT7 ," "Inactive,Active"
|
|
bitfld.word 0x00 6. " MASKIT6 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 5. " MASKIT5 ," "Inactive,Active"
|
|
bitfld.word 0x00 4. " MASKIT4 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 3. " MASKIT3 ," "Inactive,Active"
|
|
bitfld.word 0x00 2. " MASKIT2 ," "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 1. " MASKIT1 ," "Inactive,Active"
|
|
bitfld.word 0x00 0. " MASKIT0 ," "Inactive,Active"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "GPIO_DBNC,MPUIO GPIO Debouncing Register"
|
|
hexmask.word 0x00 0.--8. 1. " DEBOUNCING_REG ,0-511 cycles of T32k (32.5 us) debouncing time"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x00 "GPIO_LATCH,MPUIO GPIO Latch Register"
|
|
bitfld.word 0x00 15. " LATCH_REGISTER15 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 14. " LATCH_REGISTER14 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 13. " LATCH_REGISTER13 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 12. " LATCH_REGISTER12 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 11. " LATCH_REGISTER11 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 10. " LATCH_REGISTER10 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 9. " LATCH_REGISTER9 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 8. " LATCH_REGISTER8 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LATCH_REGISTER7 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 6. " LATCH_REGISTER6 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 5. " LATCH_REGISTER5 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 4. " LATCH_REGISTER4 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LATCH_REGISTER3 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 2. " LATCH_REGISTER2 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 1. " LATCH_REGISTER1 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
bitfld.word 0x00 0. " LATCH_REGISTER0 ,After debouncing time the MPUIO_IN bus is latched in this register" "Low,High"
|
|
tree.end
|
|
tree "MPUI Port Registers"
|
|
base AD:0xE1020000
|
|
width 0x08
|
|
wgroup.word 0x0000++0x01
|
|
line.word 0x00 "APIRI,MPUI Port Interrupt Register"
|
|
bitfld.word 0x00 07. " MPU_IRQ[7] , Interrupt flag 7" "Interrupt,No interrupt"
|
|
bitfld.word 0x00 06. " MPU_IRQ[6] , Interrupt flag 6" "Interrupt,No interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 05. " MPU_IRQ[5] , Interrupt flag 5" "Interrupt,No interrupt"
|
|
bitfld.word 0x00 04. " MPU_IRQ[4] , Interrupt flag 4" "Interrupt,No interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 03. " MPU_IRQ[3] , Interrupt flag 3" "Interrupt,No interrupt"
|
|
bitfld.word 0x00 02. " MPU_IRQ[2] , Interrupt flag 2" "Interrupt,No interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 01. " MPU_IRQ[1] , Interrupt flag 1" "Interrupt,No interrupt"
|
|
bitfld.word 0x00 00. " MPU_IRQ[0] , Interrupt flag 0" "Interrupt,No interrupt"
|
|
group.word 0x0002++0x01
|
|
line.word 0x00 "APIRS,MPUI Port Control/Status Register"
|
|
bitfld.word 0x00 03. " ENA_WPOST_APIRAM ,Enables posted write for writes to the MPUI port RAM" "Disabled,Enabled"
|
|
bitfld.word 0x00 01.--02. " SMOD[1:0] ,HOM or SAM setting for MPUI port RAM and DSP TIPB peripherals" "SAM for MPUI/DSP TIPB,HOM for DSP TIPB,HOM for MPUI,HOM for MPUI/DSP TIPB"
|
|
textline " "
|
|
bitfld.word 0x00 00. " ENA_WPOST_TIPB ,Enables posted write for writes to the DSP TIPB peripherals" "Disabled,Enabled"
|
|
tree.end
|
|
tree "MPUI Registers"
|
|
base AD:0xFFFEC900
|
|
width 0x14
|
|
group.long 0x0000++0x03
|
|
line.long 0x00 "MPUI_CONTROL,MPUI Control Register"
|
|
bitfld.long 0x00 21.--22. " WORD_SWAP_CTL ,Word swap control" "Turn on,Turn on for DSP TIPB/MPUI,Turn on for MPUI,Turn off"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " ACCESS_PRIORITY ,MPUI access priority between MPU/OCP-I/DMA requests" "MPU=1/DMA=2/OCP-I=3,MPU=1/DMA=3/OCP-I=2,MPU=2/DMA=1/OCP-I=3,MPU=2/DMA=3/OCP-I=1,MPU=1/DMA=2/OCP-I=3,MPU=3/DMA=1/OCP-I=2,MPU=3/DMA=2/OCP-I=1,MPU=3/DMA=1/OCP-I=2"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " BYTE_SWAP_CTL ,Byte swap control" "Turn off,Turn on for DSP TIPB/MPUI,Turn on,Turn on for MPUI"
|
|
textline " "
|
|
hexmask.long.byte 0x00 08.--15. 1. " TIMEOUT ,MPUI port peripherals access Time-Out"
|
|
textline " "
|
|
bitfld.long 0x00 04.--07. " ACCESS_FACTOR ,Division factor of MPUI output strobe signal from MPUI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 03. " API_ERR_EN ,Send MPUI port abort" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " TIMEOUT_EN ,Enable Time-Oout" "Disabled,Enabled"
|
|
rgroup.long 0x0004++0x13
|
|
line.long 0x00 "DEBUG_ADDRESS,Debug Address Register"
|
|
hexmask.long.tbyte 0x00 00.--23. 1. " ADR_SAV ,Saved address on abort or access size mismatch occurred"
|
|
line.long 0x04 "DEBUG_DATA,Debug Data Register"
|
|
hexmask.long 0x04 00.--31. 1. " DATA_SAV ,Saved data on read access size mismatch or write access aborted or write access size mismatch"
|
|
line.long 0x08 "DEBUG_FLAG,Debug Flag Register"
|
|
bitfld.long 0x08 13.--14. " HOST_ID ,Host ID for abort" "MPU,DMA,OCP-I,?..."
|
|
textline " "
|
|
bitfld.long 0x08 11.--12. " SMOD_SAV ,Access mode for MPUI port on abort" "Shared MPUI/Shared per,Shared MPUI/Host per,Host MPUI/Shared per,Host MPUI/Host per"
|
|
textline " "
|
|
bitfld.long 0x08 09.--10. " CS_SAV ,Chip-select on abort" "Reserved,MPUI,DSP TIPB/MPUI ctrl reg,?..."
|
|
textline " "
|
|
bitfld.long 0x08 06.--08. " BURST_SIZE_SAV ,Data burst size indicated from MPU core on abort" "1,Reserved,Reserved,4,?..."
|
|
textline " "
|
|
bitfld.long 0x08 05. " RNW_SAV ,Read or write transaction on the MPUI upon abort" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x08 04. " BYTE_SAV ,Data width of the MPUI port access upon abort" "8-bits,16-bits"
|
|
textline " "
|
|
bitfld.long 0x08 03. " BURST_SIZE_ERR ,Burst size error for MPU core" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 02. " TIMEOUT_ERR ,Time-Out Error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 01. " API_ERR ,MPUI port abort access error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x08 00. " ABORT_FLAG ,Abort status bit for MPUI access" "Not aborted,Aborted"
|
|
line.long 0x0C "MPUI_STATUS,MPUI Status Register"
|
|
bitfld.long 0x0C 11.--12. " ACCESS_STATUS ,Current access" "MPU,DMA,OCP-I,No access"
|
|
hexmask.long.byte 0x0C 03.--10. 1. " TIMEOUT_VAL ,Current value of Time-Out counter"
|
|
textline " "
|
|
bitfld.long 0x0C 02. " CS_EN ,MPUI busy status" "Busy,Not busy"
|
|
bitfld.long 0x0C 01. " ACCESS_DONE ,MPUI access status" "Not done,Done"
|
|
textline " "
|
|
bitfld.long 0x0C 00. " HOMNSAM_FLAG ,Current access mode" "SAM,HOM"
|
|
line.long 0x10 "DSP_STATUS,DSP Status Register"
|
|
bitfld.long 0x10 11. " HRHOMNSAM ,DSP HOM or SAM setting for DSP TIPB" "HOM,SAM"
|
|
bitfld.long 0x10 10. " HAHOMNSAM ,DSP HOM or SAM setting for MPUI port RAM" "HOM,SAM"
|
|
textline " "
|
|
bitfld.long 0x10 09. " PENRESETDPLL ,Level of asynchronous reset in the DSP" "Low,High"
|
|
bitfld.long 0x10 08. " PEIDLE7 ,Idle peripherals flag - bit 7 of ISTR from DSP" "No IDLE,IDLE"
|
|
textline " "
|
|
bitfld.long 0x10 07. " PEIDLE6 ,Idle peripherals flag - bit 6 of ISTR from DSP" "No IDLE,IDLE"
|
|
bitfld.long 0x10 06. " PEIDLEDPLL ,Idle DPLL flag - bit 4 of ISTR from DSP" "No IDLE,IDLE"
|
|
textline " "
|
|
bitfld.long 0x10 05. " PEIDLEPERIPH ,Idle peripherals flag - bit 3 of ISTR from DSP" "No IDLE,IDLE"
|
|
bitfld.long 0x10 04. " CPUIACK ,Level of Interrupt acknowledged signal from DSP" "Low,HIgh"
|
|
textline " "
|
|
bitfld.long 0x10 03. " CPUAVIS ,Level of Interrupt acknowledged signal" "Low,High"
|
|
bitfld.long 0x10 02. " CPUXF ,Level of XF output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x10 01. " RESET_MCU ,Level of the secondary DSP subsystem reset originating from the MPU" "Low,High"
|
|
bitfld.long 0x10 00. " RESET ,Level of DSP subsystem master reset" "Low,High"
|
|
group.long 0x0018++0x07
|
|
line.long 0x00 "DSP_BOOT_CONFIG,DSP Boot Configuration Register"
|
|
hexmask.long.byte 0x00 10.--15. 1. " BOOT_RHEA_PTR2 ,User-defined pointer"
|
|
hexmask.long.byte 0x00 04.--09. 1. " BOOT_RHEA_PTR1 ,User-defined pointer"
|
|
textline " "
|
|
bitfld.long 0x00 00.--03. " DSP_BOOT_MODE ,DSP boot mode inputs" "No boot,No boot,DSP=IDLE,16-bit boot,32-bit boot,MPUI boot,Internal boot,Internal boot,Internal boot,Internal boot,Internal boot,Internal boot,Internal boot,Internal boot,Internal boot,Internal boot"
|
|
line.long 0x04 "DSP_MPUI_CONFIG,MPUI Port RAM Configuration Register"
|
|
hexmask.long.word 0x04 00.--15. 1. " API_SIZE ,Grants the MPUI exclusive access to the specified portion of DSP SARAM in HOM"
|
|
rgroup.long 0x0020++0x03
|
|
line.long 0x00 "DSP_MISC,DSP Miscellaneous Register"
|
|
bitfld.long 0x00 08. " CPUBION ,Level of BION signal to DSP subsystem" "Low,High"
|
|
group.long 0x0024++0x03
|
|
line.long 0x00 "MPUI_ENHANCED_CTRL,MPUI Enhanced Control Register"
|
|
bitfld.long 0x00 00. " DPS_EN ,Enable dynamic power saving mode" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Pulse Width Registers"
|
|
width 12.
|
|
base AD:0xFFFB5800
|
|
group.byte 0x00++0x0 "Pulse Width Light (PWL) Registers"
|
|
line.byte 0x00 "PWL_LEVEL,PWL Level Register"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "PWL_CONTROL,PWL Control Register"
|
|
bitfld.byte 0x00 0. " CLK_ENABLE ,Internal clock enable" "Disabled,Enabled"
|
|
base AD:0xFFFB6000
|
|
if (d.b(ad:0xFFFB6000)&0x3)==0x0
|
|
group.byte 0x00++0x0 "Pulse Width Tone (PWT) Registers"
|
|
line.byte 0x00 "PWT_FCR,PWT Frequency Control Register"
|
|
bitfld.byte 0x00 2.--5. " FRQ ,Frequency selection" "4868 Hz e5,4595 Hz dis5,4337 Hz d5,4093 Hz cis5,3864 Hz c5,3647 Hz h4,3442 Hz ais4,3249 Hz a4,3066 Hz gis4,2894 Hz g4,2732 Hz fis4,2579 Hz f4,Illegal,Illegal,Illegal,Illegal"
|
|
bitfld.byte 0x00 0.--1. " OCT ,Octave selection" "4/5,3/4,2/3,1/2"
|
|
elif (d.b(ad:0xFFFB6000)&0x3)==0x1
|
|
group.byte 0x00++0x0 "Pulse Width Tone (PWT) Registers"
|
|
line.byte 0x00 "PWT_FCR,PWT Frequency Control Register"
|
|
bitfld.byte 0x00 2.--5. " FRQ ,Frequency selection" "2434 Hz e4,2297 Hz dis4,2168 Hz d4,2046 Hz cis4,1932 Hz c4,1824 Hz h3,1721 Hz ais3,1624 Hz a3,1533 Hz gis3,1447 Hz g3,1366 Hz fis3,1289 Hz f3,Illegal,Illegal,Illegal,Illegal"
|
|
bitfld.byte 0x00 0.--1. " OCT ,Octave selection" "4/5,3/4,2/3,1/2"
|
|
elif (d.b(ad:0xFFFB6000)&0x3)==0x2
|
|
group.byte 0x00++0x0 "Pulse Width Tone (PWT) Registers"
|
|
line.byte 0x00 "PWT_FCR,PWT Frequency Control Register"
|
|
bitfld.byte 0x00 2.--5. " FRQ ,Frequency selection" "1217 Hz e3,1149 Hz dis3,1084 Hz d3,1023 Hz cis3,966 Hz c3,912 Hz h2,860 Hz ais2,812 Hz a2,767 Hz gis2,723 Hz g2,683 Hz fis2,644 Hz f2,Illegal,Illegal,Illegal,Illegal"
|
|
bitfld.byte 0x00 0.--1. " OCT ,Octave selection" "4/5,3/4,2/3,1/2"
|
|
elif (d.b(ad:0xFFFB6000)&0x3)==0x3
|
|
group.byte 0x00++0x0 "Pulse Width Tone (PWT) Registers"
|
|
line.byte 0x00 "PWT_FCR,PWT Frequency Control Register"
|
|
bitfld.byte 0x00 2.--5. " FRQ ,Frequency selection" "608 Hz e2,574 Hz dis2,541 Hz d2,511 Hz cis2,483 Hz c2,456 Hz h1,430 Hz ais1,406 Hz a1,383 Hz gis1,361 Hz g1,341 Hz fis1,322 Hz f1,Illegal,Illegal,Illegal,Illegal"
|
|
bitfld.byte 0x00 0.--1. " OCT ,Octave selection" "4/5,3/4,2/3,1/2"
|
|
endif
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "PWT_VCR,PWT Volume Control Register"
|
|
bitfld.byte 0x00 1.--6. " VOL ,Volume selection" "0 - Quiet,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63 - Loud"
|
|
bitfld.byte 0x00 0. " ONOFF ,Switch ON/OFF tone" "Off,On"
|
|
group.byte 0x08++0x0
|
|
line.byte 0x00 "PWT_GCR,PWT General Control Register"
|
|
bitfld.byte 0x00 1. " TESTIN ,Divider 1/154 switched ON/OFF" "On,Off"
|
|
bitfld.byte 0x00 0. " CLK_EN ,PWT clock enable" "Disabled,Enabled"
|
|
tree.end
|
|
;base 0xFFFB7800
|
|
;%include mpu/mmc.ph 1
|
|
base AD:0xFFFB7800
|
|
width 0x10
|
|
tree "MMC/SDIO1"
|
|
if ((data.word(AD:0xFFFB7800+0x0C)&0x3000)==0x0)
|
|
group.word 0x0000++0x01
|
|
line.word 0x00 "MMC_CMD,MMC Command Register"
|
|
bitfld.word 0x00 15. " DDIR ,Data direction" "Write,Read"
|
|
bitfld.word 0x00 14. " SHR ,Stream command or broadcast host response (MMC valid)" "Normal,Stream"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TYPE ,Command type" "BC,BCR,AC,ADTC"
|
|
bitfld.word 0x00 11. " BUSY ,Command with busy response" "Without busy,With busy"
|
|
textline " "
|
|
bitfld.word 0x00 08.--10. " RSP ,Command responses" "No response,R1/R1b,R2,R3,R4,R5,R6,?..."
|
|
bitfld.word 0x00 07. " INAB ,Send initialization stream/data abort command" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 06. " ODTO ,Card open drain mode/extended command time-out mode" "Push-pull/CTO,Open drain/DTO"
|
|
bitfld.word 0x00 00.--05. " INDX ,Command index" "CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CMD8,CMD9,CMD10,CMD11,CMD12,CMD13,CMD14,CMD15,CMD16,CMD17,CMD18,CMD19,CMD20,CMD21,CMD22,CMD23,CMD24,CMD25,CMD26,CMD27,CMD28,CMD29,CMD30,CMD31,CMD32,CMD33,CMD34,CMD35,CMD36,CMD37,CMD38,CMD39,CMD40,CMD41,CMD42,CMD43,CMD44,CMD45,CMD46,CMD47,CMD48,CMD49,CMD50,CMD51,CMD52,CMD53,CMD54,CMD55,CMD56,CMD57,CMD58,CMD59,CMD60,CMD61,CMD62,CMD63"
|
|
elif ((data.word(AD:0xFFFB7800+0x0C)&0x3000)==0x1000)
|
|
group.word 0x0000++0x01
|
|
line.word 0x00 "SPI_DO,SPI Data Register"
|
|
hexmask.word 0x00 00.--15. 1. " DATA ,SPI data"
|
|
else
|
|
hgroup.word 0x0000++0x01
|
|
hide.word 0x00 "MMC_CMD/SPI_DO,MMC Command/SPI Data Register"
|
|
endif
|
|
group.word (0x0004)++0x01
|
|
line.word 0x00 "MMC_ARGL,System Argument Low Register"
|
|
hexmask.word 0x00 00.--15. 1. " ARGL ,Command argument bits [15:0]"
|
|
group.word (0x0008)++0x01
|
|
line.word 0x00 "MMC_ARGH,System Argument High Register"
|
|
hexmask.word 0x00 00.--15. 1. " ARGH ,Command argument bits [31:16]"
|
|
group.word (0x000C)++0x01
|
|
line.word 0x00 "MMC_CON,Module Configuration Register"
|
|
bitfld.word 0x00 15. " DW ,Data bus width (SD valid)" "1-bit,4-bit"
|
|
bitfld.word 0x00 12.--13. " MODE ,Operating mode select" "MMC/SD,SPI,SYSTEST,?..."
|
|
textline " "
|
|
bitfld.word 0x00 11. " POWER_UP ,Power-up control" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " BE ,Big-endian mode" "Little,Big"
|
|
textline " "
|
|
hexmask.word 0x00 00.--09. 1. " CLKD ,Clock divider"
|
|
if ((data.word(AD:0xFFFB7800+0x0C)&0x3000)==0x0)
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "MMC_STAT,Module Status Register"
|
|
eventfld.word 0x00 14. " CERR ,Card status error in response" "No error,Error"
|
|
eventfld.word 0x00 13. " CIRQ ,MMC card IRQ received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 12. " OCRB ,Operation condition register (OCR) busy" "Not busy,Busy"
|
|
eventfld.word 0x00 11. " AE ,Buffer almost empty" "Above almost,Almost"
|
|
textline " "
|
|
eventfld.word 0x00 10. " AF ,Buffer almost full" "Below almost,Almost"
|
|
eventfld.word 0x00 09. " CRW ,Card read wait (SDIO valid)" "No action,Wait"
|
|
textline " "
|
|
eventfld.word 0x00 08. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.word 0x00 07. " CTO ,Command response time-out" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 06. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.word 0x00 05. " DTO ,Data response time-out" "No action,Time-out"
|
|
textline " "
|
|
eventfld.word 0x00 04. " EOFB ,Card exit busy state" "No action,Busy"
|
|
eventfld.word 0x00 03. " BRS ,Block received/sent" "No action,Received/Sent"
|
|
textline " "
|
|
eventfld.word 0x00 02. " CB ,Card enter busy state" "No action,Busy"
|
|
eventfld.word 0x00 01. " CD ,Card detect on DAT3" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 00. " EOC ,End of command phase" "No action,EOC"
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " CERR ,Card status error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CIRQ ,Card IRQ interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " OCRB ,OCR busy interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AE ,Buffer almost empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " AF ,Buffer almost full interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 09. " CRW ,Card read wait enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 08. " CCRC ,Command CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 07. " CTO ,Command response time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 06. " DCRC ,Data CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " DTO ,Data response time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " EOFB ,Card exit busy state interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " BRS ,Block received/sent interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 02. " CB ,Card enter busy state interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 01. " CD ,Card-detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 00. " EOC ,End of command interrupt enable" "Disabled,Enabled"
|
|
elif ((data.word(AD:0xFFFB7800+0x0C)&0x3000)==0x1000)
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "MMC_STAT,Module Status Register"
|
|
eventfld.word 0x00 11. " AE ,Buffer almost empty" "Above almost,Almost"
|
|
eventfld.word 0x00 10. " AF ,Buffer almost full" "Below almost,Almost"
|
|
textline " "
|
|
eventfld.word 0x00 05. " DTO ,Data response time-out" "No action,Time-out"
|
|
eventfld.word 0x00 03. " BRS ,Block received/sent" "No action,Received/Sent"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
bitfld.word 0x00 11. " AE ,Buffer almost empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " AF ,Buffer almost full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 09. " CRW ,Card read wait enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " DTO ,Data response time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " BRS ,Block received/sent interrupt enable" "Disabled,Enabled"
|
|
elif ((data.word(AD:0xFFFB7800+0x0C)&0x3000)==0x1000)
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "MMC_STAT,Module Status Register"
|
|
eventfld.word 0x00 11. " AE ,Buffer almost empty" "Above almost,Almost"
|
|
eventfld.word 0x00 10. " AF ,Buffer almost full" "Below almost,Almost"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
bitfld.word 0x00 11. " AE ,Buffer almost empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " AF ,Buffer almost full interrupt enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.word (0x0010)++0x01
|
|
hide.word 0x00 "MMC_STAT,Module Status Register"
|
|
wgroup.word (0x0010)++0x01
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.word (0x0014)++0x01
|
|
hide.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
endif
|
|
if ((data.word(AD:0xFFFB7800+0x0C)&0x3000)==0x0)
|
|
group.word (0x0018)++0x01
|
|
line.word 0x00 "MMC_CTO,Command Time-Out Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " CTO ,MMC command time-out value"
|
|
else
|
|
hgroup.word (0x0018)++0x01
|
|
hide.word 0x00 "MMC_CTO,Command Time-Out Register"
|
|
endif
|
|
group.word (0x001C)++0x01
|
|
line.word 0x00 "MMC_DTO,Data Read Time-Out Register"
|
|
hexmask.word 0x00 00.--15. 1. " DTO ,Data read time-out"
|
|
hgroup.word (0x0020)++0x01
|
|
hide.word 0x00 "MMC_DATA,Data Access Register"
|
|
in
|
|
group.word (0x0024)++0x01
|
|
line.word 0x00 "MMC_BLEN,Block Length Register"
|
|
hexmask.word 0x00 00.--10. 1. " BLEN ,Block length value"
|
|
group.word (0x0028)++0x01
|
|
line.word 0x00 "MMC_NBLK,Number of Blocks Register"
|
|
hexmask.word 0x00 00.--10. 1. " NBLK ,Number of blocks value"
|
|
group.word (0x002C)++0x01
|
|
line.word 0x00 "MMC_BUF,Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RXDE ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 08.--12. " AFL ,Buffer almost full level" "2-byte,4-byte,6-byte,8-byte,10-byte,12-byte,14-byte,16-byte,18-byte,20-byte,22-byte,24-byte,26-byte,28-byte,30-byte,32-byte,34-byte,36-byte,38-byte,40-byte,42-byte,44-byte,46-byte,48-byte,50-byte,52-byte,54-byte,56-byte,58-byte,60-byte,62-byte,64-byte"
|
|
textline " "
|
|
bitfld.word 0x00 07. " TXDE ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 00.--04. " AEL ,Buffer almost empty level" "2-byte,4-byte,6-byte,8-byte,10-byte,12-byte,14-byte,16-byte,18-byte,20-byte,22-byte,24-byte,26-byte,28-byte,30-byte,32-byte,34-byte,36-byte,38-byte,40-byte,42-byte,44-byte,46-byte,48-byte,50-byte,52-byte,54-byte,56-byte,58-byte,60-byte,62-byte,64-byte"
|
|
group.word (0x0030)++0x01
|
|
line.word 0x00 "MMC_SPI,SPI Configuration Register"
|
|
bitfld.word 0x00 15. " STR ,Start SPI transfer" "No action,Started"
|
|
bitfld.word 0x00 14. " WNR ,Write/not read" "Read,Write"
|
|
textline " "
|
|
bitfld.word 0x00 13. " SODV ,SPI_SO serial out pin default value" "Low,High"
|
|
bitfld.word 0x00 12. " CSTR ,SPI transfer controlled start" "No action,Started"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " TCSH ,Chip-select hold time control" "0.5 clk cycle,1.5 clk cycle,2.5 clk cycle,3.5 clk cycle"
|
|
bitfld.word 0x00 08.--09. " TCSS ,Chip-select setup time control" "1 clk cycle,2 clk cycle,3 clk cycle,4 clk cycle"
|
|
textline " "
|
|
bitfld.word 0x00 07. " CSEL ,Card socket connector select" "SPI.CLK/MMC_C.Sn[0],MMC.CLK/MMC.DAT3"
|
|
textline " "
|
|
bitfld.word 0x00 04.--05. " CS ,Chip-select control" "C/S 0,C/S 1,C/S 2,C/S 3"
|
|
bitfld.word 0x00 03. " CSM ,Chip-select mode" "Automatic,Manual"
|
|
textline " "
|
|
bitfld.word 0x00 02. " CSD ,Chip-select disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 01. " PHA ,Phase control" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.word 0x00 00. " POL ,Polarity control" "Rising edge,Falling edge"
|
|
group.word (0x0034)++0x01
|
|
line.word 0x00 "MMC_SDIO,SDIO Mode Configuration Register"
|
|
bitfld.word 0x00 15. " C5E ,Card status error on bit 5 of response 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " C14E ,Card status error on bit 4 of response 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " C13E ,Card status error on bit 3 of response 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " C12E ,Card status error on bit 2 of response 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " D3PS ,DAT3 polarity control" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " D3ES ,DAT3 edge/level detection mode" "Level,Edge"
|
|
textline " "
|
|
bitfld.word 0x00 09. " CDWE ,Card-detect wake request enable (SD/SDIO valid)" "Disabled,Enabled"
|
|
bitfld.word 0x00 08. " IWE ,Interrupt wake request enable (SDIO valid)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 07. " DCR4 ,Disable CRC7 check in R4 response" "Enabled,Disabled"
|
|
bitfld.word 0x00 06. " XDTS ,Extended data time-out mode select (default OD)" "Open-drain,Time-out"
|
|
textline " "
|
|
bitfld.word 0x00 05. " DPE ,Data time-out prescaler enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " RW ,Assert read wait condition to the card (SDIO valid)" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.word 0x00 02. " CDE ,Card-detect mode enable (SD/SDIO valid)" "Disabled,Enabled"
|
|
bitfld.word 0x00 01. " RWE ,SDIO read wait mode enable (SDIO vlid)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 00. " IRQE ,SDIO interrupt mode enable (SDIO vlid)" "Disabled,Enabled"
|
|
group.word (0x0038)++0x01
|
|
line.word 0x00 "MMC_SYST,System Test Register"
|
|
bitfld.word 0x00 15. " WAKD ,WAKE_REQ output signal data value (internal signal to system)" "Low,High"
|
|
bitfld.word 0x00 14. " SSB ,Set status bits" "No action,Set"
|
|
textline " "
|
|
bitfld.word 0x00 13. " RDYD ,Ready/busy input signal data value" "Low,High"
|
|
bitfld.word 0x00 12. " DDIR ,DAT[3:0] signals direction" "Input,Output"
|
|
textline " "
|
|
bitfld.word 0x00 11. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
bitfld.word 0x00 10. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 09. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
bitfld.word 0x00 08. " D0D ,DAT0/SI input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 07. " CDIR ,CMD/SO signal direction" "Input,Output"
|
|
bitfld.word 0x00 06. " CDAT ,CMD/SO input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 05. " MCKD ,MMC clock output signal data value" "Low,High"
|
|
bitfld.word 0x00 04. " SCKD ,SPI clock output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 03. " CS3D ,C/S3 output signal data value" "Low,High"
|
|
bitfld.word 0x00 02. " CS2D ,C/S2 output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 01. " CS1D ,C/S1 output signal data value" "Low,High"
|
|
bitfld.word 0x00 00. " CS0D ,C/S0 output signal data value" "Low,High"
|
|
rgroup.word (0x003C)++0x01
|
|
line.word 0x00 "MMC_REV,Module Revision Register"
|
|
bitfld.word 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word ((0x0040+0x0))++0x01
|
|
line.word 0x00 "MMC_RSP0,MMC/SD Command Response Register 0"
|
|
hexmask.word 0x00 00.--15. 1. " RSP0 ,CMD response"
|
|
group.word ((0x0040+0x4))++0x01
|
|
line.word 0x00 "MMC_RSP1,MMC/SD Command Response Register 1"
|
|
hexmask.word 0x00 00.--15. 1. " RSP1 ,CMD response"
|
|
group.word ((0x0040+0x8))++0x01
|
|
line.word 0x00 "MMC_RSP2,MMC/SD Command Response Register 2"
|
|
hexmask.word 0x00 00.--15. 1. " RSP2 ,CMD response"
|
|
group.word ((0x0040+0xC))++0x01
|
|
line.word 0x00 "MMC_RSP3,MMC/SD Command Response Register 3"
|
|
hexmask.word 0x00 00.--15. 1. " RSP3 ,CMD response"
|
|
group.word ((0x0040+0x10))++0x01
|
|
line.word 0x00 "MMC_RSP4,MMC/SD Command Response Register 4"
|
|
hexmask.word 0x00 00.--15. 1. " RSP4 ,CMD response"
|
|
group.word ((0x0040+0x14))++0x01
|
|
line.word 0x00 "MMC_RSP5,MMC/SD Command Response Register 5"
|
|
hexmask.word 0x00 00.--15. 1. " RSP5 ,CMD response"
|
|
group.word ((0x0040+0x18))++0x01
|
|
line.word 0x00 "MMC_RSP6,MMC/SD Command Response Register 6"
|
|
hexmask.word 0x00 00.--15. 1. " RSP6 ,CMD response"
|
|
group.word ((0x0040+0x1C))++0x01
|
|
line.word 0x00 "MMC_RSP7,MMC/SD Command Response Register 7"
|
|
hexmask.word 0x00 00.--15. 1. " RSP7 ,CMD response"
|
|
group.word (0x0060)++0x01
|
|
line.word 0x00 "MMC_IOSR,SDIO Suspend/Resume Control Register"
|
|
bitfld.word 0x00 03. " STOP ,Stop core data operation request (after card grants suspend)" "No action,Stopped"
|
|
bitfld.word 0x00 02. " SAVE ,Save FIFO contents of suspended function (SDIO valid)" "No action,Saved"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RESU ,Next SD command is a resume request (SDIO valid)" "No action,RESUME"
|
|
bitfld.word 0x00 00. " SUSP ,Next SD command is a suspend request (SDIO valid)" "No action,SUSPEND"
|
|
wgroup.word (0x0064)++0x01
|
|
line.word 0x00 "MMC_SYSC,System Control Register"
|
|
bitfld.word 0x00 01. " SRST ,Software reset" "No action,Reset"
|
|
rgroup.word (0x0068)++0x01
|
|
line.word 0x00 "MMC_SYSS,System Status Register"
|
|
bitfld.word 0x00 00. " RSTD ,Reset done" "Not done,Done"
|
|
tree.end
|
|
base AD:0xFFFB7C00
|
|
width 0x10
|
|
tree "MMC/SDIO2"
|
|
if ((data.word(AD:0xFFFB7C00+0x0C)&0x3000)==0x0)
|
|
group.word 0x0000++0x01
|
|
line.word 0x00 "MMC_CMD,MMC Command Register"
|
|
bitfld.word 0x00 15. " DDIR ,Data direction" "Write,Read"
|
|
bitfld.word 0x00 14. " SHR ,Stream command or broadcast host response (MMC valid)" "Normal,Stream"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " TYPE ,Command type" "BC,BCR,AC,ADTC"
|
|
bitfld.word 0x00 11. " BUSY ,Command with busy response" "Without busy,With busy"
|
|
textline " "
|
|
bitfld.word 0x00 08.--10. " RSP ,Command responses" "No response,R1/R1b,R2,R3,R4,R5,R6,?..."
|
|
bitfld.word 0x00 07. " INAB ,Send initialization stream/data abort command" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.word 0x00 06. " ODTO ,Card open drain mode/extended command time-out mode" "Push-pull/CTO,Open drain/DTO"
|
|
bitfld.word 0x00 00.--05. " INDX ,Command index" "CMD0,CMD1,CMD2,CMD3,CMD4,CMD5,CMD6,CMD7,CMD8,CMD9,CMD10,CMD11,CMD12,CMD13,CMD14,CMD15,CMD16,CMD17,CMD18,CMD19,CMD20,CMD21,CMD22,CMD23,CMD24,CMD25,CMD26,CMD27,CMD28,CMD29,CMD30,CMD31,CMD32,CMD33,CMD34,CMD35,CMD36,CMD37,CMD38,CMD39,CMD40,CMD41,CMD42,CMD43,CMD44,CMD45,CMD46,CMD47,CMD48,CMD49,CMD50,CMD51,CMD52,CMD53,CMD54,CMD55,CMD56,CMD57,CMD58,CMD59,CMD60,CMD61,CMD62,CMD63"
|
|
elif ((data.word(AD:0xFFFB7C00+0x0C)&0x3000)==0x1000)
|
|
group.word 0x0000++0x01
|
|
line.word 0x00 "SPI_DO,SPI Data Register"
|
|
hexmask.word 0x00 00.--15. 1. " DATA ,SPI data"
|
|
else
|
|
hgroup.word 0x0000++0x01
|
|
hide.word 0x00 "MMC_CMD/SPI_DO,MMC Command/SPI Data Register"
|
|
endif
|
|
group.word (0x0004)++0x01
|
|
line.word 0x00 "MMC_ARGL,System Argument Low Register"
|
|
hexmask.word 0x00 00.--15. 1. " ARGL ,Command argument bits [15:0]"
|
|
group.word (0x0008)++0x01
|
|
line.word 0x00 "MMC_ARGH,System Argument High Register"
|
|
hexmask.word 0x00 00.--15. 1. " ARGH ,Command argument bits [31:16]"
|
|
group.word (0x000C)++0x01
|
|
line.word 0x00 "MMC_CON,Module Configuration Register"
|
|
bitfld.word 0x00 15. " DW ,Data bus width (SD valid)" "1-bit,4-bit"
|
|
bitfld.word 0x00 12.--13. " MODE ,Operating mode select" "MMC/SD,SPI,SYSTEST,?..."
|
|
textline " "
|
|
bitfld.word 0x00 11. " POWER_UP ,Power-up control" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " BE ,Big-endian mode" "Little,Big"
|
|
textline " "
|
|
hexmask.word 0x00 00.--09. 1. " CLKD ,Clock divider"
|
|
if ((data.word(AD:0xFFFB7C00+0x0C)&0x3000)==0x0)
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "MMC_STAT,Module Status Register"
|
|
eventfld.word 0x00 14. " CERR ,Card status error in response" "No error,Error"
|
|
eventfld.word 0x00 13. " CIRQ ,MMC card IRQ received" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 12. " OCRB ,Operation condition register (OCR) busy" "Not busy,Busy"
|
|
eventfld.word 0x00 11. " AE ,Buffer almost empty" "Above almost,Almost"
|
|
textline " "
|
|
eventfld.word 0x00 10. " AF ,Buffer almost full" "Below almost,Almost"
|
|
eventfld.word 0x00 09. " CRW ,Card read wait (SDIO valid)" "No action,Wait"
|
|
textline " "
|
|
eventfld.word 0x00 08. " CCRC ,Command CRC error" "No error,Error"
|
|
eventfld.word 0x00 07. " CTO ,Command response time-out" "No error,Error"
|
|
textline " "
|
|
eventfld.word 0x00 06. " DCRC ,Data CRC error" "No error,Error"
|
|
eventfld.word 0x00 05. " DTO ,Data response time-out" "No action,Time-out"
|
|
textline " "
|
|
eventfld.word 0x00 04. " EOFB ,Card exit busy state" "No action,Busy"
|
|
eventfld.word 0x00 03. " BRS ,Block received/sent" "No action,Received/Sent"
|
|
textline " "
|
|
eventfld.word 0x00 02. " CB ,Card enter busy state" "No action,Busy"
|
|
eventfld.word 0x00 01. " CD ,Card detect on DAT3" "Not detected,Detected"
|
|
textline " "
|
|
eventfld.word 0x00 00. " EOC ,End of command phase" "No action,EOC"
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
bitfld.word 0x00 14. " CERR ,Card status error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CIRQ ,Card IRQ interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " OCRB ,OCR busy interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " AE ,Buffer almost empty interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " AF ,Buffer almost full interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 09. " CRW ,Card read wait enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 08. " CCRC ,Command CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 07. " CTO ,Command response time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 06. " DCRC ,Data CRC error interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " DTO ,Data response time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 04. " EOFB ,Card exit busy state interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 03. " BRS ,Block received/sent interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 02. " CB ,Card enter busy state interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 01. " CD ,Card-detect interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 00. " EOC ,End of command interrupt enable" "Disabled,Enabled"
|
|
elif ((data.word(AD:0xFFFB7C00+0x0C)&0x3000)==0x1000)
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "MMC_STAT,Module Status Register"
|
|
eventfld.word 0x00 11. " AE ,Buffer almost empty" "Above almost,Almost"
|
|
eventfld.word 0x00 10. " AF ,Buffer almost full" "Below almost,Almost"
|
|
textline " "
|
|
eventfld.word 0x00 05. " DTO ,Data response time-out" "No action,Time-out"
|
|
eventfld.word 0x00 03. " BRS ,Block received/sent" "No action,Received/Sent"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
bitfld.word 0x00 11. " AE ,Buffer almost empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " AF ,Buffer almost full interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 09. " CRW ,Card read wait enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 05. " DTO ,Data response time-out interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " BRS ,Block received/sent interrupt enable" "Disabled,Enabled"
|
|
elif ((data.word(AD:0xFFFB7C00+0x0C)&0x3000)==0x1000)
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "MMC_STAT,Module Status Register"
|
|
eventfld.word 0x00 11. " AE ,Buffer almost empty" "Above almost,Almost"
|
|
eventfld.word 0x00 10. " AF ,Buffer almost full" "Below almost,Almost"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
bitfld.word 0x00 11. " AE ,Buffer almost empty interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " AF ,Buffer almost full interrupt enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.word (0x0010)++0x01
|
|
hide.word 0x00 "MMC_STAT,Module Status Register"
|
|
wgroup.word (0x0010)++0x01
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hgroup.word (0x0014)++0x01
|
|
hide.word 0x00 "MMC_IE,System Interrupt Enable Register"
|
|
endif
|
|
if ((data.word(AD:0xFFFB7C00+0x0C)&0x3000)==0x0)
|
|
group.word (0x0018)++0x01
|
|
line.word 0x00 "MMC_CTO,Command Time-Out Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " CTO ,MMC command time-out value"
|
|
else
|
|
hgroup.word (0x0018)++0x01
|
|
hide.word 0x00 "MMC_CTO,Command Time-Out Register"
|
|
endif
|
|
group.word (0x001C)++0x01
|
|
line.word 0x00 "MMC_DTO,Data Read Time-Out Register"
|
|
hexmask.word 0x00 00.--15. 1. " DTO ,Data read time-out"
|
|
hgroup.word (0x0020)++0x01
|
|
hide.word 0x00 "MMC_DATA,Data Access Register"
|
|
in
|
|
group.word (0x0024)++0x01
|
|
line.word 0x00 "MMC_BLEN,Block Length Register"
|
|
hexmask.word 0x00 00.--10. 1. " BLEN ,Block length value"
|
|
group.word (0x0028)++0x01
|
|
line.word 0x00 "MMC_NBLK,Number of Blocks Register"
|
|
hexmask.word 0x00 00.--10. 1. " NBLK ,Number of blocks value"
|
|
group.word (0x002C)++0x01
|
|
line.word 0x00 "MMC_BUF,Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RXDE ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 08.--12. " AFL ,Buffer almost full level" "2-byte,4-byte,6-byte,8-byte,10-byte,12-byte,14-byte,16-byte,18-byte,20-byte,22-byte,24-byte,26-byte,28-byte,30-byte,32-byte,34-byte,36-byte,38-byte,40-byte,42-byte,44-byte,46-byte,48-byte,50-byte,52-byte,54-byte,56-byte,58-byte,60-byte,62-byte,64-byte"
|
|
textline " "
|
|
bitfld.word 0x00 07. " TXDE ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 00.--04. " AEL ,Buffer almost empty level" "2-byte,4-byte,6-byte,8-byte,10-byte,12-byte,14-byte,16-byte,18-byte,20-byte,22-byte,24-byte,26-byte,28-byte,30-byte,32-byte,34-byte,36-byte,38-byte,40-byte,42-byte,44-byte,46-byte,48-byte,50-byte,52-byte,54-byte,56-byte,58-byte,60-byte,62-byte,64-byte"
|
|
group.word (0x0030)++0x01
|
|
line.word 0x00 "MMC_SPI,SPI Configuration Register"
|
|
bitfld.word 0x00 15. " STR ,Start SPI transfer" "No action,Started"
|
|
bitfld.word 0x00 14. " WNR ,Write/not read" "Read,Write"
|
|
textline " "
|
|
bitfld.word 0x00 13. " SODV ,SPI_SO serial out pin default value" "Low,High"
|
|
bitfld.word 0x00 12. " CSTR ,SPI transfer controlled start" "No action,Started"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " TCSH ,Chip-select hold time control" "0.5 clk cycle,1.5 clk cycle,2.5 clk cycle,3.5 clk cycle"
|
|
bitfld.word 0x00 08.--09. " TCSS ,Chip-select setup time control" "1 clk cycle,2 clk cycle,3 clk cycle,4 clk cycle"
|
|
textline " "
|
|
bitfld.word 0x00 07. " CSEL ,Card socket connector select" "SPI.CLK/MMC_C.Sn[0],MMC.CLK/MMC.DAT3"
|
|
textline " "
|
|
bitfld.word 0x00 04.--05. " CS ,Chip-select control" "C/S 0,C/S 1,C/S 2,C/S 3"
|
|
bitfld.word 0x00 03. " CSM ,Chip-select mode" "Automatic,Manual"
|
|
textline " "
|
|
bitfld.word 0x00 02. " CSD ,Chip-select disable" "Enabled,Disabled"
|
|
bitfld.word 0x00 01. " PHA ,Phase control" "Phase 0,Phase 1"
|
|
textline " "
|
|
bitfld.word 0x00 00. " POL ,Polarity control" "Rising edge,Falling edge"
|
|
group.word (0x0034)++0x01
|
|
line.word 0x00 "MMC_SDIO,SDIO Mode Configuration Register"
|
|
bitfld.word 0x00 15. " C5E ,Card status error on bit 5 of response 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " C14E ,Card status error on bit 4 of response 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " C13E ,Card status error on bit 3 of response 1 enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " C12E ,Card status error on bit 2 of response 1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " D3PS ,DAT3 polarity control" "Not inverted,Inverted"
|
|
bitfld.word 0x00 10. " D3ES ,DAT3 edge/level detection mode" "Level,Edge"
|
|
textline " "
|
|
bitfld.word 0x00 09. " CDWE ,Card-detect wake request enable (SD/SDIO valid)" "Disabled,Enabled"
|
|
bitfld.word 0x00 08. " IWE ,Interrupt wake request enable (SDIO valid)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 07. " DCR4 ,Disable CRC7 check in R4 response" "Enabled,Disabled"
|
|
bitfld.word 0x00 06. " XDTS ,Extended data time-out mode select (default OD)" "Open-drain,Time-out"
|
|
textline " "
|
|
bitfld.word 0x00 05. " DPE ,Data time-out prescaler enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " RW ,Assert read wait condition to the card (SDIO valid)" "Not asserted,Asserted"
|
|
textline " "
|
|
bitfld.word 0x00 02. " CDE ,Card-detect mode enable (SD/SDIO valid)" "Disabled,Enabled"
|
|
bitfld.word 0x00 01. " RWE ,SDIO read wait mode enable (SDIO vlid)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 00. " IRQE ,SDIO interrupt mode enable (SDIO vlid)" "Disabled,Enabled"
|
|
group.word (0x0038)++0x01
|
|
line.word 0x00 "MMC_SYST,System Test Register"
|
|
bitfld.word 0x00 15. " WAKD ,WAKE_REQ output signal data value (internal signal to system)" "Low,High"
|
|
bitfld.word 0x00 14. " SSB ,Set status bits" "No action,Set"
|
|
textline " "
|
|
bitfld.word 0x00 13. " RDYD ,Ready/busy input signal data value" "Low,High"
|
|
bitfld.word 0x00 12. " DDIR ,DAT[3:0] signals direction" "Input,Output"
|
|
textline " "
|
|
bitfld.word 0x00 11. " D3D ,DAT3 input/output signal data value" "Low,High"
|
|
bitfld.word 0x00 10. " D2D ,DAT2 input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 09. " D1D ,DAT1 input/output signal data value" "Low,High"
|
|
bitfld.word 0x00 08. " D0D ,DAT0/SI input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 07. " CDIR ,CMD/SO signal direction" "Input,Output"
|
|
bitfld.word 0x00 06. " CDAT ,CMD/SO input/output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 05. " MCKD ,MMC clock output signal data value" "Low,High"
|
|
bitfld.word 0x00 04. " SCKD ,SPI clock output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 03. " CS3D ,C/S3 output signal data value" "Low,High"
|
|
bitfld.word 0x00 02. " CS2D ,C/S2 output signal data value" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 01. " CS1D ,C/S1 output signal data value" "Low,High"
|
|
bitfld.word 0x00 00. " CS0D ,C/S0 output signal data value" "Low,High"
|
|
rgroup.word (0x003C)++0x01
|
|
line.word 0x00 "MMC_REV,Module Revision Register"
|
|
bitfld.word 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word ((0x0040+0x0))++0x01
|
|
line.word 0x00 "MMC_RSP0,MMC/SD Command Response Register 0"
|
|
hexmask.word 0x00 00.--15. 1. " RSP0 ,CMD response"
|
|
group.word ((0x0040+0x4))++0x01
|
|
line.word 0x00 "MMC_RSP1,MMC/SD Command Response Register 1"
|
|
hexmask.word 0x00 00.--15. 1. " RSP1 ,CMD response"
|
|
group.word ((0x0040+0x8))++0x01
|
|
line.word 0x00 "MMC_RSP2,MMC/SD Command Response Register 2"
|
|
hexmask.word 0x00 00.--15. 1. " RSP2 ,CMD response"
|
|
group.word ((0x0040+0xC))++0x01
|
|
line.word 0x00 "MMC_RSP3,MMC/SD Command Response Register 3"
|
|
hexmask.word 0x00 00.--15. 1. " RSP3 ,CMD response"
|
|
group.word ((0x0040+0x10))++0x01
|
|
line.word 0x00 "MMC_RSP4,MMC/SD Command Response Register 4"
|
|
hexmask.word 0x00 00.--15. 1. " RSP4 ,CMD response"
|
|
group.word ((0x0040+0x14))++0x01
|
|
line.word 0x00 "MMC_RSP5,MMC/SD Command Response Register 5"
|
|
hexmask.word 0x00 00.--15. 1. " RSP5 ,CMD response"
|
|
group.word ((0x0040+0x18))++0x01
|
|
line.word 0x00 "MMC_RSP6,MMC/SD Command Response Register 6"
|
|
hexmask.word 0x00 00.--15. 1. " RSP6 ,CMD response"
|
|
group.word ((0x0040+0x1C))++0x01
|
|
line.word 0x00 "MMC_RSP7,MMC/SD Command Response Register 7"
|
|
hexmask.word 0x00 00.--15. 1. " RSP7 ,CMD response"
|
|
group.word (0x0060)++0x01
|
|
line.word 0x00 "MMC_IOSR,SDIO Suspend/Resume Control Register"
|
|
bitfld.word 0x00 03. " STOP ,Stop core data operation request (after card grants suspend)" "No action,Stopped"
|
|
bitfld.word 0x00 02. " SAVE ,Save FIFO contents of suspended function (SDIO valid)" "No action,Saved"
|
|
textline " "
|
|
bitfld.word 0x00 01. " RESU ,Next SD command is a resume request (SDIO valid)" "No action,RESUME"
|
|
bitfld.word 0x00 00. " SUSP ,Next SD command is a suspend request (SDIO valid)" "No action,SUSPEND"
|
|
wgroup.word (0x0064)++0x01
|
|
line.word 0x00 "MMC_SYSC,System Control Register"
|
|
bitfld.word 0x00 01. " SRST ,Software reset" "No action,Reset"
|
|
rgroup.word (0x0068)++0x01
|
|
line.word 0x00 "MMC_SYSS,System Status Register"
|
|
bitfld.word 0x00 00. " RSTD ,Reset done" "Not done,Done"
|
|
tree.end
|
|
base AD:0xFFFB9000
|
|
tree "OS Timer Registers"
|
|
width 20.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "OS_TIMER_TICK_VAL,OS Timer 32k Tick Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TICK_VALUE_REG ,Value is loaded when the timer reaches 0 or when it starts"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "OS_TIMER_TICK_CNTR,OS Timer 32k Tick Counter Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TICK_COUNTER_REG ,Value of timer"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "OS_TIMER_CTRL,OS Timer 32k Timer Control Register"
|
|
bitfld.long 0x00 3. " ARL ,Autoreload/start" "One-shot,Autorestart"
|
|
bitfld.long 0x00 2. " IT_ENA ,Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TRB ,Timer reload bit" "Normal,Reload"
|
|
bitfld.long 0x00 0. " TSS ,Timer start/stop" "Stop,Start"
|
|
tree.end
|
|
base AD:0xFFFBA800
|
|
tree "Frame Adjustment Counter (FAC) Registers"
|
|
width 10.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "FACRC,FAC Frame Adjustment Reference Counter Register"
|
|
rgroup.word 0x04++0x1
|
|
line.word 0x00 "FSC,FAC Frame Start Count Register"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "CTRL,FAC Control and Configuration Register"
|
|
bitfld.word 0x00 2. " INT_ENABLE ,Generate an interrupt on FSC update" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RUN ,Enables operation of the counter" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CNT ,Select mode of FSC updating" "Halt,Continuous"
|
|
rgroup.word 0x0C++0x1
|
|
line.word 0x00 "STATUS,FAC Status Register"
|
|
bitfld.word 0x00 0. " FSC_FULL ,FSC status" "Read,Full"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x00 "SYNCCNT,FAC Synchronization Counter Register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "STARTCNT,FAC Start Counter Register"
|
|
tree.end
|
|
base AD:0xFFFBAC00
|
|
tree "Specially Optimized Screen Interface (SoSSI) Registers"
|
|
width 16.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "SOSSI_IDENT,SoSSI Identification Register"
|
|
line.long 0x04 "SOSSI_INIT1,SoSSI Timing For Display Register"
|
|
bitfld.long 0x04 31. " REORDERING ,Enable reordering for SOSSI_FIFO register" "Disabled,Enabled"
|
|
bitfld.long 0x04 30. " CS ,State of SOSSI.CS pin" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 24.--29. " TW1 ,Delay between two access to external device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x04 20.--23. " TW0 ,Duration of SOSSI.RD/SOSSI.WR active pulses" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x04 19. " DMA_MODE ,Possibility of DMA access" "Impossible,Possible"
|
|
bitfld.long 0x04 18. " DATA_TYPE ,State of SOSSI.CMD pin" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " NUMBER ,Number of write cycles triggered by a write to SoSSI FIFO before th SoDDI block goes back to Idle mode -1"
|
|
line.long 0x08 "SOSSI_INIT2,SoSSI Main Control Register"
|
|
bitfld.long 0x08 8. " DOUBLE ,Writing to SOSSI_FIFOB register triggers write to external device with parameters set in register" "SOSSI_INIT1,SOSSI_INIT3"
|
|
bitfld.long 0x08 7. " CPRIORITY ,Enable prioritized command mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " TS ,Use of tearing effect control logic" "Not used,Used"
|
|
bitfld.long 0x08 5. " RR ,Reset of reordering table pointer" "Not reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 4. " WE ,Disable writing to external device" "Enabled,Disabled"
|
|
bitfld.long 0x08 3. " WRIDLE ,Write process to external device ongoing" "Yes,No"
|
|
textline " "
|
|
bitfld.long 0x08 2. " FIFO_EMPTY ,Allow write to SOSSI_FIFO and SOSSI_FIFOB registers" "Not allowed,Allowed"
|
|
bitfld.long 0x08 1. " RESTART ,SOSSI block reset" "Out of reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 0. " DIFSEL ,SOSSI block enabled" "Disabled,Enabled"
|
|
line.long 0x0c "SOSSI_INIT3,SoSSI Main Control Register"
|
|
bitfld.long 0x0c 5.--9. " BUSPICKCOUNT ,Number of write cycles triggered by a write to SOSSI_FIFO register" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
bitfld.long 0x0c 0.--4. " BUSPICKWIDTH ,Number of bits each write cycle conveys" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
line.long 0x10 "SOSSI_FIFO,SoSSI FIFO Register"
|
|
line.long 0x14 "SOSSI_REOTABLE,SoSSI Reordering Table"
|
|
line.long 0x18 "SOSSI_TEARING,SoSSI Tearing Effect Register"
|
|
bitfld.long 0x18 30.--31. " VS_COUNTER ,Frame rate adjustment control" "0,1,2,3"
|
|
bitfld.long 0x18 29. " HS_INVERTED ,TE line inverted is used for HS detection" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x18 28. " VS_INVERTED ,TE line inverted is used for VS detection" "Not inverted,Inverted"
|
|
bitfld.long 0x18 26.--27. " MODE ,Hardware synchronization mode" "Disabled,Reserved,TE mode,VS-only mode"
|
|
textline " "
|
|
hexmask.long.word 0x18 15.--25. 1. " HS_COUNTER_MATCH_VALUE ,Number of Hsync before a new DMA request is sent to the MPU"
|
|
hexmask.long.word 0x18 3.--14. 1. " VS_DETECT_LIMIT ,In TE mode - any TE pulse longer than VS_DETECT_LIMIT*8 clock cycles is considered as a vertical synchronization"
|
|
textline " "
|
|
bitfld.long 0x18 0.--2. " PULSE_DETECT_LIMIT ,Any TE pulse shorter that PULSE_DETECT_LIMIT clock cycles is ignored" "0,1,2,3,4,5,6,7"
|
|
line.long 0x1c "SOSSI_INIT1B,SoSSI Part of INIT1 Register"
|
|
bitfld.long 0x1c 19. " REORDERING ,Enable reordering for SOSSI_FIFOB" "Disabled,Enabled"
|
|
bitfld.long 0x1c 18. " DATA_TYPE ,State of SOSSI.CMD pin when writing from SOSSI_FIFOB" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x1c 0.--17. 1. " NUMBER ,Number of write cycles triggered by access to SOSSI_FIFOB before SoSSI goes to idle -1"
|
|
wgroup.long 0x20++0x3
|
|
line.long 0x00 "SOSSI_FIFOB,SoSSI Part of FIFO Register"
|
|
tree.end
|
|
base AD:0xFFFBC000
|
|
tree "HDQ/1-Wire Interface Registers"
|
|
width 15.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "HDQ_TX_DATA,HDQ Transmit Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WD ,Write data"
|
|
hgroup.long 0x04++0x3
|
|
hide.long 0x00 "HDQ_RX_BUF,HDQ Receive Buffer Register"
|
|
;hexmask.long.byte 0x00 0.--7. 1. " RD ,Next received character"
|
|
in
|
|
if (d.l(ad:0xFFFBC008)&0x1)==0x0
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "HDQ_CNTL_STAT,HDQ Control and Status Register"
|
|
bitfld.long 0x00 6. " IM ,Interrupt mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " PDM ,Power-down mode - clock enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GB ,Go bit" "Normal,Send commands"
|
|
bitfld.long 0x00 2. " IP ,Send initialization pulse" "Normal,Send"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWB ,R/W bit (determines if next command is read or write)" "Write,Read"
|
|
bitfld.long 0x00 0. " MODE ,Set mode" "HDQ,1-Wire"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "HDQ_INT_STAT,HDQ Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TC ,TX completed" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " RC ,Read complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " DTO ,Time-out on read" "No time-out,Time-out"
|
|
else
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "HDQ_CNTL_STAT,HDQ Control and Status Register"
|
|
bitfld.long 0x00 7. " SBM ,Single-bit mode" "Not single,Single"
|
|
bitfld.long 0x00 6. " IM ,Interrupt mask" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " PDM ,Power-down mode - clock enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " GB ,Go bit" "Normal,Send commands"
|
|
bitfld.long 0x00 3. " PD ,Presence detect received" "Not detected,Detected"
|
|
bitfld.long 0x00 2. " IP ,Send initialization pulse" "Normal,Send"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RWB ,R/W bit (determines if next command is read or write)" "Write,Read"
|
|
bitfld.long 0x00 0. " MODE ,Set mode" "HDQ,1-Wire"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "HDQ_INT_STAT,HDQ Interrupt Status Register"
|
|
bitfld.long 0x00 2. " TC ,TX completed" "Not completed,Completed"
|
|
bitfld.long 0x00 1. " RC ,Read complete" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " DTO ,Presence detect" "Not present,Present"
|
|
endif
|
|
tree.end
|
|
tree "LED Pulse Generators"
|
|
width 14.
|
|
base AD:0xFFFBD000
|
|
width 15.
|
|
group.byte 0x00++0x0 "LED Pulse Generator 1 (LPG1) Registers"
|
|
line.byte 0x00 "LPG1_CNTL,LPG1 Control Register"
|
|
bitfld.byte 0x00 7. " PERM_ON ,Force permanent light on" "Not forced,Forced"
|
|
bitfld.byte 0x00 6. " LPGRES ,LPG counter reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--5. " ONCTRL ,Time LED is on parameter (time ms/clock cycles)" "3.889/1,7.789/2,15.59/4,31.39/8,46.59/12,62.59/16,78.39/20,93.59/24"
|
|
bitfld.byte 0x00 0.--2. " PERCTRL ,LED blink frequency (period ms/clock cycles)" "125 /32,250 /64,500 /128,1000/256,1500/384,2000/512,2500/640,3000/768"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "LPG1_PWR_MNGT,LPG1 Power Management Register"
|
|
bitfld.byte 0x00 0. " CLK_EN ,Functional clock enable" "Disabled,Enabled"
|
|
base AD:0xFFFBD800
|
|
width 15.
|
|
group.byte 0x00++0x0 "LED Pulse Generator 2 (LPG2) Registers"
|
|
line.byte 0x00 "LPG2_CNTL,LPG2 Control Register"
|
|
bitfld.byte 0x00 7. " PERM_ON ,Force permanent light on" "Not forced,Forced"
|
|
bitfld.byte 0x00 6. " LPGRES ,LPG counter reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.byte 0x00 3.--5. " ONCTRL ,Time LED is on parameter (time ms/clock cycles)" "3.889/1,7.789/2,15.59/4,31.39/8,46.59/12,62.59/16,78.39/20,93.59/24"
|
|
bitfld.byte 0x00 0.--2. " PERCTRL ,LED blink frequency (period ms/clock cycles)" "125 /32,250 /64,500 /128,1000/256,1500/384,2000/512,2500/640,3000/768"
|
|
group.byte 0x04++0x0
|
|
line.byte 0x00 "LPG2_PWR_MNGT,LPG2 Power Management Register"
|
|
bitfld.byte 0x00 0. " CLK_EN ,Functional clock enable" "Disabled,Enabled"
|
|
tree.end
|
|
;base AD:0xFFFEC900
|
|
;%include mpu/mpui_ctrl.ph
|
|
base AD:0xFFFBCC00
|
|
tree "NAND Flash Registers"
|
|
width 17.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "NND_REVISION,Indicates the current revision number of the NFC"
|
|
hexfld.byte 0x00 " NND_REVISION ,Revision Number"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "NND_ACCESS,Indicates the location where a read of program (write) operation is to be performed"
|
|
line.long 0x04 "NND_ADDR_SRC,Contains the byte address of the location in the NFMC"
|
|
group.long 0x10++0x1b
|
|
line.long 0x00 "NND_CTRL,NAND controller"
|
|
bitfld.long 0x00 17. " PREFETCH ,Enable prefetch mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " POSTWRITE ,Enable postwrite mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " WRITEPROT3 ,WriteProtect3 / Voltage generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 14. " CHIPEN3 ,ChipEnable3 / NFMC device selection" "Selected,Not selected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WRITEPROT2 ,WriteProtect2 / Voltage generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 12. " CHIPEN2 ,ChipEnable2 / NFMC device selection" "Selected,Not selected"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WRITEPROT1 ,WriteProtect1 / Voltage generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 10. " CHIPEN1 ,ChipEnable1 / NFMC device selection" "Selected,Not selected"
|
|
textline " "
|
|
bitfld.long 0x00 9. " WRITEPROT0 ,WriteProtect0 / Voltage generator reset" "Reset,No reset"
|
|
bitfld.long 0x00 8. " CHIPEN0 ,ChipEnable0 / NFMC device selection" "Selected,Not selected"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " ADRCNT ,Address counter for sending bytes to NFMC" "4,3,2,1"
|
|
bitfld.long 0x00 4. " A8 ,Send Bit A8 of address register to NFMC" "Not send,Send"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BE ,Switch big/little endian" "Little,Big"
|
|
bitfld.long 0x00 1. " ECC_256 ,ECC calculation" "512B,256B"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ECC_ON ,Enable ECC logic" "Disabled,Enabled"
|
|
line.long 0x04 "NND_MASK,Used to mask event sources"
|
|
bitfld.long 0x04 3. " MSK_EMPTY ,Do not mask event for FIFO empty" "Mask,Not mask"
|
|
bitfld.long 0x04 2. " MSK_FULL ,Do not mask event for FIFO full" "Mask,Not mask"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MSK_COUNT ,Do not mask event for counter reaching zero" "Mask,Not mask"
|
|
bitfld.long 0x04 0. " MSK_READY ,Do not mask event for data ready" "Mask,Not mask"
|
|
line.long 0x08 "NND_STATUS,Used to mask event sources"
|
|
bitfld.long 0x08 3. " FIFO_EMPTY ,FIFO is empty" "No,Yes"
|
|
bitfld.long 0x08 2. " FIFO_FULL ,FIFO is full" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 1. " COUNT_ZERO ,Internal counter reaches zero" "No,Yes"
|
|
bitfld.long 0x08 0. " READY_EVENT ,R/B_ goes from 0 to 1" "No,Yes"
|
|
line.long 0x0c "NND_READY,Used to poll the readlines of the NFMC"
|
|
bitfld.long 0x0c 0. " READY ,NFMC is ready for next operation" "No,Yes"
|
|
line.long 0x10 "NND_COMMAND,Used to write a specific command to the NFMC"
|
|
hexfld.byte 0x10 " COMMAND ,Command operation code"
|
|
line.long 0x14 "NND_COMMAND_SEC,Writing to this register does not send any address to the NFMC"
|
|
hexfld.byte 0x14 " COMMAND ,Command operation code"
|
|
line.long 0x18 "NND_ECC_SELECT,Defines the number of NND_ECC registers per enable"
|
|
bitfld.long 0x18 0.--2. " ECC_SELECT ,Defines the number of NND_ECC registers per enable" "NND_ECC[1-3],NND_ECC[1-4],NND_ECC[1-5],NND_ECC[1-6],NND_ECC[1-7],NND_ECC[1-8],NND_ECC[1-9],NND_ECC[1-9]"
|
|
rgroup.long 0x2C++0x23
|
|
line.long 0x00 "NND_ECC1,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x00 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x00 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x00 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x00 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x00 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x00 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x04 "NND_ECC2,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x04 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x04 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x04 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x04 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x04 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x04 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x08 "NND_ECC3,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x08 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x08 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x08 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x08 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x08 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x08 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x08 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x0c "NND_ECC4,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x0c 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x0c 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x0c 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x0c 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x0c 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x0c 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x10 "NND_ECC5,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x10 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x10 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x10 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x10 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x10 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x10 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x10 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x14 "NND_ECC6,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x14 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x14 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x14 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x14 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x14 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x14 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x14 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x18 "NND_ECC7,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x18 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x18 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x18 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x18 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x18 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x18 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x18 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x1c "NND_ECC8,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x1c 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1c 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x1c 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x1c 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1c 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x1c 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x1c 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x1c 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x1c 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
line.long 0x20 "NND_ECC9,Holds the ECC code calculated while reading/writing to the NFMC"
|
|
bitfld.long 0x20 27. " P2048o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 26. " P1024o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 25. " P512o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 24. " P256o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 23. " P128o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 22. " P64o ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 21. " P32o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 20. " P16o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 19. " P8o ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 18. " P4o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x20 17. " P2o ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x20 16. " P1o ,Holds ECC code parities accumulated on column" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 11. " P2048e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 10. " P1024e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 9. " P512e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 8. " P256e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 7. " P128e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 6. " P64e ,Holds ECC code parities accumulated on row" "0,1"
|
|
textline " "
|
|
bitfld.long 0x20 5. " P32e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 4. " P16e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 3. " P8e ,Holds ECC code parities accumulated on row" "0,1"
|
|
bitfld.long 0x20 2. " P4e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x20 1. " P2e ,Holds ECC code parities accumulated on column" "0,1"
|
|
bitfld.long 0x20 0. " P1e ,Holds ECC code parities accumulated on column" "0,1"
|
|
group.long 0x50++0x2B
|
|
line.long 0x00 "NND_RESET,NAND controller reset register"
|
|
bitfld.long 0x00 7. " RESETDMASYNCHRO ,Asser high the DMA request signal" "No,Yes"
|
|
bitfld.long 0x00 0. " RESET_ECC ,Reset NND_ECC[0-9] registers" "No reset,Reset"
|
|
line.long 0x04 "NND_FIFO,Used to access the FIFO when prefetch or postwrite mode is selected"
|
|
hexmask.long.byte 0x04 28.--31. 1. " DATA "
|
|
line.long 0x08 "NND_FIFOCTRL,Holds the size of the FIFO and the number of blocks of (FIFO_SIZE) bytes to fetch/write tto access a full page"
|
|
bitfld.long 0x08 24.--31. " FIFO_SIZE ,Holds the size in bytes of the FIFO" "16,1,2,16,4,16,16,16,8,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16"
|
|
hexfld.word 0x08 " BLOCK_COUNT ,Holds the block count of (FIFO_SIZE) bytes to read/write in advance"
|
|
line.long 0x0c "NND_PSC_CLK,The NFC uses the 4-bit value in this register to divide the interface clock to adjust the timing for the signals on the NFMC"
|
|
bitfld.long 0x0c 0.--3. " PSC_CLK ,Prescale sampling clock divier value" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x10 "NND_SYSTEST,Used to test some features of the NFC"
|
|
bitfld.long 0x10 15. " TEST-UNLOCK ,Unlocks test features" "Locked,Unlocked"
|
|
bitfld.long 0x10 2. " MAP ,Map the internal FIFO as registers" "Not mapped,Mapped"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACCESS ,Unlock registers for read/write access" "Locked,Unlocked"
|
|
bitfld.long 0x10 0. " ALLOW_INT ,Allow initiating interrupts" "Forbidden,Allowed"
|
|
line.long 0x14 "NND_SYSCFG,NAND controller system configuration"
|
|
bitfld.long 0x14 1. " SOFTRESET ,Start software reset sequence" "No reset,Reset"
|
|
bitfld.long 0x14 0. " AUTOIDLE ,Controls clock activity" "Free-running,Power-saving"
|
|
line.long 0x18 "NND_SYSSTATUS,NAND controller system status"
|
|
bitfld.long 0x18 0. " RESETDONE ,Internal reset monitoring" "In progress,Done"
|
|
line.long 0x1c "NND_FIFOTEST1,NAND controller FIFO test register 1"
|
|
line.long 0x20 "NND_FIFOTEST2,NAND controller FIFO test register 2"
|
|
line.long 0x24 "NND_FIFOTEST3,NAND controller FIFO test register 3"
|
|
line.long 0x28 "NND_FIFOTEST4,NAND controller FIFO test register 4"
|
|
tree.end
|
|
base AD:0xFFFBE000
|
|
tree "CompactFlash Controller Registers"
|
|
width 16.
|
|
rgroup.word 0x00++0x5
|
|
line.word 0x00 "CF_STATUS_REG,CFC Controller Registers"
|
|
bitfld.word 0x00 2. " LAST_READ_ACCESS ,Bad read access" "Bad,OK"
|
|
textline " "
|
|
bitfld.word 0x00 1. " LAST_WRITE_ACCESS ,Bad write access" "Bad,OK"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CARD_DETECT ,CompactFlash correctly connected" "OK,Error"
|
|
line.word 0x02 "CF_CFG_REG_I,CFC configuration register 1"
|
|
bitfld.word 0x02 3. " CHIP-SELECT_3_CONFIGURATION ,Chip-select is connected on chip-select 3" "Connected,Disconnected"
|
|
textline " "
|
|
bitfld.word 0x02 2. " CHIP-SELECT_2_CONFIGURATION ,Chip-select is connected on chip-select 2" "Connected,Disconnected"
|
|
textline " "
|
|
bitfld.word 0x02 1. " CHIP-SELECT_1_CONFIGURATION ,Chip-select is connected on chip-select 1" "Connected,Disconnected"
|
|
textline " "
|
|
bitfld.word 0x02 0. " CHIP-SELECT_0_CONFIGURATION ,Chip-select is connected on chip-select 0" "Connected,Disconnected"
|
|
line.word 0x04 "CF_CONTROL_REG,CFC control register"
|
|
bitfld.word 0x04 0. " CF_CARD_RESET ,CompactFlash card reset" "Reset,No reset"
|
|
tree.end
|
|
base AD:0xFFFEB000
|
|
tree "Watchdog Timer Registers"
|
|
width 14.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "WIDR,Watchdog HW revision (ID)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " WD_REV ,Module HW revision number"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "WD_SYSCONFIG,Watchdog system configuration"
|
|
bitfld.long 0x00 5. " EMUFREE ,Enable sensitivity to suspend signal (emulation)" "Suspend,Ignore"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Internal OCP gating strategy" "Inactive,Active"
|
|
rgroup.long 0x14++0x3
|
|
line.long 0x00 "WD_SYSSTATUS,Watchdog status"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal reset monitoring" "Ongoing,Complete"
|
|
group.long 0x24++0xF
|
|
line.long 0x00 "WCLR,Watchdog control"
|
|
bitfld.long 0x00 5. " PRE ,Select input pin to clock the counter" "Timer clock,Divided"
|
|
bitfld.long 0x00 2.--4. " PTV ,Prescaler ratio value" "0,1,2,3,4,5,6,7"
|
|
line.long 0x04 "WCRR,Watchdog counter"
|
|
line.long 0x08 "WLDR,Watchdog load"
|
|
line.long 0x0c "WTGR,Watchdog trigger"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x00 "WWPS,Watchdog write pending"
|
|
bitfld.long 0x00 4. " W_PEND_WSPR ,A write is pending to the WSPR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_WTGR ,A write is pending to the WTGR register" "Normal,Pending"
|
|
bitfld.long 0x00 2. " W_PEND_WLDR ,A write is pending to the WLDR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 1. " W_PEND_WCRR ,A write is pending to the WCRR register" "Normal,Pending"
|
|
bitfld.long 0x00 0. " W_PEND_WCLR ,A write is pending to the WCLR register" "Normal,Pending"
|
|
group.long 0x48++0x3
|
|
line.long 0x00 "WSPR,Watchdog start/stop"
|
|
tree.end
|
|
base AD:0xFFFBC800
|
|
tree "CCP Registers"
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "CCPIDR,CCP ID"
|
|
hexmask.long.long 0x00 0.--31. 1. " IDR ,ID string of the component"
|
|
line.long 0x04 "CCPFSCR,CCP frame start code"
|
|
hexmask.long.long 0x04 0.--31. 1. " FSC ,Frame start code"
|
|
line.long 0x08 "CCPFECR,Frame end code"
|
|
hexmask.long.long 0x08 0.--31. 1. " FEC ,Frame end code"
|
|
line.long 0x0c "CCPLSCR,Line start code"
|
|
hexmask.long.long 0x0c 0.--31. 1. " LSC ,Line start code"
|
|
line.long 0x10 "CCPLECR,Lend end code"
|
|
hexmask.long.long 0x10 0.--31. 1. " LEC ,Line end code"
|
|
line.long 0x14 "CCPCR,Control"
|
|
bitfld.long 0x14 10. " LINECOUNTENABLE ,Disable/Count to upper limit" "Disabled,Count"
|
|
hexmask.long.word 0x14 0.--9. 1. " LINECOUNTERLIMIT ,upper limit of the line counter 0-1023"
|
|
line.long 0x18 "CCPDFR,Data format"
|
|
bitfld.long 0x18 1.--2. " DATAFORMATSELECT ," "YUV,RGB565,YUV,RGB444"
|
|
bitfld.long 0x18 0. " CCPSOFTRESET ,Reset receiving state machine" "No reset,Reset"
|
|
rgroup.long 0x1C++0x7
|
|
line.long 0x00 "CCPFIFODATAR,FIFO data"
|
|
hexmask.long.long 0x00 0.--31. 1. " FIFODATAIN ,Bit image data from SIPO to VIA interface"
|
|
line.long 0x04 "CCPSTATUS,Status"
|
|
bitfld.long 0x04 11.--12. " LASTSYNCCODE ,Last arrived sync code" "FSC,LEC,LSC,FEC"
|
|
bitfld.long 0x04 10. " FIFONOTEMPTY ,From FIFO: FIFO is not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x04 9. " SHIFTEDSYNCCODE ,From SIPO: Shifted sync code is detected" "Not detected,Detected"
|
|
bitfld.long 0x04 8. " FALSESYNCCODE ,From SIPO: False sync code is detected" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FIFOFULL ,From FIFO: FIFO buffer is full (no register slot available)" "Not full,Full"
|
|
bitfld.long 0x04 6. " FIFOOF ,From FIFO: Data is written to full FIFO" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FIFOTRIGLVL ,From FIFO: FIFODIFF>=4" "Not set,Set"
|
|
bitfld.long 0x04 4. " FSCSTATUS ,From SIPO: FSC has arrived" "Not arrived,Arrived"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FECSTATUS ,From SIPO: FEC has arrived" "Not arrived,Arrived"
|
|
bitfld.long 0x04 2. " LSCSTATUS ,From SIPO: LSC has arrived" "Not arrived,Arrived"
|
|
textline " "
|
|
bitfld.long 0x04 1. " LECSTATUS ,From SIPO: LEC has arrived" "Not arrived,Arrived"
|
|
bitfld.long 0x04 0. " COUNTERLIMITSTATUS ,From SIPO: Line cunter limit exceeded" "Not exceeded,Exceeded"
|
|
group.long 0x24++0x7
|
|
line.long 0x00 "CCPSTATUSMASKR,Status mask"
|
|
bitfld.long 0x00 9. " SHIFTEDSYNCCODEMASK ,SHIFTEDSYNCCODE interrupt source is masked" "Not masked,Masked"
|
|
bitfld.long 0x00 8. " FALSESYNCCODEMASK ,FALSESYNCCODE interrupt source is masked" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FIFOFULLMASK ,FIFOFULL interrupt source is masked" "Not masked,Masked"
|
|
bitfld.long 0x00 6. " FIFOOFMASK ,FIFOOF interrupt source is masked" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FIFOTRIGLVLMASK ,FIFOTRIGLVL interrupt source is masked" "Not masked,Masked"
|
|
bitfld.long 0x00 4. " FSCSTATUSMASK ,FSCSTATUS interrupt source is masked" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FECSTATUSMASK ,FECSTATUS interrupt source is masked" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " LSCSTATUSMASK ,LSCSTATUS interrupt source is masked" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LECSTATUSMASK ,LECSTATUS interrupt source is masked" "Not masked,Masked"
|
|
bitfld.long 0x00 0. " COUNTERLIMITSTATUSMASK ,COUNTERLIMITSTATUS interrupt source is masked" "Not masked,Masked"
|
|
line.long 0x04 "CCPBUSCLKENR,Bus clock enable"
|
|
bitfld.long 0x04 0. " BUSCLKEN ,Enable BUSCLK" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Camera Interface"
|
|
tree "L3 OCP T1"
|
|
base AD:0x2007D800
|
|
width 14.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRLCLOCK,Clock control"
|
|
bitfld.long 0x00 7. " LCLK_EN ,Enable incoming CAM.LCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MCLK_EN ,Enable internal clock of interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAMEXCLK_EN ,Enable CAM.EXCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " POLCLK ,Set polarity of CAM.LCLK" "Rising egde,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " FOSCMOD ,Set the frequency of the CAM.EXCLK clock" "ARM_PER_CK/8,ARM_PER_CK/3,ARM_PER_CK/16,ARM_PER_CK/2,ARM_PER_CK/10,ARM_PER_CK/4,ARM_PER_CK/12,Inactive"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "IT_STATUS,Interrupt source status"
|
|
bitfld.long 0x00 5. " DATA_TRANSFER ,Data transfer status. The trigger is reached" "Not reached,Reached"
|
|
bitfld.long 0x00 4. " FIFO_FULL ,Detects rising edge on FIFO full flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " H_DOWN ,Horizontal synchronous falling edge occured" "No edge,Edge"
|
|
bitfld.long 0x00 2. " H_UP ,Horizontal synchronous rising edge occured" "No edge,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " V_DOWN ,Vertical synchronous falling edge occured" "No edge,Edge"
|
|
bitfld.long 0x00 0. " V_UP ,Vertical synchronous rising edge occured" "No edge,Edge"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "MODE,Camera interface mode configuration"
|
|
bitfld.long 0x00 18. " RAZ_FIFO ,Clear data in the FIFO; reinitialize read and write pointers; clear FIFO full interrupt and FIFO peak counter; resynchronize" "No reinit,Reinit"
|
|
bitfld.long 0x00 17. " EN_FIFO_FULL ,Enable interrupt on FIFO_FULL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_NIRQ ,Enable data transfer interrupt (bypass DMA mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 9.--15. 1. " THRESHOLD ,Programmable DMA request triger value"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Enable DMA mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EN_H_DOWN ,Enable interrupt on HSYNC falling edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EN_H_UP ,Enable interrupt on HSYNC rising edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN_V_DOWN ,Enable interrupt on VSYNC falling edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_V_UP ,Enable interrupt on VSYNC rising edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ORDERCAMD ,Set order of 2 consecutive bytes received from camera (YUV format)" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " IMGSIZE ,Set image size" "CIF,QCIF,VGA,QVGA"
|
|
bitfld.long 0x00 0. " CAMOSC ,Set (a)synchronous mode (no effect currently)" "Synchronous,Asynchronous"
|
|
rgroup.long 0x0C++0x7
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 1. " HSTATUS ,CAM_HS status (edge detection)" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " VSTATUS ,CAM_VS status (edge detection)" "Not detected,Detected"
|
|
line.long 0x04 "CAMDATA,Image data"
|
|
hexfld.long 0x04 " CAMDATA ,Image data from FIFO"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "GPIO,Camera interface GPIO (general purpose input/output)"
|
|
bitfld.long 0x00 0. " CAM_RST ,Reset for camera module" "No reset,Reset"
|
|
line.long 0x04 "PEAK_COUNTER,FIFO peak counter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " PEAK_COUNTER ,Maximum number of words written to FIFO during the transfer since the last clear to zero"
|
|
tree.end
|
|
tree "L3 OCP T2"
|
|
base AD:0x3007D800
|
|
width 14.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "CTRLCLOCK,Clock control"
|
|
bitfld.long 0x00 7. " LCLK_EN ,Enable incoming CAM.LCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MCLK_EN ,Enable internal clock of interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CAMEXCLK_EN ,Enable CAM.EXCLK" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " POLCLK ,Set polarity of CAM.LCLK" "Rising egde,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " FOSCMOD ,Set the frequency of the CAM.EXCLK clock" "ARM_PER_CK/8,ARM_PER_CK/3,ARM_PER_CK/16,ARM_PER_CK/2,ARM_PER_CK/10,ARM_PER_CK/4,ARM_PER_CK/12,Inactive"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "IT_STATUS,Interrupt source status"
|
|
bitfld.long 0x00 5. " DATA_TRANSFER ,Data transfer status. The trigger is reached" "Not reached,Reached"
|
|
bitfld.long 0x00 4. " FIFO_FULL ,Detects rising edge on FIFO full flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 3. " H_DOWN ,Horizontal synchronous falling edge occured" "No edge,Edge"
|
|
bitfld.long 0x00 2. " H_UP ,Horizontal synchronous rising edge occured" "No edge,Edge"
|
|
textline " "
|
|
bitfld.long 0x00 1. " V_DOWN ,Vertical synchronous falling edge occured" "No edge,Edge"
|
|
bitfld.long 0x00 0. " V_UP ,Vertical synchronous rising edge occured" "No edge,Edge"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "MODE,Camera interface mode configuration"
|
|
bitfld.long 0x00 18. " RAZ_FIFO ,Clear data in the FIFO; reinitialize read and write pointers; clear FIFO full interrupt and FIFO peak counter; resynchronize" "No reinit,Reinit"
|
|
bitfld.long 0x00 17. " EN_FIFO_FULL ,Enable interrupt on FIFO_FULL" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EN_NIRQ ,Enable data transfer interrupt (bypass DMA mode)" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 9.--15. 1. " THRESHOLD ,Programmable DMA request triger value"
|
|
textline " "
|
|
bitfld.long 0x00 8. " DMA ,Enable DMA mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " EN_H_DOWN ,Enable interrupt on HSYNC falling edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " EN_H_UP ,Enable interrupt on HSYNC rising edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EN_V_DOWN ,Enable interrupt on VSYNC falling edge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " EN_V_UP ,Enable interrupt on VSYNC rising edge" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " ORDERCAMD ,Set order of 2 consecutive bytes received from camera (YUV format)" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x00 1.--2. " IMGSIZE ,Set image size" "CIF,QCIF,VGA,QVGA"
|
|
bitfld.long 0x00 0. " CAMOSC ,Set (a)synchronous mode (no effect currently)" "Synchronous,Asynchronous"
|
|
rgroup.long 0x0C++0x7
|
|
line.long 0x00 "STATUS,Status"
|
|
bitfld.long 0x00 1. " HSTATUS ,CAM_HS status (edge detection)" "Not detected,Detected"
|
|
bitfld.long 0x00 0. " VSTATUS ,CAM_VS status (edge detection)" "Not detected,Detected"
|
|
line.long 0x04 "CAMDATA,Image data"
|
|
hexfld.long 0x04 " CAMDATA ,Image data from FIFO"
|
|
group.long 0x14++0x7
|
|
line.long 0x00 "GPIO,Camera interface GPIO (general purpose input/output)"
|
|
bitfld.long 0x00 0. " CAM_RST ,Reset for camera module" "No reset,Reset"
|
|
line.long 0x04 "PEAK_COUNTER,FIFO peak counter"
|
|
hexmask.long.byte 0x04 0.--6. 1. " PEAK_COUNTER ,Maximum number of words written to FIFO during the transfer since the last clear to zero"
|
|
tree.end
|
|
tree.end
|
|
tree.end
|
|
tree "MPU/DSP Shared Peripheral Registers"
|
|
tree "UARTs"
|
|
width 0x0E
|
|
base AD:0xFFFB0000
|
|
tree "UART 1"
|
|
if (((data.byte(AD:0xFFFB0000+0x0C)&0x80)==0)&&(((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3)))
|
|
hgroup.byte 0x0000++0x00
|
|
hide.byte 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
textfld " "
|
|
in
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif (((data.byte(AD:0xFFFB0000+0x0C)&0x80)==0)&&(((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5)))
|
|
hgroup.byte 0x0000++0x00
|
|
hide.byte 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
textfld " "
|
|
in
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 07. " EOF_IT ,Enable received EOF interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,Enable TX status interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " STS_FIFO_TRIG_IT ,Enable status FIFO trigger level interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OVERRUN_IT ,Enable RX overrun interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " LAST_RX_BYTE_IT ,Enable last byte of frame in RX FIFO interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " RHR_IT ,Enable RHR interrupt" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0000++0x01
|
|
line.byte 0x00 "DLL,Divisor Latches Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.byte 0x0004++0x01
|
|
line.byte 0x00 "DLH,Divisor Latches High Register"
|
|
hexmask.byte 0x00 00.--05. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((data.byte(AD:0xFFFB0000+0x0c)&0xFF)==0xBF)
|
|
group.byte 0x0008++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 07. " AUTO_CTS_EN ,Auto-#CTS enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " AUTO_RTS_EN ,Auto-#RTS enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SPECIAL_CHAR_DETECT ,Special character detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " ENHANCED_EN ,Enhanced functions write enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 02.--03. " SW_FLOW_CONTROL[TX] ,Software flow control TX" "Not transmitted,Transmitted XON1/XOFF1,Transmitted XON2/XOFF2,Transmitted XON1/XOFF1/XON2/XOFF2"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " SW_FLOW_CONTROL[RX] ,Software flow control RX" "Not received,Received XON1/XOFF1,Received XON2/XOFF2,Received XON1/XOFF1/XON2/XOFF2"
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB0000+0x0c)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3))
|
|
rgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "IIR,Interrupt Identification Register (UART mode)"
|
|
bitfld.byte 0x00 07. " FCR_MIRROR[1] ,FCR[0] mirror" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " FCR_MIRROR[0] ,FCR[0] mirror" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,TX status interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 04. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OE_IT ,RX overrun interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 02. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,THR interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 00. " RHR_IT ,RHR interrupt" "Inactivated,Activated"
|
|
wgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "FCR,FIFO Control Register"
|
|
bitfld.byte 0x00 06.--07. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.byte 0x00 04.--05. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DMA_MODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.byte 0x00 02. " TX_FIFO_CLEAR ,Clear transmit FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_FIFO_CLEAR ,Clear receive FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 00. " FIFO_EN ,Enable FIFO" "Disabled,Enabled"
|
|
elif (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
rgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "IIR,Interrupt Identification Register (IRDA mode)"
|
|
bitfld.byte 0x00 07. " EOF_IT ,Received EOF interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 06. " LINE_STS_IT ,Receiver line status interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,TX status interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 04. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OE_IT ,RX overrun interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 02. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,THR interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 00. " RHR_IT ,RHR interrupt" "Inactivated,Activated"
|
|
wgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "FCR,FIFO Control Register"
|
|
bitfld.byte 0x00 06.--07. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.byte 0x00 04.--05. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DMA_MODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.byte 0x00 02. " TX_FIFO_CLEAR ,Clear transmit FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_FIFO_CLEAR ,Clear receive FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 00. " FIFO_EN ,Enable FIFO" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x0C)&0x03)==0)&&(((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3)))
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.byte 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " NB_STOP ,Number of stop bits" "1-bit,1.5-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " CHAR_LENGTH ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
elif (((data.byte(AD:0xFFFB0000+0x0C)&0x03)!=0)&&(((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3)))
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.byte 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " NB_STOP ,Number of stop bits" "1-bit,2-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " CHAR_LENGTH ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3)))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "XON1,XON1 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XON_WORD1 ,8-bit XON1 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
line.byte 0x00 "XON2,XON2 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XON_WORD2 ,8-bit XON2 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB0000+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5)))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "ADDR1,Address 1 Register"
|
|
hexmask.byte 0x00 00.--07. 1. " ADDR1 ,Address 1"
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
line.byte 0x00 "ADDR2,Address 2 Register"
|
|
hexmask.byte 0x00 00.--07. 1. " ADDR2 ,Address 2"
|
|
textline " "
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.byte 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.byte 0x0014++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No errors,Error"
|
|
bitfld.byte 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.byte 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.byte 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.byte 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.byte 0x0014++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 07. " THR_EMPTY ,Transmit holding register empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 06. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " RX_LAST_BYTE ,RX FIFO contains the last byte of the frame to be read" "Not contained,Contained"
|
|
bitfld.byte 0x00 04. " FRAME_TOO_byte ,Frame too-byte error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " ABORT ,Abort pattern error" "No error,Error"
|
|
bitfld.byte 0x00 02. " CRC ,CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
else
|
|
group.byte 0x0010++0x00
|
|
hide.byte 0x00 "MCR/XON1/ADDR1,Modem Control Register/XON1 Character Register/Address 1 Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
hide.byte 0x00 "LSR/XON2/ADDR2,Line Status Register/XON2 Character Register/Address 2 Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x0C)&0xFF)!=0xBF)&&(((data.byte(AD:0xFFFB0000+0x08)&0x10)==0x00)||((data.byte(AD:0xFFFB0000+0x10)&0x40)==0x00)))
|
|
rgroup.byte 0x0018++0x00
|
|
line.byte 0x00 "MSR,Modem Status Register (EFR[4]=0 or MCR[6]=0)"
|
|
bitfld.byte 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.byte 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.byte 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.byte 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.byte 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "SPR,Scratchpad Register"
|
|
hexmask.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif (((data.byte(AD:0xFFFB0000+0x08)&0x10)==0x10)&&((data.byte(AD:0xFFFB0000+0x10)&0x40)==0x40))
|
|
group.byte 0x0018++0x00
|
|
line.byte 0x00 "TCR,Transmission Control Register (EFR[4] = 1 and MCR[6] = 1)"
|
|
bitfld.byte 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.byte 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "TLR,Trigger Level Register (EFR[4] = 1 and MCR[6] = 1)"
|
|
bitfld.byte 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.byte 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((data.byte(AD:0xFFFB0000+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB0000+0x08)&0x10)==0x00)||((data.byte(AD:0xFFFB0000+0x10)&0x40)==0x00)))
|
|
group.byte 0x0018++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "XOFF2,XOFF2 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
else
|
|
group.byte 0x0018++0x00
|
|
hide.byte 0x00 "MSR/TCR/XOFF1,Modem Status Register/Transmission Control Register/XOFF1 Character Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
hide.byte 0x00 "SPR/TLR/XOFF2,Scratchpad Register/Trigger Level Register/XOFF2 Character Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x3)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x6)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x7))
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
elif (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SCT ,Store and control the transmission" "Started when wr to THR,Started with ctrl ACREG[2]"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " SET_TXIR ,to configure the IrDA transceiver" "No action,Forced TXIR"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " IR_SLEEP ,IrDA sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 06. " SIP_MODE ,Sip mode" "Manual,Automatic"
|
|
else
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SCT ,Store and control the transmission" "Started when wr to THR,Started with ctrl ACREG[2]"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " SET_TXIR ,to configure the IrDA transceiver" "No action,Forced TXIR"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " IR_SLEEP ,IrDA sleep mode" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
group.byte 0x0024++0x00
|
|
line.byte 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.byte 0x00 01.--02. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " IRTX_UNDERRUN ,IRDA transmission status interrupt" "Not occurred,Occurred"
|
|
else
|
|
group.byte 0x0024++0x00
|
|
hide.byte 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
rgroup.byte 0x0028++0x00
|
|
line.byte 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.byte 0x00 04. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 03. " FRAME_TOO_BYTE_ERROR ,Frame-length too byte error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " ABORT_DETECT ,Abort pattern" "Not detected,Detected"
|
|
bitfld.byte 0x00 01. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.byte 0x0028++0x00
|
|
line.byte 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " TXFLL ,Frame length"
|
|
rgroup.byte 0x002C++0x00
|
|
line.byte 0x00 "RESUME,Resume Register"
|
|
hexmask.byte 0x00 00.--07. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.byte 0x002C++0x00
|
|
line.byte 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.byte 0x00 00.--07. 1. " TXFLH ,Frame length"
|
|
rgroup.byte 0x0030++0x00
|
|
line.byte 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.byte 0x00 00.--07. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.byte 0x0030++0x00
|
|
line.byte 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " RXFLL ,LSB frame length in reception"
|
|
rgroup.byte 0x0034++0x00
|
|
line.byte 0x00 "SFREGH,Status FIFO Register High"
|
|
hexmask.byte 0x00 00.--03. 1. " SFREGH ,MSB part of the frame length"
|
|
wgroup.byte 0x0034++0x00
|
|
line.byte 0x00 "RXFLH,Received Frame Length High Register"
|
|
hexmask.byte 0x00 00.--03. 1. " RXFLH ,MSB frame length in reception"
|
|
else
|
|
group.byte 0x0028++0x00
|
|
hide.byte 0x00 "SFLSR/TXFLL,Status FIFO Line Status Register/Transmit Frame Length Low Register"
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x002C++0x00
|
|
hide.byte 0x00 "RESUME/TXFLH,Resume Register/Transmit Frame Length High Register"
|
|
textline " "
|
|
group.byte 0x0030++0x00
|
|
hide.byte 0x00 "SFREGL/RXFLL,Status FIFO Register Low/Received Frame Length Low Register"
|
|
textline " "
|
|
group.byte 0x0034++0x00
|
|
hide.byte 0x00 "SFREGH/RXFLH,Status FIFO Register High/Received Frame Length High Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
group.byte 0x0038++0x00
|
|
line.byte 0x00 "BLR,BOF Control Register"
|
|
bitfld.byte 0x00 07. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.byte 0x00 06. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
elif ((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x2)
|
|
rgroup.byte 0x0038++0x00
|
|
line.byte 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.byte 0x00 06.--07. " PARITY_TYPE ,Parity type" "No parity,Parity space,Even parity,Odd parity"
|
|
bitfld.byte 0x00 05. " BIT_BY_CHAR ,Char length" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--04. " SPEED ,speed identified" "Not identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,Reserved,Reserved,Reserved,Reserved,Reserved ,?..."
|
|
else
|
|
group.byte 0x0038++0x00
|
|
hide.byte 0x00 "BLR/UASR,BOF Control Register/UART Autobauding Status Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
group.byte 0x003C++0x00
|
|
line.byte 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.byte 0x00 07. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.byte 0x00 06. " SD_MOD ,SD pin" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " DIS_IR_RX ,Disable RXIR input" "Enabled,Disabled"
|
|
bitfld.byte 0x00 04. " DIS_TX_UNDERRUN ,Disable TX underrun" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " SEND_SIP ,Send serial infrared interaction pulse" "Not send,Send"
|
|
bitfld.byte 0x00 02. " SCTX_EN ,Store and controlled TX start" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " ABORT_EN ,Frame abort" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " EOT_EN ,EOT (end of transmission)" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x003C++0x00
|
|
hide.byte 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
group.byte 0x0040++0x00
|
|
line.byte 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.byte 0x00 07. " RX_TRIG_GRANU1 ,Granularity of 1 for trigger RX level" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " TX_TRIG_GRANU1 ,Granularity of 1 for trigger TX level" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " DSR_IT ,#DSR interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " RX_CTS_DSR_WAKE_UP_ENABLE ,Wake-up interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " TX_EMPTY_CTL_IT ,Control THR interrupt" "Normal mode,When empty"
|
|
bitfld.byte 0x00 01.--02. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DMA_MODE_CTL ,DMA mode control" "FCR[DMA_MODE],SCR[DMA_MODE_2]"
|
|
rgroup.byte 0x0044++0x00
|
|
line.byte 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.byte 0x00 01. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX/#CTS/#DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
if (((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0000+0x20)&0x07)==0x5))
|
|
group.byte 0x0048++0x00
|
|
line.byte 0x00 "EBLR,BOF Length Register"
|
|
hexmask.byte 0x00 00.--07. 1. " EBLR ,Definition xBOFs"
|
|
else
|
|
group.byte 0x0048++0x00
|
|
hide.byte 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.byte 0x0050++0x00
|
|
line.byte 0x00 "MVR,Module Version Register"
|
|
bitfld.byte 0x00 04.--07. " MAJOR_REV ,Major revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 00.--03. " MINOR_REV ,Minor revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x0054++0x00
|
|
line.byte 0x00 "SYSC,System Configuration Register"
|
|
bitfld.byte 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "Forced IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.byte 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.byte 0x0058++0x00
|
|
line.byte 0x00 "SYSS,System Status Register"
|
|
bitfld.byte 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.byte 0x005C++0x00
|
|
line.byte 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.byte 0x00 06. " EVENT_6 ,Receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " EVENT_5 ,RHR interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " EVENT_4 ,RX/RXIR activity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " EVENT_3 ,DCD (CD) activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " EVENT_2 ,RI activity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 01. " EVENT_1 ,DSR activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " EVENT_0 ,CTS activity" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0E
|
|
base AD:0xFFFB0800
|
|
tree "UART 2"
|
|
if (((data.byte(AD:0xFFFB0800+0x0C)&0x80)==0)&&(((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3)))
|
|
hgroup.byte 0x0000++0x00
|
|
hide.byte 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
textfld " "
|
|
in
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif (((data.byte(AD:0xFFFB0800+0x0C)&0x80)==0)&&(((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5)))
|
|
hgroup.byte 0x0000++0x00
|
|
hide.byte 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
textfld " "
|
|
in
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 07. " EOF_IT ,Enable received EOF interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,Enable TX status interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " STS_FIFO_TRIG_IT ,Enable status FIFO trigger level interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OVERRUN_IT ,Enable RX overrun interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " LAST_RX_BYTE_IT ,Enable last byte of frame in RX FIFO interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " RHR_IT ,Enable RHR interrupt" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0000++0x00
|
|
line.byte 0x00 "DLL,Divisor Latches Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "DLH,Divisor Latches High Register"
|
|
hexmask.byte 0x00 00.--05. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((data.byte(AD:0xFFFB0800+0x0C)&0xFF)==0xBF)
|
|
group.byte 0x0008++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 07. " AUTO_CTS_EN ,Auto-#CTS enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " AUTO_RTS_EN ,Auto-#RTS enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SPECIAL_CHAR_DETECT ,Special character detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " ENHANCED_EN ,Enhanced functions write enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 02.--03. " SW_FLOW_CONTROL[TX] ,Software flow control TX" "Not transmitted,Transmitted XON1/XOFF1,Transmitted XON2/XOFF2,Transmitted XON1/XOFF1/XON2/XOFF2"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " SW_FLOW_CONTROL[RX] ,Software flow control RX" "Not received,Received XON1/XOFF1,Received XON2/XOFF2,Received XON1/XOFF1/XON2/XOFF2"
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB0800+0x0C)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3))
|
|
rgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "IIR,Interrupt Identification Register (UART mode)"
|
|
bitfld.byte 0x00 07. " FCR_MIRROR[1] ,FCR[0] mirror" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " FCR_MIRROR[0] ,FCR[0] mirror" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,TX status interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 04. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OE_IT ,RX overrun interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 02. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,THR interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 00. " RHR_IT ,RHR interrupt" "Inactivated,Activated"
|
|
wgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "FCR,FIFO Control Register"
|
|
bitfld.byte 0x00 06.--07. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.byte 0x00 04.--05. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DMA_MODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.byte 0x00 02. " TX_FIFO_CLEAR ,Clear transmit FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_FIFO_CLEAR ,Clear receive FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 00. " FIFO_EN ,Enable FIFO" "Disabled,Enabled"
|
|
elif (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
rgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "IIR,Interrupt Identification Register (IRDA mode)"
|
|
bitfld.byte 0x00 07. " EOF_IT ,Received EOF interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 06. " LINE_STS_IT ,Receiver line status interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,TX status interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 04. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OE_IT ,RX overrun interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 02. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,THR interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 00. " RHR_IT ,RHR interrupt" "Inactivated,Activated"
|
|
wgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "FCR,FIFO Control Register"
|
|
bitfld.byte 0x00 06.--07. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.byte 0x00 04.--05. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DMA_MODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.byte 0x00 02. " TX_FIFO_CLEAR ,Clear transmit FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_FIFO_CLEAR ,Clear receive FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 00. " FIFO_EN ,Enable FIFO" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x0C)&0x03)==0)&&(((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3)))
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.byte 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " NB_STOP ,Number of stop bits" "1-bit,1.5-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " CHAR_LENGTH ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
elif (((data.byte(AD:0xFFFB0800+0x0C)&0x03)!=0)&&(((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3)))
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.byte 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " NB_STOP ,Number of stop bits" "1-bit,2-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " CHAR_LENGTH ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3)))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "XON1,XON1 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XON_WORD1 ,8-bit XON1 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
line.byte 0x00 "XON2,XON2 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XON_WORD2 ,8-bit XON2 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB0800+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5)))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "ADDR1,Address 1 Register"
|
|
hexmask.byte 0x00 00.--07. 1. " ADDR1 ,Address 1"
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
line.byte 0x00 "ADDR2,Address 2 Register"
|
|
hexmask.byte 0x00 00.--07. 1. " ADDR2 ,Address 2"
|
|
textline " "
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.byte 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.byte 0x0014++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No errors,Error"
|
|
bitfld.byte 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.byte 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.byte 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.byte 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.byte 0x0014++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 07. " THR_EMPTY ,Transmit holding register empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 06. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " RX_LAST_BYTE ,RX FIFO contains the last byte of the frame to be read" "Not contained,Contained"
|
|
bitfld.byte 0x00 04. " FRAME_TOO_byte ,Frame too-byte error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " ABORT ,Abort pattern error" "No error,Error"
|
|
bitfld.byte 0x00 02. " CRC ,CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
else
|
|
group.byte 0x0010++0x00
|
|
hide.byte 0x00 "MCR/XON1/ADDR1,Modem Control Register/XON1 Character Register/Address 1 Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
hide.byte 0x00 "LSR/XON2/ADDR2,Line Status Register/XON2 Character Register/Address 2 Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x0C)&0xFF)!=0xBF)&&(((data.byte(AD:0xFFFB0800+0x08)&0x10)==0x00)||((data.byte(AD:0xFFFB0800+0x10)&0x40)==0x00)))
|
|
rgroup.byte 0x0018++0x00
|
|
line.byte 0x00 "MSR,Modem Status Register (EFR[4]=0 or MCR[6]=0)"
|
|
bitfld.byte 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.byte 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.byte 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.byte 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.byte 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "SPR,Scratchpad Register"
|
|
hexmask.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif (((data.byte(AD:0xFFFB0800+0x08)&0x10)==0x10)&&((data.byte(AD:0xFFFB0800+0x10)&0x40)==0x40))
|
|
group.byte 0x0018++0x00
|
|
line.byte 0x00 "TCR,Transmission Control Register (EFR[4] = 1 and MCR[6] = 1)"
|
|
bitfld.byte 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.byte 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "TLR,Trigger Level Register (EFR[4] = 1 and MCR[6] = 1)"
|
|
bitfld.byte 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.byte 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((data.byte(AD:0xFFFB0800+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB0800+0x08)&0x10)==0x00)||((data.byte(AD:0xFFFB0800+0x10)&0x40)==0x00)))
|
|
group.byte 0x0018++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "XOFF2,XOFF2 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
else
|
|
group.byte 0x0018++0x00
|
|
hide.byte 0x00 "MSR/TCR/XOFF1,Modem Status Register/Transmission Control Register/XOFF1 Character Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
hide.byte 0x00 "SPR/TLR/XOFF2,Scratchpad Register/Trigger Level Register/XOFF2 Character Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x3)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x6)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x7))
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
elif (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SCT ,Store and control the transmission" "Started when wr to THR,Started with ctrl ACREG[2]"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " SET_TXIR ,to configure the IrDA transceiver" "No action,Forced TXIR"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " IR_SLEEP ,IrDA sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 06. " SIP_MODE ,Sip mode" "Manual,Automatic"
|
|
else
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SCT ,Store and control the transmission" "Started when wr to THR,Started with ctrl ACREG[2]"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " SET_TXIR ,to configure the IrDA transceiver" "No action,Forced TXIR"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " IR_SLEEP ,IrDA sleep mode" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
group.byte 0x0024++0x00
|
|
line.byte 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.byte 0x00 01.--02. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " IRTX_UNDERRUN ,IRDA transmission status interrupt" "Not occurred,Occurred"
|
|
else
|
|
group.byte 0x0024++0x00
|
|
hide.byte 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
rgroup.byte 0x0028++0x00
|
|
line.byte 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.byte 0x00 04. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 03. " FRAME_TOO_BYTE_ERROR ,Frame-length too byte error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " ABORT_DETECT ,Abort pattern" "Not detected,Detected"
|
|
bitfld.byte 0x00 01. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.byte 0x0028++0x00
|
|
line.byte 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " TXFLL ,Frame length"
|
|
rgroup.byte 0x002C++0x00
|
|
line.byte 0x00 "RESUME,Resume Register"
|
|
hexmask.byte 0x00 00.--07. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.byte 0x002C++0x00
|
|
line.byte 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.byte 0x00 00.--07. 1. " TXFLH ,Frame length"
|
|
rgroup.byte 0x0030++0x00
|
|
line.byte 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.byte 0x00 00.--07. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.byte 0x0030++0x00
|
|
line.byte 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " RXFLL ,LSB frame length in reception"
|
|
rgroup.byte 0x0034++0x00
|
|
line.byte 0x00 "SFREGH,Status FIFO Register High"
|
|
hexmask.byte 0x00 00.--03. 1. " SFREGH ,MSB part of the frame length"
|
|
wgroup.byte 0x0034++0x00
|
|
line.byte 0x00 "RXFLH,Received Frame Length High Register"
|
|
hexmask.byte 0x00 00.--03. 1. " RXFLH ,MSB frame length in reception"
|
|
else
|
|
group.byte 0x0028++0x00
|
|
hide.byte 0x00 "SFLSR/TXFLL,Status FIFO Line Status Register/Transmit Frame Length Low Register"
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x002C++0x00
|
|
hide.byte 0x00 "RESUME/TXFLH,Resume Register/Transmit Frame Length High Register"
|
|
textline " "
|
|
group.byte 0x0030++0x00
|
|
hide.byte 0x00 "SFREGL/RXFLL,Status FIFO Register Low/Received Frame Length Low Register"
|
|
textline " "
|
|
group.byte 0x0034++0x00
|
|
hide.byte 0x00 "SFREGH/RXFLH,Status FIFO Register High/Received Frame Length High Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
group.byte 0x0038++0x00
|
|
line.byte 0x00 "BLR,BOF Control Register"
|
|
bitfld.byte 0x00 07. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.byte 0x00 06. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
elif ((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x2)
|
|
rgroup.byte 0x0038++0x00
|
|
line.byte 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.byte 0x00 06.--07. " PARITY_TYPE ,Parity type" "No parity,Parity space,Even parity,Odd parity"
|
|
bitfld.byte 0x00 05. " BIT_BY_CHAR ,Char length" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--04. " SPEED ,speed identified" "Not identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,Reserved,Reserved,Reserved,Reserved,Reserved ,?..."
|
|
else
|
|
hgroup.byte 0x0038++0x00
|
|
hide.byte 0x00 "BLR/UASR,BOF Control Register/UART Autobauding Status Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
group.byte 0x003C++0x00
|
|
line.byte 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.byte 0x00 07. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.byte 0x00 06. " SD_MOD ,SD pin" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " DIS_IR_RX ,Disable RXIR input" "Enabled,Disabled"
|
|
bitfld.byte 0x00 04. " DIS_TX_UNDERRUN ,Disable TX underrun" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " SEND_SIP ,Send serial infrared interaction pulse" "Not send,Send"
|
|
bitfld.byte 0x00 02. " SCTX_EN ,Store and controlled TX start" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " ABORT_EN ,Frame abort" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " EOT_EN ,EOT (end of transmission)" "Disabled,Enabled"
|
|
else
|
|
hgroup.byte 0x003C++0x00
|
|
hide.byte 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
group.byte 0x0040++0x00
|
|
line.byte 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.byte 0x00 07. " RX_TRIG_GRANU1 ,Granularity of 1 for trigger RX level" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " TX_TRIG_GRANU1 ,Granularity of 1 for trigger TX level" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " DSR_IT ,#DSR interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " RX_CTS_DSR_WAKE_UP_ENABLE ,Wake-up interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " TX_EMPTY_CTL_IT ,Control THR interrupt" "Normal mode,When empty"
|
|
bitfld.byte 0x00 01.--02. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DMA_MODE_CTL ,DMA mode control" "FCR[DMA_MODE],SCR[DMA_MODE_2]"
|
|
rgroup.byte 0x0044++0x00
|
|
line.byte 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.byte 0x00 01. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX/#CTS/#DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
if (((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB0800+0x20)&0x07)==0x5))
|
|
group.byte 0x0048++0x00
|
|
line.byte 0x00 "EBLR,BOF Length Register"
|
|
hexmask.byte 0x00 00.--07. 1. " EBLR ,Definition xBOFs"
|
|
else
|
|
hgroup.byte 0x0048++0x00
|
|
hide.byte 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.byte 0x0050++0x00
|
|
line.byte 0x00 "MVR,Module Version Register"
|
|
bitfld.byte 0x00 04.--07. " MAJOR_REV ,Major revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 00.--03. " MINOR_REV ,Minor revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x0054++0x00
|
|
line.byte 0x00 "SYSC,System Configuration Register"
|
|
bitfld.byte 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "Forced IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.byte 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.byte 0x0058++0x00
|
|
line.byte 0x00 "SYSS,System Status Register"
|
|
bitfld.byte 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.byte 0x005C++0x00
|
|
line.byte 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.byte 0x00 06. " EVENT_6 ,Receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " EVENT_5 ,RHR interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " EVENT_4 ,RX/RXIR activity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " EVENT_3 ,DCD (CD) activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " EVENT_2 ,RI activity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 01. " EVENT_1 ,DSR activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " EVENT_0 ,CTS activity" "Disabled,Enabled"
|
|
tree.end
|
|
width 0x0E
|
|
base AD:0xFFFB9800
|
|
tree "UART 3"
|
|
if (((data.byte(AD:0xFFFB9800+0x0C)&0x80)==0)&&(((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3)))
|
|
hgroup.byte 0x0000++0x00
|
|
hide.byte 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
textfld " "
|
|
in
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 07. " CTS_IT ,Enable #CTS interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " RTS_IT ,Enable #RTS interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " XOFF_IT ,Enable XOFF interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " SLEEP_MODE ,Enable SLEEP mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " MODEM_STS_IT ,Enable modem status register interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " RHR_IT ,Enable RHR interrupt and time-out interrupt" "Disabled,Enabled"
|
|
elif (((data.byte(AD:0xFFFB9800+0x0C)&0x80)==0)&&(((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5)))
|
|
hgroup.byte 0x0000++0x00
|
|
hide.byte 0x00 "RHR/THR,Receive/Transmit Holding Register"
|
|
textfld " "
|
|
in
|
|
group.byte 0x0004++0x00
|
|
line.byte 0x00 "IER,Interrupt Enable Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 07. " EOF_IT ,Enable received EOF interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " LINE_STS_IT ,Enable receiver line status interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,Enable TX status interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " STS_FIFO_TRIG_IT ,Enable status FIFO trigger level interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OVERRUN_IT ,Enable RX overrun interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " LAST_RX_BYTE_IT ,Enable last byte of frame in RX FIFO interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,Enable THR interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " RHR_IT ,Enable RHR interrupt" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x0000++0x01
|
|
line.byte 0x00 "DLL,Divisor Latches Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " CLOCK_LSB ,8-bit LSB divisor value"
|
|
group.byte 0x0004++0x01
|
|
line.byte 0x00 "DLH,Divisor Latches High Register"
|
|
hexmask.byte 0x00 00.--05. 1. " CLOCK_MSB ,6-bit MSB divisor value"
|
|
endif
|
|
if ((data.byte(AD:0xFFFB9800+0x0c)&0xFF)==0xBF)
|
|
group.byte 0x0008++0x00
|
|
line.byte 0x00 "EFR,Enhanced Feature Register"
|
|
bitfld.byte 0x00 07. " AUTO_CTS_EN ,Auto-#CTS enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " AUTO_RTS_EN ,Auto-#RTS enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SPECIAL_CHAR_DETECT ,Special character detect enable bit" "Disabled,Enabled"
|
|
bitfld.byte 0x00 04. " ENHANCED_EN ,Enhanced functions write enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 02.--03. " SW_FLOW_CONTROL[TX] ,Software flow control TX" "Not transmitted,Transmitted XON1/XOFF1,Transmitted XON2/XOFF2,Transmitted XON1/XOFF1/XON2/XOFF2"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " SW_FLOW_CONTROL[RX] ,Software flow control RX" "Not received,Received XON1/XOFF1,Received XON2/XOFF2,Received XON1/XOFF1/XON2/XOFF2"
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB9800+0x0c)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3))
|
|
rgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "IIR,Interrupt Identification Register (UART mode)"
|
|
bitfld.byte 0x00 07. " FCR_MIRROR[1] ,FCR[0] mirror" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " FCR_MIRROR[0] ,FCR[0] mirror" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,TX status interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 04. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OE_IT ,RX overrun interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 02. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,THR interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 00. " RHR_IT ,RHR interrupt" "Inactivated,Activated"
|
|
wgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "FCR,FIFO Control Register"
|
|
bitfld.byte 0x00 06.--07. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.byte 0x00 04.--05. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DMA_MODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.byte 0x00 02. " TX_FIFO_CLEAR ,Clear transmit FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_FIFO_CLEAR ,Clear receive FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 00. " FIFO_EN ,Enable FIFO" "Disabled,Enabled"
|
|
elif (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
rgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "IIR,Interrupt Identification Register (IRDA mode)"
|
|
bitfld.byte 0x00 07. " EOF_IT ,Received EOF interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 06. " LINE_STS_IT ,Receiver line status interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_STATUS_IT ,TX status interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 04. " STS_FIFO_IT ,Status FIFO trigger level interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_OE_IT ,RX overrun interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 02. " RX_FIFO_LAST_BYTE_IT ,Last byte of frame in RX FIFO interrupt" "Inactivated,Activated"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " THR_IT ,THR interrupt" "Inactivated,Activated"
|
|
bitfld.byte 0x00 00. " RHR_IT ,RHR interrupt" "Inactivated,Activated"
|
|
wgroup.byte 0x0008++0x00
|
|
line.byte 0x00 "FCR,FIFO Control Register"
|
|
bitfld.byte 0x00 06.--07. " RX_FIFO_TRIG ,Trigger level for the RX FIFO" "8 characters,16 characters,56 characters,60 characters"
|
|
bitfld.byte 0x00 04.--05. " TX_FIFO_TRIG ,Trigger level for the TX FIFO" "8 spaces,16 spaces,32 spaces,56 spaces"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DMA_MODE ,DMA mode" "Mode 0,Mode 1"
|
|
bitfld.byte 0x00 02. " TX_FIFO_CLEAR ,Clear transmit FIFO" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_FIFO_CLEAR ,Clear receive FIFO" "Not cleared,Cleared"
|
|
bitfld.byte 0x00 00. " FIFO_EN ,Enable FIFO" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x0C)&0x03)==0)&&(((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3)))
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.byte 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " NB_STOP ,Number of stop bits" "1-bit,1.5-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " CHAR_LENGTH ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
elif (((data.byte(AD:0xFFFB9800+0x0C)&0x03)!=0)&&(((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3)))
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " BREAK_EN ,Break control bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " PARITY_TYPE2 ,Parity type" "0,1"
|
|
bitfld.byte 0x00 04. " PARITY_TYPE1 ,Parity type" "Odd,Even"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " PARITY_EN ,Enable parity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 02. " NB_STOP ,Number of stop bits" "1-bit,2-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--01. " CHAR_LENGTH ,Word length" "5-bit,6-bit,7-bit,8-bit"
|
|
else
|
|
group.byte 0x000C++0x00
|
|
line.byte 0x00 "LCR,Line Control Register"
|
|
bitfld.byte 0x00 07. " DIV_EN ,Enable divisor latch" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3)))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "XON1,XON1 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XON_WORD1 ,8-bit XON1 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
line.byte 0x00 "XON2,XON2 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XON_WORD2 ,8-bit XON2 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB9800+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5)))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "ADDR1,Address 1 Register"
|
|
hexmask.byte 0x00 00.--07. 1. " ADDR1 ,Address 1"
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
line.byte 0x00 "ADDR2,Address 2 Register"
|
|
hexmask.byte 0x00 00.--07. 1. " ADDR2 ,Address 2"
|
|
textline " "
|
|
textline " "
|
|
elif (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.byte 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.byte 0x0014++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 07. " RX_FIFO_STS ,Receive FIFO status" "No errors,Error"
|
|
bitfld.byte 0x00 06. " TX_SR_E ,Transmitter hold and shift registers empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " TX_FIFO_E ,Transmit FIFO empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 04. " RX_BI ,Receive break" "No break,Break"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " RX_FE ,Receive framing error" "No error,Error"
|
|
bitfld.byte 0x00 02. " RX_PE ,Receive parity error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " RX_OE ,Receive overrun error" "No error,Error"
|
|
bitfld.byte 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
elif (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
group.byte 0x0010++0x00
|
|
line.byte 0x00 "MCR,Modem Control Register (EFR[4]=1)"
|
|
bitfld.byte 0x00 06. " TCR_TLR ,Enable access to TCR/TLR registers" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " XON_EN ,Enable XON any function" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " LOOPBACK_EN ,Enable LOOPBACK mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " CD_STS_CH ,Force #DCD input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " RI_STS_CH ,Force #RI input" "High,Low"
|
|
bitfld.byte 0x00 01. " RTS ,Force #RTS output" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DTR ,Force #DTR output" "High,Low"
|
|
rgroup.byte 0x0014++0x00
|
|
line.byte 0x00 "LSR,Line Status Register"
|
|
bitfld.byte 0x00 07. " THR_EMPTY ,Transmit holding register empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 06. " STS_FIFO_FULL ,Status FIFO full" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " RX_LAST_BYTE ,RX FIFO contains the last byte of the frame to be read" "Not contained,Contained"
|
|
bitfld.byte 0x00 04. " FRAME_TOO_byte ,Frame too-byte error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " ABORT ,Abort pattern error" "No error,Error"
|
|
bitfld.byte 0x00 02. " CRC ,CRC error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " STS_FIFO_E ,Status FIFO empty" "Not empty,Empty"
|
|
bitfld.byte 0x00 00. " RX_FIFO_E ,Receive FIFO empty" "Not empty,Empty"
|
|
else
|
|
group.byte 0x0010++0x00
|
|
hide.byte 0x00 "MCR/XON1/ADDR1,Modem Control Register/XON1 Character Register/Address 1 Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x0014++0x00
|
|
hide.byte 0x00 "LSR/XON2/ADDR2,Line Status Register/XON2 Character Register/Address 2 Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x0C)&0xFF)!=0xBF)&&(((data.byte(AD:0xFFFB9800+0x08)&0x10)==0x00)||((data.byte(AD:0xFFFB9800+0x10)&0x40)==0x00)))
|
|
rgroup.byte 0x0018++0x00
|
|
line.byte 0x00 "MSR,Modem Status Register (EFR[4]=0 or MCR[6]=0)"
|
|
bitfld.byte 0x00 07. " NCD_STS ,Complement of the #DCD input" "High,Low"
|
|
bitfld.byte 0x00 06. " NRI_STS ,Complement of the #RI input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " NDSR_STS ,Complement of the #DSR input" "High,Low"
|
|
bitfld.byte 0x00 04. " NCTS_STS ,Complement of the #CTS input" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " DCD_STS ,#DCD input status" "Not changed,Changed"
|
|
bitfld.byte 0x00 02. " RI_STS ,#RI input status" "Not changed,Changed"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " DSR_STS ,#DSR input status" "Not changed,Changed"
|
|
bitfld.byte 0x00 00. " CTS_STS ,#CTS input status" "Not changed,Changed"
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "SPR,Scratchpad Register"
|
|
hexmask.byte 0x00 00.--07. 1. " SPR_WORD ,Scratchpad register"
|
|
elif (((data.byte(AD:0xFFFB9800+0x08)&0x10)==0x10)&&((data.byte(AD:0xFFFB9800+0x10)&0x40)==0x40))
|
|
group.byte 0x0018++0x00
|
|
line.byte 0x00 "TCR,Transmission Control Register (EFR[4] = 1 and MCR[6] = 1)"
|
|
bitfld.byte 0x00 04.--07. " RX_FIFO_TRIG_START ,RCV FIFO trigger level to RESTORE transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.byte 0x00 00.--03. " RX_FIFO_TRIG_HALT ,RCV FIFO trigger level to HALT transmission" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "TLR,Trigger Level Register (EFR[4] = 1 and MCR[6] = 1)"
|
|
bitfld.byte 0x00 04.--07. " RX_FIFO_TRIG_DMA ,RCV FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
bitfld.byte 0x00 00.--03. " TX_FIFO_TRIG_DMA ,Transmit FIFO trigger level" "0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60"
|
|
elif (((data.byte(AD:0xFFFB9800+0x0C)&0xFF)==0xBF)&&(((data.byte(AD:0xFFFB9800+0x08)&0x10)==0x00)||((data.byte(AD:0xFFFB9800+0x10)&0x40)==0x00)))
|
|
group.byte 0x0018++0x00
|
|
line.byte 0x00 "XOFF1,XOFF1 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XOFF_WORD1 ,8-bit XOFF1 character"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
line.byte 0x00 "XOFF2,XOFF2 Character Register"
|
|
hexmask.byte 0x00 00.--07. 1. " XOFF_WORD2 ,8-bit XOFF2 character"
|
|
else
|
|
group.byte 0x0018++0x00
|
|
hide.byte 0x00 "MSR/TCR/XOFF1,Modem Status Register/Transmission Control Register/XOFF1 Character Register"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x001C++0x00
|
|
hide.byte 0x00 "SPR/TLR/XOFF2,Scratchpad Register/Trigger Level Register/XOFF2 Character Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x0)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x3)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x6)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x7))
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
elif (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SCT ,Store and control the transmission" "Started when wr to THR,Started with ctrl ACREG[2]"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " SET_TXIR ,to configure the IrDA transceiver" "No action,Forced TXIR"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " IR_SLEEP ,IrDA sleep mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 06. " SIP_MODE ,Sip mode" "Manual,Automatic"
|
|
else
|
|
group.byte 0x0020++0x00
|
|
line.byte 0x00 "MDR1,Mode Definition Register 1"
|
|
bitfld.byte 0x00 07. " FRAME_END_MODE ,Frame end mode" "Frame-length,EOT"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--02. " MODE_SELECT ,Select mode" "UART 16x,SIR,UART 16x autobaud,UART 13x,MIR,FIR,Reserved,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " SCT ,Store and control the transmission" "Started when wr to THR,Started with ctrl ACREG[2]"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " SET_TXIR ,to configure the IrDA transceiver" "No action,Forced TXIR"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " IR_SLEEP ,IrDA sleep mode" "Disabled,Enabled"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
group.byte 0x0024++0x00
|
|
line.byte 0x00 "MDR2,Mode Definition Register 2"
|
|
bitfld.byte 0x00 01.--02. " STS_FIFO_TRIG ,Frame status FIFO threshold select" "1 entry,4 entries,7 entries,8 entries"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " IRTX_UNDERRUN ,IRDA transmission status interrupt" "Not occurred,Occurred"
|
|
else
|
|
group.byte 0x0024++0x00
|
|
hide.byte 0x00 "MDR2,Mode Definition Register 2"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
rgroup.byte 0x0028++0x00
|
|
line.byte 0x00 "SFLSR,Status FIFO Line Status Register"
|
|
bitfld.byte 0x00 04. " OE_ERROR ,Overrun error" "No error,Error"
|
|
bitfld.byte 0x00 03. " FRAME_TOO_BYTE_ERROR ,Frame-length too byte error" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " ABORT_DETECT ,Abort pattern" "Not detected,Detected"
|
|
bitfld.byte 0x00 01. " CRC_ERROR ,CRC error" "No error,Error"
|
|
wgroup.byte 0x0028++0x00
|
|
line.byte 0x00 "TXFLL,Transmit Frame Length Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " TXFLL ,Frame length"
|
|
rgroup.byte 0x002C++0x00
|
|
line.byte 0x00 "RESUME,Resume Register"
|
|
hexmask.byte 0x00 00.--07. 1. " RESUME ,Dummy read to restart the TX or RX"
|
|
wgroup.byte 0x002C++0x00
|
|
line.byte 0x00 "TXFLH,Transmit Frame Length High Register"
|
|
hexmask.byte 0x00 00.--07. 1. " TXFLH ,Frame length"
|
|
rgroup.byte 0x0030++0x00
|
|
line.byte 0x00 "SFREGL,Status FIFO Register Low"
|
|
hexmask.byte 0x00 00.--07. 1. " SFREGL ,LSB part of the frame length"
|
|
wgroup.byte 0x0030++0x00
|
|
line.byte 0x00 "RXFLL,Received Frame Length Low Register"
|
|
hexmask.byte 0x00 00.--07. 1. " RXFLL ,LSB frame length in reception"
|
|
rgroup.byte 0x0034++0x00
|
|
line.byte 0x00 "SFREGH,Status FIFO Register High"
|
|
hexmask.byte 0x00 00.--03. 1. " SFREGH ,MSB part of the frame length"
|
|
wgroup.byte 0x0034++0x00
|
|
line.byte 0x00 "RXFLH,Received Frame Length High Register"
|
|
hexmask.byte 0x00 00.--03. 1. " RXFLH ,MSB frame length in reception"
|
|
else
|
|
group.byte 0x0028++0x00
|
|
hide.byte 0x00 "SFLSR/TXFLL,Status FIFO Line Status Register/Transmit Frame Length Low Register"
|
|
textline " "
|
|
textline " "
|
|
group.byte 0x002C++0x00
|
|
hide.byte 0x00 "RESUME/TXFLH,Resume Register/Transmit Frame Length High Register"
|
|
textline " "
|
|
group.byte 0x0030++0x00
|
|
hide.byte 0x00 "SFREGL/RXFLL,Status FIFO Register Low/Received Frame Length Low Register"
|
|
textline " "
|
|
group.byte 0x0034++0x00
|
|
hide.byte 0x00 "SFREGH/RXFLH,Status FIFO Register High/Received Frame Length High Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
group.byte 0x0038++0x00
|
|
line.byte 0x00 "BLR,BOF Control Register"
|
|
bitfld.byte 0x00 07. " STS_FIFO_RESET ,Status FIFO reset" "No reset,Reset"
|
|
bitfld.byte 0x00 06. " XBOF_TYPE ,SIR xBOF select" "0xFF,0xC0"
|
|
elif ((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x2)
|
|
rgroup.byte 0x0038++0x00
|
|
line.byte 0x00 "UASR,UART Autobauding Status Register"
|
|
bitfld.byte 0x00 06.--07. " PARITY_TYPE ,Parity type" "No parity,Parity space,Even parity,Odd parity"
|
|
bitfld.byte 0x00 05. " BIT_BY_CHAR ,Char length" "7-bit,8-bit"
|
|
textline " "
|
|
bitfld.byte 0x00 00.--04. " SPEED ,speed identified" "Not identified,115200 bauds,57600 bauds,38400 bauds,28800 bauds,19200 bauds,14400 bauds,9600 bauds,4800 bauds,2400 bauds,1200 bauds,Reserved,Reserved,Reserved,Reserved,Reserved ,?..."
|
|
else
|
|
group.byte 0x0038++0x00
|
|
hide.byte 0x00 "BLR/UASR,BOF Control Register/UART Autobauding Status Register"
|
|
endif
|
|
if (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
group.byte 0x003C++0x00
|
|
line.byte 0x00 "ACREG,Auxiliary Control Register"
|
|
bitfld.byte 0x00 07. " PULSE_TYPE ,SIR pulse width select" "3/16 baud-rate,1.6 us"
|
|
bitfld.byte 0x00 06. " SD_MOD ,SD pin" "High,Low"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " DIS_IR_RX ,Disable RXIR input" "Enabled,Disabled"
|
|
bitfld.byte 0x00 04. " DIS_TX_UNDERRUN ,Disable TX underrun" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " SEND_SIP ,Send serial infrared interaction pulse" "Not send,Send"
|
|
bitfld.byte 0x00 02. " SCTX_EN ,Store and controlled TX start" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " ABORT_EN ,Frame abort" "Disabled,Enabled"
|
|
bitfld.byte 0x00 00. " EOT_EN ,EOT (end of transmission)" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x003C++0x00
|
|
hide.byte 0x00 "ACREG,Auxiliary Control Register"
|
|
endif
|
|
group.byte 0x0040++0x00
|
|
line.byte 0x00 "SCR,Supplementary Control Register"
|
|
bitfld.byte 0x00 07. " RX_TRIG_GRANU1 ,Granularity of 1 for trigger RX level" "Disabled,Enabled"
|
|
bitfld.byte 0x00 06. " TX_TRIG_GRANU1 ,Granularity of 1 for trigger TX level" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 05. " DSR_IT ,#DSR interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " RX_CTS_DSR_WAKE_UP_ENABLE ,Wake-up interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 03. " TX_EMPTY_CTL_IT ,Control THR interrupt" "Normal mode,When empty"
|
|
bitfld.byte 0x00 01.--02. " DMA_MODE_2 ,DMA mode" "Mode 0,Mode 1,Mode 2,Mode 3"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " DMA_MODE_CTL ,DMA mode control" "FCR[DMA_MODE],SCR[DMA_MODE_2]"
|
|
rgroup.byte 0x0044++0x00
|
|
line.byte 0x00 "SSR,Supplementary Status Register"
|
|
bitfld.byte 0x00 01. " RX_CTS_DSR_WAKE_UP_STS ,Falling edge occurred on RX/#CTS/#DSR" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " TX_FIFO_FULL ,TX FIFO full" "Not full,Full"
|
|
if (((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x1)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x4)||((data.byte(AD:0xFFFB9800+0x20)&0x07)==0x5))
|
|
group.byte 0x0048++0x00
|
|
line.byte 0x00 "EBLR,BOF Length Register"
|
|
hexmask.byte 0x00 00.--07. 1. " EBLR ,Definition xBOFs"
|
|
else
|
|
group.byte 0x0048++0x00
|
|
hide.byte 0x00 "EBLR,BOF Length Register"
|
|
endif
|
|
rgroup.byte 0x0050++0x00
|
|
line.byte 0x00 "MVR,Module Version Register"
|
|
bitfld.byte 0x00 04.--07. " MAJOR_REV ,Major revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.byte 0x00 00.--03. " MINOR_REV ,Minor revision number of module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.byte 0x0054++0x00
|
|
line.byte 0x00 "SYSC,System Configuration Register"
|
|
bitfld.byte 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "Forced IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.byte 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.byte 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.byte 0x0058++0x00
|
|
line.byte 0x00 "SYSS,System Status Register"
|
|
bitfld.byte 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.byte 0x005C++0x00
|
|
line.byte 0x00 "WER,Wake-Up Enable Register"
|
|
bitfld.byte 0x00 06. " EVENT_6 ,Receiver line status interrupt" "Disabled,Enabled"
|
|
bitfld.byte 0x00 05. " EVENT_5 ,RHR interrupt" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 04. " EVENT_4 ,RX/RXIR activity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 03. " EVENT_3 ,DCD (CD) activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 02. " EVENT_2 ,RI activity" "Disabled,Enabled"
|
|
bitfld.byte 0x00 01. " EVENT_1 ,DSR activity" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 00. " EVENT_0 ,CTS activity" "Disabled,Enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "General-Purpose Timers"
|
|
base AD:0xFFFB1400
|
|
tree "General-Purpose Timer 1 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR1_TIDR,GPTimer1 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR1_TIOCP_CFG,GPTimer1 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR1_TISTAT,GPTimer1 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR1_TISR,GPTimer1 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR1_TIER,GPTimer1 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR1_TWER,GPTimer1 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR1_TCLR,GPTimer1 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR1_TCRR,GPTimer1 Counter Register"
|
|
line.long (0x14) "GPTMR1_TLDR,GPTimer1 Load Register"
|
|
line.long (0x18) "GPTMR1_TTGR,GPTimer1 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR1_TWPS,GPTimer1 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR1_TMAR,GPTimer1 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR1_TSICR,GPTimer1 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB1C00
|
|
tree "General-Purpose Timer 2 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR2_TIDR,GPTimer2 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR2_TIOCP_CFG,GPTimer2 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR2_TISTAT,GPTimer2 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR2_TISR,GPTimer2 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR2_TIER,GPTimer2 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR2_TWER,GPTimer2 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR2_TCLR,GPTimer2 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR2_TCRR,GPTimer2 Counter Register"
|
|
line.long (0x14) "GPTMR2_TLDR,GPTimer2 Load Register"
|
|
line.long (0x18) "GPTMR2_TTGR,GPTimer2 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR2_TWPS,GPTimer2 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR2_TMAR,GPTimer2 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR2_TSICR,GPTimer2 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB2400
|
|
tree "General-Purpose Timer 3 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR3_TIDR,GPTimer3 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR3_TIOCP_CFG,GPTimer3 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR3_TISTAT,GPTimer3 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR3_TISR,GPTimer3 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR3_TIER,GPTimer3 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR3_TWER,GPTimer3 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR3_TCLR,GPTimer3 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR3_TCRR,GPTimer3 Counter Register"
|
|
line.long (0x14) "GPTMR3_TLDR,GPTimer3 Load Register"
|
|
line.long (0x18) "GPTMR3_TTGR,GPTimer3 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR3_TWPS,GPTimer3 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR3_TMAR,GPTimer3 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR3_TSICR,GPTimer3 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB2C00
|
|
tree "General-Purpose Timer 4 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR4_TIDR,GPTimer4 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR4_TIOCP_CFG,GPTimer4 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR4_TISTAT,GPTimer4 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR4_TISR,GPTimer4 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR4_TIER,GPTimer4 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR4_TWER,GPTimer4 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR4_TCLR,GPTimer4 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR4_TCRR,GPTimer4 Counter Register"
|
|
line.long (0x14) "GPTMR4_TLDR,GPTimer4 Load Register"
|
|
line.long (0x18) "GPTMR4_TTGR,GPTimer4 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR4_TWPS,GPTimer4 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR4_TMAR,GPTimer4 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR4_TSICR,GPTimer4 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB3400
|
|
tree "General-Purpose Timer 5 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR5_TIDR,GPTimer5 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR5_TIOCP_CFG,GPTimer5 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR5_TISTAT,GPTimer5 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR5_TISR,GPTimer5 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR5_TIER,GPTimer5 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR5_TWER,GPTimer5 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR5_TCLR,GPTimer5 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR5_TCRR,GPTimer5 Counter Register"
|
|
line.long (0x14) "GPTMR5_TLDR,GPTimer5 Load Register"
|
|
line.long (0x18) "GPTMR5_TTGR,GPTimer5 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR5_TWPS,GPTimer5 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR5_TMAR,GPTimer5 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR5_TSICR,GPTimer5 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB3C00
|
|
tree "General-Purpose Timer 6 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR6_TIDR,GPTimer6 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR6_TIOCP_CFG,GPTimer6 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR6_TISTAT,GPTimer6 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR6_TISR,GPTimer6 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR6_TIER,GPTimer6 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR6_TWER,GPTimer6 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR6_TCLR,GPTimer6 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR6_TCRR,GPTimer6 Counter Register"
|
|
line.long (0x14) "GPTMR6_TLDR,GPTimer6 Load Register"
|
|
line.long (0x18) "GPTMR6_TTGR,GPTimer6 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR6_TWPS,GPTimer6 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR6_TMAR,GPTimer6 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR6_TSICR,GPTimer6 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB7400
|
|
tree "General-Purpose Timer 7 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR7_TIDR,GPTimer7 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR7_TIOCP_CFG,GPTimer7 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR7_TISTAT,GPTimer7 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR7_TISR,GPTimer7 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR7_TIER,GPTimer7 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR7_TWER,GPTimer7 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR7_TCLR,GPTimer7 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR7_TCRR,GPTimer7 Counter Register"
|
|
line.long (0x14) "GPTMR7_TLDR,GPTimer7 Load Register"
|
|
line.long (0x18) "GPTMR7_TTGR,GPTimer7 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR7_TWPS,GPTimer7 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR7_TMAR,GPTimer7 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR7_TSICR,GPTimer7 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFBD400
|
|
tree "General-Purpose Timer 8 Registers"
|
|
width 18.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "GPTMR8_TIDR,GPTimer8 Identification Register"
|
|
hexfld.byte 0x00 " TID_REV ,Module HW revision number of the current timer module"
|
|
group.long (0x10)++0x3
|
|
line.long 0x00 "GPTMR8_TIOCP_CFG,GPTimer8 OCP Configuration Register"
|
|
bitfld.long 0x00 5. " EMUFREE ,The timer is frozen/free in emulation mode" "Frozen,Free"
|
|
bitfld.long 0x00 3.--4. " IDLE_MODE ,Power management, request/acknowledge control" "Force idle,No idle,Smart idle,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SOFTRESET ,Software reset" "Normal,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " AUTOIDLE ,Interface clocks gating strategy" "Free-running,Autogating"
|
|
rgroup.long (0x14)++0x3
|
|
line.long 0x00 "GPTMR8_TISTAT,GPTimer8 System Status Register"
|
|
bitfld.long 0x00 0. " RESETDONE ,Internal global reset monitoring" "Ongoing,Completed"
|
|
group.long (0x18)++(0x18+0x03)
|
|
line.long 0x00 "GPTMR8_TISR,GPTimer8 Status Register"
|
|
bitfld.long 0x00 2. " TCAR_IT_FLAG ,Capture interrupt request" "No,Yes"
|
|
bitfld.long 0x00 1. " OVF_IT_FLAG ,Overflow interrupt request" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MAT_IT_FLAG ,Compare interrupt request" "No,Yes"
|
|
line.long (0x04) "GPTMR8_TIER,GPTimer8 Interrupt Enable Register"
|
|
bitfld.long (0x04) 2. " TCAR_IT_ENA ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x04) 1. " OVF_IT_ENA ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 0. " MAT_IT_ENA ,Compare interrupt enable" "Disabled,Enabled"
|
|
line.long (0x08) "GPTMR8_TWER,GPTimer8 Wake-up Enable Register"
|
|
bitfld.long (0x08) 2. " TCAR_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
bitfld.long (0x08) 1. " OVF_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x08) 0. " MAT_WUP_ENA ,Wake-up generation enable" "Disabled,Enabled"
|
|
line.long (0x0c) "GPTMR8_TCLR,GPTimer8 Control Register"
|
|
bitfld.long (0x0c) 12. " PT ,Pulse or toggle mode on timer PWM output pin" "Pulse,Toggle"
|
|
bitfld.long (0x0c) 10.--11. " TRG ,Trigger output mode on timer PWM output pin" "Disabled,On overflow, On overflow+match,?..."
|
|
textline " "
|
|
bitfld.long (0x0c) 8.--9. " TCM ,Transition capture mode on event capture input pin" "Disabled,Low -> High,High -> Low,Both edge"
|
|
bitfld.long (0x0c) 7. " SCPWM ,Set/Clear PWM" "Clear,Set"
|
|
textline " "
|
|
bitfld.long (0x0c) 6. " CE ,Compare mode enable" "Disabled,Enabled"
|
|
bitfld.long (0x0c) 5. " PRE ,Prescaler enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x0c) 2.--4. " PTV ,Prescale clock timer value" "0,1,2,3,4,5,6,7"
|
|
bitfld.long (0x0c) 1. " AR ,Autoreload enable" "One-shot,Autoreload"
|
|
textline " "
|
|
bitfld.long (0x0c) 0. " ST ,Start/Stop timer" "Stop,Start"
|
|
line.long (0x10) "GPTMR8_TCRR,GPTimer8 Counter Register"
|
|
line.long (0x14) "GPTMR8_TLDR,GPTimer8 Load Register"
|
|
line.long (0x18) "GPTMR8_TTGR,GPTimer8 Trigger Register"
|
|
rgroup.long (0x34)++0x3
|
|
line.long 0x00 "GPTMR8_TWPS,GPTimer8 Write Posted Register"
|
|
bitfld.long 0x00 4. " W_PEND_TMAR ,A write is pending to the TMAR register" "Normal,Pending"
|
|
bitfld.long 0x00 3. " W_PEND_TTGR ,A write is pending to the TTGR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 2. " W_PEND_TLDR ,A write is pending to the TLDR register" "Normal,Pending"
|
|
bitfld.long 0x00 1. " W_PEND_TCRR ,A write is pending to the TCRR register" "Normal,Pending"
|
|
textline " "
|
|
bitfld.long 0x00 0. " W_PEND_TCLR ,A write is pending to the TCLR register" "Normal,Pending"
|
|
group.long (0x38)++0x3
|
|
line.long 0x00 "GPTMR8_TMAR,GPTimer8 Match Register"
|
|
group.long (0x40)++0x3
|
|
line.long 0x00 "GPTMR8_TSICR,GPTimer8 Synchronization Interface Control Register"
|
|
bitfld.long 0x00 2. " POSTED ,Posted mode activate" "Inactive,Active"
|
|
bitfld.long 0x00 1. " SFT ,This bit resets the all of the functional parts of the module" "Disabled,Enabled"
|
|
tree.end
|
|
tree.end
|
|
tree "General-Purpose Input/Output Registers"
|
|
width 0x17
|
|
base AD:0xFFFBE400
|
|
tree "GPIO 1"
|
|
rgroup.long 0x0000++0x03
|
|
line.long 0x00 "GPIO_REVISION,Revision Register"
|
|
bitfld.long 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x0010)++0x03
|
|
line.long 0x00 "GPIO_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.long 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.long (0x0014)++0x03
|
|
line.long 0x00 "GPIO_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long (0x0018)++0x03
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt Status Register 1"
|
|
eventfld.long 0x00 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x001C)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE1,Interrupt Enable Register 1"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0020)++0x03
|
|
line.long (0x00) "GPIO_IRQSTATUS2,Interrupt Status Register 2"
|
|
eventfld.long (0x00) 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x0024)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE2,Interrupt Enable Register 2"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0028)++0x03
|
|
line.long (0x00) "GPIO_WAKEUPENABLE,Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " WAKEUP_EN[16] ,GPIO 16 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " WAKEUP_EN[15] ,GPIO 15 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " WAKEUP_EN[14] ,GPIO 14 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " WAKEUP_EN[13] ,GPIO 13 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " WAKEUP_EN[12] ,GPIO 12 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " WAKEUP_EN[11] ,GPIO 11 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " WAKEUP_EN[10] ,GPIO 10 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " WAKEUP_EN[9] ,GPIO 9 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " WAKEUP_EN[8] ,GPIO 8 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " WAKEUP_EN[7] ,GPIO 7 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " WAKEUP_EN[6] ,GPIO 6 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " WAKEUP_EN[5] ,GPIO 5 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " WAKEUP_EN[4] ,GPIO 4 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " WAKEUP_EN[3] ,GPIO 3 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " WAKEUP_EN[2] ,GPIO 2 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " WAKEUP_EN[1] ,GPIO 1 wake-up enable" "Disabled,Enabled"
|
|
rgroup.long (0x002C)++0x03
|
|
line.long 0x00 "GPIO_DATAIN,Data Input Register"
|
|
bitfld.long 0x00 15. " IN[16] ,GPIO 16 input value" "Low,High"
|
|
bitfld.long 0x00 14. " IN[15] ,GPIO 15 input value" "Low,High"
|
|
bitfld.long 0x00 13. " IN[14] ,GPIO 14 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IN[13] ,GPIO 13 input value" "Low,High"
|
|
bitfld.long 0x00 11. " IN[12] ,GPIO 12 input value" "Low,High"
|
|
bitfld.long 0x00 10. " IN[11] ,GPIO 11 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IN[10] ,GPIO 10 input value" "Low,High"
|
|
bitfld.long 0x00 08. " IN[9] ,GPIO 9 input value" "Low,High"
|
|
bitfld.long 0x00 07. " IN[8] ,GPIO 8 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IN[7] ,GPIO 7 input value" "Low,High"
|
|
bitfld.long 0x00 05. " IN[6] ,GPIO 6 input value" "Low,High"
|
|
bitfld.long 0x00 04. " IN[5] ,GPIO 5 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " IN[4] ,GPIO 4 input value" "Low,High"
|
|
bitfld.long 0x00 02. " IN[3] ,GPIO 3 input value" "Low,High"
|
|
bitfld.long 0x00 01. " IN[2] ,GPIO 2 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " IN[1] ,GPIO 1 input value" "Low,High"
|
|
group.long (0x0030)++0x03
|
|
line.long 0x00 "GPIO_DATAOUT,Data Output Register"
|
|
bitfld.long 0x00 15. " OUT[16] ,GPIO 16 output value" "Low,High"
|
|
bitfld.long 0x00 14. " OUT[15] ,GPIO 15 output value" "Low,High"
|
|
bitfld.long 0x00 13. " OUT[14] ,GPIO 14 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OUT[13] ,GPIO 13 output value" "Low,High"
|
|
bitfld.long 0x00 11. " OUT[12] ,GPIO 12 output value" "Low,High"
|
|
bitfld.long 0x00 10. " OUT[11] ,GPIO 11 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " OUT[10] ,GPIO 10 output value" "Low,High"
|
|
bitfld.long 0x00 08. " OUT[9] ,GPIO 9 output value" "Low,High"
|
|
bitfld.long 0x00 07. " OUT[8] ,GPIO 8 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " OUT[7] ,GPIO 7 output value" "Low,High"
|
|
bitfld.long 0x00 05. " OUT[6] ,GPIO 6 output value" "Low,High"
|
|
bitfld.long 0x00 04. " OUT[5] ,GPIO 5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " OUT[4] ,GPIO 4 output value" "Low,High"
|
|
bitfld.long 0x00 02. " OUT[3] ,GPIO 3 output value" "Low,High"
|
|
bitfld.long 0x00 01. " OUT[2] ,GPIO 2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " OUT[1] ,GPIO 1 output value" "Low,High"
|
|
group.long (0x0034)++0x03
|
|
line.long (0x00) "GPIO_DIRECTION,Direction Control Register"
|
|
bitfld.long (0x00) 15. " DIR[16] ,GPIO 16 direction" "Output,Input"
|
|
bitfld.long (0x00) 14. " DIR[15] ,GPIO 15 direction" "Output,Input"
|
|
bitfld.long (0x00) 13. " DIR[14] ,GPIO 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 12. " DIR[13] ,GPIO 13 direction" "Output,Input"
|
|
bitfld.long (0x00) 11. " DIR[12] ,GPIO 12 direction" "Output,Input"
|
|
bitfld.long (0x00) 10. " DIR[11] ,GPIO 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " DIR[10] ,GPIO 10 direction" "Output,Input"
|
|
bitfld.long (0x00) 08. " DIR[9] ,GPIO 9 direction" "Output,Input"
|
|
bitfld.long (0x00) 07. " DIR[8] ,GPIO 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 06. " DIR[7] ,GPIO 7 direction" "Output,Input"
|
|
bitfld.long (0x00) 05. " DIR[6] ,GPIO 6 direction" "Output,Input"
|
|
bitfld.long (0x00) 04. " DIR[5] ,GPIO 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " DIR[4] ,GPIO 4 direction" "Output,Input"
|
|
bitfld.long (0x00) 02. " DIR[3] ,GPIO 3 direction" "Output,Input"
|
|
bitfld.long (0x00) 01. " DIR[2] ,GPIO 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 00. " DIR[1] ,GPIO 1 direction" "Output,Input"
|
|
group.long (0x0038)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL1,Edge Control Register 1"
|
|
bitfld.long (0x00) 14.--15. " EDGE[8] ,GPIO 8 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[7] ,GPIO 7 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[6] ,GPIO 6 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[5] ,GPIO 5 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[4] ,GPIO 4 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[3] ,GPIO 3 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[2] ,GPIO 2 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[1] ,GPIO 1 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
group.long (0x003C)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL2,Edge Control Register 2"
|
|
bitfld.long (0x00) 14.--15. " EDGE[16] ,GPIO 16 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[15] ,GPIO 15 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[14] ,GPIO 14 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[13] ,GPIO 13 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[12] ,GPIO 12 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[11] ,GPIO 11 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[10] ,GPIO 10 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[9] ,GPIO 9 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
wgroup.long (0x009C)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE1,Clear Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A4)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE2,Clear Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A8)++0x03
|
|
line.long (0x00) "GPIO_CLEAR_WAKEUPENA,Clear Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " CLR_WAKEUP_EN[16] ,Clear wake-up enable 16" "No effect,Cleared"
|
|
bitfld.long (0x00) 14. " CLR_WAKEUP_EN[15] ,Clear wake-up enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " CLR_WAKEUP_EN[14] ,Clear wake-up enable 14" "No effect,Cleared"
|
|
bitfld.long (0x00) 12. " CLR_WAKEUP_EN[13] ,Clear wake-up enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " CLR_WAKEUP_EN[12] ,Clear wake-up enable 12" "No effect,Cleared"
|
|
bitfld.long (0x00) 10. " CLR_WAKEUP_EN[11] ,Clear wake-up enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " CLR_WAKEUP_EN[10] ,Clear wake-up enable 10" "No effect,Cleared"
|
|
bitfld.long (0x00) 08. " CLR_WAKEUP_EN[9] ,Clear wake-up enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " CLR_WAKEUP_EN[8] ,Clear wake-up enable 8" "No effect,Cleared"
|
|
bitfld.long (0x00) 06. " CLR_WAKEUP_EN[7] ,Clear wake-up enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " CLR_WAKEUP_EN[6] ,Clear wake-up enable 6" "No effect,Cleared"
|
|
bitfld.long (0x00) 04. " CLR_WAKEUP_EN[5] ,Clear wake-up enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " CLR_WAKEUP_EN[4] ,Clear wake-up enable 4" "No effect,Cleared"
|
|
bitfld.long (0x00) 02. " CLR_WAKEUP_EN[3] ,Clear wake-up enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " CLR_WAKEUP_EN[2] ,Clear wake-up enable 2" "No effect,Cleared"
|
|
bitfld.long (0x00) 00. " CLR_WAKEUP_EN[1] ,Clear wake-up enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00B0)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_DATAOUT,Clear Data Output Register"
|
|
bitfld.long 0x00 15. " CLR_OUT[15] ,Clear output 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_OUT[14] ,Clear output 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_OUT[13] ,Clear output 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_OUT[12] ,Clear output 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_OUT[11] ,Clear output 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_OUT[10] ,Clear output 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_OUT[9] ,Clear output 9" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_OUT[8] ,Clear output 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_OUT[7] ,Clear output 7" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_OUT[6] ,Clear output 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_OUT[5] ,Clear output 5" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_OUT[4] ,Clear output 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_OUT[3] ,Clear output 3" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_OUT[2] ,Clear output 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_OUT[1] ,Clear output 1" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_OUT[0] ,Clear output 0" "No effect,Cleared"
|
|
wgroup.long (0x00DC)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE1,Set Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E4)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE2,Set Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E8)++0x03
|
|
line.long (0x00) "GPIO_SET_WAKEUPENA,Set Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " SET_WAKEUP_EN[15] ,Set wake-up enable 15" "No effect,Set"
|
|
bitfld.long (0x00) 14. " SET_WAKEUP_EN[14] ,Set wake-up enable 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " SET_WAKEUP_EN[13] ,Set wake-up enable 13" "No effect,Set"
|
|
bitfld.long (0x00) 12. " SET_WAKEUP_EN[12] ,Set wake-up enable 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " SET_WAKEUP_EN[11] ,Set wake-up enable 11" "No effect,Set"
|
|
bitfld.long (0x00) 10. " SET_WAKEUP_EN[10] ,Set wake-up enable 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " SET_WAKEUP_EN[9] ,Set wake-up enable 9" "No effect,Set"
|
|
bitfld.long (0x00) 08. " SET_WAKEUP_EN[8] ,Set wake-up enable 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " SET_WAKEUP_EN[7] ,Set wake-up enable 7" "No effect,Set"
|
|
bitfld.long (0x00) 06. " SET_WAKEUP_EN[6] ,Set wake-up enable 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " SET_WAKEUP_EN[5] ,Set wake-up enable 5" "No effect,Set"
|
|
bitfld.long (0x00) 04. " SET_WAKEUP_EN[4] ,Set wake-up enable 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " SET_WAKEUP_EN[3] ,Set wake-up enable 3" "No effect,Set"
|
|
bitfld.long (0x00) 02. " SET_WAKEUP_EN[2] ,Set wake-up enable 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " SET_WAKEUP_EN[1] ,Set wake-up enable 1" "No effect,Set"
|
|
bitfld.long (0x00) 00. " SET_WAKEUP_EN[0] ,Set wake-up enable 0" "No effect,Set"
|
|
wgroup.long (0x00F0)++0x03
|
|
line.long 0x00 "GPIO_SET_DATAOUT,Set Data Output Register"
|
|
bitfld.long 0x00 15. " SET_OUT[15] ,Set output 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_OUT[14] ,Set output 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_OUT[13] ,Set output 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_OUT[12] ,Set output 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_OUT[11] ,Set output 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_OUT[10] ,Set output 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_OUT[9] ,Set output 9" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_OUT[8] ,Set output 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_OUT[7] ,Set output 7" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_OUT[6] ,Set output 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_OUT[5] ,Set output 5" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_OUT[4] ,Set output 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_OUT[3] ,Set output 3" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_OUT[2] ,Set output 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_OUT[1] ,Set output 1" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_OUT[0] ,Set output 0" "No effect,Set"
|
|
tree.end
|
|
width 0x17
|
|
base AD:0xFFFBEC00
|
|
tree "GPIO 2"
|
|
rgroup.long 0x0000++0x03
|
|
line.long 0x00 "GPIO_REVISION,Revision Register"
|
|
bitfld.long 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x0010)++0x03
|
|
line.long 0x00 "GPIO_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.long 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.long (0x0014)++0x03
|
|
line.long 0x00 "GPIO_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long (0x0018)++0x03
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt Status Register 1"
|
|
eventfld.long 0x00 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x001C)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE1,Interrupt Enable Register 1"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0020)++0x03
|
|
line.long (0x00) "GPIO_IRQSTATUS2,Interrupt Status Register 2"
|
|
eventfld.long (0x00) 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x0024)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE2,Interrupt Enable Register 2"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0028)++0x03
|
|
line.long (0x00) "GPIO_WAKEUPENABLE,Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " WAKEUP_EN[16] ,GPIO 16 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " WAKEUP_EN[15] ,GPIO 15 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " WAKEUP_EN[14] ,GPIO 14 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " WAKEUP_EN[13] ,GPIO 13 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " WAKEUP_EN[12] ,GPIO 12 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " WAKEUP_EN[11] ,GPIO 11 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " WAKEUP_EN[10] ,GPIO 10 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " WAKEUP_EN[9] ,GPIO 9 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " WAKEUP_EN[8] ,GPIO 8 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " WAKEUP_EN[7] ,GPIO 7 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " WAKEUP_EN[6] ,GPIO 6 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " WAKEUP_EN[5] ,GPIO 5 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " WAKEUP_EN[4] ,GPIO 4 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " WAKEUP_EN[3] ,GPIO 3 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " WAKEUP_EN[2] ,GPIO 2 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " WAKEUP_EN[1] ,GPIO 1 wake-up enable" "Disabled,Enabled"
|
|
rgroup.long (0x002C)++0x03
|
|
line.long 0x00 "GPIO_DATAIN,Data Input Register"
|
|
bitfld.long 0x00 15. " IN[16] ,GPIO 16 input value" "Low,High"
|
|
bitfld.long 0x00 14. " IN[15] ,GPIO 15 input value" "Low,High"
|
|
bitfld.long 0x00 13. " IN[14] ,GPIO 14 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IN[13] ,GPIO 13 input value" "Low,High"
|
|
bitfld.long 0x00 11. " IN[12] ,GPIO 12 input value" "Low,High"
|
|
bitfld.long 0x00 10. " IN[11] ,GPIO 11 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IN[10] ,GPIO 10 input value" "Low,High"
|
|
bitfld.long 0x00 08. " IN[9] ,GPIO 9 input value" "Low,High"
|
|
bitfld.long 0x00 07. " IN[8] ,GPIO 8 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IN[7] ,GPIO 7 input value" "Low,High"
|
|
bitfld.long 0x00 05. " IN[6] ,GPIO 6 input value" "Low,High"
|
|
bitfld.long 0x00 04. " IN[5] ,GPIO 5 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " IN[4] ,GPIO 4 input value" "Low,High"
|
|
bitfld.long 0x00 02. " IN[3] ,GPIO 3 input value" "Low,High"
|
|
bitfld.long 0x00 01. " IN[2] ,GPIO 2 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " IN[1] ,GPIO 1 input value" "Low,High"
|
|
group.long (0x0030)++0x03
|
|
line.long 0x00 "GPIO_DATAOUT,Data Output Register"
|
|
bitfld.long 0x00 15. " OUT[16] ,GPIO 16 output value" "Low,High"
|
|
bitfld.long 0x00 14. " OUT[15] ,GPIO 15 output value" "Low,High"
|
|
bitfld.long 0x00 13. " OUT[14] ,GPIO 14 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OUT[13] ,GPIO 13 output value" "Low,High"
|
|
bitfld.long 0x00 11. " OUT[12] ,GPIO 12 output value" "Low,High"
|
|
bitfld.long 0x00 10. " OUT[11] ,GPIO 11 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " OUT[10] ,GPIO 10 output value" "Low,High"
|
|
bitfld.long 0x00 08. " OUT[9] ,GPIO 9 output value" "Low,High"
|
|
bitfld.long 0x00 07. " OUT[8] ,GPIO 8 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " OUT[7] ,GPIO 7 output value" "Low,High"
|
|
bitfld.long 0x00 05. " OUT[6] ,GPIO 6 output value" "Low,High"
|
|
bitfld.long 0x00 04. " OUT[5] ,GPIO 5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " OUT[4] ,GPIO 4 output value" "Low,High"
|
|
bitfld.long 0x00 02. " OUT[3] ,GPIO 3 output value" "Low,High"
|
|
bitfld.long 0x00 01. " OUT[2] ,GPIO 2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " OUT[1] ,GPIO 1 output value" "Low,High"
|
|
group.long (0x0034)++0x03
|
|
line.long (0x00) "GPIO_DIRECTION,Direction Control Register"
|
|
bitfld.long (0x00) 15. " DIR[16] ,GPIO 16 direction" "Output,Input"
|
|
bitfld.long (0x00) 14. " DIR[15] ,GPIO 15 direction" "Output,Input"
|
|
bitfld.long (0x00) 13. " DIR[14] ,GPIO 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 12. " DIR[13] ,GPIO 13 direction" "Output,Input"
|
|
bitfld.long (0x00) 11. " DIR[12] ,GPIO 12 direction" "Output,Input"
|
|
bitfld.long (0x00) 10. " DIR[11] ,GPIO 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " DIR[10] ,GPIO 10 direction" "Output,Input"
|
|
bitfld.long (0x00) 08. " DIR[9] ,GPIO 9 direction" "Output,Input"
|
|
bitfld.long (0x00) 07. " DIR[8] ,GPIO 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 06. " DIR[7] ,GPIO 7 direction" "Output,Input"
|
|
bitfld.long (0x00) 05. " DIR[6] ,GPIO 6 direction" "Output,Input"
|
|
bitfld.long (0x00) 04. " DIR[5] ,GPIO 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " DIR[4] ,GPIO 4 direction" "Output,Input"
|
|
bitfld.long (0x00) 02. " DIR[3] ,GPIO 3 direction" "Output,Input"
|
|
bitfld.long (0x00) 01. " DIR[2] ,GPIO 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 00. " DIR[1] ,GPIO 1 direction" "Output,Input"
|
|
group.long (0x0038)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL1,Edge Control Register 1"
|
|
bitfld.long (0x00) 14.--15. " EDGE[8] ,GPIO 8 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[7] ,GPIO 7 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[6] ,GPIO 6 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[5] ,GPIO 5 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[4] ,GPIO 4 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[3] ,GPIO 3 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[2] ,GPIO 2 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[1] ,GPIO 1 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
group.long (0x003C)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL2,Edge Control Register 2"
|
|
bitfld.long (0x00) 14.--15. " EDGE[16] ,GPIO 16 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[15] ,GPIO 15 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[14] ,GPIO 14 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[13] ,GPIO 13 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[12] ,GPIO 12 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[11] ,GPIO 11 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[10] ,GPIO 10 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[9] ,GPIO 9 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
wgroup.long (0x009C)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE1,Clear Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A4)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE2,Clear Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A8)++0x03
|
|
line.long (0x00) "GPIO_CLEAR_WAKEUPENA,Clear Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " CLR_WAKEUP_EN[16] ,Clear wake-up enable 16" "No effect,Cleared"
|
|
bitfld.long (0x00) 14. " CLR_WAKEUP_EN[15] ,Clear wake-up enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " CLR_WAKEUP_EN[14] ,Clear wake-up enable 14" "No effect,Cleared"
|
|
bitfld.long (0x00) 12. " CLR_WAKEUP_EN[13] ,Clear wake-up enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " CLR_WAKEUP_EN[12] ,Clear wake-up enable 12" "No effect,Cleared"
|
|
bitfld.long (0x00) 10. " CLR_WAKEUP_EN[11] ,Clear wake-up enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " CLR_WAKEUP_EN[10] ,Clear wake-up enable 10" "No effect,Cleared"
|
|
bitfld.long (0x00) 08. " CLR_WAKEUP_EN[9] ,Clear wake-up enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " CLR_WAKEUP_EN[8] ,Clear wake-up enable 8" "No effect,Cleared"
|
|
bitfld.long (0x00) 06. " CLR_WAKEUP_EN[7] ,Clear wake-up enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " CLR_WAKEUP_EN[6] ,Clear wake-up enable 6" "No effect,Cleared"
|
|
bitfld.long (0x00) 04. " CLR_WAKEUP_EN[5] ,Clear wake-up enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " CLR_WAKEUP_EN[4] ,Clear wake-up enable 4" "No effect,Cleared"
|
|
bitfld.long (0x00) 02. " CLR_WAKEUP_EN[3] ,Clear wake-up enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " CLR_WAKEUP_EN[2] ,Clear wake-up enable 2" "No effect,Cleared"
|
|
bitfld.long (0x00) 00. " CLR_WAKEUP_EN[1] ,Clear wake-up enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00B0)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_DATAOUT,Clear Data Output Register"
|
|
bitfld.long 0x00 15. " CLR_OUT[15] ,Clear output 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_OUT[14] ,Clear output 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_OUT[13] ,Clear output 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_OUT[12] ,Clear output 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_OUT[11] ,Clear output 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_OUT[10] ,Clear output 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_OUT[9] ,Clear output 9" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_OUT[8] ,Clear output 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_OUT[7] ,Clear output 7" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_OUT[6] ,Clear output 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_OUT[5] ,Clear output 5" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_OUT[4] ,Clear output 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_OUT[3] ,Clear output 3" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_OUT[2] ,Clear output 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_OUT[1] ,Clear output 1" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_OUT[0] ,Clear output 0" "No effect,Cleared"
|
|
wgroup.long (0x00DC)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE1,Set Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E4)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE2,Set Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E8)++0x03
|
|
line.long (0x00) "GPIO_SET_WAKEUPENA,Set Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " SET_WAKEUP_EN[15] ,Set wake-up enable 15" "No effect,Set"
|
|
bitfld.long (0x00) 14. " SET_WAKEUP_EN[14] ,Set wake-up enable 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " SET_WAKEUP_EN[13] ,Set wake-up enable 13" "No effect,Set"
|
|
bitfld.long (0x00) 12. " SET_WAKEUP_EN[12] ,Set wake-up enable 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " SET_WAKEUP_EN[11] ,Set wake-up enable 11" "No effect,Set"
|
|
bitfld.long (0x00) 10. " SET_WAKEUP_EN[10] ,Set wake-up enable 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " SET_WAKEUP_EN[9] ,Set wake-up enable 9" "No effect,Set"
|
|
bitfld.long (0x00) 08. " SET_WAKEUP_EN[8] ,Set wake-up enable 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " SET_WAKEUP_EN[7] ,Set wake-up enable 7" "No effect,Set"
|
|
bitfld.long (0x00) 06. " SET_WAKEUP_EN[6] ,Set wake-up enable 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " SET_WAKEUP_EN[5] ,Set wake-up enable 5" "No effect,Set"
|
|
bitfld.long (0x00) 04. " SET_WAKEUP_EN[4] ,Set wake-up enable 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " SET_WAKEUP_EN[3] ,Set wake-up enable 3" "No effect,Set"
|
|
bitfld.long (0x00) 02. " SET_WAKEUP_EN[2] ,Set wake-up enable 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " SET_WAKEUP_EN[1] ,Set wake-up enable 1" "No effect,Set"
|
|
bitfld.long (0x00) 00. " SET_WAKEUP_EN[0] ,Set wake-up enable 0" "No effect,Set"
|
|
wgroup.long (0x00F0)++0x03
|
|
line.long 0x00 "GPIO_SET_DATAOUT,Set Data Output Register"
|
|
bitfld.long 0x00 15. " SET_OUT[15] ,Set output 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_OUT[14] ,Set output 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_OUT[13] ,Set output 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_OUT[12] ,Set output 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_OUT[11] ,Set output 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_OUT[10] ,Set output 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_OUT[9] ,Set output 9" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_OUT[8] ,Set output 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_OUT[7] ,Set output 7" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_OUT[6] ,Set output 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_OUT[5] ,Set output 5" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_OUT[4] ,Set output 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_OUT[3] ,Set output 3" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_OUT[2] ,Set output 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_OUT[1] ,Set output 1" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_OUT[0] ,Set output 0" "No effect,Set"
|
|
tree.end
|
|
width 0x17
|
|
base AD:0xFFFBB400
|
|
tree "GPIO 3"
|
|
rgroup.long 0x0000++0x03
|
|
line.long 0x00 "GPIO_REVISION,Revision Register"
|
|
bitfld.long 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x0010)++0x03
|
|
line.long 0x00 "GPIO_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.long 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.long (0x0014)++0x03
|
|
line.long 0x00 "GPIO_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long (0x0018)++0x03
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt Status Register 1"
|
|
eventfld.long 0x00 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x001C)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE1,Interrupt Enable Register 1"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0020)++0x03
|
|
line.long (0x00) "GPIO_IRQSTATUS2,Interrupt Status Register 2"
|
|
eventfld.long (0x00) 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x0024)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE2,Interrupt Enable Register 2"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0028)++0x03
|
|
line.long (0x00) "GPIO_WAKEUPENABLE,Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " WAKEUP_EN[16] ,GPIO 16 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " WAKEUP_EN[15] ,GPIO 15 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " WAKEUP_EN[14] ,GPIO 14 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " WAKEUP_EN[13] ,GPIO 13 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " WAKEUP_EN[12] ,GPIO 12 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " WAKEUP_EN[11] ,GPIO 11 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " WAKEUP_EN[10] ,GPIO 10 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " WAKEUP_EN[9] ,GPIO 9 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " WAKEUP_EN[8] ,GPIO 8 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " WAKEUP_EN[7] ,GPIO 7 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " WAKEUP_EN[6] ,GPIO 6 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " WAKEUP_EN[5] ,GPIO 5 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " WAKEUP_EN[4] ,GPIO 4 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " WAKEUP_EN[3] ,GPIO 3 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " WAKEUP_EN[2] ,GPIO 2 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " WAKEUP_EN[1] ,GPIO 1 wake-up enable" "Disabled,Enabled"
|
|
rgroup.long (0x002C)++0x03
|
|
line.long 0x00 "GPIO_DATAIN,Data Input Register"
|
|
bitfld.long 0x00 15. " IN[16] ,GPIO 16 input value" "Low,High"
|
|
bitfld.long 0x00 14. " IN[15] ,GPIO 15 input value" "Low,High"
|
|
bitfld.long 0x00 13. " IN[14] ,GPIO 14 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IN[13] ,GPIO 13 input value" "Low,High"
|
|
bitfld.long 0x00 11. " IN[12] ,GPIO 12 input value" "Low,High"
|
|
bitfld.long 0x00 10. " IN[11] ,GPIO 11 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IN[10] ,GPIO 10 input value" "Low,High"
|
|
bitfld.long 0x00 08. " IN[9] ,GPIO 9 input value" "Low,High"
|
|
bitfld.long 0x00 07. " IN[8] ,GPIO 8 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IN[7] ,GPIO 7 input value" "Low,High"
|
|
bitfld.long 0x00 05. " IN[6] ,GPIO 6 input value" "Low,High"
|
|
bitfld.long 0x00 04. " IN[5] ,GPIO 5 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " IN[4] ,GPIO 4 input value" "Low,High"
|
|
bitfld.long 0x00 02. " IN[3] ,GPIO 3 input value" "Low,High"
|
|
bitfld.long 0x00 01. " IN[2] ,GPIO 2 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " IN[1] ,GPIO 1 input value" "Low,High"
|
|
group.long (0x0030)++0x03
|
|
line.long 0x00 "GPIO_DATAOUT,Data Output Register"
|
|
bitfld.long 0x00 15. " OUT[16] ,GPIO 16 output value" "Low,High"
|
|
bitfld.long 0x00 14. " OUT[15] ,GPIO 15 output value" "Low,High"
|
|
bitfld.long 0x00 13. " OUT[14] ,GPIO 14 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OUT[13] ,GPIO 13 output value" "Low,High"
|
|
bitfld.long 0x00 11. " OUT[12] ,GPIO 12 output value" "Low,High"
|
|
bitfld.long 0x00 10. " OUT[11] ,GPIO 11 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " OUT[10] ,GPIO 10 output value" "Low,High"
|
|
bitfld.long 0x00 08. " OUT[9] ,GPIO 9 output value" "Low,High"
|
|
bitfld.long 0x00 07. " OUT[8] ,GPIO 8 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " OUT[7] ,GPIO 7 output value" "Low,High"
|
|
bitfld.long 0x00 05. " OUT[6] ,GPIO 6 output value" "Low,High"
|
|
bitfld.long 0x00 04. " OUT[5] ,GPIO 5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " OUT[4] ,GPIO 4 output value" "Low,High"
|
|
bitfld.long 0x00 02. " OUT[3] ,GPIO 3 output value" "Low,High"
|
|
bitfld.long 0x00 01. " OUT[2] ,GPIO 2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " OUT[1] ,GPIO 1 output value" "Low,High"
|
|
group.long (0x0034)++0x03
|
|
line.long (0x00) "GPIO_DIRECTION,Direction Control Register"
|
|
bitfld.long (0x00) 15. " DIR[16] ,GPIO 16 direction" "Output,Input"
|
|
bitfld.long (0x00) 14. " DIR[15] ,GPIO 15 direction" "Output,Input"
|
|
bitfld.long (0x00) 13. " DIR[14] ,GPIO 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 12. " DIR[13] ,GPIO 13 direction" "Output,Input"
|
|
bitfld.long (0x00) 11. " DIR[12] ,GPIO 12 direction" "Output,Input"
|
|
bitfld.long (0x00) 10. " DIR[11] ,GPIO 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " DIR[10] ,GPIO 10 direction" "Output,Input"
|
|
bitfld.long (0x00) 08. " DIR[9] ,GPIO 9 direction" "Output,Input"
|
|
bitfld.long (0x00) 07. " DIR[8] ,GPIO 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 06. " DIR[7] ,GPIO 7 direction" "Output,Input"
|
|
bitfld.long (0x00) 05. " DIR[6] ,GPIO 6 direction" "Output,Input"
|
|
bitfld.long (0x00) 04. " DIR[5] ,GPIO 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " DIR[4] ,GPIO 4 direction" "Output,Input"
|
|
bitfld.long (0x00) 02. " DIR[3] ,GPIO 3 direction" "Output,Input"
|
|
bitfld.long (0x00) 01. " DIR[2] ,GPIO 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 00. " DIR[1] ,GPIO 1 direction" "Output,Input"
|
|
group.long (0x0038)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL1,Edge Control Register 1"
|
|
bitfld.long (0x00) 14.--15. " EDGE[8] ,GPIO 8 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[7] ,GPIO 7 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[6] ,GPIO 6 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[5] ,GPIO 5 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[4] ,GPIO 4 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[3] ,GPIO 3 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[2] ,GPIO 2 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[1] ,GPIO 1 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
group.long (0x003C)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL2,Edge Control Register 2"
|
|
bitfld.long (0x00) 14.--15. " EDGE[16] ,GPIO 16 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[15] ,GPIO 15 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[14] ,GPIO 14 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[13] ,GPIO 13 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[12] ,GPIO 12 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[11] ,GPIO 11 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[10] ,GPIO 10 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[9] ,GPIO 9 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
wgroup.long (0x009C)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE1,Clear Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A4)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE2,Clear Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A8)++0x03
|
|
line.long (0x00) "GPIO_CLEAR_WAKEUPENA,Clear Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " CLR_WAKEUP_EN[16] ,Clear wake-up enable 16" "No effect,Cleared"
|
|
bitfld.long (0x00) 14. " CLR_WAKEUP_EN[15] ,Clear wake-up enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " CLR_WAKEUP_EN[14] ,Clear wake-up enable 14" "No effect,Cleared"
|
|
bitfld.long (0x00) 12. " CLR_WAKEUP_EN[13] ,Clear wake-up enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " CLR_WAKEUP_EN[12] ,Clear wake-up enable 12" "No effect,Cleared"
|
|
bitfld.long (0x00) 10. " CLR_WAKEUP_EN[11] ,Clear wake-up enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " CLR_WAKEUP_EN[10] ,Clear wake-up enable 10" "No effect,Cleared"
|
|
bitfld.long (0x00) 08. " CLR_WAKEUP_EN[9] ,Clear wake-up enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " CLR_WAKEUP_EN[8] ,Clear wake-up enable 8" "No effect,Cleared"
|
|
bitfld.long (0x00) 06. " CLR_WAKEUP_EN[7] ,Clear wake-up enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " CLR_WAKEUP_EN[6] ,Clear wake-up enable 6" "No effect,Cleared"
|
|
bitfld.long (0x00) 04. " CLR_WAKEUP_EN[5] ,Clear wake-up enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " CLR_WAKEUP_EN[4] ,Clear wake-up enable 4" "No effect,Cleared"
|
|
bitfld.long (0x00) 02. " CLR_WAKEUP_EN[3] ,Clear wake-up enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " CLR_WAKEUP_EN[2] ,Clear wake-up enable 2" "No effect,Cleared"
|
|
bitfld.long (0x00) 00. " CLR_WAKEUP_EN[1] ,Clear wake-up enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00B0)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_DATAOUT,Clear Data Output Register"
|
|
bitfld.long 0x00 15. " CLR_OUT[15] ,Clear output 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_OUT[14] ,Clear output 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_OUT[13] ,Clear output 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_OUT[12] ,Clear output 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_OUT[11] ,Clear output 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_OUT[10] ,Clear output 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_OUT[9] ,Clear output 9" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_OUT[8] ,Clear output 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_OUT[7] ,Clear output 7" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_OUT[6] ,Clear output 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_OUT[5] ,Clear output 5" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_OUT[4] ,Clear output 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_OUT[3] ,Clear output 3" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_OUT[2] ,Clear output 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_OUT[1] ,Clear output 1" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_OUT[0] ,Clear output 0" "No effect,Cleared"
|
|
wgroup.long (0x00DC)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE1,Set Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E4)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE2,Set Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E8)++0x03
|
|
line.long (0x00) "GPIO_SET_WAKEUPENA,Set Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " SET_WAKEUP_EN[15] ,Set wake-up enable 15" "No effect,Set"
|
|
bitfld.long (0x00) 14. " SET_WAKEUP_EN[14] ,Set wake-up enable 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " SET_WAKEUP_EN[13] ,Set wake-up enable 13" "No effect,Set"
|
|
bitfld.long (0x00) 12. " SET_WAKEUP_EN[12] ,Set wake-up enable 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " SET_WAKEUP_EN[11] ,Set wake-up enable 11" "No effect,Set"
|
|
bitfld.long (0x00) 10. " SET_WAKEUP_EN[10] ,Set wake-up enable 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " SET_WAKEUP_EN[9] ,Set wake-up enable 9" "No effect,Set"
|
|
bitfld.long (0x00) 08. " SET_WAKEUP_EN[8] ,Set wake-up enable 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " SET_WAKEUP_EN[7] ,Set wake-up enable 7" "No effect,Set"
|
|
bitfld.long (0x00) 06. " SET_WAKEUP_EN[6] ,Set wake-up enable 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " SET_WAKEUP_EN[5] ,Set wake-up enable 5" "No effect,Set"
|
|
bitfld.long (0x00) 04. " SET_WAKEUP_EN[4] ,Set wake-up enable 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " SET_WAKEUP_EN[3] ,Set wake-up enable 3" "No effect,Set"
|
|
bitfld.long (0x00) 02. " SET_WAKEUP_EN[2] ,Set wake-up enable 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " SET_WAKEUP_EN[1] ,Set wake-up enable 1" "No effect,Set"
|
|
bitfld.long (0x00) 00. " SET_WAKEUP_EN[0] ,Set wake-up enable 0" "No effect,Set"
|
|
wgroup.long (0x00F0)++0x03
|
|
line.long 0x00 "GPIO_SET_DATAOUT,Set Data Output Register"
|
|
bitfld.long 0x00 15. " SET_OUT[15] ,Set output 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_OUT[14] ,Set output 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_OUT[13] ,Set output 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_OUT[12] ,Set output 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_OUT[11] ,Set output 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_OUT[10] ,Set output 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_OUT[9] ,Set output 9" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_OUT[8] ,Set output 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_OUT[7] ,Set output 7" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_OUT[6] ,Set output 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_OUT[5] ,Set output 5" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_OUT[4] ,Set output 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_OUT[3] ,Set output 3" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_OUT[2] ,Set output 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_OUT[1] ,Set output 1" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_OUT[0] ,Set output 0" "No effect,Set"
|
|
tree.end
|
|
width 0x17
|
|
base AD:0xFFFBBC00
|
|
tree "GPIO 4"
|
|
rgroup.long 0x0000++0x03
|
|
line.long 0x00 "GPIO_REVISION,Revision Register"
|
|
bitfld.long 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x0010)++0x03
|
|
line.long 0x00 "GPIO_SYSCONFIG,System Configuration Register"
|
|
bitfld.long 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.long 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.long (0x0014)++0x03
|
|
line.long 0x00 "GPIO_SYSSTATUS,System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long (0x0018)++0x03
|
|
line.long 0x00 "GPIO_IRQSTATUS1,Interrupt Status Register 1"
|
|
eventfld.long 0x00 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long 0x00 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x00 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x001C)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE1,Interrupt Enable Register 1"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0020)++0x03
|
|
line.long (0x00) "GPIO_IRQSTATUS2,Interrupt Status Register 2"
|
|
eventfld.long (0x00) 15. " INT[16] ,GPIO 16 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 14. " INT[15] ,GPIO 15 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 13. " INT[14] ,GPIO 14 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 12. " INT[13] ,GPIO 13 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 11. " INT[12] ,GPIO 12 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 10. " INT[11] ,GPIO 11 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 09. " INT[10] ,GPIO 10 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 08. " INT[9] ,GPIO 9 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 07. " INT[8] ,GPIO 8 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 06. " INT[7] ,GPIO 7 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 05. " INT[6] ,GPIO 6 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 04. " INT[5] ,GPIO 5 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 03. " INT[4] ,GPIO 4 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 02. " INT[3] ,GPIO 3 interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.long (0x00) 01. " INT[2] ,GPIO 2 interrupt" "No interrupt,Interrupt"
|
|
eventfld.long (0x00) 00. " INT[1] ,GPIO 1 interrupt" "No interrupt,Interrupt"
|
|
group.long (0x0024)++0x03
|
|
line.long (0x00) "GPIO_IRQENABLE2,Interrupt Enable Register 2"
|
|
bitfld.long (0x00) 15. " INT_EN[16] ,GPIO 16 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " INT_EN[15] ,GPIO 15 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " INT_EN[14] ,GPIO 14 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " INT_EN[13] ,GPIO 13 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " INT_EN[12] ,GPIO 12 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " INT_EN[11] ,GPIO 11 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " INT_EN[10] ,GPIO 10 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " INT_EN[9] ,GPIO 9 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " INT_EN[8] ,GPIO 8 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " INT_EN[7] ,GPIO 7 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " INT_EN[6] ,GPIO 6 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " INT_EN[5] ,GPIO 5 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " INT_EN[4] ,GPIO 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " INT_EN[3] ,GPIO 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " INT_EN[2] ,GPIO 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " INT_EN[1] ,GPIO 1 interrupt enable" "Disabled,Enabled"
|
|
group.long (0x0028)++0x03
|
|
line.long (0x00) "GPIO_WAKEUPENABLE,Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " WAKEUP_EN[16] ,GPIO 16 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 14. " WAKEUP_EN[15] ,GPIO 15 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " WAKEUP_EN[14] ,GPIO 14 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 12. " WAKEUP_EN[13] ,GPIO 13 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " WAKEUP_EN[12] ,GPIO 12 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 10. " WAKEUP_EN[11] ,GPIO 11 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " WAKEUP_EN[10] ,GPIO 10 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 08. " WAKEUP_EN[9] ,GPIO 9 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " WAKEUP_EN[8] ,GPIO 8 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 06. " WAKEUP_EN[7] ,GPIO 7 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " WAKEUP_EN[6] ,GPIO 6 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 04. " WAKEUP_EN[5] ,GPIO 5 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " WAKEUP_EN[4] ,GPIO 4 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 02. " WAKEUP_EN[3] ,GPIO 3 wake-up enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " WAKEUP_EN[2] ,GPIO 2 wake-up enable" "Disabled,Enabled"
|
|
bitfld.long (0x00) 00. " WAKEUP_EN[1] ,GPIO 1 wake-up enable" "Disabled,Enabled"
|
|
rgroup.long (0x002C)++0x03
|
|
line.long 0x00 "GPIO_DATAIN,Data Input Register"
|
|
bitfld.long 0x00 15. " IN[16] ,GPIO 16 input value" "Low,High"
|
|
bitfld.long 0x00 14. " IN[15] ,GPIO 15 input value" "Low,High"
|
|
bitfld.long 0x00 13. " IN[14] ,GPIO 14 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IN[13] ,GPIO 13 input value" "Low,High"
|
|
bitfld.long 0x00 11. " IN[12] ,GPIO 12 input value" "Low,High"
|
|
bitfld.long 0x00 10. " IN[11] ,GPIO 11 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " IN[10] ,GPIO 10 input value" "Low,High"
|
|
bitfld.long 0x00 08. " IN[9] ,GPIO 9 input value" "Low,High"
|
|
bitfld.long 0x00 07. " IN[8] ,GPIO 8 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " IN[7] ,GPIO 7 input value" "Low,High"
|
|
bitfld.long 0x00 05. " IN[6] ,GPIO 6 input value" "Low,High"
|
|
bitfld.long 0x00 04. " IN[5] ,GPIO 5 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " IN[4] ,GPIO 4 input value" "Low,High"
|
|
bitfld.long 0x00 02. " IN[3] ,GPIO 3 input value" "Low,High"
|
|
bitfld.long 0x00 01. " IN[2] ,GPIO 2 input value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " IN[1] ,GPIO 1 input value" "Low,High"
|
|
group.long (0x0030)++0x03
|
|
line.long 0x00 "GPIO_DATAOUT,Data Output Register"
|
|
bitfld.long 0x00 15. " OUT[16] ,GPIO 16 output value" "Low,High"
|
|
bitfld.long 0x00 14. " OUT[15] ,GPIO 15 output value" "Low,High"
|
|
bitfld.long 0x00 13. " OUT[14] ,GPIO 14 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OUT[13] ,GPIO 13 output value" "Low,High"
|
|
bitfld.long 0x00 11. " OUT[12] ,GPIO 12 output value" "Low,High"
|
|
bitfld.long 0x00 10. " OUT[11] ,GPIO 11 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 09. " OUT[10] ,GPIO 10 output value" "Low,High"
|
|
bitfld.long 0x00 08. " OUT[9] ,GPIO 9 output value" "Low,High"
|
|
bitfld.long 0x00 07. " OUT[8] ,GPIO 8 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " OUT[7] ,GPIO 7 output value" "Low,High"
|
|
bitfld.long 0x00 05. " OUT[6] ,GPIO 6 output value" "Low,High"
|
|
bitfld.long 0x00 04. " OUT[5] ,GPIO 5 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 03. " OUT[4] ,GPIO 4 output value" "Low,High"
|
|
bitfld.long 0x00 02. " OUT[3] ,GPIO 3 output value" "Low,High"
|
|
bitfld.long 0x00 01. " OUT[2] ,GPIO 2 output value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 00. " OUT[1] ,GPIO 1 output value" "Low,High"
|
|
group.long (0x0034)++0x03
|
|
line.long (0x00) "GPIO_DIRECTION,Direction Control Register"
|
|
bitfld.long (0x00) 15. " DIR[16] ,GPIO 16 direction" "Output,Input"
|
|
bitfld.long (0x00) 14. " DIR[15] ,GPIO 15 direction" "Output,Input"
|
|
bitfld.long (0x00) 13. " DIR[14] ,GPIO 14 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 12. " DIR[13] ,GPIO 13 direction" "Output,Input"
|
|
bitfld.long (0x00) 11. " DIR[12] ,GPIO 12 direction" "Output,Input"
|
|
bitfld.long (0x00) 10. " DIR[11] ,GPIO 11 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " DIR[10] ,GPIO 10 direction" "Output,Input"
|
|
bitfld.long (0x00) 08. " DIR[9] ,GPIO 9 direction" "Output,Input"
|
|
bitfld.long (0x00) 07. " DIR[8] ,GPIO 8 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 06. " DIR[7] ,GPIO 7 direction" "Output,Input"
|
|
bitfld.long (0x00) 05. " DIR[6] ,GPIO 6 direction" "Output,Input"
|
|
bitfld.long (0x00) 04. " DIR[5] ,GPIO 5 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " DIR[4] ,GPIO 4 direction" "Output,Input"
|
|
bitfld.long (0x00) 02. " DIR[3] ,GPIO 3 direction" "Output,Input"
|
|
bitfld.long (0x00) 01. " DIR[2] ,GPIO 2 direction" "Output,Input"
|
|
textline " "
|
|
bitfld.long (0x00) 00. " DIR[1] ,GPIO 1 direction" "Output,Input"
|
|
group.long (0x0038)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL1,Edge Control Register 1"
|
|
bitfld.long (0x00) 14.--15. " EDGE[8] ,GPIO 8 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[7] ,GPIO 7 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[6] ,GPIO 6 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[5] ,GPIO 5 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[4] ,GPIO 4 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[3] ,GPIO 3 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[2] ,GPIO 2 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[1] ,GPIO 1 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
group.long (0x003C)++0x03
|
|
line.long (0x00) "GPIO_EDGE_CTRL2,Edge Control Register 2"
|
|
bitfld.long (0x00) 14.--15. " EDGE[16] ,GPIO 16 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 12.--13. " EDGE[15] ,GPIO 15 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 10.--11. " EDGE[14] ,GPIO 14 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 08.--09. " EDGE[13] ,GPIO 13 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 06.--07. " EDGE[12] ,GPIO 12 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 04.--05. " EDGE[11] ,GPIO 11 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
textline " "
|
|
bitfld.long (0x00) 02.--03. " EDGE[10] ,GPIO 10 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
bitfld.long (0x00) 00.--01. " EDGE[9] ,GPIO 9 edge control" "No edge,Falling edge,Rising edge,Both edges"
|
|
wgroup.long (0x009C)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE1,Clear Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A4)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_IRQENABLE2,Clear Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " CLR_IRQ_EN[16] ,Clear interrupt enable 16" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_IRQ_EN[15] ,Clear interrupt enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_IRQ_EN[14] ,Clear interrupt enable 14" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_IRQ_EN[13] ,Clear interrupt enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_IRQ_EN[12] ,Clear interrupt enable 12" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_IRQ_EN[11] ,Clear interrupt enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_IRQ_EN[10] ,Clear interrupt enable 10" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_IRQ_EN[9] ,Clear interrupt enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_IRQ_EN[8] ,Clear interrupt enable 8" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_IRQ_EN[7] ,Clear interrupt enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_IRQ_EN[6] ,Clear interrupt enable 6" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_IRQ_EN[5] ,Clear interrupt enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_IRQ_EN[4] ,Clear interrupt enable 4" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_IRQ_EN[3] ,Clear interrupt enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_IRQ_EN[2] ,Clear interrupt enable 2" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_IRQ_EN[1] ,Clear interrupt enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00A8)++0x03
|
|
line.long (0x00) "GPIO_CLEAR_WAKEUPENA,Clear Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " CLR_WAKEUP_EN[16] ,Clear wake-up enable 16" "No effect,Cleared"
|
|
bitfld.long (0x00) 14. " CLR_WAKEUP_EN[15] ,Clear wake-up enable 15" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " CLR_WAKEUP_EN[14] ,Clear wake-up enable 14" "No effect,Cleared"
|
|
bitfld.long (0x00) 12. " CLR_WAKEUP_EN[13] ,Clear wake-up enable 13" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " CLR_WAKEUP_EN[12] ,Clear wake-up enable 12" "No effect,Cleared"
|
|
bitfld.long (0x00) 10. " CLR_WAKEUP_EN[11] ,Clear wake-up enable 11" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " CLR_WAKEUP_EN[10] ,Clear wake-up enable 10" "No effect,Cleared"
|
|
bitfld.long (0x00) 08. " CLR_WAKEUP_EN[9] ,Clear wake-up enable 9" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " CLR_WAKEUP_EN[8] ,Clear wake-up enable 8" "No effect,Cleared"
|
|
bitfld.long (0x00) 06. " CLR_WAKEUP_EN[7] ,Clear wake-up enable 7" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " CLR_WAKEUP_EN[6] ,Clear wake-up enable 6" "No effect,Cleared"
|
|
bitfld.long (0x00) 04. " CLR_WAKEUP_EN[5] ,Clear wake-up enable 5" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " CLR_WAKEUP_EN[4] ,Clear wake-up enable 4" "No effect,Cleared"
|
|
bitfld.long (0x00) 02. " CLR_WAKEUP_EN[3] ,Clear wake-up enable 3" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " CLR_WAKEUP_EN[2] ,Clear wake-up enable 2" "No effect,Cleared"
|
|
bitfld.long (0x00) 00. " CLR_WAKEUP_EN[1] ,Clear wake-up enable 1" "No effect,Cleared"
|
|
wgroup.long (0x00B0)++0x03
|
|
line.long 0x00 "GPIO_CLEAR_DATAOUT,Clear Data Output Register"
|
|
bitfld.long 0x00 15. " CLR_OUT[15] ,Clear output 15" "No effect,Cleared"
|
|
bitfld.long 0x00 14. " CLR_OUT[14] ,Clear output 14" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CLR_OUT[13] ,Clear output 13" "No effect,Cleared"
|
|
bitfld.long 0x00 12. " CLR_OUT[12] ,Clear output 12" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLR_OUT[11] ,Clear output 11" "No effect,Cleared"
|
|
bitfld.long 0x00 10. " CLR_OUT[10] ,Clear output 10" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 09. " CLR_OUT[9] ,Clear output 9" "No effect,Cleared"
|
|
bitfld.long 0x00 08. " CLR_OUT[8] ,Clear output 8" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 07. " CLR_OUT[7] ,Clear output 7" "No effect,Cleared"
|
|
bitfld.long 0x00 06. " CLR_OUT[6] ,Clear output 6" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 05. " CLR_OUT[5] ,Clear output 5" "No effect,Cleared"
|
|
bitfld.long 0x00 04. " CLR_OUT[4] ,Clear output 4" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 03. " CLR_OUT[3] ,Clear output 3" "No effect,Cleared"
|
|
bitfld.long 0x00 02. " CLR_OUT[2] ,Clear output 2" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 01. " CLR_OUT[1] ,Clear output 1" "No effect,Cleared"
|
|
bitfld.long 0x00 00. " CLR_OUT[0] ,Clear output 0" "No effect,Cleared"
|
|
wgroup.long (0x00DC)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE1,Set Interrupt Enable Register 1"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E4)++0x03
|
|
line.long 0x00 "GPIO_SET_IRQENABLE2,Set Interrupt Enable Register 2"
|
|
bitfld.long 0x00 15. " SET_IRQ_EN[16] ,Set interrupt enable 16" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_IRQ_EN[15] ,Set interrupt enable 15" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_IRQ_EN[14] ,Set interrupt enable 14" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_IRQ_EN[13] ,Set interrupt enable 13" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_IRQ_EN[12] ,Set interrupt enable 12" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_IRQ_EN[11] ,Set interrupt enable 11" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_IRQ_EN[10] ,Set interrupt enable 10" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_IRQ_EN[9] ,Set interrupt enable 9" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_IRQ_EN[8] ,Set interrupt enable 8" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_IRQ_EN[7] ,Set interrupt enable 7" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_IRQ_EN[6] ,Set interrupt enable 6" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_IRQ_EN[5] ,Set interrupt enable 5" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_IRQ_EN[4] ,Set interrupt enable 4" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_IRQ_EN[3] ,Set interrupt enable 3" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_IRQ_EN[2] ,Set interrupt enable 2" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_IRQ_EN[1] ,Set interrupt enable 1" "No effect,Set"
|
|
wgroup.long (0x00E8)++0x03
|
|
line.long (0x00) "GPIO_SET_WAKEUPENA,Set Wake-up Enable Register"
|
|
bitfld.long (0x00) 15. " SET_WAKEUP_EN[15] ,Set wake-up enable 15" "No effect,Set"
|
|
bitfld.long (0x00) 14. " SET_WAKEUP_EN[14] ,Set wake-up enable 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 13. " SET_WAKEUP_EN[13] ,Set wake-up enable 13" "No effect,Set"
|
|
bitfld.long (0x00) 12. " SET_WAKEUP_EN[12] ,Set wake-up enable 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 11. " SET_WAKEUP_EN[11] ,Set wake-up enable 11" "No effect,Set"
|
|
bitfld.long (0x00) 10. " SET_WAKEUP_EN[10] ,Set wake-up enable 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 09. " SET_WAKEUP_EN[9] ,Set wake-up enable 9" "No effect,Set"
|
|
bitfld.long (0x00) 08. " SET_WAKEUP_EN[8] ,Set wake-up enable 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 07. " SET_WAKEUP_EN[7] ,Set wake-up enable 7" "No effect,Set"
|
|
bitfld.long (0x00) 06. " SET_WAKEUP_EN[6] ,Set wake-up enable 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 05. " SET_WAKEUP_EN[5] ,Set wake-up enable 5" "No effect,Set"
|
|
bitfld.long (0x00) 04. " SET_WAKEUP_EN[4] ,Set wake-up enable 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 03. " SET_WAKEUP_EN[3] ,Set wake-up enable 3" "No effect,Set"
|
|
bitfld.long (0x00) 02. " SET_WAKEUP_EN[2] ,Set wake-up enable 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long (0x00) 01. " SET_WAKEUP_EN[1] ,Set wake-up enable 1" "No effect,Set"
|
|
bitfld.long (0x00) 00. " SET_WAKEUP_EN[0] ,Set wake-up enable 0" "No effect,Set"
|
|
wgroup.long (0x00F0)++0x03
|
|
line.long 0x00 "GPIO_SET_DATAOUT,Set Data Output Register"
|
|
bitfld.long 0x00 15. " SET_OUT[15] ,Set output 15" "No effect,Set"
|
|
bitfld.long 0x00 14. " SET_OUT[14] ,Set output 14" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 13. " SET_OUT[13] ,Set output 13" "No effect,Set"
|
|
bitfld.long 0x00 12. " SET_OUT[12] ,Set output 12" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET_OUT[11] ,Set output 11" "No effect,Set"
|
|
bitfld.long 0x00 10. " SET_OUT[10] ,Set output 10" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 09. " SET_OUT[9] ,Set output 9" "No effect,Set"
|
|
bitfld.long 0x00 08. " SET_OUT[8] ,Set output 8" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 07. " SET_OUT[7] ,Set output 7" "No effect,Set"
|
|
bitfld.long 0x00 06. " SET_OUT[6] ,Set output 6" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 05. " SET_OUT[5] ,Set output 5" "No effect,Set"
|
|
bitfld.long 0x00 04. " SET_OUT[4] ,Set output 4" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 03. " SET_OUT[3] ,Set output 3" "No effect,Set"
|
|
bitfld.long 0x00 02. " SET_OUT[2] ,Set output 2" "No effect,Set"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SET_OUT[1] ,Set output 1" "No effect,Set"
|
|
bitfld.long 0x00 00. " SET_OUT[0] ,Set output 0" "No effect,Set"
|
|
tree.end
|
|
tree.end
|
|
base AD:0xFFFB0C00
|
|
tree "SPI Registers"
|
|
width 0x0A
|
|
rgroup.long (0x0000)++0x03
|
|
line.long 0x00 "SPI_REV,Identification Register Bit Description"
|
|
bitfld.long 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long (0x0010)++0x03
|
|
line.long 0x00 "SPI_SCR,System Configuration Register"
|
|
bitfld.long 0x00 03.--04. " IDLEMODE ,Power management request/acknowledge control" "IDLE,No IDLE,Smart IDLE,?..."
|
|
bitfld.long 0x00 02. " ENAWAKEUP ,Wake-up feature control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 01. " SOFTRESET ,Software reset" "No reset,Reset"
|
|
bitfld.long 0x00 00. " AUTOIDLE ,Internal OCP clock gating strategy" "Disabled,Enabled"
|
|
rgroup.long (0x0014)++0x03
|
|
line.long 0x00 "SPI_SSR,System Status Register"
|
|
bitfld.long 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.long (0x0018)++(0x04+0x03)
|
|
line.long 0x00 "SPI_ISR,Interrupt Status Register"
|
|
eventfld.long 0x00 04. " WAKEUP ,Wake-up" "Not occurred,Occurred"
|
|
eventfld.long 0x00 03. " TX_UNDERFLOW ,Transmit underflow" "No underflow,Underflowed"
|
|
textline " "
|
|
eventfld.long 0x00 02. " RX_OVERFLOW ,Receive overflow" "No overflow,Overflowed"
|
|
eventfld.long 0x00 01. " WE ,Write end" "No end,End"
|
|
textline " "
|
|
eventfld.long 0x00 00. " RE ,Read end" "No end,End"
|
|
;group (0x001C)++0x03
|
|
line.long (0x04) "SPI_IER,Interrupt Enable Register"
|
|
bitfld.long (0x04) 04. " MSK_WAKEUP ,Enable interrupt wake-up (MSK4)" "Disabled,Enabled"
|
|
bitfld.long (0x04) 03. " MSK_TX_UNDERFLOW ,Enable interrupt transmit underflow (MSK3)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 02. " MSK_RX_OVERFLOW ,Enable interrupt receive overflow (MSK2)" "Disabled,Enabled"
|
|
bitfld.long (0x04) 01. " MSK_WE ,Enable interrupt write end (MSK1)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long (0x04) 00. " MSK_RE ,Enable interrupt read end (MSK0)" "Disabled,Enabled"
|
|
group.long (0x0024)++(0x08+0x03)
|
|
line.long 0x00 "SPI_SET1,Set Up SPI 1 Register"
|
|
bitfld.long 0x00 05. " DMA_EN ,Enable DMA protocol" "Disabled,Enabled"
|
|
bitfld.long 0x00 01.--04. " PTV ,Prescale time value" "1,2,4,8,16,32,64,128,256,512,1024,2048,4096,4096,4096,4096"
|
|
textline " "
|
|
bitfld.long 0x00 00. " EN_CLK ,SPI functional clock enable" "Disabled,Enabled"
|
|
;group (0x0028)++0x03
|
|
line.long (0x04) "SPI_SET2,Set Up SPI 2 Register"
|
|
bitfld.long (0x04) 15. " MODE ,Device mode" "Slave,Master"
|
|
bitfld.long (0x04) 14. " CP[4] ,Shift register clock begin toggle on device 4" "Half transfer,Begin transfer"
|
|
textline " "
|
|
bitfld.long (0x04) 13. " CP[3] ,Shift register clock begin toggle on device 3" "Half transfer,Begin transfer"
|
|
bitfld.long (0x04) 12. " CP[2] ,Shift register clock begin toggle on device 2" "Half transfer,Begin transfer"
|
|
textline " "
|
|
bitfld.long (0x04) 11. " CP[1] ,Shift register clock begin toggle on device 1" "Half transfer,Begin transfer"
|
|
bitfld.long (0x04) 10. " CP[0] ,Shift register clock begin toggle on device 0" "Half transfer,Begin transfer"
|
|
textline " "
|
|
bitfld.long (0x04) 09. " CE[4] ,Shift register enable active level on device 4" "Low,High"
|
|
bitfld.long (0x04) 08. " CE[3] ,Shift register enable active level on device 3" "Low,High"
|
|
textline " "
|
|
bitfld.long (0x04) 07. " CE[2] ,Shift register enable active level on device 2" "Low,High"
|
|
bitfld.long (0x04) 06. " CE[1] ,Shift register enable active level on device 1" "Low,High"
|
|
textline " "
|
|
bitfld.long (0x04) 05. " CE[0] ,Shift register enable active level on device 0" "Low,High"
|
|
bitfld.long (0x04) 04. " CI[4] ,Inactive edge of the shift register clock on device 4" "Low,High"
|
|
textline " "
|
|
bitfld.long (0x04) 03. " CI[3] ,Inactive edge of the shift register clock on device 3" "Low,High"
|
|
bitfld.long (0x04) 02. " CI[2] ,Inactive edge of the shift register clock on device 2" "Low,High"
|
|
textline " "
|
|
bitfld.long (0x04) 01. " CI[1] ,Inactive edge of the shift register clock on device 1" "Low,High"
|
|
bitfld.long (0x04) 00. " CI[0] ,Inactive edge of the shift register clock on device 0" "Low,High"
|
|
;group (0x002C)++0x03
|
|
line.long (0x08) "SPI_CTRL,Control SPI Register"
|
|
bitfld.long (0x08) 07.--09. " AD ,Addressed device" "0,1,2,3,4,?..."
|
|
bitfld.long (0x08) 02.--06. " NB ,Number of bits to receive/transmit" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32"
|
|
textline " "
|
|
bitfld.long (0x08) 01. " WR ,Write process activation" "Not activated,Activated"
|
|
bitfld.long (0x08) 00. " RD ,Read process activation" "Not activated,Activated"
|
|
rgroup.long (0x0030)++0x03
|
|
line.long 0x00 "SPI_DSR,Shift Status Register"
|
|
bitfld.long 0x00 01. " TX_EMPTY ,Shift register is empty" "Not empty,Empty"
|
|
bitfld.long 0x00 00. " RX_FULL ,Receive register is full" "Not full,Full"
|
|
group.long (0x0034)++0x03
|
|
line.long 0x00 "SPI_TX,Transmit Register"
|
|
hexmask.long 0x00 00.--31. 1. " SPI_TX ,Data to transmit"
|
|
hgroup.long (0x0038)++0x03
|
|
hide.long 0x00 "SPI_RX,Receive Register"
|
|
textfld " "
|
|
in
|
|
group.long (0x003C)++0x03
|
|
line.long 0x00 "SPI_TEST,Test Register"
|
|
bitfld.long 0x00 10. " RTSPEN[4] ,Read value of TSPEN[4]" "Low,High"
|
|
bitfld.long 0x00 09. " RTSPEN[3] ,Read value of TSPEN[3]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 08. " RTSPEN[2] ,Read value of TSPEN[2]" "Low,High"
|
|
bitfld.long 0x00 07. " RTSPEN[1] ,Read value of TSPEN[1]" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 06. " RTSPEN[0] ,Read value of TSPEN[0]" "Low,High"
|
|
bitfld.long 0x00 05. " RCV ,Read clock value" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 04. " WCV ,Write clock value" "Low,High"
|
|
bitfld.long 0x00 03. " RTV ,Read test value (TSPDI)" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 02. " WTV ,Write test value (TSPDO)" "Low,High"
|
|
bitfld.long 0x00 01. " FDO ,Force TSPDO to read value from WTV bit" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 00. " TMODE ,Test mode enable" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFB1000
|
|
tree "McBSP2"
|
|
width 0x06
|
|
tree "Data Registers"
|
|
hgroup.word (0x0002)++0x01
|
|
hide.word 0x00 "DRR1,Data Receive Register 1"
|
|
in
|
|
hgroup.word (0x0000)++0x01
|
|
hide.word 0x00 "DRR2,Data Receive Register 2"
|
|
in
|
|
wgroup.word (0x0006)++0x01
|
|
line.word 0x00 "DXR1,Data Transmit Register 1"
|
|
textfld " "
|
|
hexmask.word 0x00 00.--15. 1. " DATAL ,Receive data or low part of receive data (8-bit,12-bit,16-bit)"
|
|
wgroup.word (0x0004)++0x01
|
|
line.word 0x00 "DXR2,Data Transmit Register 2"
|
|
textfld " "
|
|
hexmask.word 0x00 00.--15. 1. " DATAH ,High part of transmit data (20-bit,24-bit,32-bit)"
|
|
tree.end
|
|
width 0x07
|
|
tree "Control Registers"
|
|
group.word (0x000A)++0x01
|
|
line.word 0x00 "SPCR1,Serial Port Control Register 1"
|
|
bitfld.word 0x00 15. " DLB ,Digital loopback mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13.--14. " RJUST ,Receive sign-extension and justification mode" "Right justify/Zero fill,Right justify/Sign extend,Left justify/Zero fill,?..."
|
|
textline " "
|
|
bitfld.word 0x00 11.--12. " CLKSTP ,Clock stop mode" "Disabled,Disabled,No delay,Half-cycle delay"
|
|
bitfld.word 0x00 07. " DXENA ,DX delay enabler mode" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 04.--05. " RINTM ,Receive interrupt mode" "RRDY changed,Received block,Detected frame-sync,RSYNCERR set"
|
|
bitfld.word 0x00 03. " RSYNCERR ,Receive frame-sync error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RFULL ,Receiver full" "Not full,Full"
|
|
bitfld.word 0x00 01. " RRDY ,Receiver ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 00. " RRST ,Receiver reset" "Reset,No reset"
|
|
group.word (0x0008)++0x01
|
|
line.word 0x00 "SPCR2,Serial Port Control Register 2"
|
|
bitfld.word 0x00 09. " FREE ,Free run" "Disabled,Enabled"
|
|
bitfld.word 0x00 08. " SOFT ,Soft stop" "Hard,Soft"
|
|
textline " "
|
|
bitfld.word 0x00 07. " FRST ,Frame-synchronization logic reset" "Reset,No reset"
|
|
bitfld.word 0x00 06. " GRST ,Sample rate generator reset" "Reset,No reset"
|
|
textline " "
|
|
bitfld.word 0x00 04.--05. " XINTM ,Transmit interrupt mode" "XRDY changed,Transmitted block,Detected frame-sync,XSYNCERR set"
|
|
bitfld.word 0x00 03. " XSYNCERR ,Transmit frame-synchronization error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 02. " XEMPTY ,Transmitter empty" "Empty,Not empty"
|
|
bitfld.word 0x00 01. " XRDY ,Transmitter ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.word 0x00 00. " XRST ,Transmitter reset" "Reset,No reset"
|
|
group.word (0x000E)++0x01
|
|
line.word 0x00 "RCR1,Receive Control Register 1"
|
|
hexmask.word.byte 0x00 08.--14. 1. 1. " RFRLEN1 ,Receive frame length 1"
|
|
bitfld.word 0x00 05.--07. " RWDLEN1 ,Receive word length 1" "8-bit,12-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.word (0x000C)++0x01
|
|
line.word 0x00 "RCR2,Receive Control Register 2"
|
|
bitfld.word 0x00 15. " RPHASE ,Receive phase number" "Single,Dual"
|
|
hexmask.word.byte 0x00 08.--14. 1. 1. " RFRLEN2 ,Receive frame length 2"
|
|
textline " "
|
|
bitfld.word 0x00 05.--07. " RWDLEN2 ,Receive word length 2" "8-bit,12-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 03.--04. " RCOMPAND ,Receive companding mode" "No companding/any size/MSB first,No companding/8-bit/LSB first,u-law companding/8-bit/MSB first,A-law companding/8-bit/MSB first"
|
|
textline " "
|
|
bitfld.word 0x00 02. " RFIG ,Receive frame-synchronization ignore" "Not ignored,Ignored"
|
|
bitfld.word 0x00 00.--01. " RDATDLY ,Receive data delay" "0-bit,1-bit,2-bit,?..."
|
|
group.word (0x0012)++0x01
|
|
line.word 0x00 "XCR1,Transmit Control Register 1"
|
|
hexmask.word.byte 0x00 08.--14. 1. 1. " XFRLEN1 ,Transmit frame length 1"
|
|
bitfld.word 0x00 05.--07. " XWDLEN1 ,Transmit word length 1" "8-bit,12-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
group.word (0x0010)++0x01
|
|
line.word 0x00 "XCR2,Transmit Control Register 2"
|
|
bitfld.word 0x00 15. " XPHASE ,Transmit phase number" "Single,Dual"
|
|
hexmask.word.byte 0x00 08.--14. 1. 1. " XFRLEN2 ,Transmit frame length 2"
|
|
textline " "
|
|
bitfld.word 0x00 05.--07. " XWDLEN2 ,Transmit word length 2" "8-bit,12-bit,16-bit,20-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 03.--04. " XCOMPAND ,Transmit companding mode" "No companding/any size/MSB first,No companding/8-bit/LSB first,u-law companding/8-bit/MSB first,A-law companding/8-bit/MSB first"
|
|
textline " "
|
|
bitfld.word 0x00 02. " XFIG ,Transmit frame-synchronization ignore" "Not ignored,Ignored"
|
|
bitfld.word 0x00 00.--01. " XDATDLY ,Transmit data delay" "0-bit,1-bit,2-bit,?..."
|
|
group.word (0x0016)++0x01
|
|
line.word 0x00 "SRGR1,Sample Rate Generator Register 1"
|
|
hexmask.word.byte 0x00 08.--15. 1. 1. " FWID ,Frame-synchronization pulse width for FSG"
|
|
hexmask.word.byte 0x00 00.--07. 1. 1. " CLKGDV ,Divide-down value for CLKG"
|
|
if ((data.word(AD:0xFFFB1000+0x0024)&0x0080)==0x0)
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "SRGR2,Sample Rate Generator Register 2"
|
|
bitfld.word 0x00 15. " GSYNC ,Clock synchronization mode for CLKG" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " CLKSP ,CLKS pin polarity" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CLKSM ,Sample rate generator input clock mode" "CLKS pin,CPU clk"
|
|
bitfld.word 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "McBSP,Sample rate generator"
|
|
textline " "
|
|
hexmask.word 0x00 00.--11. 1. 1. " FPER ,Frame-synchronization period for FSG"
|
|
else
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "SRGR2,Sample Rate Generator Register 2"
|
|
bitfld.word 0x00 15. " GSYNC ,Clock synchronization mode for CLKG" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " CLKSP ,CLKS pin polarity" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 13. " CLKSM ,Sample rate generator input clock mode" "CLKR pin,CLKX pin"
|
|
bitfld.word 0x00 12. " FSGM ,Sample rate generator transmit frame-synchronization mode" "McBSP,Sample rate generator"
|
|
textline " "
|
|
hexmask.word 0x00 00.--11. 1. 1. " FPER ,Frame-synchronization period for FSG"
|
|
endif
|
|
if (d.w(AD:0xFFFB1000+0x0D)&0x0201)==0x0001
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "MCR1,Multichannel register 1"
|
|
bitfld.word 0x00 9. " RMCME ,Receive multichannel partition mode bit" "2-partition,8-partition"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " RPBBLK ,Receive partition B block bits" "Block 1 [16..31],Block 3 [48..63],Block 5 [80..95],Block 7 [112..127]"
|
|
bitfld.word 0x00 5.--6. " RPABLK ,Receive partition A block bits" "Block 0 [0..15],Block 2 [32..47],Block 4 [64..79],Block 6 [96..111]"
|
|
textline " "
|
|
bitfld.word 0x00 2.--4. " RCBLK ,Receive current block indicator" "Block 0 [0..15],Block 1 [16..31],Block 2 [32..47],Block 3 [48..63],Block 4 [64..79],Block 5 [80..95],Block 6 [96..111],Block 7 [112..127]"
|
|
bitfld.word 0x00 0. " RMCM ,Receive multichannel selection mode bit" "All 128 channels,Multichannel selection"
|
|
elif (d.w(AD:0xFFFB1000+0x0D)&0x0001)==0x0001
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "MCR1,Multichannel register 1"
|
|
bitfld.word 0x00 9. " RMCME ,Receive multichannel partition mode bit" "2-partition,8-partition"
|
|
textline " "
|
|
textline " "
|
|
bitfld.word 0x00 2.--4. " RCBLK ,Receive current block indicator" "Block 0 [0..15],Block 1 [16..31],Block 2 [32..47],Block 3 [48..63],Block 4 [64..79],Block 5 [80..95],Block 6 [96..111],Block 7 [112..127]"
|
|
bitfld.word 0x00 0. " RMCM ,Receive multichannel selection mode bit" "All 128 channels,Multichannel selection"
|
|
else
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "MCR1,Multichannel register 1"
|
|
textline " "
|
|
textline " "
|
|
bitfld.word 0x00 2.--4. " RCBLK ,Receive current block indicator" "Block 0 [0..15],Block 1 [16..31],Block 2 [32..47],Block 3 [48..63],Block 4 [64..79],Block 5 [80..95],Block 6 [96..111],Block 7 [112..127]"
|
|
bitfld.word 0x00 0. " RMCM ,Receive multichannel selection mode bit" "All 128 channels,Multichannel selection"
|
|
endif
|
|
if ((d.w(AD:0xFFFB1000+0xC)&0x0200)==0x0000)&&((d.w(AD:0xFFFB1000+0xC)&0x0003)!=0x0000)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "MCR2,Multichannel register 2"
|
|
bitfld.word 0x00 9. " XMCME ,Transmit multichannel partition mode bit" "2-partition,8-partition"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " XPBBLK ,Transmit partition B block bits" "Block 1 [16..31],Block 3 [48..63],Block 5 [80..95],Block 7 [112..127]"
|
|
bitfld.word 0x00 5.--6. " XPABLK ,Transmit partition A block bits" "Block 0 [0..15],Block 2 [32..47],Block 4 [64..79],Block 6 [96..111]"
|
|
textline " "
|
|
bitfld.word 0x00 2.--4. " XCBLK ,Transmit current block indicator" "Block 0 [0..15],Block 1 [16..31],Block 2 [32..47],Block 3 [48..63],Block 4 [64..79],Block 5 [80..95],Block 6 [96..111],Block 7 [112..127]"
|
|
bitfld.word 0x00 0.--1. " XMCM ,Transmit multichannel selection mode bit" "Multichannel selection off,All channels disabled,All channels enabled,Symmetric TX/RX"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0003)!=0x0000
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "MCR2,Multichannel register 2"
|
|
bitfld.word 0x00 9. " XMCME ,Transmit multichannel partition mode bit" "2-partition,8-partition"
|
|
textline " "
|
|
textline " "
|
|
bitfld.word 0x00 2.--4. " XCBLK ,Transmit current block indicator" "Block 0 [0..15],Block 1 [16..31],Block 2 [32..47],Block 3 [48..63],Block 4 [64..79],Block 5 [80..95],Block 6 [96..111],Block 7 [112..127]"
|
|
bitfld.word 0x00 0.--1. " XMCM ,Transmit multichannel selection mode bit" "Multichannel selection off,All channels disabled,All channels enabled,Symmetric TX/RX"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "MCR2,Multichannel register 2"
|
|
textline " "
|
|
textline " "
|
|
bitfld.word 0x00 2.--4. " XCBLK ,Transmit current block indicator" "Block 0 [0..15],Block 1 [16..31],Block 2 [32..47],Block 3 [48..63],Block 4 [64..79],Block 5 [80..95],Block 6 [96..111],Block 7 [112..127]"
|
|
bitfld.word 0x00 0.--1. " XMCM ,Transmit multichannel selection mode bit" "Multichannel selection off,All channels disabled,All channels enabled,Symmetric TX/RX"
|
|
endif
|
|
if ((data.word(AD:0xFFFB1000+0x0014)&0x2000)==0x0)
|
|
group.word (0x0024)++0x01
|
|
line.word 0x00 "PCR,Pin Control Register"
|
|
bitfld.word 0x00 14. " IDLEEN ,Idle enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XIOEN ,Transmit I/O enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " RIOEN ,Receive I/O enable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,Internal"
|
|
bitfld.word 0x00 09. " CLKXM ,Transmit clock mode" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 08. " CLKRM ,Receive clock mode" "External,Internal"
|
|
bitfld.word 0x00 07. " SCLKME ,Sample rate generator input clock mode" "CLKS pin,CLKR pin"
|
|
textline " "
|
|
bitfld.word 0x00 06. " CLKSSTAT ,CLKS pin status" "Low,High"
|
|
bitfld.word 0x00 05. " DXSTAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 04. " DRSTAT ,DR pin status" "Low,High"
|
|
bitfld.word 0x00 03. " FSXP ,Transmit frame-synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " FSRP ,Receive frame-synchronization polarity" "Active high,Active low"
|
|
bitfld.word 0x00 01. " CLKXP ,Transmit clock polarity" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 00. " CLKRP ,Receive clock polarity" "Falling edge,Rising edge"
|
|
else
|
|
group.word (0x0024)++0x01
|
|
line.word 0x00 "PCR,Pin Control Register"
|
|
bitfld.word 0x00 14. " IDLEEN ,Idle enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XIOEN ,Transmit I/O enable" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " RIOEN ,Receive I/O enable" "Enabled,Disabled"
|
|
bitfld.word 0x00 11. " FSXM ,Transmit frame-synchronization mode" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 10. " FSRM ,Receive frame-synchronization mode" "External,Internal"
|
|
bitfld.word 0x00 09. " CLKXM ,Transmit clock mode" "External,Internal"
|
|
textline " "
|
|
bitfld.word 0x00 08. " CLKRM ,Receive clock mode" "External,Internal"
|
|
bitfld.word 0x00 07. " SCLKME ,Sample rate generator input clock mode" "CPU clk,CLKX pin"
|
|
textline " "
|
|
bitfld.word 0x00 06. " CLKSSTAT ,CLKS pin status" "Low,High"
|
|
bitfld.word 0x00 05. " DXSTAT ,DX pin status" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x00 04. " DRSTAT ,DR pin status" "Low,High"
|
|
bitfld.word 0x00 03. " FSXP ,Transmit frame-synchronization polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 02. " FSRP ,Receive frame-synchronization polarity" "Active high,Active low"
|
|
bitfld.word 0x00 01. " CLKXP ,Transmit clock polarity" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.word 0x00 00. " CLKRP ,Receive clock polarity" "Falling edge,Rising edge"
|
|
endif
|
|
group.word (0x003E)++0x01
|
|
line.word 0x00 "REV,McBSP2 Version Register"
|
|
tree.end
|
|
tree "Receive channel enable registers"
|
|
width 6.
|
|
if (d.w(AD:0xFFFB1000+0xD)&0x0001)==0x0000
|
|
hgroup.word 0x1C++0x01
|
|
hide.word 0x00 "RCERA,Receive channel enable register partition A"
|
|
elif ((d.w(AD:0xFFFB1000+0xD)&0x0200)==0x0200)||((d.w(AD:0xFFFB1000+0x0d)&0x0260)==0x0000)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RCERA,Receive channel enable register partition A"
|
|
bitfld.word 0x00 15. " RCE15 ,Receive channel 15 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE14 ,Receive channel 14 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE13 ,Receive channel 13 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE12 ,Receive channel 12 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE11 ,Receive channel 11 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE10 ,Receive channel 10 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE9 ,Receive channel 9 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE8 ,Receive channel 8 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE7 ,Receive channel 7 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE6 ,Receive channel 6 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE5 ,Receive channel 5 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE4 ,Receive channel 4 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE3 ,Receive channel 3 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE2 ,Receive channel 2 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE1 ,Receive channel 1 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE0 ,Receive channel 0 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xD)&0x0260)==0x0020
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RCERA,Receive channel enable register partition A"
|
|
bitfld.word 0x00 15. " RCE47 ,Receive channel 47 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE46 ,Receive channel 46 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE45 ,Receive channel 45 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE44 ,Receive channel 44 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE43 ,Receive channel 43 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE42 ,Receive channel 42 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE41 ,Receive channel 41 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE40 ,Receive channel 40 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE39 ,Receive channel 39 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE38 ,Receive channel 38 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE37 ,Receive channel 37 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE36 ,Receive channel 36 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE35 ,Receive channel 35 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE34 ,Receive channel 34 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE33 ,Receive channel 33 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE32 ,Receive channel 32 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xD)&0x0260)==0x0040
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RCERA,Receive channel enable register partition A"
|
|
bitfld.word 0x00 15. " RCE79 ,Receive channel 79 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE78 ,Receive channel 78 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE77 ,Receive channel 77 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE76 ,Receive channel 76 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE75 ,Receive channel 75 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE74 ,Receive channel 74 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE73 ,Receive channel 73 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE72 ,Receive channel 72 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE71 ,Receive channel 71 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE70 ,Receive channel 70 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE69 ,Receive channel 69 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE68 ,Receive channel 68 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE67 ,Receive channel 67 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE66 ,Receive channel 66 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE65 ,Receive channel 65 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE64 ,Receive channel 64 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xD)&0x0260)==0x0060
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RCERA,Receive channel enable register partition A"
|
|
bitfld.word 0x00 15. " RCE111 ,Receive channel 111 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE110 ,Receive channel 110 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE109 ,Receive channel 109 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE108 ,Receive channel 108 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE107 ,Receive channel 107 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE106 ,Receive channel 106 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE105 ,Receive channel 105 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE104 ,Receive channel 104 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE103 ,Receive channel 103 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE102 ,Receive channel 102 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE101 ,Receive channel 101 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE100 ,Receive channel 100 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE99 ,Receive channel 99 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE98 ,Receive channel 98 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE97 ,Receive channel 97 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE96 ,Receive channel 96 enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (d.w(AD:0xFFFB1000+0xD)&0x0001)==0x0000
|
|
hgroup.word 0x1E++0x01
|
|
hide.word 0x00 "RCERB,Receive channel enable register partition B"
|
|
elif ((d.w(AD:0xFFFB1000+0xD)&0x0200)==0x0200)||((d.w(AD:0xFFFB1000+0x0d)&0x0380)==0x0000)
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "RCERB,Receive channel enable register partition B"
|
|
bitfld.word 0x00 15. " RCE31 ,Receive channel 31 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE30 ,Receive channel 30 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE29 ,Receive channel 29 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE28 ,Receive channel 28 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE27 ,Receive channel 27 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE26 ,Receive channel 26 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE25 ,Receive channel 25 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE24 ,Receive channel 24 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE23 ,Receive channel 23 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE22 ,Receive channel 22 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE21 ,Receive channel 21 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE20 ,Receive channel 20 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE19 ,Receive channel 19 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE18 ,Receive channel 18 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE17 ,Receive channel 17 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE16 ,Receive channel 16 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xD)&0x0380)==0x0080
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "RCERB,Receive channel enable register partition B"
|
|
bitfld.word 0x00 15. " RCE63 ,Receive channel 63 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE62 ,Receive channel 62 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE61 ,Receive channel 61 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE60 ,Receive channel 60 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE59 ,Receive channel 59 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE58 ,Receive channel 58 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE57 ,Receive channel 57 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE56 ,Receive channel 56 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE55 ,Receive channel 55 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE54 ,Receive channel 54 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE53 ,Receive channel 53 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE52 ,Receive channel 52 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE51 ,Receive channel 51 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE50 ,Receive channel 50 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE49 ,Receive channel 49 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE48 ,Receive channel 48 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xD)&0x0380)==0x0100
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "RCERB,Receive channel enable register partition B"
|
|
bitfld.word 0x00 15. " RCE95 ,Receive channel 95 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE94 ,Receive channel 94 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE93 ,Receive channel 93 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE92 ,Receive channel 92 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE91 ,Receive channel 91 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE90 ,Receive channel 90 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE89 ,Receive channel 89 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE88 ,Receive channel 88 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE87 ,Receive channel 87 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE86 ,Receive channel 86 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE85 ,Receive channel 85 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE84 ,Receive channel 84 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE83 ,Receive channel 83 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE82 ,Receive channel 82 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE81 ,Receive channel 81 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE80 ,Receive channel 80 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xD)&0x0380)==0x0180
|
|
group.word 0x1E++0x01
|
|
line.word 0x00 "RCERB,Receive channel enable register partition B"
|
|
bitfld.word 0x00 15. " RCE127 ,Receive channel 127 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE126 ,Receive channel 126 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE125 ,Receive channel 125 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE124 ,Receive channel 124 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE123 ,Receive channel 123 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE122 ,Receive channel 122 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE121 ,Receive channel 121 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE120 ,Receive channel 120 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE119 ,Receive channel 119 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE118 ,Receive channel 118 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE117 ,Receive channel 117 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE116 ,Receive channel 116 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE115 ,Receive channel 115 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE114 ,Receive channel 114 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE113 ,Receive channel 113 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE112 ,Receive channel 112 enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (d.w(AD:0xFFFB1000+0xD)&0x0201)==0x0201
|
|
group.word 0x26++0x13
|
|
line.word 0x00 "RCERC,Receive channel enable register partition C"
|
|
bitfld.word 0x00 15. " RCE47 ,Receive channel 47 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RCE46 ,Receive channel 46 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " RCE45 ,Receive channel 45 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " RCE44 ,Receive channel 44 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " RCE43 ,Receive channel 43 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " RCE42 ,Receive channel 42 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " RCE41 ,Receive channel 41 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " RCE40 ,Receive channel 40 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " RCE39 ,Receive channel 39 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " RCE38 ,Receive channel 38 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " RCE37 ,Receive channel 37 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " RCE36 ,Receive channel 36 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " RCE35 ,Receive channel 35 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " RCE34 ,Receive channel 34 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " RCE33 ,Receive channel 33 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RCE32 ,Receive channel 32 enable bit" "Disabled,Enabled"
|
|
line.word 0X02 "RCERD,Receive channel enable register partition D"
|
|
bitfld.word 0X02 15. " RCE63 ,Receive channel 63 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 14. " RCE62 ,Receive channel 62 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 13. " RCE61 ,Receive channel 61 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 12. " RCE60 ,Receive channel 60 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0X02 11. " RCE59 ,Receive channel 59 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 10. " RCE58 ,Receive channel 58 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 9. " RCE57 ,Receive channel 57 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 8. " RCE56 ,Receive channel 56 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0X02 7. " RCE55 ,Receive channel 55 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 6. " RCE54 ,Receive channel 54 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 5. " RCE53 ,Receive channel 53 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 4. " RCE52 ,Receive channel 52 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0X02 3. " RCE51 ,Receive channel 51 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 2. " RCE50 ,Receive channel 50 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 1. " RCE49 ,Receive channel 49 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0X02 0. " RCE48 ,Receive channel 48 enable bit" "Disabled,Enabled"
|
|
line.word 0x08 "RCERE,Receive channel enable register partition E"
|
|
bitfld.word 0x08 15. " RCE79 ,Receive channel 79 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 14. " RCE78 ,Receive channel 78 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 13. " RCE77 ,Receive channel 77 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 12. " RCE76 ,Receive channel 76 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " RCE75 ,Receive channel 75 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " RCE74 ,Receive channel 74 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " RCE73 ,Receive channel 73 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " RCE72 ,Receive channel 72 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 7. " RCE71 ,Receive channel 71 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6. " RCE70 ,Receive channel 70 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 5. " RCE69 ,Receive channel 69 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 4. " RCE68 ,Receive channel 68 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 3. " RCE67 ,Receive channel 67 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 2. " RCE66 ,Receive channel 66 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 1. " RCE65 ,Receive channel 65 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 0. " RCE64 ,Receive channel 64 enable bit" "Disabled,Enabled"
|
|
line.word 0x0A "RCERF,Receive channel enable register partition F"
|
|
bitfld.word 0x0A 15. " RCE95 ,Receive channel 95 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 14. " RCE94 ,Receive channel 94 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 13. " RCE93 ,Receive channel 93 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 12. " RCE92 ,Receive channel 92 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0A 11. " RCE91 ,Receive channel 91 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 10. " RCE90 ,Receive channel 90 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 9. " RCE89 ,Receive channel 89 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 8. " RCE88 ,Receive channel 88 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0A 7. " RCE87 ,Receive channel 87 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6. " RCE86 ,Receive channel 86 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 5. " RCE85 ,Receive channel 85 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 4. " RCE84 ,Receive channel 84 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0A 3. " RCE83 ,Receive channel 83 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 2. " RCE82 ,Receive channel 82 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 1. " RCE81 ,Receive channel 81 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 0. " RCE80 ,Receive channel 80 enable bit" "Disabled,Enabled"
|
|
line.word 0x10 "RCERG,Receive channel enable register partition G"
|
|
bitfld.word 0x10 15. " RCE111 ,Receive channel 111 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 14. " RCE110 ,Receive channel 110 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 13. " RCE109 ,Receive channel 109 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 12. " RCE108 ,Receive channel 108 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x10 11. " RCE107 ,Receive channel 107 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 10. " RCE106 ,Receive channel 106 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 9. " RCE105 ,Receive channel 105 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 8. " RCE104 ,Receive channel 104 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x10 7. " RCE103 ,Receive channel 103 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6. " RCE102 ,Receive channel 102 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 5. " RCE101 ,Receive channel 101 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 4. " RCE100 ,Receive channel 100 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x10 3. " RCE99 ,Receive channel 99 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 2. " RCE98 ,Receive channel 98 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 1. " RCE97 ,Receive channel 97 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 0. " RCE96 ,Receive channel 96 enable bit" "Disabled,Enabled"
|
|
line.word 0x12 "RCERH,Receive channel enable register partition H"
|
|
bitfld.word 0x12 15. " RCE127 ,Receive channel 127 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 14. " RCE126 ,Receive channel 126 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 13. " RCE125 ,Receive channel 125 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 12. " RCE124 ,Receive channel 124 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x12 11. " RCE123 ,Receive channel 123 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 10. " RCE122 ,Receive channel 122 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 9. " RCE121 ,Receive channel 121 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 8. " RCE120 ,Receive channel 120 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x12 7. " RCE119 ,Receive channel 119 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 6. " RCE118 ,Receive channel 118 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 5. " RCE117 ,Receive channel 117 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 4. " RCE116 ,Receive channel 116 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x12 3. " RCE115 ,Receive channel 115 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 2. " RCE114 ,Receive channel 114 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 1. " RCE113 ,Receive channel 113 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 0. " RCE112 ,Receive channel 112 enable bit" "Disabled,Enabled"
|
|
else
|
|
rgroup.word 0x26++0x13
|
|
hide.word 0x00 "RCERC,Receive channel enable register partition C"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x02 "RCERD,Receive channel enable register partition D"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x08 "RCERE,Receive channel enable register partition E"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x0A "RCERF,Receive channel enable register partition F"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x10 "RCERG,Receive channel enable register partition G"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x12 "RCERH,Receive channel enable register partition H"
|
|
endif
|
|
tree.end
|
|
tree "Transmit channel enable registers"
|
|
width 6.
|
|
if (d.w(AD:0xFFFB1000+0xC)&0x0003)==0x0000
|
|
rgroup.word 0x20++0x01
|
|
hide.word 0x00 "XCERA,Trasmit channel enable register partition A"
|
|
elif ((d.w(AD:0xFFFB1000+0xC)&0x0200)==0x0200)||((d.w(AD:0xFFFB1000+0xC)&0x0260)==0x0000)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "XCERA,Trasmit channel enable register partition A"
|
|
bitfld.word 0x00 15. " XCE15 ,Transmit channel 15 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE14 ,Transmit channel 14 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE13 ,Transmit channel 13 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE12 ,Transmit channel 12 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE11 ,Transmit channel 11 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE10 ,Transmit channel 10 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE9 ,Transmit channel 9 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE8 ,Transmit channel 8 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE7 ,Transmit channel 7 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE6 ,Transmit channel 6 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE5 ,Transmit channel 5 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE4 ,Transmit channel 4 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE3 ,Transmit channel 3 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE2 ,Transmit channel 2 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE1 ,Transmit channel 1 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE0 ,Transmit channel 0 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0260)==0x0020
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "XCERA,Trasmit channel enable register partition A"
|
|
bitfld.word 0x00 15. " XCE47 ,Transmit channel 47 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE46 ,Transmit channel 46 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE45 ,Transmit channel 45 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE44 ,Transmit channel 44 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE43 ,Transmit channel 43 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE42 ,Transmit channel 42 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE41 ,Transmit channel 41 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE40 ,Transmit channel 40 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE39 ,Transmit channel 39 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE38 ,Transmit channel 38 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE37 ,Transmit channel 37 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE36 ,Transmit channel 36 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE35 ,Transmit channel 35 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE34 ,Transmit channel 34 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE33 ,Transmit channel 33 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE32 ,Transmit channel 32 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0260)==0x0040
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "XCERA,Trasmit channel enable register partition A"
|
|
bitfld.word 0x00 15. " XCE79 ,Transmit channel 79 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE78 ,Transmit channel 78 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE77 ,Transmit channel 77 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE76 ,Transmit channel 76 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE75 ,Transmit channel 75 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE74 ,Transmit channel 74 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE73 ,Transmit channel 73 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE72 ,Transmit channel 72 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE71 ,Transmit channel 71 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE70 ,Transmit channel 70 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE69 ,Transmit channel 69 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE68 ,Transmit channel 68 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE67 ,Transmit channel 67 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE66 ,Transmit channel 66 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE65 ,Transmit channel 65 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE64 ,Transmit channel 64 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0260)==0x0060
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "XCERA,Trasmit channel enable register partition A"
|
|
bitfld.word 0x00 15. " XCE111 ,Transmit channel 111 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE110 ,Transmit channel 110 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE109 ,Transmit channel 109 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE108 ,Transmit channel 108 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE107 ,Transmit channel 107 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE106 ,Transmit channel 106 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE105 ,Transmit channel 105 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE104 ,Transmit channel 104 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE103 ,Transmit channel 103 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE102 ,Transmit channel 102 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE101 ,Transmit channel 101 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE100 ,Transmit channel 100 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE99 ,Transmit channel 99 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE98 ,Transmit channel 98 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE97 ,Transmit channel 97 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE96 ,Transmit channel 96 enable bit" "Disabled,Enabled"
|
|
endif
|
|
if (d.w(AD:0xFFFB1000+0xC)&0x0003)==0x0000
|
|
rgroup.word 0x22++0x01
|
|
hide.word 0x00 "XCERB,Trasmit channel enable register partition B"
|
|
elif ((d.w(AD:0xFFFB1000+0xC)&0x0200)==0x0200)||((d.w(AD:0xFFFB1000+0xC)&0x0380)==0x0000)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "XCERB,Trasmit channel enable register partition B"
|
|
bitfld.word 0x00 15. " XCE31 ,Transmit channel 31 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE30 ,Transmit channel 30 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE29 ,Transmit channel 29 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE28 ,Transmit channel 28 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE27 ,Transmit channel 27 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE26 ,Transmit channel 26 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE25 ,Transmit channel 25 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE24 ,Transmit channel 24 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE23 ,Transmit channel 23 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE22 ,Transmit channel 22 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE21 ,Transmit channel 21 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE20 ,Transmit channel 20 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE19 ,Transmit channel 19 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE18 ,Transmit channel 18 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE17 ,Transmit channel 17 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE16 ,Transmit channel 16 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0380)==0x0080
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "XCERB,Trasmit channel enable register partition B"
|
|
bitfld.word 0x00 15. " XCE63 ,Transmit channel 63 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE62 ,Transmit channel 62 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE61 ,Transmit channel 61 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE60 ,Transmit channel 60 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE59 ,Transmit channel 59 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE58 ,Transmit channel 58 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE57 ,Transmit channel 57 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE56 ,Transmit channel 56 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE55 ,Transmit channel 55 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE54 ,Transmit channel 54 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE53 ,Transmit channel 53 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE52 ,Transmit channel 52 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE51 ,Transmit channel 51 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE50 ,Transmit channel 50 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE49 ,Transmit channel 49 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE48 ,Transmit channel 48 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0380)==0x0100
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "XCERB,Trasmit channel enable register partition B"
|
|
bitfld.word 0x00 15. " XCE95 ,Transmit channel 95 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE94 ,Transmit channel 94 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE93 ,Transmit channel 93 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE92 ,Transmit channel 92 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE91 ,Transmit channel 91 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE90 ,Transmit channel 90 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE89 ,Transmit channel 89 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE88 ,Transmit channel 88 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE87 ,Transmit channel 87 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE86 ,Transmit channel 86 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE85 ,Transmit channel 85 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE84 ,Transmit channel 84 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE83 ,Transmit channel 83 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE82 ,Transmit channel 82 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE81 ,Transmit channel 81 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE80 ,Transmit channel 80 enable bit" "Disabled,Enabled"
|
|
elif (d.w(AD:0xFFFB1000+0xC)&0x0380)==0x0180
|
|
group.word 0x22++0x01
|
|
line.word 0x00 "XCERB,Trasmit channel enable register partition B"
|
|
bitfld.word 0x00 15. " XCE127 ,Transmit channel 127 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE126 ,Transmit channel 126 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE125 ,Transmit channel 125 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE124 ,Transmit channel 124 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE123 ,Transmit channel 123 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE122 ,Transmit channel 122 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE121 ,Transmit channel 121 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE120 ,Transmit channel 120 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE119 ,Transmit channel 119 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE118 ,Transmit channel 118 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE117 ,Transmit channel 117 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE116 ,Transmit channel 116 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE115 ,Transmit channel 115 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE114 ,Transmit channel 114 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE113 ,Transmit channel 113 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE112 ,Transmit channel 112 enable bit" "Disabled,Enabled"
|
|
endif
|
|
if ((d.w(AD:0xFFFB1000+0xC)&0x0200)==0x0200)&&((d.w(AD:0xFFFB1000+0xC)&0x0003)!=0x0000)
|
|
group.word 0x2A++0x13
|
|
line.word 0x00 "XCERC,Trasmit channel enable register partition C"
|
|
bitfld.word 0x00 15. " XCE47 ,Transmit channel 47 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " XCE46 ,Transmit channel 46 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " XCE45 ,Transmit channel 45 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " XCE44 ,Transmit channel 44 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " XCE43 ,Transmit channel 43 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " XCE42 ,Transmit channel 42 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " XCE41 ,Transmit channel 41 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " XCE40 ,Transmit channel 40 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " XCE39 ,Transmit channel 39 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " XCE38 ,Transmit channel 38 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " XCE37 ,Transmit channel 37 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " XCE36 ,Transmit channel 36 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " XCE35 ,Transmit channel 35 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " XCE34 ,Transmit channel 34 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " XCE33 ,Transmit channel 33 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " XCE32 ,Transmit channel 32 enable bit" "Disabled,Enabled"
|
|
line.word 0x02 "XCERD,Trasmit channel enable register partition D"
|
|
bitfld.word 0x02 15. " XCE63 ,Transmit channel 63 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 14. " XCE62 ,Transmit channel 62 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 13. " XCE61 ,Transmit channel 61 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 12. " XCE60 ,Transmit channel 60 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 11. " XCE59 ,Transmit channel 59 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " XCE58 ,Transmit channel 58 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 9. " XCE57 ,Transmit channel 57 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " XCE56 ,Transmit channel 56 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 7. " XCE55 ,Transmit channel 55 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " XCE54 ,Transmit channel 54 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " XCE53 ,Transmit channel 53 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " XCE52 ,Transmit channel 52 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 3. " XCE51 ,Transmit channel 51 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 2. " XCE50 ,Transmit channel 50 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " XCE49 ,Transmit channel 49 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " XCE48 ,Transmit channel 48 enable bit" "Disabled,Enabled"
|
|
line.word 0x08 "XCERE,Trasmit channel enable register partition E"
|
|
bitfld.word 0x08 15. " XCE79 ,Transmit channel 79 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 14. " XCE78 ,Transmit channel 78 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 13. " XCE77 ,Transmit channel 77 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 12. " XCE76 ,Transmit channel 76 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 11. " XCE75 ,Transmit channel 75 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 10. " XCE74 ,Transmit channel 74 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 9. " XCE73 ,Transmit channel 73 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 8. " XCE72 ,Transmit channel 72 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 7. " XCE71 ,Transmit channel 71 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 6. " XCE70 ,Transmit channel 70 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 5. " XCE69 ,Transmit channel 69 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 4. " XCE68 ,Transmit channel 68 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x08 3. " XCE67 ,Transmit channel 67 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 2. " XCE66 ,Transmit channel 66 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 1. " XCE65 ,Transmit channel 65 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x08 0. " XCE64 ,Transmit channel 64 enable bit" "Disabled,Enabled"
|
|
line.word 0x0A "XCERF,Trasmit channel enable register partition F"
|
|
bitfld.word 0x0A 15. " XCE95 ,Transmit channel 95 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 14. " XCE94 ,Transmit channel 94 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 13. " XCE93 ,Transmit channel 93 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 12. " XCE92 ,Transmit channel 92 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0A 11. " XCE91 ,Transmit channel 91 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 10. " XCE90 ,Transmit channel 90 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 9. " XCE89 ,Transmit channel 89 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 8. " XCE88 ,Transmit channel 88 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0A 7. " XCE87 ,Transmit channel 87 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 6. " XCE86 ,Transmit channel 86 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 5. " XCE85 ,Transmit channel 85 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 4. " XCE84 ,Transmit channel 84 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0A 3. " XCE83 ,Transmit channel 83 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 2. " XCE82 ,Transmit channel 82 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 1. " XCE81 ,Transmit channel 81 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x0A 0. " XCE80 ,Transmit channel 80 enable bit" "Disabled,Enabled"
|
|
line.word 0x10 "XCERG,Trasmit channel enable register partition G"
|
|
bitfld.word 0x10 15. " XCE111 ,Transmit channel 111 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 14. " XCE110 ,Transmit channel 110 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 13. " XCE109 ,Transmit channel 109 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 12. " XCE108 ,Transmit channel 108 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x10 11. " XCE107 ,Transmit channel 107 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 10. " XCE106 ,Transmit channel 106 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 9. " XCE105 ,Transmit channel 105 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 8. " XCE104 ,Transmit channel 104 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x10 7. " XCE103 ,Transmit channel 103 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 6. " XCE102 ,Transmit channel 102 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 5. " XCE101 ,Transmit channel 101 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 4. " XCE100 ,Transmit channel 100 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x10 3. " XCE99 ,Transmit channel 99 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 2. " XCE98 ,Transmit channel 98 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 1. " XCE97 ,Transmit channel 97 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x10 0. " XCE96 ,Transmit channel 96 enable bit" "Disabled,Enabled"
|
|
line.word 0x12 "XCERH,Trasmit channel enable register partition H"
|
|
bitfld.word 0x12 15. " XCE127 ,Transmit channel 127 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 14. " XCE126 ,Transmit channel 126 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 13. " XCE125 ,Transmit channel 125 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 12. " XCE124 ,Transmit channel 124 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x12 11. " XCE123 ,Transmit channel 123 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 10. " XCE122 ,Transmit channel 122 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 9. " XCE121 ,Transmit channel 121 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 8. " XCE120 ,Transmit channel 120 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x12 7. " XCE119 ,Transmit channel 119 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 6. " XCE118 ,Transmit channel 118 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 5. " XCE117 ,Transmit channel 117 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 4. " XCE116 ,Transmit channel 116 enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x12 3. " XCE115 ,Transmit channel 115 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 2. " XCE114 ,Transmit channel 114 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 1. " XCE113 ,Transmit channel 113 enable bit" "Disabled,Enabled"
|
|
bitfld.word 0x12 0. " XCE112 ,Transmit channel 112 enable bit" "Disabled,Enabled"
|
|
else
|
|
group.word 0x2A++0x13
|
|
hide.word 0x00 "XCERC,Trasmit channel enable register partition C"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x02 "XCERD,Trasmit channel enable register partition D"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x08 "XCERE,Trasmit channel enable register partition E"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x0A "XCERF,Trasmit channel enable register partition F"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x10 "XCERG,Trasmit channel enable register partition G"
|
|
textline " "
|
|
textline " "
|
|
textline " "
|
|
hide.word 0x12 "XCERH,Trasmit channel enable register partition H"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
base AD:0xFFFB3800
|
|
width 0x0D
|
|
tree "I2C Interface"
|
|
rgroup.word 0x0000++0x01
|
|
line.word 0x00 "I2C_REV,Identification Register Bit Description"
|
|
bitfld.word 0x00 04.--07. " REV_MAJOR ,Revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 00.--03. " REV_MINOR ,Revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.word 0x0004++0x01
|
|
line.word 0x00 "I2C_IE,Interrupt Enable Register"
|
|
bitfld.word 0x00 05. " GC_IE ,General call interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 04. " XRDY_IE ,Transmit data ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 03. " RRDY_IE ,Receive data ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 02. " ARDY_IE ,Register access ready interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 01. " NACK_IE ,No acknowledgment interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 00. " AL_IE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
group.word 0x0008++0x01
|
|
line.word 0x00 "I2C_STAT,Status Register"
|
|
bitfld.word 0x00 15. " SBD ,Single byte data" "No action,Valid read"
|
|
bitfld.word 0x00 12. " BB ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x00 11. " ROVR ,Receive overrun" "No overrun,Overrun"
|
|
bitfld.word 0x00 10. " XUDF ,Transmit underflow" "No undeflow,Underflowed"
|
|
textline " "
|
|
bitfld.word 0x00 09. " AAS ,Address as slave" "No action,Slave"
|
|
eventfld.word 0x00 05. " GC ,General call" "No action,Called"
|
|
textline " "
|
|
eventfld.word 0x00 04. " XRDY ,Transmit data ready" "Not ready,Ready"
|
|
eventfld.word 0x00 03. " RRDY ,Receive data ready" "Not ready,Ready"
|
|
textline " "
|
|
eventfld.word 0x00 02. " ARDY ,Register access ready" "No action,Ready"
|
|
eventfld.word 0x00 01. " NACK ,No acknowledgment interrupt" "No interrupt,Interrupt"
|
|
textline " "
|
|
eventfld.word 0x00 00. " AL ,Arbitration lost interrupt" "No interrupt,Interrupt"
|
|
rgroup.word (0x0010)++0x01
|
|
line.word 0x00 "I2C_SYSS,System Status Register"
|
|
bitfld.word 0x00 00. " RESETDONE ,Internal reset monitoring" "Not done,Done"
|
|
group.word (0x0014)++0x01
|
|
line.word 0x00 "I2C_BUF,Buffer Configuration Register"
|
|
bitfld.word 0x00 15. " RDMA_EN ,Receive DMA channel enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 07. " XDMA_EN ,Transmit DMA channel enable" "Disabled,Enabled"
|
|
if (((data.word(AD:0xFFFB3800+0x24))&0x0400)==0)
|
|
group.word (0x0018)++0x01
|
|
hide.word 0x00 "I2C_CNT,Data Counter Register"
|
|
else
|
|
group.word (0x0018)++0x01
|
|
line.word 0x00 "I2C_CNT,Data Counter Register"
|
|
hexmask.word 0x00 00.--15. 1. " DCOUNT ,Data count"
|
|
endif
|
|
hgroup.word (0x001C)++0x01
|
|
hide.word 0x00 "I2C_DATA,Data Access Register"
|
|
in
|
|
group.word (0x0020)++0x01
|
|
line.word 0x00 "I2C_SYSC,I2C System Configuration Register"
|
|
bitfld.word 0x00 01. " SRST ,Soft reset" "No reset,Reset"
|
|
if (((data.word(AD:0xFFFB3800+0x24))&0x0400)==0)
|
|
group.word (0x0024)++0x01
|
|
line.word 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " BE ,Big endian mode" "Little,Big"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 08. " XA ,Expand address" "7-bit,10-bit"
|
|
else
|
|
group.word (0x0024)++0x01
|
|
line.word 0x00 "I2C_CON,I2C Configuration Register"
|
|
bitfld.word 0x00 15. " I2C_EN ,I2C module enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " BE ,Big endian mode" "Little,Big"
|
|
bitfld.word 0x00 10. " MST ,Master/slave mode" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 08. " XA ,Expand address" "7-bit,10-bit"
|
|
bitfld.word 0x00 11. " STB ,Start byte mode" "Normal,Start byte"
|
|
bitfld.word 0x00 09. " TRX ,Transmitter/Receiver mode" "Receiver,Transmitter"
|
|
textline " "
|
|
bitfld.word 0x00 01. " STP ,Stop condition" "Not stopped,Stopped"
|
|
bitfld.word 0x00 00. " STT ,Start condition" "Not started,Started"
|
|
endif
|
|
if (((data.word(AD:0xFFFB3800+0x24))&0x0100)==0x0)
|
|
group.word 0x0028++0x01
|
|
line.word 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.word.byte 0x00 00.--06. 1. " OA ,Own address"
|
|
group.word 0x002c++0x01
|
|
line.word (0x00) "I2C_SA,I2C Slave Address Register"
|
|
hexmask.word.byte (0x00) 00.--06. 1. " SA ,Slave address"
|
|
else
|
|
group.word (0x0028)++0x09
|
|
line.word 0x00 "I2C_OA,I2C Own Address Register"
|
|
hexmask.word 0x00 00.--09. 1. " OA ,Own address"
|
|
group.word 0x002C++0x01
|
|
line.word (0x00) "I2C_SA,I2C Slave Address Register"
|
|
hexmask.word (0x00) 00.--09. 1. " SA ,Slave address"
|
|
endif
|
|
group.word (0x0030)++0x01
|
|
line.word 0x00 "I2C_PSC,I2C Clock Prescaler Register"
|
|
hexmask.word.byte 0x00 00.--07. 1. " PSC ,Prescale sampling clock divider value"
|
|
group.word 0x0034++0x01
|
|
line.word (0x00) "I2C_SCLL,I2C SCL Low Time Control Register"
|
|
hexmask.word.byte (0x00) 00.--07. 1. " SCLL ,SCL low time"
|
|
group.word 0x0038++0x01
|
|
line.word (0x00) "I2C_SCLH,I2C SCL High Time Control Register"
|
|
hexmask.word.byte (0x00) 00.--07. 1. " SCLH ,SCL high time"
|
|
group (0x003C)++0x01
|
|
line.word (0x00) "I2C_SYSTEST,System Test Register"
|
|
bitfld.word (0x00) 15. " ST_EN ,System test enable" "Disabled,Enabled"
|
|
bitfld.word (0x00) 14. " FREE ,Free running mode" "Disabled,Enabled"
|
|
bitfld.word (0x00) 12.--13. " TMODE ,Test mode select" "Functional,Reserved,Test SCL counters,Loop-back/SDA-SCL IO"
|
|
textline " "
|
|
bitfld.word (0x00) 11. " SSB ,Set status bits" "No action,Set"
|
|
bitfld.word (0x00) 03. " SCL_I ,SCL line sense input value" "Low,High"
|
|
bitfld.word (0x00) 02. " SCL_O ,SCL line drive output value" "Low,Hi-Z"
|
|
textline " "
|
|
bitfld.word (0x00) 01. " SDA_I ,SDA line sense input value" "Low,High"
|
|
bitfld.word (0x00) 00. " SDA_O ,SDA line drive output value" "Low,Hi-Z"
|
|
tree.end
|
|
base AD:0xFFFBC400
|
|
tree "32-kHz Synchronized Timer"
|
|
width 0x13
|
|
rgroup.word (0x0000*1)++0x01
|
|
line.word 0x00 "32KSYNCNT_REV_LSW,Identification Register"
|
|
bitfld.word 0x00 04.--07. " CID_REV_MAJOR ,Module revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 00.--03. " CID_REV_MINOR ,Module revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (0x0002*1)++0x01
|
|
line.word 0x00 "32KSYNCNT_REV_MSW,Identification Register"
|
|
bitfld.word 0x00 04.--07. " CID_REV_MAJOR ,Module revision number (major)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 00.--03. " CID_REV_MINOR ,Module revision number (minor)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.word (0x0010*1)++0x05
|
|
line.word 0x00 "CR_LSW,Read Counter Register"
|
|
hexmask.word.word 0x00 00.--15. 1. " COUNTER_LO ,Value of 32-kHz SYNCH counter (LSB)"
|
|
rgroup (0x0012*1)++0x01
|
|
line.word 0x00 "CR_MSW,Read Counter Register"
|
|
hexmask.word.word 0x00 00.--15. 1. " COUNTER_HI ,Value of 32-kHz SYNCH counter (MSB)"
|
|
tree.end
|
|
base AD:0xFFFCF000
|
|
tree "MPU Shared Mailbox Registers"
|
|
width 15.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "MPU2DSP1A,MPU to DSP Mailbox 1A"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "MPU2DSP1B,MPU to DSP Mailbox 1B"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "DSP2MPU1A,DSP to MPU Mailbox 1A"
|
|
rgroup.word 0x0c++0x01
|
|
line.word 0x00 "DSP2MPU1B,DSP to MPU Mailbox 1B"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "DSP2MPU2A,DSP to MPU Mailbox 2A"
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "DSP2MPU2B,DSP to MPU Mailbox 2B"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "MPU2DSP1_FLAG,MPU to DSP Mailbox 1 Flag"
|
|
bitfld.word 0x00 0. " INT ,Interrupt pending" "No interrupt,Interrupt"
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "MPU2DSP2A,MPU to DSP Mailbox 2A"
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "MPU2DSP2B,MPU to DSP Mailbox 2B"
|
|
rgroup 0x2C++0x1
|
|
line.word 0x00 "MPU2DSP2_FLAG,MPU to DSP Mailbox 2 Flag"
|
|
bitfld.word 0x00 0. " INT ,Interrupt pending" "No interrupt,Interrupt"
|
|
tree.end
|
|
tree.end
|
|
tree "MPU Configuration Registers"
|
|
base AD:0xFFFBC800
|
|
tree "MPU TIPB Bus Switch Registers"
|
|
base AD:0xFFFBC800
|
|
width 21.
|
|
group.word (0*(0x020*1))++0x1
|
|
line.word 0x00 "UART1_SSW_MPU_CONF,UART1 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (1*(0x020*1))++0x1
|
|
line.word 0x00 "UART2_SSW_MPU_CONF,UART2 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (2*(0x020*1))++0x1
|
|
line.word 0x00 "UART3_SSW_MPU_CONF,UART3 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (0x90*1)++0x1
|
|
line.word 0x00 "McBSP_SSW_MPU_CONF,McBSP MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (0xA0*1)++0x1
|
|
line.word 0x00 "I2C_SSW_MPU_CONF,I2C MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (0xB0*1)++0x1
|
|
line.word 0x00 "SPI_SSW_MPU_CONF,SPI MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word ((0x0C0*1)+(0*(0x10*1)))++0x1
|
|
line.word 0x00 "TIMER1_SSW_MPU_CONF,TIMER1 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word ((0x0C0*1)+(1*(0x10*1)))++0x1
|
|
line.word 0x00 "TIMER2_SSW_MPU_CONF,TIMER2 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word ((0x0C0*1)+(2*(0x10*1)))++0x1
|
|
line.word 0x00 "TIMER3_SSW_MPU_CONF,TIMER3 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word ((0x0C0*1)+(3*(0x10*1)))++0x1
|
|
line.word 0x00 "TIMER4_SSW_MPU_CONF,TIMER4 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word ((0x0C0*1)+(4*(0x10*1)))++0x1
|
|
line.word 0x00 "TIMER5_SSW_MPU_CONF,TIMER5 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word ((0x0C0*1)+(5*(0x10*1)))++0x1
|
|
line.word 0x00 "TIMER6_SSW_MPU_CONF,TIMER6 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (0x130*1)++0x1
|
|
line.word 0x00 "TIMER7_SSW_MPU_CONF,TIMER7 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (0x140*1)++0x1
|
|
line.word 0x00 "TIMER8_SSW_MPU_CONF,TIMER8 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
width 21.
|
|
group.word (0x160*1)++0x1
|
|
line.word 0x00 "MMCSD2_SSW_MPU_CONF,MMCSD2 MPU Static Switch Configuration Register"
|
|
bitfld.word 0x00 01. " DSP_SWITCH ,DSP TIPB bridge access" "Not required,Required"
|
|
bitfld.word 0x00 00. " MPU_SWITCH ,MPU TIPB bridge access" "Not required,Required"
|
|
tree.end
|
|
base AD:0xFFFE0800
|
|
tree "Ultra Low-Power Device Peripheral Registers"
|
|
width 24.
|
|
rgroup.word 0x00++0x1
|
|
line.word 0x00 "COUNTER_32_LSB,ULPD 32-kHz Counter Register LSB"
|
|
hexmask.word 0x00 0.--15. 1. " COUNTER_SLEEP_CLK_LSB ,Lower value of the number of sleep clock cycles during gauging time"
|
|
rgroup.word 0x4++0x1
|
|
line.word 0x0 "COUNTER_32_MSB,ULPD 32-kHz Counter Register MSB"
|
|
hexmask.word 0x0 0.--3. 1. " COUNTER_32_MSB ,Upper value of the number of 32-kHz clock cycles during gauging time"
|
|
rgroup.word 0x8++0x1
|
|
line.word 0x0 "COUNTER_HIGH_FREQ_LSB,ULPD High-Frequency Counter LSB"
|
|
hexmask.word 0x0 0.--15. 1. " COUNTER_HIGH_FREQ_LSB ,Lower value of the number of high-frequency clock during gauging time"
|
|
rgroup.word 0xC++0x1
|
|
line.word 0x0 "COUNTER_HIGH_FREQ_MSB,ULPD High-Frequency COunter MSB"
|
|
hexmask.word 0x0 0.--5. 1. " COUNTER_HIGH_FREQ_MSB ,Upper value of high-frequency clock during gauging time"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "GAUGING_CTRL_REG,ULPD Gauging Control Register"
|
|
bitfld.word 0x00 1. " SELECT_HI_FREQ_CLOCK ,Select the high-frequency clock" "12-MHz,Auxiliary"
|
|
bitfld.word 0x00 0. " GAUGING_EN ,Enable gauging" "Stopped,Running"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "IT_STATUS_REG,ULPD Interrupt Status Register"
|
|
bitfld.word 0x00 3. " IT_WAKEUP_USB ,Wake-up interrupt from USB W2FC" "No,Yes"
|
|
bitfld.word 0x00 2. " OVERFLOW_32 ,An overflow occured on the 32-kHz counter during gauging" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 1. " OVERFLOW_HI_FREQ ,An overflow occured on the hi_freq counter during gauging versus high-frequency clock" "No,Yes"
|
|
bitfld.word 0x00 0. " IT_GAUGING ,To inform CPU that gauging is stopped and high-and-low-frequency registers can be read" "No,Yes"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "SETUP_ANALOG_CELL3_REG,Setup Analog Cell3 ULPD1 Register"
|
|
hexfld.word 0x00 " SETUP_ANALOG_CELL3 ,Setup time of analog cell3 in number of sleep clock cycles"
|
|
group.word 0x28++0x1
|
|
line.word 0x0 "SETUP_ANALOG_CELL2_REG,Setup Analog Cell2 ULPD1 Register"
|
|
hexfld.word 0x0 " SETUP_ANALOG_CELL2 ,Setup time of analog cell2 in number of sleep clock cycles"
|
|
group.word 0x2C++0x1
|
|
line.word 0x0 "SETUP_ANALOG_CELL1_REG,Setup Analog Cell1 ULPD1 Register"
|
|
hexfld.word 0x0 " SETUP_ANALOG_CELL1 ,Setup time of analog cell1 in number of sleep clock cycles"
|
|
group.word 0x30++0x1
|
|
line.word 0x0 "CLOCK_CTRL_REG,ULPD Clock Control Register"
|
|
bitfld.word 0x0 5. " DIS_USB_PVCI_CLK ,Disable USB W2FC PVCI clock" "Enabled,Disabled"
|
|
bitfld.word 0x0 4. " USB_MCLK_EN ,Enable USB hub clock output" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 3. " TI_RESERVED_EN ,Enable clock on SYS_CLK_OUT output" "Disabled,Enabled"
|
|
bitfld.word 0x0 2. " SDW_MCLK_INV ,Select BLUETOOTH_CLK inactive state" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x0 1. " COM_MCLK_INV ,Select Modem clock inactive state" "Low,High"
|
|
bitfld.word 0x0 0. " MODEM_32K_EN ,Enable sleep clock on UART" "Disabled,Enabled"
|
|
group.word 0x34++0x1
|
|
line.word 0x0 "SOFT_REQ_REG,Software Request Register"
|
|
bitfld.word 0x0 15. " SOFT_CLOCK2_DPLL_REQ ,PLL software request reserved for future use" "Inactive,Active"
|
|
bitfld.word 0x0 14. " SOFT_CLOCK1_DPLL_REQ ,PLL software reserved for future use" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 13. " SOFT_MMC_DPLL_REQ ,ULPD_PLL clock request for MMC2" "Inactive,Active"
|
|
bitfld.word 0x0 12. " SOFT_MMC_DPLL_REQ ,Software ULPD_PLL request for MMC" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 11. " SOFT_UART3_DPLL_REQ ,Software UART3 ULPD_PLL" "Inactive,Active"
|
|
bitfld.word 0x0 10. " SOFT_UART2_DPLL_REQ ,Software UART2 ULPD_PLL" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 9. " SOFT_UART1_DPLL_REQ ,Software UART1 ULPD_PLL" "Inactive,Active"
|
|
bitfld.word 0x0 8. " SOFT_USB_OTG_DPLL_REQ ,Software request for USB OTG for ULPD_PLL clock" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 7. " SOFT_CAM_DPLL_MCKO_REQ ,Software camera ULPD_PLL request" "Inactive,Active"
|
|
bitfld.word 0x0 6. " SOFT_COM_MCKO_REQ ,Software request for COM_MCKO clock" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 5. " SOFT_PERIPH_/REQ ,Software system clock request for UART2" "Inactive,Active"
|
|
bitfld.word 0x0 4. " USB_REQ_EN ,Enable USB client hardware DPLL request" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0 3. " SOFT_USB_REQ ,Software system clock request for USB host" "Inactive,Active"
|
|
bitfld.word 0x0 2. " SOFT_SDW_REQ ,Software system clock request for Bluetooth" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 1. " SOFT_COM_REQ ,Software system clock request for com processor" "Inactive,Active"
|
|
bitfld.word 0x0 0. " SOFT_DPLL_REQ ,Software ULPD_PLL clock request" "Inactive,Active"
|
|
group.word 0x38++0x1
|
|
line.word 0x0 "COUNTER_32_FIQ_REG,ULPD Modem Shutdown Delay Register"
|
|
hexfld.byte 0x0 " COUNTER_32_FIQ ,Number of 32-kHz clock cycles to delay active modem shutdown signal after receiving FIQ"
|
|
group.word 0x3C++0x1
|
|
line.word 0x0 "DPLL_CTRL_REG,ULPD USB DPLL Control Register"
|
|
rgroup.word 0x42++0x1
|
|
line.word 0x0 "STATUS_REQ_REG,ULPD Hardware Request Status Register"
|
|
bitfld.word 0x0 15. " CLOCK3_DPLL_REQ ,ULPD_PLL clock request form request RESERVED3" "Inactive,Active"
|
|
bitfld.word 0x0 14. " CLOCK2_DPLL_REQ ,ULPD_PLL clock request from request RESERVED2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 13. " CLOCK1_DPLL_REQ ,ULPD_PLL clock request from request RESERVED1" "Inactive,Active"
|
|
bitfld.word 0x0 12. " MMC_DPLL_REQ ,ULPD_PLL clock request from MMC" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 11. " UART3_DPLL_REQ ,ULPD_PLL clock request from UART3" "Inactive,Active"
|
|
bitfld.word 0x0 10. " UART2_DPLL_REQ ,ULPD_PLL clock request from UART2" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 9. " UART1_DPLL_REQ ,ULPD_PLL clock request from UART1" "Inactive,Active"
|
|
bitfld.word 0x0 8. " USB_HOST_DPLL_REQ ,ULPD_PLL clock requets from USB host" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 7. " CAM_DPLL_MCKL_REQ ,ULPD_PLL clock request from camera interface" "Inactive,Active"
|
|
bitfld.word 0x0 6. " USB_DPLL_MCLK_REQ ,ULPD_PLL clock request from USB client" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 5. " USB_MCLK_REQ ,Hardware system clock request by USB client" "Inactive,Active"
|
|
bitfld.word 0x0 4. " SDW_MCLK_REQ ,Hardware system clock request from Bluetooth" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x0 3. " COM_MCLK_REQ ,System clock request from com processor" "Inactive,Active"
|
|
bitfld.word 0x0 2. " PERIPH_/REQ ,System clock request from UART2" "Active,Inactive"
|
|
textline " "
|
|
bitfld.word 0x0 1. " WAKEUP_/REQ ,System clock request from OMAP" "Active,Inactive"
|
|
bitfld.word 0x0 0. " CHIP_IDLE ,Sleep request received from OMAP" "Inactive,Active"
|
|
group.word 0x44++0x1
|
|
line.word 0x00 "PLL_DIV_REG ,PLL Division Register"
|
|
hexmask.word.word 0x00 0.--15. 2. " PLL_DIV_FACTOR ,PLL clk out division factor. Bypassed if programmed value is 0"
|
|
group.word 0x48++0x1
|
|
line.word 0x0 "LOCK_TIME_REG,ULPD APLL Lock Time Register"
|
|
group.word 0x4C++0x1
|
|
line.word 0x0 "APLL_CTRL_REG,ULPD APLL Control Register"
|
|
bitfld.word 0x0 15. " LOCK STATUS ,Gives the lock status of the module that provides the high frequency clock" "Unlocked,Locked"
|
|
bitfld.word 0x0 0.--2. " PLL_CONTROL ,Select the APLL mode" "19.2 MHz,Reserved,13 MHz,12 MHz,?..."
|
|
group.word 0x50++0x1
|
|
line.word 0x0 "POWER_CTRL_REG,ULPD Power Control Register"
|
|
bitfld.word 0x0 12. " ISOLATION_CONTROL ,Electrical isolation" "Inactive,Active"
|
|
bitfld.word 0x0 11. " MIN_MAX_REG ,Select the operation voltage" "Nominal,Minimum"
|
|
textline " "
|
|
bitfld.word 0x0 10. " DVS_ENABLE ,Enable DVS feature" "Disabled,Enabled"
|
|
bitfld.word 0x0 9. " OSC_STOP_EN ,Stop the oscillator in deep sleep mode" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x0 7.--8. " LDO_CTRL_EN+SOFT_LDO_SLEEP ,Control the sleep of the e-LDO that supplies the DPLL" "Not in sleep,Power down,Active state,Active state"
|
|
bitfld.word 0x0 6. " LDO_STEADY ,Stability of LDO output voltage status" "Not stable,Stable"
|
|
textline " "
|
|
bitfld.word 0x0 4. " DEEP_SLEEP_TRANSITION_EN ,Allow transition to deep sleep mode" "Forbidden,Allowed"
|
|
bitfld.word 0x0 3. " SW_/SHUTDOWN ,Software generation of RST_HOST_OUT - Force RST_HOST_OUT to low" "Yes,No"
|
|
textline " "
|
|
bitfld.word 0x0 2. " SW_/SHUTDOWN_RST ,Allow to deactivate the output RST_HOST_OUT" "No,Yes"
|
|
bitfld.word 0x0 1. " LOW_PWR_REQ ,Low-power software request - Force the LOW_PWR siganl to active state" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x0 0. " LOW_PWR_EN ,Enable low-power feature" "Disabled,Enabled"
|
|
rgroup.word 0x54++0x1
|
|
line.word 0x00 "STATUS_REQ_REG2 ,Status Request Register 2"
|
|
bitfld.word 0x00 0. " MMC_DPLL_REQ ,Status of the MMC2_PLL_REQ" "Inactive,Active"
|
|
rgroup.word 0x58++0x1
|
|
line.word 0x0 "SLEEP_STATUS,Sleep Status Register"
|
|
bitfld.word 0x0 1. " BIG_SLEEP ,Waking up big sleep" "Sleeping,Waking"
|
|
bitfld.word 0x0 0. " DEEP_SLEEP ,Waking up from deep sleep" "Sleeping,Waking"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "SETUP_ANALOG_CELL4_REG,Setup Analog Cell4 ULPD1 Register"
|
|
hexfld.word 0x00 " SETUP_ANALOG_CELL4 ,Setup time of analog cell4 in number of sleep clock cycles"
|
|
group.word 0x60++0x1
|
|
line.word 0x0 "SETUP_ANALOG_CELL5_REG,Setup Analog Cell5 ULPD1 Register"
|
|
hexfld.word 0x0 " SETUP_ANALOG_CELL5 ,Setup time of analog cell5 in number of sleep clock cycles"
|
|
group.word 0x64++0x1
|
|
line.word 0x0 "SETUP_ANALOG_CELL6_REG,Setup Analog Cell6 ULPD1 Register"
|
|
hexfld.word 0x0 " SETUP_ANALOG_CELL6 ,Setup time of analog cell6 in number of sleep clock cycles"
|
|
group.word 0x68++0x1
|
|
line.word 0x0 "SOFT_DISABLE_REQ_REG,Software Disable Request Register"
|
|
bitfld.word 0x0 14. " DIS_CLOCK3_DPLL_REQ ,Disable for the PLL hardware request reserved (CLOCK3_DPLL_REQ)" "Enabled,Disabled"
|
|
bitfld.word 0x0 13. " DIS_CLOCK2_DPLL_REQ ,Disable for the PLL hardware request reserved (CLOCK2_DPLL_REQ)" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 12. " DIS_CLOCK1_DPLL_REQ ,Disable for the PLL hardware request reserved (CLOCK1_DPLL_REQ)" "Enabled,Disabled"
|
|
bitfld.word 0x0 11. " DIS_MMC2_DPLL_REQ ,Disable for hardware request MMC_DPLL_REQ" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 10. " DIS_MMC_DPLL_REQ ,Disable the current hardware request if active" "Enabled,Disabled"
|
|
bitfld.word 0x0 9. " DIS_UART3_DPLL_REQ ,Disable hardware request for UART3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 8. " DIS_UART2_DPLL_REQ ,Disable hardware request for UART2" "Enabled,Disabled"
|
|
bitfld.word 0x0 7. " DIS_UART1_DPLL_REQ ,Disable hardware request for UART1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 6. " DIS_USB_HOST_DPLL_REQ ,Disable the USB host system clock hardware" "Enabled,Disabled"
|
|
bitfld.word 0x0 5. " DIS_CAM_DPLL_MCLK_REQ ,Disable hardware CAM_PLL_MCLK_REQ" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 3. " /DIS_PERIPH_REQ ,Disable hardware /PERIPH_REQ request" "Enabled,Disabled"
|
|
bitfld.word 0x0 1. " DIS_SDW_MCLK_REQ ,Disable SDW_MCLK_REQ if active" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 0. " DIS_COM_MCLK_REQ ,Disable COM_MCLK_REQ and COM_MCKO_SEL if active" "Enabled,Disabled"
|
|
group.word 0x6C++0x1
|
|
line.word 0x0 "RESET_STATUS,Reset Status Register"
|
|
bitfld.word 0x0 3. " 32K_WATCHDOG_TIME_OUT ,A 32-kHz watchdog time-out event has occured" "No,Yes"
|
|
bitfld.word 0x0 2. " SECURITY_VIOLATION ,A security violation evemt has occured" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x0 1. " SECURE_WATCHDOG_TIME_OUT ,A secure watchdog time-out event has occured" "No,Yes"
|
|
bitfld.word 0x0 0. " POWER_ON_RESET ,A /PWRON_RESET has occured" "No,Yes"
|
|
rgroup.word 0x70++0x1
|
|
line.word 0x00 "REVISION_NUMBER,Revision Number Register"
|
|
hexfld.byte 0x00 " REVISION_NUMBER ,Indicates the revision number of the ULPD"
|
|
group.word 0x74++0x1
|
|
line.word 0x00 "SDW_CLK_DIV_CTRL_SEL,SDW Clock Divider Control Select Register"
|
|
bitfld.word 0x00 2.--7. " SDW_RATIO_SEL ,Select the divider ratio to apply to the APLL output clock to generate to generate BCLK" "1,1.5,2,2.5,3,3.5,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,?..."
|
|
bitfld.word 0x00 1. " SDW_ULPD_PLL_CLK_REQ ,BCLK clock software request" "Inactive,Active"
|
|
textline " "
|
|
bitfld.word 0x00 0. " SDW_SYSCLK_PLLCLK_SEL " "APLL output,SYSTEM_CLOCK"
|
|
group.word 0x78++0x1
|
|
line.word 0x0 "COM_CLK_DIV_CTRL_SEL,COM Clock Divider Control Select Register"
|
|
bitfld.word 0x0 2.--7. " COM_RATIO_SEL ,Select the divider ratio to apply to the APLL output clock to generate to generate MCLK" "1,1.5,2,2.5,3,3.5,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,?..."
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bitfld.word 0x0 1. " COM_ULPD_PLL_CLK_REQ ,MCLK clock software request" "Inactive,Active"
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textline " "
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bitfld.word 0x0 0. " COM_SYSCLK_PLLCLK_SEL " "APLL output,SYSTEM_CLOCK"
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group.word 0x7C++0x1
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line.word 0x0 "CAM_CLK_CTRL,CAM Clock Control Register"
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bitfld.word 0x0 2. " SYSTEM_CLK_EN ,Clock enable of the system clock GPIO modules" "Disabled,Enabled"
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bitfld.word 0x0 1. " CAM_CLK_DIV ,Select the division factor for CAM.CLKOUT as a system clock" "1,2"
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textline " "
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bitfld.word 0x0 0. " CAM_CLK_EN ,Enable of the CAM.CLKOUT" "Off,On"
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group.word 0x80++0x1
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line.word 0x0 "SOFT_REQ_REG2,Software Request Register2"
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bitfld.word 0x0 0. " SOFT_CLOCK3_DPLL_REQ ,PLL software request reserved for future use" "Inactive,Active"
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tree.end
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base AD:0xFFFE1000
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tree "OMAP5912 Configuration Registers"
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tree "Functional Multiplexing Control"
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width 18.
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group.long 0x00++0xB
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line.long 0x00 "FUNC_MUX_CTRL_0,Functional Mux Register 0"
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bitfld.long 0x00 31. " CTRL_288_1 ,This bit configures the control mode 288_1 which enables the control of the OMP CHIP_NWAKEUP signal from the RTCK pad" "ULPD,RTCK"
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bitfld.long 0x00 28. " OBS_288_1 ,Enable observation mode" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 20. " LRU_SEL ,This field configures the OMAP traffic controller arbitration algorithm. Select the priority scheme" "LRU,Fixed"
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bitfld.long 0x00 14. " NRESET_ENABLE ,Allows AND gating of outputs with the OMAP CHIP_NRESET_OUT" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 13. " PWR_MASK_IN ,This register enables the Inhibit2 function" "Disabled,Enabled"
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bitfld.long 0x00 12. " PWR_MASK_OUT ,This register enables the Gated2 function" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " BVLZ_MASK_IN ,This register enables the Inhibit1 function" "Disabled,Enabled"
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bitfld.long 0x00 10. " BVLZ_MASK_OUT ,This register enables teh Gated1 function" "Disabled,Enabled"
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line.long 0x04 "FUNC_MUX_CTRL_1,Functional Mux Register 1 (Reserved)"
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line.long 0x08 "FUNC_MUX_CTRL_2,Functional Mux Register 2"
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bitfld.long 0x08 24.--27. " CONF_OBS_MUX_SEL_R ,Sets the parallel observation multiplexing mode" "0,1,2,3,4,5,6,7,8,9,10,?..."
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hexmask.long.byte 0x08 19.--23. 1. " CONF_DSP_DMA_REQ_19 ,Maps DSP DMA_REQUEST for observability"
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textline " "
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hexmask.long.byte 0x08 13.--18. 1. " CONF_ARM_DMA_SEL_REQ31 ,Maps MPU DMA_REQUEST for observability"
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hexmask.long.byte 0x08 7.--12. 1. " CONF_DSP_INT_SEL_R ,Selects the DSP level 2 interrupts to be observed"
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textline " "
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hexmask.long.byte 0x08 0.--6. 1. " CONF_ARM_INT_SEL_R ,Selects the MPU level 2 interrupts to be observed"
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group.long 0x10++0x2B
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line.long 0x0 "FUNC_MUX_CTRL_3,Functional Mux Register 3"
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bitfld.long 0x0 27.--29. " CONF_F19 ,Controls the multiplexing on F19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x0 24.--26. " CONF_H14 ,Controls the multiplexing on H14" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x0 21.--23. " CONF_E20 ,Controls the multiplexing on E20" "000,001,010,011,100,101,110,111"
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bitfld.long 0x0 18.--20. " CONF_E19 ,Controls the multiplexing on E19" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x0 15.--17. " CONF_F18 ,Controls the multiplexing on F18" "000,001,010,011,100,101,110,111"
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bitfld.long 0x0 12.--14. " CONF_D20 ,Controls the multiplexing on D20" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x0 9.--11. " CONF_D19 ,Controls the multiplexing on D19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x0 6.--8. " CONF_E18 ,Controls the multiplexing on E18" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x0 3.--5. " CONF_C21 ,Controls the multiplexing on C21" "000,001,010,011,100,101,110,111"
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bitfld.long 0x0 0.--2. " CONF_G19 ,Controls the multiplexing on G19" "000,001,010,011,100,101,110,111"
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line.long 0x4 "FUNC_MUX_CTRL_4,Functional Mux Register 4"
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bitfld.long 0x4 27.--29. " CONF_J18 ,Controls the multiplexing on J18" "000,001,010,011,100,101,110,111"
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bitfld.long 0x4 24.--26. " CONF_J15 ,Controls the multiplexing on J15" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x4 21.--23. " CONF_H19 ,Controls the multiplexing on H19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x4 18.--20. " CONF_H20 ,Controls the multiplexing on H20" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x4 15.--17. " CONF_H18 ,Controls the multiplexing on H18" "000,001,010,011,100,101,110,111"
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bitfld.long 0x4 12.--14. " CONF_H15 ,Controls the multiplexing on H15" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x4 9.--11. " CONF_G21 ,Controls the multiplexing on G21" "000,001,010,011,100,101,110,111"
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bitfld.long 0x4 6.--8. " CONF_G20 ,Controls the multiplexing on G20" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x4 0.--2. " CONF_G18 ,Controls the multiplexing on G18" "000,001,010,011,100,101,110,111"
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line.long 0x8 "FUNC_MUX_CTRL_5,Functional Mux Register 5"
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bitfld.long 0x8 27.--29. " CONF_M19 ,Controls the multiplexing on M19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x8 24.--26. " CONF_L15 ,Controls the multiplexing on L15" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x8 21.--23. " CONF_L18 ,Controls the multiplexing on L20" "000,001,010,011,100,101,110,111"
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bitfld.long 0x8 18.--20. " CONF_L19 ,Controls the multiplexing on L19" "000,001,010,011,100,101,110,111"
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textline " "
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|
bitfld.long 0x8 15.--17. " CONF_K14 ,Controls the multiplexing on K14" "000,001,010,011,100,101,110,111"
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bitfld.long 0x8 12.--14. " CONF_K15 ,Controls the multiplexing on K15" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
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bitfld.long 0x8 9.--11. " CONF_K19 ,Controls the multiplexing on K19" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x8 6.--8. " CONF_K18 ,Controls the multiplexing on K18" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x8 3.--5. " CONF_J14 ,Controls the multiplexing on J14" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x8 0.--2. " CONF_J19 ,Controls the multiplexing on J19" "000,001,010,011,100,101,110,111"
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line.long 0xc "FUNC_MUX_CTRL_6,Functional Mux Register 6"
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bitfld.long 0xc 27.--29. " CONF_P20 ,Controls the multiplexing on P20" "000,001,010,011,100,101,110,111"
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bitfld.long 0xc 24.--26. " CONF_P19 ,Controls the multiplexing on P19" "000,001,010,011,100,101,110,111"
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textline " "
|
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bitfld.long 0xc 21.--23. " CONF_M15 ,Controls the multiplexing on M15" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0xc 18.--20. " CONF_N20 ,Controls the multiplexing on N20" "000,001,010,011,100,101,110,111"
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textline " "
|
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bitfld.long 0xc 15.--17. " CONF_N18 ,Controls the multiplexing on N18" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0xc 12.--14. " CONF_N19 ,Controls the multiplexing on N19" "000,001,010,011,100,101,110,111"
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|
textline " "
|
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bitfld.long 0xc 9.--11. " CONF_N21 ,Controls the multiplexing on N21" "000,001,010,011,100,101,110,111"
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bitfld.long 0xc 6.--8. " CONF_M20 ,Controls the multiplexing on M20" "000,001,010,011,100,101,110,111"
|
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textline " "
|
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bitfld.long 0xc 3.--5. " CONF_L14 ,Controls the multiplexing on L14" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0xc 0.--2. " CONF_M18 ,Controls the multiplexing on M18" "000,001,010,011,100,101,110,111"
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line.long 0x10 "FUNC_MUX_CTRL_7,Functional Mux Register 7"
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bitfld.long 0x10 27.--29. " CONF_V20 ,Controls the multiplexing on R19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x10 24.--26. " CONF_T18 ,Controls the multiplexing on T18" "000,001,010,011,100,101,110,111"
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textline " "
|
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bitfld.long 0x10 21.--23. " CONF_U19 ,Controls the multiplexing on U19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x10 18.--20. " CONF_N15 ,Controls the multiplexing on N15" "000,001,010,011,100,101,110,111"
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textline " "
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bitfld.long 0x10 15.--17. " CONF_T19 ,Controls the multiplexing on T19" "000,001,010,011,100,101,110,111"
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bitfld.long 0x10 12.--14. " CONF_T20 ,Controls the multiplexing on T20" "000,001,010,011,100,101,110,111"
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textline " "
|
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bitfld.long 0x10 9.--11. " CONF_R18 ,Controls the multiplexing on R18" "000,001,010,011,100,101,110,111"
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bitfld.long 0x10 6.--8. " CONF_R19 ,Controls the multiplexing on R19" "000,001,010,011,100,101,110,111"
|
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textline " "
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bitfld.long 0x10 3.--5. " CONF_M14 ,Controls the multiplexing on M14" "000,001,010,011,100,101,110,111"
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bitfld.long 0x10 0.--2. " CONF_P18 ,Controls the multiplexing on P18" "000,001,010,011,100,101,110,111"
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line.long 0x14 "FUNC_MUX_CTRL_8,Functional Mux Register 8"
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bitfld.long 0x14 27.--29. " CONF_J20 ,Controls the multiplexing on J20" "000,001,010,011,100,101,110,111"
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bitfld.long 0x14 24.--26. " CONF_W17 ,Controls the multiplexing on W17" "000,001,010,011,100,101,110,111"
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textline " "
|
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bitfld.long 0x14 21.--23. " CONF_V16 ,Controls the multiplexing on V16" "000,001,010,011,100,101,110,111"
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bitfld.long 0x14 18.--20. " CONF_Y12 ,Controls the multiplexing on Y12" "000,001,010,011,100,101,110,111"
|
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textline " "
|
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bitfld.long 0x14 15.--17. " CONF_W19 ,Controls the multiplexing on W19" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x14 12.--14. " CONF_P15 ,Controls the multiplexing on P15" "000,001,010,011,100,101,110,111"
|
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textline " "
|
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bitfld.long 0x14 9.--11. " CONF_N14 ,Controls the multiplexing on N14" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x14 6.--8. " CONF_V19 ,Controls the multiplexing on V19" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
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bitfld.long 0x14 3.--5. " CONF_W21 ,Controls the multiplexing on W21" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x14 0.--2. " CONF_U18 ,Controls the multiplexing on U18" "000,001,010,011,100,101,110,111"
|
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line.long 0x18 "FUNC_MUX_CTRL_9,Functional Mux Register 9"
|
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bitfld.long 0x18 27.--29. " CONF_W15 ,Controls the multiplexing on W15" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x18 24.--26. " CONF_W14 ,Controls the multiplexing on W14" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x18 21.--23. " CONF_Y14 ,Controls the multiplexing on Y14" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x18 18.--20. " CONF_V14 ,Controls the multiplexing on V14" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x18 15.--17. " CONF_R14 ,Controls the multiplexing on R14" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x18 12.--14. " CONF_AA15 ,Controls the multiplexing on AA15" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x18 9.--11. " CONF_AA20 ,Controls the multiplexing on AA20" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x18 6.--8. " CONF_U20 ,Controls the multiplexing on U20" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x18 3.--5. " CONF_W16 ,Controls the multiplexing on W16" "000,001,010,011,100,101,110,111"
|
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bitfld.long 0x18 0.--2. " CONF_W13 ,Controls the multiplexing on W13" "000,001,010,011,100,101,110,111"
|
|
line.long 0x1c "FUNC_MUX_CTRL_A,Functional Mux Register A"
|
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bitfld.long 0x1c 27.--29. " CONF_P11 ,Controls the multiplexing on P11" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x1c 24.--26. " CONF_V10 ,Controls the multiplexing on V10" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x1c 21.--23. " CONF_V11 ,Controls the multiplexing on V11" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x1c 18.--20. " CONF_W10 ,Controls the multiplexing on W10" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x1c 15.--17. " CONF_P13 ,Controls the multiplexing on P13" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x1c 12.--14. " CONF_R13 ,Controls the multiplexing on R13" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x1c 9.--11. " CONF_V15 ,Controls the multiplexing on V15" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x1c 6.--8. " CONF_P14 ,Controls the multiplexing on P14" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x1c 3.--5. " CONF_AA17 ,Controls the multiplexing on AA17" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x1c 0.--2. " CONF_Y15 ,Controls the multiplexing on Y15" "000,001,010,011,100,101,110,111"
|
|
line.long 0x20 "FUNC_MUX_CTRL_B,Functional Mux Register B"
|
|
bitfld.long 0x20 27.--29. " CONF_V8 ,Controls the multiplexing on V8" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x20 24.--26. " CONF_Y8 ,Controls the multiplexing on Y8" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x20 21.--23. " CONF_W8 ,Controls the multiplexing on W8" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x20 18.--20. " CONF_R10 ,Controls the multiplexing on R10" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x20 15.--17. " CONF_V5 ,Controls the multiplexing on V5" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x20 12.--14. " CONF_V9 ,Controls the multiplexing on V9" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x20 9.--11. " CONF_W9 ,Controls the multiplexing on W9" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x20 6.--8. " CONF_AA9 ,Controls the multiplexing on AA9" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x20 3.--5. " CONF_Y10 ,Controls the multiplexing on Y10" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x20 0.--2. " CONF_R11 ,Controls the multiplexing on R11" "000,001,010,011,100,101,110,111"
|
|
line.long 0x24 "FUNC_MUX_CTRL_C,Functional Mux Register C"
|
|
bitfld.long 0x24 27.--29. " CONF_V6 ,Controls the multiplexing on V6" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x24 24.--26. " CONF_W5 ,Controls the multiplexing on W5" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x24 21.--23. " CONF_Y5 ,Controls the multiplexing on Y5" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x24 18.--20. " CONF_R9 ,Controls the multiplexing on R9" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x24 15.--17. " CONF_AA5 ,Controls the multiplexing on AA5" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x24 12.--14. " CONF_W6 ,Controls the multiplexing on W6" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x24 9.--11. " CONF_Y6 ,Controls the multiplexing on Y6" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x24 6.--8. " CONF_V7 ,Controls the multiplexing on V7" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x24 3.--5. " CONF_W7 ,Controls the multiplexing on W7" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x24 0.--2. " CONF_P10 ,Controls the multiplexing on P10" "000,001,010,011,100,101,110,111"
|
|
line.long 0x28 "FUNC_MUX_CTRL_D,Functional Mux Register D"
|
|
bitfld.long 0x28 27.--29. " CONF_G13 ,Controls the multiplexing on G13" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x28 24.--26. " CONF_A17 ,Controls the multiplexing on A17" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x28 21.--23. " CONF_C16 ,Controls the multiplexing on C16" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x28 18.--20. " CONF_D15 ,Controls the multiplexing on D15" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x28 15.--17. " CONF_C15 ,Controls the multiplexing on C15" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x28 12.--14. " CONF_C20 ,Controls the multiplexing on C20" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x28 9.--11. " CONF_B15 ,Controls the multiplexing on B15" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x28 6.--8. " CONF_M4 ,Controls the multiplexing on M4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x28 3.--5. " CONF_W4 ,Controls the multiplexing on W4" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x28 0.--2. " CONF_Y4 ,Controls the multiplexing on Y4" "000,001,010,011,100,101,110,111"
|
|
group.long 0x90++0x13
|
|
line.long 0x00 "FUNC_MUX_CTRL_E,Functional Mux Register E"
|
|
bitfld.long 0x00 27.--29. " CONF_G14 ,Controls the multiplexing on G14" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 24.--26. " CONF_H13 ,Controls the multiplexing on H13" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x00 21.--23. " CONF_A20 ,Controls the multiplexing on A20" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 18.--20. " CONF_B19 ,Controls the multiplexing on B19" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x00 15.--17. " CONF_C18 ,Controls the multiplexing on C18" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 12.--14. " CONF_D17 ,Controls the multiplexing on D17" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " CONF_B18 ,Controls the multiplexing on B18" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 6.--8. " CONF_D16 ,Controls the multiplexing on D16" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " CONF_C17 ,Controls the multiplexing on C17" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x00 0.--2. " CONF_B17 ,Controls the multiplexing on B17" "000,001,010,011,100,101,110,111"
|
|
line.long 0x04 "FUNC_MUX_CTRL_F,Functional Mux Register F"
|
|
bitfld.long 0x04 27.--29. " CONF_V2 ,Controls the multiplexing on V2" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 24.--26. " CONF_U4 ,Controls the multiplexing on U4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " CONF_W1 ,Controls the multiplexing on W1" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 18.--20. " CONF_W2 ,Controls the multiplexing on W2" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " CONF_V4 ,Controls the multiplexing on V4" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 12.--14. " CONF_Y1 ,Controls the multiplexing on Y4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x04 9.--11. " CONF_Y17 ,Controls the multiplexing on Y17" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 6.--8. " CONF_D18 ,Controls the multiplexing on D18" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x04 3.--5. " CONF_B21 ,Controls the multiplexing on B21" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 0.--2. " CONF_C19 ,Controls the multiplexing on C19" "000,001,010,011,100,101,110,111"
|
|
line.long 0x08 "FUNC_MUX_CTRL_10,Functional Mux Register 10"
|
|
bitfld.long 0x08 27.--29. " CONF_M3 ,Controls the multiplexing on M3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x08 24.--26. " CONF_N8 ,Controls the multiplexing on N8" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x08 21.--23. " CONF_N3 ,Controls the multiplexing on N3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x08 18.--20. " CONF_P3 ,Controls the multiplexing on P3" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x08 15.--17. " CONF_W11 ,Controls the multiplexing on W11" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x08 9.--11. " CONF_L4 ,Controls the multiplexing on L4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x08 6.--8. " CONF_L3 ,Controls the multiplexing on L3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x08 3.--5. " CONF_M8 ,Controls the multiplexing on M8" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x08 0.--2. " CONF_M7 ,Controls the multiplexing on M7" "000,001,010,011,100,101,110,111"
|
|
line.long 0x0c "FUNC_MUX_CTRL_11,Functional Mux Register 11"
|
|
bitfld.long 0x0c 24.--26. " CONF_F3 ,Controls the multiplexing on F3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x0c 21.--23. " CONF_G4 ,Controls the multiplexing on G4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x0c 18.--20. " CONF_G3 ,Controls the multiplexing on G3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x0c 15.--17. " CONF_G2 ,Controls the multiplexing on G2" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x0c 12.--14. " CONF_K8 ,Controls the multiplexing on K8" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x0c 9.--11. " CONF_H4 ,Controls the multiplexing on H4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x0c 6.--8. " CONF_H3 ,Controls the multiplexing on H3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x0c 3.--5. " CONF_K7 ,Controls the multiplexing on K7" "000,001,010,011,100,101,110,111"
|
|
line.long 0x10 "FUNC_MUX_CTRL_12,Functional Mux Register 12"
|
|
bitfld.long 0x10 24.--26. " CONF_J8 ,Controls the multiplexing on J8" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 21.--23. " CONF_D3 ,Controls the multiplexing on D3" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x10 18.--20. " CONF_C1 ,Controls the multiplexing on C1" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 15.--17. " CONF_E4 ,Controls the multiplexing on E4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x10 12.--14. " CONF_D2 ,Controls the multiplexing on D2" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 9.--11. " CONF_F4 ,Controls the multiplexing on F4" "000,001,010,011,100,101,110,111"
|
|
textline " "
|
|
bitfld.long 0x10 6.--8. " CONF_E3 ,Controls the multiplexing on E3" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x10 3.--5. " CONF_J7 ,Controls the multiplexing on J7" "000,001,010,011,100,101,110,111"
|
|
tree.end
|
|
tree "Pull-Down Control"
|
|
width 17.
|
|
group.long 0x40++0xF
|
|
line.long 0x00 "PULL_DWN_CTRL_0,Pull-Down Control Register 0"
|
|
bitfld.long 0x00 31. " CONF_PDEN_L14 ,Enables pull-up or pull-down on L14" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " CONF_PDEN_M18 ,Enables pull-up or pull-down on M18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CONF_PDEN_M19 ,Enables pull-up or pull-down on M19" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " CONF_PDEN_L15 ,Enables pull-up or pull-down on L15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CONF_PDEN_L18 ,Enables pull-up or pull-down on L18" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " CONF_PDEN_L19 ,Enables pull-up or pull-down on L19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CONF_PDEN_K14 ,Enables pull-up or pull-down on K14" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " CONF_PDEN_K15 ,Enables pull-up or pull-down on K15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CONF_PDEN_K19 ,Enables pull-up or pull-down on K19" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " CONF_PDEN_K18 ,Enables pull-up or pull-down on K18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CONF_PDEN_J14 ,Enables pull-up or pull-down on J14" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " CONF_PDEN_J19 ,Enables pull-up or pull-down on J19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CONF_PDEN_J18 ,Enables pull-up or pull-down on J18" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " CONF_PDEN_J15 ,Enables pull-up or pull-down on J15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONF_PDEN_H19 ,Enables pull-up or pull-down on H19" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " CONF_PDEN_H20 ,Enables pull-up or pull-down on H20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CONF_PDEN_H18 ,Enables pull-up or pull-down on H18" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " CONF_PDEN_H15 ,Enables pull-up or pull-down on H15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CONF_PDEN_G21 ,Enables pull-up or pull-down on G21" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " CONF_PDEN_G20 ,Enables pull-up or pull-down on G20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CONF_PDEN_G18 ,Enables pull-up or pull-down on G18" "Enabled,Disabled"
|
|
bitfld.long 0x00 9. " CONF_PDEN_F19 ,Enables pull-up or pull-down on F19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CONF_PDEN_H14 ,Enables pull-up or pull-down on H14" "Enabled,Disabled"
|
|
bitfld.long 0x00 7. " CONF_PDEN_E20 ,Enables pull-up or pull-down on E20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CONF_PDEN_E19 ,Enables pull-up or pull-down on E19" "Enabled,Disabled"
|
|
bitfld.long 0x00 5. " CONF_PDEN_F18 ,Enables pull-up or pull-down on F18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CONF_PDEN_D20 ,Enables pull-up or pull-down on D20" "Enabled,Disabled"
|
|
bitfld.long 0x00 3. " CONF_PDEN_D19 ,Enables pull-up or pull-down on D19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CONF_PDEN_E18 ,Enables pull-up or pull-down on E18" "Enabled,Disabled"
|
|
bitfld.long 0x00 1. " CONF_PDEN_C21 ,Enables pull-up or pull-down on C21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONF_PDEN_G19 ,Enables pull-up or pull-down on G19" "Enabled,Disabled"
|
|
line.long 0x04 "PULL_DWN_CTRL_1,Pull Down Control Register 1"
|
|
bitfld.long 0x04 31. " CONF_PDEN_AA20 ,Enables pull-up or pull-down on AA20" "Enabled,Disabled"
|
|
bitfld.long 0x04 30. " CONF_PDEN_U20 ,Enables pull-up or pull-down on U20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 29. " CONF_PDEN_W16 ,Enables pull-up or pull-down on W16" "Enabled,Disabled"
|
|
bitfld.long 0x04 28. " CONF_PDEN_W13 ,Enables pull-up or pull-down on W13" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CONF_PDEN_J20 ,Enables pull-up or pull-down on J20" "Enabled,Disabled"
|
|
bitfld.long 0x04 26. " CONF_PDEN_W17 ,Enables pull-up or pull-down on W17" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 25. " CONF_PDEN_V16 ,Enables pull-up or pull-down on V16" "Enabled,Disabled"
|
|
bitfld.long 0x04 24. " CONF_PDEN_Y12 ,Enables pull-up or pull-down on Y12" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CONF_PDEN_W19 ,Enables pull-up or pull-down on W19" "Enabled,Disabled"
|
|
bitfld.long 0x04 22. " CONF_PDEN_P15 ,Enables pull-up or pull-down on P15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 21. " CONF_PDEN_N14 ,Enables pull-up or pull-down on N14" "Enabled,Disabled"
|
|
bitfld.long 0x04 20. " CONF_PDEN_V19 ,Enables pull-up or pull-down on V19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CONF_PDEN_W21 ,Enables pull-up or pull-down on W21" "Enabled,Disabled"
|
|
bitfld.long 0x04 18. " CONF_PDEN_U18 ,Enables pull-up or pull-down on U18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CONF_PDEN_U19 ,Enables pull-up or pull-down on U19" "Enabled,Disabled"
|
|
bitfld.long 0x04 14. " CONF_PDEN_N15 ,Enables pull-up or pull-down on N15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CONF_PDEN_T19 ,Enables pull-up or pull-down on T19" "Enabled,Disabled"
|
|
bitfld.long 0x04 12. " CONF_PDEN_T20 ,Enables pull-up or pull-down on T20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CONF_PDEN_R18 ,Enables pull-up or pull-down on R18" "Enabled,Disabled"
|
|
bitfld.long 0x04 10. " CONF_PDEN_R19 ,Enables pull-up or pull-down on R19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CONF_PDEN_M14 ,Enables pull-up or pull-down on M14" "Enabled,Disabled"
|
|
bitfld.long 0x04 8. " CONF_PDEN_P18 ,Enables pull-up or pull-down on P18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CONF_PDEN_P20 ,Enables pull-up or pull-down on P20" "Enabled,Disabled"
|
|
bitfld.long 0x04 6. " CONF_PDEN_P19 ,Enables pull-up or pull-down on P19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CONF_PDEN_M15 ,Enables pull-up or pull-down on M15" "Enabled,Disabled"
|
|
bitfld.long 0x04 4. " CONF_PDEN_N20 ,Enables pull-up or pull-down on N20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CONF_PDEN_N18 ,Enables pull-up or pull-down on N18" "Enabled,Disabled"
|
|
bitfld.long 0x04 2. " CONF_PDEN_N19 ,Enables pull-up or pull-down on N19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CONF_PDEN_N21 ,Enables pull-up or pull-down on N21" "Enabled,Disabled"
|
|
bitfld.long 0x04 0. " CONF_PDEN_M20 ,Enables pull-up or pull-down on M20" "Enabled,Disabled"
|
|
line.long 0x08 "PULL_DWN_CTRL_2,Pull Down Control Register 2"
|
|
bitfld.long 0x08 31. " CONF_PDEN_AA5 ,Enables pull-up or pull-down on AA5" "Enabled,Disabled"
|
|
bitfld.long 0x08 30. " CONF_PDEN_W6 ,Enables pull-up or pull-down on W6" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 29. " CONF_PDEN_Y6 ,Enables pull-up or pull-down on Y6" "Enabled,Disabled"
|
|
bitfld.long 0x08 28. " CONF_PDEN_V7 ,Enables pull-up or pull-down on V7" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 27. " CONF_PDEN_W7 ,Enables pull-up or pull-down on W7" "Enabled,Disabled"
|
|
bitfld.long 0x08 26. " CONF_PDEN_P10 ,Enables pull-up or pull-down on P10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 25. " CONF_PDEN_V8 ,Enables pull-up or pull-down on V8" "Enabled,Disabled"
|
|
bitfld.long 0x08 24. " CONF_PDEN_Y8 ,Enables pull-up or pull-down on Y8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 23. " CONF_PDEN_W8 ,Enables pull-up or pull-down on W8" "Enabled,Disabled"
|
|
bitfld.long 0x08 22. " CONF_PDEN_R10 ,Enables pull-up or pull-down on R10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 21. " CONF_PDEN_V5 ,Enables pull-up or pull-down on V5" "Enabled,Disabled"
|
|
bitfld.long 0x08 20. " CONF_PDEN_V9 ,Enables pull-up or pull-down on V9" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CONF_PDEN_W9 ,Enables pull-up or pull-down on W9" "Enabled,Disabled"
|
|
bitfld.long 0x08 18. " CONF_PDEN_AA9 ,Enables pull-up or pull-down on AA9" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 17. " CONF_PDEN_Y10 ,Enables pull-up or pull-down on Y10" "Enabled,Disabled"
|
|
bitfld.long 0x08 16. " CONF_PDEN_R11 ,Enables pull-up or pull-down on R11" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 15. " CONF_PDEN_P11 ,Enables pull-up or pull-down on P11" "Enabled,Disabled"
|
|
bitfld.long 0x08 14. " CONF_PDEN_V10 ,Enables pull-up or pull-down on V10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 13. " CONF_PDEN_V11 ,Enables pull-up or pull-down on V11" "Enabled,Disabled"
|
|
bitfld.long 0x08 12. " CONF_PDEN_W10 ,Enables pull-up or pull-down on W10" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CONF_PDEN_P13 ,Enables pull-up or pull-down on P13" "Enabled,Disabled"
|
|
bitfld.long 0x08 10. " CONF_PDEN_R13 ,Enables pull-up or pull-down on R13" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CONF_PDEN_V15 ,Enables pull-up or pull-down on V15" "Enabled,Disabled"
|
|
bitfld.long 0x08 8. " CONF_PDEN_P14 ,Enables pull-up or pull-down on P14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CONF_PDEN_AA17 ,Enables pull-up or pull-down on AA17" "Enabled,Disabled"
|
|
bitfld.long 0x08 6. " CONF_PDEN_Y15 ,Enables pull-up or pull-down on Y15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CONF_PDEN_W15 ,Enables pull-up or pull-down on W15" "Enabled,Disabled"
|
|
bitfld.long 0x08 4. " CONF_PDEN_W14 ,Enables pull-up or pull-down on W14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CONF_PDEN_Y14 ,Enables pull-up or pull-down on Y14" "Enabled,Disabled"
|
|
bitfld.long 0x08 2. " CONF_PDEN_V14 ,Enables pull-up or pull-down on V14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CONF_PDEN_R14 ,Enables pull-up or pull-down on R14" "Enabled,Disabled"
|
|
bitfld.long 0x08 0. " CONF_PDEN_AA15 ,Enables pull-up or pull-down on AA15" "Enabled,Disabled"
|
|
line.long 0x0c "PULL_DWN_CTRL_3,Pull Down Control Register 3"
|
|
bitfld.long 0x0c 31. " CONF_PDEN_W2 ,Enables pull-up or pull-down on W2" "Enabled,Disabled"
|
|
bitfld.long 0x0c 30. " CONF_PDEN_V4 ,Enables pull-up or pull-down on V4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " CONF_PDEN_Y1 ,Enables pull-up or pull-down on Y1" "Enabled,Disabled"
|
|
bitfld.long 0x0c 28. " CONF_PDEN_Y17 ,Enables pull-up or pull-down on Y17" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " CONF_PDEN_D18 ,Enables pull-up or pull-down on D18" "Enabled,Disabled"
|
|
bitfld.long 0x0c 26. " CONF_PDEN_B21 ,Enables pull-up or pull-down on B21" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " CONF_PDEN_C19 ,Enables pull-up or pull-down on C21" "Enabled,Disabled"
|
|
bitfld.long 0x0c 24. " CONF_PDEN_G14 ,Enables pull-up or pull-down on G14" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " CONF_PDEN_H13 ,Enables pull-up or pull-down on H13" "Enabled,Disabled"
|
|
bitfld.long 0x0c 22. " CONF_PDEN_A20 ,Enables pull-up or pull-down on A20" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " CONF_PDEN_B19 ,Enables pull-up or pull-down on B19" "Enabled,Disabled"
|
|
bitfld.long 0x0c 20. " CONF_PDEN_C18 ,Enables pull-up or pull-down on C18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " CONF_PDEN_D17 ,Enables pull-up or pull-down on D17" "Enabled,Disabled"
|
|
bitfld.long 0x0c 17. " CONF_PDEN_D16 ,Enables pull-up or pull-down on D16" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " CONF_PDEN_C17 ,Enables pull-up or pull-down on C17" "Enabled,Disabled"
|
|
bitfld.long 0x0c 15. " CONF_PDEN_B17 ,Enables pull-up or pull-down on B17" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " CONF_PDEN_G13 ,Enables pull-up or pull-down on G13" "Enabled,Disabled"
|
|
bitfld.long 0x0c 13. " CONF_PDEN_A17 ,Enables pull-up or pull-down on A17" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " CONF_PDEN_C16 ,Enables pull-up or pull-down on C16" "Enabled,Disabled"
|
|
bitfld.long 0x0c 11. " CONF_PDEN_D15 ,Enables pull-up or pull-down on D15" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " CONF_PDEN_W11 ,Enables pull-up or pull-down on W11" "Enabled,Disabled"
|
|
bitfld.long 0x0c 6. " CONF_PDEN_M4 ,Enables pull-up or pull-down on M4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " CONF_PDEN_W4 ,Enables pull-up or pull-down on W4" "Enabled,Disabled"
|
|
bitfld.long 0x0c 4. " CONF_PDEN_Y4 ,Enables pull-up or pull-down on Y4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " CONF_PDEN_V6 ,Enables pull-up or pull-down on V6" "Enabled,Disabled"
|
|
bitfld.long 0x0c 2. " CONF_PDEN_W5 ,Enables pull-up or pull-down on W5" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " CONF_PDEN_Y5 ,Enables pull-up or pull-down on Y5" "Enabled,Disabled"
|
|
bitfld.long 0x0c 0. " CONF_PDEN_R9 ,Enables pull-up or pull-down on R9" "Enabled,Disabled"
|
|
group.long 0xAC++0x3
|
|
line.long 0x00 "PULL_DWN_CTRL_4,Pull Down Control Register 4"
|
|
bitfld.long 0x00 31. " CONF_PDEN_Y18 ,Enables pull-up or pull-down on Y18" "Enabled,Disabled"
|
|
bitfld.long 0x00 30. " CONF_PDEN_W18 ,Enables pull-up or pull-down on W18" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CONF_PDEN_V17 ,Enables pull-up or pull-down on V17" "Enabled,Disabled"
|
|
bitfld.long 0x00 28. " CONF_PDEN_Y19 ,Enables pull-up or pull-down on Y19" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CONF_PDEN_V18 ,Enables pull-up or pull-down on V18" "Enabled,Disabled"
|
|
bitfld.long 0x00 26. " CONF_PDEN_L3 ,Enables pull-up or pull-down on L3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CONF_PDEN_M8 ,Enables pull-up or pull-down on M8" "Enabled,Disabled"
|
|
bitfld.long 0x00 24. " CONF_PDEN_M7 ,Enables pull-up or pull-down on M7" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CONF_PDEN_M3 ,Enables pull-up or pull-down on M3" "Enabled,Disabled"
|
|
bitfld.long 0x00 22. " CONF_PDEN_N8 ,Enables pull-up or pull-down on N8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CONF_PDEN_N3 ,Enables pull-up or pull-down on N3" "Enabled,Disabled"
|
|
bitfld.long 0x00 20. " CONF_PDEN_J8 ,Enables pull-up or pull-down on J8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CONF_PDEN_D3 ,Enables pull-up or pull-down on D3" "Enabled,Disabled"
|
|
bitfld.long 0x00 18. " CONF_PDEN_C1 ,Enables pull-up or pull-down on C1" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONF_PDEN_E4 ,Enables pull-up or pull-down on E4" "Enabled,Disabled"
|
|
bitfld.long 0x00 16. " CONF_PDEN_D2 ,Enables pull-up or pull-down on D2" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CONF_PDEN_F4 ,Enables pull-up or pull-down on F4" "Enabled,Disabled"
|
|
bitfld.long 0x00 14. " CONF_PDEN_E3 ,Enables pull-up or pull-down on E3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CONF_PDEN_J7 ,Enables pull-up or pull-down on J7" "Enabled,Disabled"
|
|
bitfld.long 0x00 12. " CONF_PDEN_F3 ,Enables pull-up or pull-down on F3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CONF_PDEN_G4 ,Enables pull-up or pull-down on G4" "Enabled,Disabled"
|
|
bitfld.long 0x00 10. " CONF_PDEN_G3 ,Enables pull-up or pull-down on G3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CONF_PDEN_G2 ,Enables pull-up or pull-down on G2" "Enabled,Disabled"
|
|
bitfld.long 0x00 8. " CONF_PDEN_K8 ,Enables pull-up or pull-down on K8" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CONF_PDEN_H4 ,Enables pull-up or pull-down on H4" "Enabled,Disabled"
|
|
bitfld.long 0x00 6. " CONF_PDEN_H3 ,Enables pull-up or pull-down on H3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CONF_PDEN_K7 ,Enables pull-up or pull-down on K7" "Enabled,Disabled"
|
|
bitfld.long 0x00 4. " CONF_PDEN_L4 ,Enables pull-up or pull-down on L4" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONF_PDEN_V2 ,Enables pull-up or pull-down on V2" "Enabled,Disabled"
|
|
bitfld.long 0x00 2. " CONF_PDEN_P3 ,Enables pull-up or pull-down on P3" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONF_PDEN_U4 ,Enables pull-up or pull-down on U4" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " CONF_PDEN_W1 ,Enables pull-up or pull-down on W1" "Enabled,Disabled"
|
|
tree.end
|
|
tree "Pull-Up Pull-Down Selection"
|
|
width 13.
|
|
group.long 0xB4++0x13
|
|
line.long 0x00 "PU_PD_SEL_0,Pull-Up Pull-Down Selection Register 0"
|
|
bitfld.long 0x00 31. " CONF_PU_PD_L14 ,Configure pullup or pulldown on L14" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 30. " CONF_PU_PD_M18 ,Configure pullup or pulldown on M18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 29. " CONF_PU_PD_M19 ,Configure pullup or pulldown on M19" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 28. " CONF_PU_PD_L15 ,Configure pullup or pulldown on L15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CONF_PU_PD_L18 ,Configure pullup or pulldown on L18" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 26. " CONF_PU_PD_L19 ,Configure pullup or pulldown on L19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 25. " CONF_PU_PD_K14 ,Configure pullup or pulldown on K14" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 24. " CONF_PU_PD_K15 ,Configure pullup or pulldown on K15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CONF_PU_PD_K19 ,Configure pullup or pulldown on K19" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 22. " CONF_PU_PD_K18 ,Configure pullup or pulldown on K18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CONF_PU_PD_J14 ,Configure pullup or pulldown on J14" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 20. " CONF_PU_PD_J19 ,Configure pullup or pulldown on J19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CONF_PU_PD_J18 ,Configure pullup or pulldown on J18" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 18. " CONF_PU_PD_J15 ,Configure pullup or pulldown on J15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CONF_PU_PD_H19 ,Configure pullup or pulldown on H19" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 16. " CONF_PU_PD_H20 ,Configure pullup or pulldown on H20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CONF_PU_PD_H18 ,Configure pullup or pulldown on H18" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 14. " CONF_PU_PD_H15 ,Configure pullup or pulldown on H15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CONF_PU_PD_G21 ,Configure pullup or pulldown on G21" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 12. " CONF_PU_PD_G20 ,Configure pullup or pulldown on G20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CONF_PU_PD_G18 ,Configure pullup or pulldown on G18" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 9. " CONF_PU_PD_F19 ,Configure pullup or pulldown on F19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CONF_PU_PD_H14 ,Configure pullup or pulldown on H14" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 7. " CONF_PU_PD_E20 ,Configure pullup or pulldown on E20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CONF_PU_PD_E19 ,Configure pullup or pulldown on E19" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 5. " CONF_PU_PD_F18 ,Configure pullup or pulldown on F18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CONF_PU_PD_D20 ,Configure pullup or pulldown on D20" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 3. " CONF_PU_PD_D19 ,Configure pullup or pulldown on D19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CONF_PU_PD_E18 ,Configure pullup or pulldown on E18" "Pull-down,Pull-up"
|
|
bitfld.long 0x00 1. " CONF_PU_PD_C21 ,Configure pullup or pulldown on C21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONF_PU_PD_G19 ,Configure pullup or pulldown on G19" "Pull-down,Pull-up"
|
|
line.long 0x04 "PU_PD_SEL_1,Pull-Up Pull-Down Selection Register 1"
|
|
bitfld.long 0x04 31. " CONF_PU_PD_AA20 ,Configure pullup or pulldown on AA20" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 30. " CONF_PU_PD_U20 ,Configure pullup or pulldown on U20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 29. " CONF_PU_PD_W16 ,Configure pullup or pulldown on W16" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 28. " CONF_PU_PD_W13 ,Configure pullup or pulldown on W13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 27. " CONF_PU_PD_J20 ,Configure pullup or pulldown on J20" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 26. " CONF_PU_PD_W17 ,Configure pullup or pulldown on W17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 25. " CONF_PU_PD_V16 ,Configure pullup or pulldown on V16" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 24. " CONF_PU_PD_Y12 ,Configure pullup or pulldown on Y12" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 23. " CONF_PU_PD_W19 ,Configure pullup or pulldown on W19" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 22. " CONF_PU_PD_P15 ,Configure pullup or pulldown on P15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 21. " CONF_PU_PD_N14 ,Configure pullup or pulldown on N14" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 20. " CONF_PU_PD_V19 ,Configure pullup or pulldown on V19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 19. " CONF_PU_PD_W21 ,Configure pullup or pulldown on W21" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 18. " CONF_PU_PD_U18 ,Configure pullup or pulldown on U18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 15. " CONF_PU_PD_U19 ,Configure pullup or pulldown on U19" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 14. " CONF_PU_PD_N15 ,Configure pullup or pulldown on N15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 13. " CONF_PU_PD_T19 ,Configure pullup or pulldown on T19" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 12. " CONF_PU_PD_T20 ,Configure pullup or pulldown on T20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 11. " CONF_PU_PD_R18 ,Configure pullup or pulldown on R18" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 10. " CONF_PU_PD_R19 ,Configure pullup or pulldown on R19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 9. " CONF_PU_PD_M14 ,Configure pullup or pulldown on M14" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 8. " CONF_PU_PD_P18 ,Configure pullup or pulldown on P18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 7. " CONF_PU_PD_P20 ,Configure pullup or pulldown on P20" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 6. " CONF_PU_PD_P19 ,Configure pullup or pulldown on P19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 5. " CONF_PU_PD_M15 ,Configure pullup or pulldown on M15" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 4. " CONF_PU_PD_N20 ,Configure pullup or pulldown on N20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 3. " CONF_PU_PD_N18 ,Configure pullup or pulldown on N18" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 2. " CONF_PU_PD_N19 ,Configure pullup or pulldown on N19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x04 1. " CONF_PU_PD_N21 ,Configure pullup or pulldown on N21" "Pull-down,Pull-up"
|
|
bitfld.long 0x04 0. " CONF_PU_PD_M20 ,Configure pullup or pulldown on M20" "Pull-down,Pull-up"
|
|
line.long 0x08 "PU_PD_SEL_2,Pull-Up Pull-Down Selection Register 2"
|
|
bitfld.long 0x08 31. " CONF_PU_PD_AA5 ,Configure pullup or pulldown on AA5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 30. " CONF_PU_PD_W6 ,Configure pullup or pulldown on W6" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 29. " CONF_PU_PD_Y6 ,Configure pullup or pulldown on Y6" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 28. " CONF_PU_PD_V7 ,Configure pullup or pulldown on V7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 27. " CONF_PU_PD_W7 ,Configure pullup or pulldown on W7" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 26. " CONF_PU_PD_P10 ,Configure pullup or pulldown on P10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 25. " CONF_PU_PD_V8 ,Configure pullup or pulldown on V8" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 24. " CONF_PU_PD_Y8 ,Configure pullup or pulldown on Y8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 23. " CONF_PU_PD_W8 ,Configure pullup or pulldown on W8" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 22. " CONF_PU_PD_R10 ,Configure pullup or pulldown on R10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 21. " CONF_PU_PD_V5 ,Configure pullup or pulldown on V5" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 20. " CONF_PU_PD_V9 ,Configure pullup or pulldown on V9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 19. " CONF_PU_PD_W9 ,Configure pullup or pulldown on W9" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 18. " CONF_PU_PD_AA9 ,Configure pullup or pulldown on AA9" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 17. " CONF_PU_PD_Y10 ,Configure pullup or pulldown on Y10" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 16. " CONF_PU_PD_R11 ,Configure pullup or pulldown on R11" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 15. " CONF_PU_PD_P11 ,Configure pullup or pulldown on P11" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 14. " CONF_PU_PD_V10 ,Configure pullup or pulldown on V10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 13. " CONF_PU_PD_V11 ,Configure pullup or pulldown on V11" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 12. " CONF_PU_PD_W10 ,Configure pullup or pulldown on W10" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 11. " CONF_PU_PD_P13 ,Configure pullup or pulldown on P13" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 10. " CONF_PU_PD_R13 ,Configure pullup or pulldown on R13" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 9. " CONF_PU_PD_V15 ,Configure pullup or pulldown on V15" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 8. " CONF_PU_PD_P14 ,Configure pullup or pulldown on P14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 7. " CONF_PU_PD_AA17 ,Configure pullup or pulldown on AA17" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 6. " CONF_PU_PD_Y15 ,Configure pullup or pulldown on Y15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 5. " CONF_PU_PD_W15 ,Configure pullup or pulldown on W15" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 4. " CONF_PU_PD_W14 ,Configure pullup or pulldown on W14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 3. " CONF_PU_PD_Y14 ,Configure pullup or pulldown on Y14" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 2. " CONF_PU_PD_V14 ,Configure pullup or pulldown on V14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x08 1. " CONF_PU_PD_R14 ,Configure pullup or pulldown on R14" "Pull-down,Pull-up"
|
|
bitfld.long 0x08 0. " CONF_PU_PD_AA15 ,Configure pullup or pulldown on AA15" "Pull-down,Pull-up"
|
|
line.long 0x0c "PU_PD_SEL_3,Pull-Up Pull-Down Selection Register 3"
|
|
bitfld.long 0x0c 31. " CONF_PU_PD_W2 ,Configure pullup or pulldown on W2" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 30. " CONF_PU_PD_V4 ,Configure pullup or pulldown on V4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 29. " CONF_PU_PD_Y1 ,Configure pullup or pulldown on Y1" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 28. " CONF_PU_PD_Y17 ,Configure pullup or pulldown on Y17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 27. " CONF_PU_PD_D18 ,Configure pullup or pulldown on D18" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 26. " CONF_PU_PD_B21 ,Configure pullup or pulldown on B21" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " CONF_PU_PD_C19 ,Configure pullup or pulldown on C21" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 24. " CONF_PU_PD_G14 ,Configure pullup or pulldown on G14" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 23. " CONF_PU_PD_H13 ,Configure pullup or pulldown on H13" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 22. " CONF_PU_PD_A20 ,Configure pullup or pulldown on A20" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 21. " CONF_PU_PD_B19 ,Configure pullup or pulldown on B19" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 20. " CONF_PU_PD_C18 ,Configure pullup or pulldown on C18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 18. " CONF_PU_PD_D17 ,Configure pullup or pulldown on D17" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 17. " CONF_PU_PD_D16 ,Configure pullup or pulldown on D16" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 16. " CONF_PU_PD_C17 ,Configure pullup or pulldown on C17" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 15. " CONF_PU_PD_B17 ,Configure pullup or pulldown on B17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 14. " CONF_PU_PD_G13 ,Configure pullup or pulldown on G13" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 13. " CONF_PU_PD_A17 ,Configure pullup or pulldown on A17" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 12. " CONF_PU_PD_C16 ,Configure pullup or pulldown on C16" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 11. " CONF_PU_PD_D15 ,Configure pullup or pulldown on D15" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 8. " CONF_PU_PD_W11 ,Configure pullup or pulldown on W11" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 6. " CONF_PU_PD_M4 ,Configure pullup or pulldown on M4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " CONF_PU_PD_W4 ,Configure pullup or pulldown on W4" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 4. " CONF_PU_PD_Y4 ,Configure pullup or pulldown on Y4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " CONF_PU_PD_V6 ,Configure pullup or pulldown on V6" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 2. " CONF_PU_PD_W5 ,Configure pullup or pulldown on W5" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " CONF_PU_PD_Y5 ,Configure pullup or pulldown on Y5" "Pull-down,Pull-up"
|
|
bitfld.long 0x0c 0. " CONF_PU_PD_R9 ,Configure pullup or pulldown on R9" "Pull-down,Pull-up"
|
|
line.long 0x10 "PU_PD_SEL_4,Pull-Up Pull-Down Selection Register 4"
|
|
bitfld.long 0x10 31. " CONF_PU_PD_Y18 ,Configure pullup or pulldown on Y18" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 30. " CONF_PU_PD_W18 ,Configure pullup or pulldown on W18" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 29. " CONF_PU_PD_V17 ,Configure pullup or pulldown on V17" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 28. " CONF_PU_PD_Y19 ,Configure pullup or pulldown on Y19" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 27. " CONF_PU_PD_V18 ,Configure pullup or pulldown on V18" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 26. " CONF_PU_PD_L3 ,Configure pullup or pulldown on L3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 25. " CONF_PU_PD_M8 ,Configure pullup or pulldown on M8" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 24. " CONF_PU_PD_M7 ,Configure pullup or pulldown on M7" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 23. " CONF_PU_PD_M3 ,Configure pullup or pulldown on M3" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 22. " CONF_PU_PD_N8 ,Configure pullup or pulldown on N8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 21. " CONF_PU_PD_N3 ,Configure pullup or pulldown on N3" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 20. " CONF_PU_PD_J8 ,Configure pullup or pulldown on J8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 19. " CONF_PU_PD_D3 ,Configure pullup or pulldown on D3" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 18. " CONF_PU_PD_C1 ,Configure pullup or pulldown on C1" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 17. " CONF_PU_PD_E4 ,Configure pullup or pulldown on E4" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 16. " CONF_PU_PD_D2 ,Configure pullup or pulldown on D2" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 15. " CONF_PU_PD_F4 ,Configure pullup or pulldown on F4" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 14. " CONF_PU_PD_E3 ,Configure pullup or pulldown on E3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 13. " CONF_PU_PD_J7 ,Configure pullup or pulldown on J7" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 12. " CONF_PU_PD_F3 ,Configure pullup or pulldown on F3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 11. " CONF_PU_PD_G4 ,Configure pullup or pulldown on G4" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 10. " CONF_PU_PD_G3 ,Configure pullup or pulldown on G3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 9. " CONF_PU_PD_G2 ,Configure pullup or pulldown on G2" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 8. " CONF_PU_PD_K8 ,Configure pullup or pulldown on K8" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 7. " CONF_PU_PD_H4 ,Configure pullup or pulldown on H4" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 6. " CONF_PU_PD_H3 ,Configure pullup or pulldown on H3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 5. " CONF_PU_PD_K7 ,Configure pullup or pulldown on K7" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 4. " CONF_PU_PD_L4 ,Configure pullup or pulldown on L4" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 3. " CONF_PU_PD_V2 ,Configure pullup or pulldown on V2" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 2. " CONF_PU_PD_P3 ,Configure pullup or pulldown on P3" "Pull-down,Pull-up"
|
|
textline " "
|
|
bitfld.long 0x10 1. " CONF_PU_PD_U4 ,Configure pullup or pulldown on U4" "Pull-down,Pull-up"
|
|
bitfld.long 0x10 0. " CONF_PU_PD_W1 ,Configure pullup or pulldown on W1" "Pull-down,Pull-up"
|
|
tree.end
|
|
tree "Functional Multiplexing DSP/ARM DMA"
|
|
width 20.
|
|
group.long 0xD0++0xF
|
|
textline ""
|
|
line.long 0x00 "FUNC_MUX_DSP_DMA_A,Functional Multiplexing DSP DMA Register A"
|
|
bitfld.long 0x00 25.--29. " CONF_DSP_DMA_REQ_06 ,The DMA request source to DSP DMA controller DMA_REQ(6)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x00 20.--24. " CONF_DSP_DMA_REQ_05 ,The DMA request source to DSP DMA controller DMA_REQ(5)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x00 15.--19. " CONF_DSP_DMA_REQ_04 ,The DMA request source to DSP DMA controller DMA_REQ(4)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x00 10.--14. " CONF_DSP_DMA_REQ_03 ,The DMA request source to DSP DMA controller DMA_REQ(3)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x00 5.--9. " CONF_DSP_DMA_REQ_02 ,The DMA request source to DSP DMA controller DMA_REQ(2)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " CONF_DSP_DMA_REQ_01 ,The DMA request source to DSP DMA controller DMA_REQ(1)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
line.long 0x04 "FUNC_MUX_DSP_DMA_B,Functional Multiplexing DSP DMA Register B"
|
|
bitfld.long 0x04 25.--29. " CONF_DSP_DMA_REQ_12 ,The DMA request source to DSP DMA controller DMA_REQ(12)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x04 20.--24. " CONF_DSP_DMA_REQ_11 ,The DMA request source to DSP DMA controller DMA_REQ(11)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x04 15.--19. " CONF_DSP_DMA_REQ_10 ,The DMA request source to DSP DMA controller DMA_REQ(10)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x04 10.--14. " CONF_DSP_DMA_REQ_09 ,The DMA request source to DSP DMA controller DMA_REQ(9)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x04 5.--9. " CONF_DSP_DMA_REQ_08 ,The DMA request source to DSP DMA controller DMA_REQ(8)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x04 0.--4. " CONF_DSP_DMA_REQ_07 ,The DMA request source to DSP DMA controller DMA_REQ(7)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
line.long 0x08 "FUNC_MUX_DSP_DMA_C,Functional Multiplexing DSP DMA Register C"
|
|
bitfld.long 0x08 25.--29. " CONF_DSP_DMA_REQ_18 ,The DMA request source to DSP DMA controller DMA_REQ(18)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x08 20.--24. " CONF_DSP_DMA_REQ_17 ,The DMA request source to DSP DMA controller DMA_REQ(17)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x08 15.--19. " CONF_DSP_DMA_REQ_16 ,The DMA request source to DSP DMA controller DMA_REQ(16)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x08 10.--14. " CONF_DSP_DMA_REQ_15 ,The DMA request source to DSP DMA controller DMA_REQ(15)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x08 5.--9. " CONF_DSP_DMA_REQ_14 ,The DMA request source to DSP DMA controller DMA_REQ(14)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
textline " "
|
|
bitfld.long 0x08 0.--4. " CONF_DSP_DMA_REQ_13 ,The DMA request source to DSP DMA controller DMA_REQ(13)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
line.long 0x0c "FUNC_MUX_DSP_DMA_D,Functional Multiplexing DSP DMA Register D"
|
|
bitfld.long 0x0c 0.--4. " CONF_DSP_DMA_REQ_19 ,The DMA request source to DSP DMA controller DMA_REQ(19)" "MCSI1 TX,MCSI1 RX,MCSI2 TX,MCSI2 RX,MMC/SDIO2 TX,MMC/SDIO2 RX,Reserved,McBSP1 TX,McBSP1 RX,McBSP3 TX,McBSP3 RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,I2C RX,I2C TX,UART3 TX,UART3 RX,CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),NAND flash end of burst,SPI TX,SPI RX,McBSP2 TX,McBSP2 RX,Unconnected,Unconnected,Unconnected,Unconnected"
|
|
group.long 0xEC++0x1B
|
|
line.long 0x0 "FUNC_MUX_MPU_DMA_A,Functional Multiplexing MPU DMA Register A"
|
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bitfld.long 0x0 24.--29. " CONF_ARM_DMA_REQ_05 ,DMA request source to system DMA controller DMA_REQ(5)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x0 18.--23. " CONF_ARM_DMA_REQ_04 ,DMA request source to system DMA controller DMA_REQ(4)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x0 12.--17. " CONF_ARM_DMA_REQ_03 ,DMA request source to system DMA controller DMA_REQ(3)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x0 6.--11. " CONF_ARM_DMA_REQ_02 ,DMA request source to system DMA controller DMA_REQ(2)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x0 0.--5. " CONF_ARM_DMA_REQ_01 ,DMA request source to system DMA controller DMA_REQ(1)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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line.long 0x4 "FUNC_MUX_MPU_DMA_B,Functional Multiplexing MPU DMA Register B"
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bitfld.long 0x4 24.--29. " CONF_ARM_DMA_REQ_10 ,DMA request source to system DMA controller DMA_REQ(10)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x4 18.--23. " CONF_ARM_DMA_REQ_09 ,DMA request source to system DMA controller DMA_REQ(9)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x4 12.--17. " CONF_ARM_DMA_REQ_08 ,DMA request source to system DMA controller DMA_REQ(8)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x4 6.--11. " CONF_ARM_DMA_REQ_07 ,DMA request source to system DMA controller DMA_REQ(7)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x4 0.--5. " CONF_ARM_DMA_REQ_06 ,DMA request source to system DMA controller DMA_REQ(6)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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line.long 0x8 "FUNC_MUX_MPU_DMA_C,Functional Multiplexing MPU DMA Register C"
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bitfld.long 0x8 24.--29. " CONF_ARM_DMA_REQ_15 ,DMA request source to system DMA controller DMA_REQ(15)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x8 18.--23. " CONF_ARM_DMA_REQ_14 ,DMA request source to system DMA controller DMA_REQ(14)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x8 12.--17. " CONF_ARM_DMA_REQ_13 ,DMA request source to system DMA controller DMA_REQ(13)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x8 6.--11. " CONF_ARM_DMA_REQ_12 ,DMA request source to system DMA controller DMA_REQ(12)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x8 0.--5. " CONF_ARM_DMA_REQ_11 ,DMA request source to system DMA controller DMA_REQ(11)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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line.long 0xC "FUNC_MUX_MPU_DMA_D,Functional Multiplexing MPU DMA Register D"
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bitfld.long 0xC 24.--29. " CONF_ARM_DMA_REQ_20 ,DMA request source to system DMA controller DMA_REQ(20)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0xC 18.--23. " CONF_ARM_DMA_REQ_19 ,DMA request source to system DMA controller DMA_REQ(19)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0xC 12.--17. " CONF_ARM_DMA_REQ_18 ,DMA request source to system DMA controller DMA_REQ(18)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0xC 6.--11. " CONF_ARM_DMA_REQ_17 ,DMA request source to system DMA controller DMA_REQ(17)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0xC 0.--5. " CONF_ARM_DMA_REQ_16 ,DMA request source to system DMA controller DMA_REQ(16)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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line.long 0x10 "FUNC_MUX_MPU_DMA_E,Functional Multiplexing MPU DMA Register E"
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bitfld.long 0x10 24.--29. " CONF_ARM_DMA_REQ_25 ,DMA request source to system DMA controller DMA_REQ(25)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x10 18.--23. " CONF_ARM_DMA_REQ_24 ,DMA request source to system DMA controller DMA_REQ(24)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x10 12.--17. " CONF_ARM_DMA_REQ_23 ,DMA request source to system DMA controller DMA_REQ(23)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x10 6.--11. " CONF_ARM_DMA_REQ_22 ,DMA request source to system DMA controller DMA_REQ(22)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x10 0.--5. " CONF_ARM_DMA_REQ_21 ,DMA request source to system DMA controller DMA_REQ(21)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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line.long 0x14 "FUNC_MUX_MPU_DMA_F,Functional Multiplexing MPU DMA Register F"
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bitfld.long 0x14 24.--29. " CONF_ARM_DMA_REQ_30 ,DMA request source to system DMA controller DMA_REQ(30)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x14 18.--23. " CONF_ARM_DMA_REQ_29 ,DMA request source to system DMA controller DMA_REQ(29)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x14 12.--17. " CONF_ARM_DMA_REQ_28 ,DMA request source to system DMA controller DMA_REQ(28)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x14 6.--11. " CONF_ARM_DMA_REQ_27 ,DMA request source to system DMA controller DMA_REQ(27)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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textline " "
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bitfld.long 0x14 0.--5. " CONF_ARM_DMA_REQ_26 ,DMA request source to system DMA controller DMA_REQ(26)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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line.long 0x18 "FUNC_MUX_MPU_DMA_G,Functional Multiplexing MPU DMA Register G"
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bitfld.long 0x18 0.--5. " CONF_ARM_DMA_REQ_31 ,DMA request source to system DMA controller DMA_REQ(31)" "MCSI1 TX,MCSI1 RX,I2C RX,I2C TX,External DMA request 0,External DMA request 1,MicroWire TX,McBSP1 DMA TX,McBSP1 DMA RX,McBSP3 DMA TX,McBSP3 DMA RX,UART1 TX,UART1 RX,UART2 TX,UART2 RX,McBSP2 TX,McBSP2 RX,UART3 TX,UART3 RX,Camera IF RX,MMC/SDIO1 TX,MMC/SDIO1 RX,NAND flash end of burst,IRQ_LCD_LINE,Memory Stick,USB W2FC RX0,USB W2FC RX1,USB W2FC RX2,USB W2FC TX0,USB W2FC TX1,USB W2FC TX2,DES/3DES3 in,SPI TX,SPI RX,SHA-1/MD5,CCP Attn,CCP FIFO not empty,CMT-APE TX (channel 0),CMT-APE RV (channel 0),CMT-APE TX (channel 1),CMT-APE RV (channel 1),CMT-APE TX (channel 2),CMT-APE RV (channel 2),CMT-APE TX (channel 3),CMT-APE RV (channel 3),CMT-APE TX (channel 4),CMT-APE RV (channel 4),CMT-APE TX (channel 5),CMT-APE RV (channel 5),CMT-APE TX (channel 6),CMT-APE RV (channel 6),CMT-APE TX (channel 7),CMT-APE RV (channel 7),MMC/SDIO2 TX,MMC/SDIO2 RX,DES/3DES out,VLYNQ,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected,Unconnected"
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tree.end
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textline " "
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width 22.
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group.long 0x0C++0x3
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line.long 0x00 "COMP_MODE_CTRL_0,I/O Multiplex Enable Register 0"
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hexfld.word 0x00 " CONF_MUX_EN_R ,Write 0xEAEF to enable multiplexing"
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group.long 0x50++0x3
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line.long 0x0 "GATE_INH_CTRL_0,Gate Inhibit Control Register 0"
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bitfld.long 0x0 3. " CONF_HIGH_IMP3 ,Control high impedance on MCSI.DOUT" "Normal,Hi-Z"
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textline " "
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bitfld.long 0x0 2. " CONF_SOFTWARE_PWR_R ,Controls software gating and inhibiting of the I/O, which is gated or inhibited by COM_PWR status" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 1. " CONF_SOFTWARE_BVLZ_R ,Control software gating and inhibiting of the I/O, which is gated or inhibited by the BFAIL or /EXT_FIQ signal" "Disabled,Enabled"
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textline " "
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bitfld.long 0x0 0. " CONF_SOFWTARE_GATE_ENA_R ,Controls software gating of the I/O which is gated or inhibited" "Disabled,Enabled"
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rgroup.long 0x58++0x3
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line.long 0x00 "CONF_REV,Configuration Revision"
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hexmask.long.byte 0x00 0.--7. 1. " CONF_REV_R ,Revision number of the current module"
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group.long 0x60++0xB
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line.long 0x00 "VOLTAGE_CTRL_0,Voltage Control Register 0"
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bitfld.long 0x00 13. " SUBLVDS_CONF_VALID_R ,Protects the CCP IO cells comparator after reset" "Protect,Unprotect"
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textline " "
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bitfld.long 0x00 12. " CONF_VOLTAGE_RTC_R ,Controls the drive strength of the DVDD10 RTC voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 11. " CONF_VOLTAGE_VDDSHV9_R ,Controls the drive strength of the DVDD9 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 10. " CONF_VOLTAGE_VDDSHV8_R ,Controls the drive strength of the DVDD8 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 9. " CONF_VOLTAGE_VDDHSV7_R ,Controls the drive strength of the DVDD7 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 8. " CONF_VOLTAGE_VDDHSV6_R ,Controls the drive strength of the DVDD6 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 7. " CONF_VOLTAGE_VDDSHV2_R ,Controls the drive strength of the DVDD2 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 6. " CONF_VOLTAGE_VDDSHV1_R ,Controls the drive strength of the DVDD1 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 2. " CONF_VOLTAGE_COMIF_R ,Controls the drive strength of the DVDD3 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 1. " CONF_VOLTAGE_SDRAM_R ,Controls the drive strength of the DVDD4 voltage domain" "Low,High"
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textline " "
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bitfld.long 0x00 0. " CONF_VOLTAGE_FLASH_R ,Controls the drive strength of the DVDD5 voltage domain" "Low,High"
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line.long 0x04 "USB_TRANSCEIVER_CTRL,USB Transceiver Control Register"
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bitfld.long 0x04 8. " CONF_USB2_UNI_R ,The way USB port 2 interfaces with external USB transceiver" "Bidirectional,Unidirectional"
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textline " "
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bitfld.long 0x04 7. " CONF_USB1_UNI_R ,The way USB port 1 interfaces with external USB transceiver" "Bidirectional,Unidirectional"
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textline " "
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bitfld.long 0x04 4.--6. " CONF_USB_PORT0_R ,Control the multiplexing on the I/O" "USB.DP/USB.DM,Disallowed,Disallowed,Disallowed,I2C.SDA/I2C.SCI,UART1.RX/UART1.TX,Disallowed,USB2.PUEN/HI-Z"
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textline " "
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bitfld.long 0x04 3. " CONF_USB0_ISOLATE_R ,Isolates the USB port 0 controller from the intagrated USB transceiver" "Normal,Isolation"
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textline " "
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bitfld.long 0x04 2. " CONF_USB_PWRDN_DM_R ,Enable of pulldown on USB DM pin" "Enabled,Disabled"
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textline " "
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bitfld.long 0x04 1. " CONF_USB_PWRDN_DP_R ,Enable of pulldown on USB DP pin" "Enabled,Disabled"
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line.long 0x08 "LDO_PWRDN_CTRL,LDO Power Down Control Register"
|
|
bitfld.long 0x08 0. " CONF_KDO_PWRWN_CNTRL_R ,Allow the LDO to be powered-down and bypassed" "Disallow,Allow"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "TEST_DBG_CTRL_0,Test debug control 0"
|
|
bitfld.long 0x0 21. " CONF_RNG_TEST_OSC ,Ring oscillator divider enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " CONF_RNG_SELECT_OSC ,Ring oscillator selection for characterization" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " CONF_DSP_BRTE_WRITE_R ,DFT WRITE signal to control DSP BRTE memories" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 18. " CONF_DSP_BRTE_READ_R ,DFT READ signal to control DSP BRTE memories" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CONF_TEST_VBUS_CELL ,This bit test the UIS480 VBUS detect cell" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CONF_DPLL_EXT_SEL ,Select 48-MHz clock source" "APLL,GPIO14"
|
|
textline " "
|
|
bitfld.long 0x0 2. " CONF_VBOX_EN ,OMAP VBOX SW test enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CONF_VBOX2 ,OMAP VBOX 2 - DFT WRITE signal to control MPU BRTE memories" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CONF_VBOX1 ,OMAP VBOX 1 - DFT READ signal to control MPU BRTE memories" "Disabled,Enabled"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "MOD_CONF_CTRL_0,Module Configuration Control Register 0"
|
|
bitfld.long 0x0 31. " CONF_MOD_UART3_CLK_MODE_R ,This bit determines the 48-MHz clock request for UART3" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 30. " CONF_MOD_UART2_CLK_MODE_R ,This bit determines the clock source of UART2" "UART_MCLKO,48 MHz"
|
|
textline " "
|
|
bitfld.long 0x0 29. " CONF_MOD_UART1_CLK_MODE_R ,This bit determines whether 48-MHz clock request for UART1 is active" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x0 23. " CONF_MOD_MMC_SD_CLK_REQ_R ,This is the functional 48-MHz clock request for the MMCSDIO1 interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 20. " CONF_MOD_MMC_SD2_CLK_REQ_R ,This is the functional 48-MHz clock request for the devcie MMC/SD 2 interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 19. " CONF_MOD_MCBSP3_CLK_SEL_R ,This bit determines the method of frame sync wrap-around used on MCBSP3" "External+DSPXOR_CLK,Internal+DSPPER_CLK"
|
|
textline " "
|
|
bitfld.long 0x0 18. " CONF_MOD_MCBSP1_CLKS_SEL_R ,This register selects the clock used for the McBSP1 clocks input" "McBSP1.CLKS,OMAP DPLL1"
|
|
textline " "
|
|
bitfld.long 0x0 17. " CONF_MOD_USB_W2FC_VBUS_MODE_R ,This bit determines the method used for USB VBUS detection" "GPIO_0,DVDD2"
|
|
textline " "
|
|
bitfld.long 0x0 14. " CONF_MOD_MCBSP1_CLK_SEL_R ,This register selects the clock used for the McBSP1 module" "DSPXOR_CLK,DSPPER_CLK"
|
|
textline " "
|
|
bitfld.long 0x0 13. " CONF_MOD_MMC2_CLK_SEL_R ,This register selects the clock used for the MMC/SD2 module" "ULPD 48MHz MMC2_DPLL_CLK,OMAP ARM_XOR_CLK"
|
|
textline " "
|
|
bitfld.long 0x0 12. " CONF_MOD_COM_MCLK_12_48_SEL_R ,This register determines whether MCLK of the device outputs the system clock or the 48-MHz clock" "System,48-MHz"
|
|
textline " "
|
|
bitfld.long 0x0 11. " CONF_MOD_USB_HOST_UART_SELECT_R ,Enable UART multiplexing on USB port 1" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 9. " CONF_MOD_USB_HOST_HHC_UHOST_EN_R ,Enable input for functional-mode clocking of USB_HHC" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 8. " CONF_MOD_USB_HOST_MMC_TLL_SPEED_R ,Transceiverless link logic (TLL) USB speed control" "Low-speed,High-speed"
|
|
textline " "
|
|
bitfld.long 0x0 7. " CONF_MOD_USB_HOST_MMC_ATTACH_R ,Transceiver link logic (TLL) USB attach control" "No pullup,Pullup"
|
|
textline " "
|
|
hexmask.long.byte 0x0 1.--6. 1. " CONF_MOD_USB_HOST_HMC_MODE_R ,USB_HHC port multiplexing control"
|
|
group.long 0x110++0x3
|
|
line.long 0x00 "MOD_CONF_CTRL_1,Module Configuration Control Register 1"
|
|
bitfld.long 0x00 31. " CONF_CAM_CLKMUX_R ,Selection of camera_interface clock (MCLK)" "OMAP ARMMXOR,ULPD CAM_MCKO"
|
|
textline " "
|
|
bitfld.long 0x00 29.--30. " CONF_PMT_DCB_SELECT_R ,Generates the selection signal for the multiplexer in OMAP3.2 for observability of DLL output bus(DCB[7:0])" "URD_DLL,URD_DLL,WRQ_DLL,WRQ_DLL"
|
|
textline " "
|
|
bitfld.long 0x00 28. " CONF_OSC1_GZ_R ,Disables oscillator" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " CONF_OSC1_PWRDN_R ,Powers-down the Oscillator" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 26. " SSI_INTERCONNECT_GATE_EN_R ,Enables the SSI interconnect to use its autoidle features" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " OCP_INTERCON_GATE_R ,Enables the OCP interconnect to use its autoidle feauture on OCP interface" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CONF_MMC2_CLKFB_SEL_R ,Selects clock feedback into MMC/SDIO" "MMC/SDIO,Pad"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CONF_SOSSI_RESET_R ,Controls the reset of the SoSSI module" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 22. " CONF_MCBSP3_CLK_DIS_R ,Enables the McBSP3 interface clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " CONF_MCBSP2_CLK_DIS_R ,Enables the McBSP2 interface clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " CONF_MCBSP1_CLK_DIS_R ,Enables the McBSP1 interface clock" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " CONF_MOD_SOSSI_CLK_SEL_R ,Configuration of the SoSSI clock divider ratio" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CONF_MOD_SOSSI_CLK_EN_R ,Configures the enable of the SoSSI LCD interface module" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " CONF_MOD_GPTIMER8_CLK_SEL_R ,Selects the clock source for general-purpose timer 8" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONF_MOD_GPTIMER7_CLK_SEL_R ,Selects the clock source for general-purpose timer 7" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " CONF_MOD_GPTIMER6_CLK_SEL_R ,Selects the clock source for general-purpose timer 6" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CONF_MOD_GPTIMER5_CLK_SEL_R ,Selects the clock source for general-purpose timer 5" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CONF_MOD_GPTIMER4_CLK_SEL_R ,Selects the clock source for general-purpose timer 4" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONF_MOD_GPTIMER3_CLK_SEL_R ,Selects the clock source for general-purpose timer 3" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " CONF_MOD_GPTIMER2_CLK_SEL_R ,Selects the clock source for general-purpose timer 2" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CONF_MOD_GPTIMER1_CLK_SEL_R ,Selects the clock source for general-purpose timer 1" "ARMXOR_CLK,32-kHz clock,EXT_CLK,?..."
|
|
group.long 0x120++0x3
|
|
line.long 0x0 "SECCTRL,Secure Mode Control Register"
|
|
bitfld.long 0x0 11. " CONF_RNG_EN_R ,RNG module access control register" "Nonsecure,Secure"
|
|
textline " "
|
|
bitfld.long 0x0 10. " CONF_DES_EN_R ,DES/3DES module access control register" "Nonsecure,Secure"
|
|
textline " "
|
|
bitfld.long 0x0 9. " CONF_MUX_CTRL_R ,Control access to the registers that configure multiplexing the device pins and the pullup/pulldown functions (programmable only in secure mode)" "Anytime,Secure mode only"
|
|
textline " "
|
|
bitfld.long 0x0 8. " CONF_SHA_EN_R ,SHA-1 module access control register" "Nonsecure,Secure"
|
|
textline " "
|
|
bitfld.long 0x0 7. " NORMAL_EMU_MODE_R ,Information about the security type" "Normal,Debug"
|
|
textline " "
|
|
bitfld.long 0x0 6. " CONF_JTAG_EN_R ,MPU JTAG enable control register" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CONF_ETM_EN_R ,ETM enable control register" "Disabled,Not affected"
|
|
textline " "
|
|
bitfld.long 0x0 4. " CONF_CKEY_ACC_R ,CKEY access control register" "Disallowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CONF_RKEY_ACC_R ,RKEY access control register" "Disallowed,Allowed"
|
|
textline " "
|
|
bitfld.long 0x0 2. " CONF_ICE_EN_R ,MPU emulation enable control register" "Disabled,Not affected"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CONF_WD_REG_EN ,Secure watchdog registers update the access control register" "Access done/granted,Error generated/rejected"
|
|
textline " "
|
|
bitfld.long 0x0 0. " CONF_WD_OP_DIS ,Secure watchdog operation enables the control register" "Running,Frozen"
|
|
rgroup.long 0x130++0x3
|
|
line.long 0x00 "CONF_STATUS,Configuration Status Register"
|
|
bitfld.long 0x00 4.--5. " CONF_DEVICE_TYPE_R ,Contains the status of the eFuses that determine the type of device" "Production,Bad,Emulator,Test"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONF_STATUS ,Contains the status of GPIO1 input pin" "Nonaddress,Address"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CONF_EMIFS_MUX_STAT_R ,Contains information about EMIFS protocol at boot" "Nonaddress,Address"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONF_ARM_BOOT_STAT_R ,This register contains boot mode active chip-select" "Internal ROM,External memory"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONF_RESET_MODE_STAT_R ,This register contains the status of the RESET_MODE pin" "0,1"
|
|
group.long 0x140++0x3
|
|
line.long 0x00 "RESET_CTRL,Reset Control Register"
|
|
bitfld.long 0x00 6. " CONF_RNG_IDLE_MODE ,RNGidle control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " CONF_CAMERAIF_RESET_R ,Controls reset of the camer IF and th CCP" "Reset,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 4. " CONF_UWIRE_RESET_R ,Controls reset of the uWire" "Reset,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONF_OSTIMER_RESET_R ,Controls reset of the OS timer" "Reset,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CONF_ARMIO_RESET_R ,Controls reset of the MPUIO" "Reset,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CONF_SSI_RESET_R ,Controls reset of the SSI interconnect" "Reset,Functional"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CONF_OCP_RESET_R ,Controls reset of the OCP interconnect" "Reset,Functional"
|
|
group.long 0x150++0x3
|
|
line.long 0x0 "MOD_CONF_CTRL_2,Module Configuration Control Register 2"
|
|
bitfld.long 0x0 3. " SERCK ,VLYNQ serial clock enable" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x0 2. " SYSCK ,VLYNQ system clock enable" "On,Off"
|
|
textline " "
|
|
bitfld.long 0x0 0. " VLYNQ_EN ,OCP static switch command" "VLYNQ -> GDD/SSI,GDD/SSI -> VLYNQ"
|
|
tree.end
|
|
base AD:0xFFFE1800
|
|
tree "OMAP Device Identification Registers"
|
|
width 22.
|
|
rgroup.long 0x0++0x7
|
|
line.long 0x00 "OMAP_DIE_ID_0,OMAP Die ID Register 0 (Reserved)"
|
|
line.long 0x04 "OMAP_DIE_ID_1,OMAP Die ID Register 1"
|
|
bitfld.long 0x04 17.--20. " DEV_REV ,Device revision" "0x0,0x1,0x2,?..."
|
|
rgroup.long 0x800++0x7
|
|
line.long 0x00 "OMAP_PRODUCTION_ID_0, OMAP Die ID Register Register 0"
|
|
bitfld.long 0x00 30.--31. " SECURITY ,Security device type" "GP,?..."
|
|
hexmask.long.word 0x00 9.--24. 1. " ID_KEY , Reserved for special identification"
|
|
bitfld.long 0x00 8. " SP ,Secure protect" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 7. " WA ,DFT write MPU. MPU DFT write value" "0,1"
|
|
bitfld.long 0x00 6. " RA ,DFT read MPU. DFT write value" "0,1"
|
|
bitfld.long 0x00 5. " WD ,DFT write MGS3. MGS3 DFT write value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RD ,DFT read MGS3. MGS3 DFT read value" "0,1"
|
|
bitfld.long 0x00 2.--3. " NORMAL ,A normal device" "Not normal,Normal,Normal,Normal"
|
|
bitfld.long 0x00 0.--1. " EMULATION ,An emulation device" "Not emulation,Emulation,Emulation,Emulation"
|
|
line.long 0x04 "OMAP_PRODUCTION_ID_1, Production Identification Register 1"
|
|
hexmask.long.word 0x04 1.--16. 1. " PROD_ID ,Prod ID"
|
|
rgroup.long 0xBC00++0x3
|
|
line.long 0x00 "OMAP32_ID,OMAP 3.2 device revision"
|
|
tree.end
|
|
base AD:0xFFFEC320
|
|
tree "L3 OCP Initiator Registers"
|
|
width 13.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "OCPI_AFR,OCPI Address Fault Register"
|
|
line.long 0x04 "OCPI_MCFR,OCPI Master Command Fault Register"
|
|
bitfld.long 0x04 0.--2. " MCMD , Command that caused an abort or error" "Idle,Write,Read,ReadEX,Not supported,Not supported,Not supported,Not supported"
|
|
rgroup.long 0xC++0x3
|
|
line.long 0x0 "OCPI_ATYPER,Abort Type Register"
|
|
bitfld.long 0x0 3. " BURST_ERR ,Burst access to the MPUI or TIPB was requested" "No requested,Requested"
|
|
bitfld.long 0x0 2. " PROTECT ,Address hit a protected area" "Not hit,Hit"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRGABORT ,Abort coming from the accessed target" "No,Yes"
|
|
bitfld.long 0x0 0. " ADDDEC ,Address decoding error (initiator sent unknown address)" "No error,Error"
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "OCPI_PR,Memory Protect Register"
|
|
bitfld.long 0x00 7. " API ,Access to MPUI is prohibited" "Not prohibited,Prohibited"
|
|
bitfld.long 0x00 6. " RHEA_PUB ,Access to MPU public TIPB is prohibited" "Not prohibited,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RHEA_PRIV ,Access to MPU private TIPB is prohibited" "Not prohibited,Prohibited"
|
|
bitfld.long 0x00 4. " OCPMULT ,Access to OCPT multibank is prohibited" "Not prohibited,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCPT2 ,Access to OCPT2 is prohibited" "Not prohibited,Prohibited"
|
|
bitfld.long 0x00 2. " OCPT1 ,Access to OCPT1 is prohibited" "Not prohibited,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EMIFF ,Access to EMIFF is prohibited" "Not prohibited,Prohibited"
|
|
bitfld.long 0x00 0. " EMIFS ,Access to EMIFS is prohibited" "Not prohibited,Prohibited"
|
|
line.long 0x04 "SECURE_MODE,Secure Mode Register"
|
|
bitfld.long 0x04 6. " API ,In secure mode" "Allowed,Prohibited"
|
|
bitfld.long 0x04 5. " RHEA_PRIV ,In secure mode" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x04 4. " OCPMULT ,In secure mode" "Allowed,Prohibited"
|
|
bitfld.long 0x04 3. " OCPT2 ,In secure mode" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OCPT1 ,In secure mode" "Allowed,Prohibited"
|
|
bitfld.long 0x04 1. " EMIFF ,In secure mode" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x04 0. " EMIFS ,In secure mode" "Allowed,Prohibited"
|
|
tree.end
|
|
base AD:0xFFFECA00
|
|
tree "TIPB Private Bridge 1 Configuration Registers"
|
|
width 20.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIPB_CNTL,Private TIPB Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TIMEOUT ,TIPB bus access time-out"
|
|
bitfld.word 0x00 4.--7. " ACCESS_FACTOR1 ,Clock period multiplication factor for TIPB strobe 1" "x2,x2,x4,x6,x8,x10,x12,x14,x16,x18,x20,x22,x24,x26,x28,x30"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " ACCESS_FACTOR0 ,Clock period multiplication factor for TIPB strobe 0" "x2,x2,x4,x6,x8,x10,x12,x14,x16,x18,x20,x22,x24,x26,x28,x30"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIPB_BUS_ALLOC,Private TIPB Bus Allocation Register"
|
|
bitfld.word 0x0 5. " EXTNINT_PRIORITY ,Priority between DMA and OCP-I when fixed priority scheme is selected" "DMA,OCP-I"
|
|
bitfld.word 0x0 4. " FIXNROUND_PRIORITY ,Type of priority scheme used in DMA and OCP-I arbitration" "Round-robin,Fixed"
|
|
textline " "
|
|
bitfld.word 0x0 3. " PRIORITY_ENABLE " "RHEA_PRIORITY,MPU=OCP-I"
|
|
bitfld.word 0x0 0.--2. " RHEA_PRIORITY ,Defines TIPB priority between MPU and DMA/OCP-I" "MPU > DMA/OCP-I,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "MPU_TIPB_CNTL,Private MPU TIPB Control Register"
|
|
bitfld.word 0x0 1. " W_BUF_EN_1 ,Posted write buffer enable for TIPB strobe 1" "Bypassed,Enabled"
|
|
bitfld.word 0x0 0. " W_BUF_EN_0 ,Posted write buffer enable for TIPB strobe 0" "Bypassed,Enabled"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "ENHANCED_TIPB_CNTL,Private Enhanced TIPB Control Register"
|
|
bitfld.word 0x0 3. " MASK_ABORT ,Do not send the abort signal to the MPU whenever an MPU to TIPB access is aborted" "No mask,Mask"
|
|
bitfld.word 0x0 1. " MASK_IT ,Do not send the interrupt to the MPU whenever a TIPB write access (from MPU/DMA/OCP-I) is aborted or any TIPB access has a size mismatch" "No mask,Mask"
|
|
textline " "
|
|
bitfld.word 0x0 0. " TIMEOUT_EN ,Enable the TIMEOUT feature" "No,Yes"
|
|
rgroup.word 0x10++0xF
|
|
line.word 0x00 "ADDRESS_DBG,Private Debug Address Register"
|
|
line.word 0x04 "DATA_DEBUG_LOW,Private Debug Data LSB Register"
|
|
line.word 0x08 "DATA_DEBUG_HIGH,Private Debug Data MSB Register"
|
|
line.word 0x0c "DEBUG_CNTR_SIG,Private Debug Control Signals Register"
|
|
bitfld.word 0x0c 9.--10. " HOST_ID ,Host-ID that caused the abort" "MPU,DMA,OCP-I,?..."
|
|
bitfld.word 0x0c 8. " BURST_ACC ,Indicates single or burst access on the TIPB; saved when abort or access size mismatch occurs" "Single,Burst"
|
|
textline " "
|
|
bitfld.word 0x0c 6.--7. " DBG_PERHMAS ,Peripheral memory access size on TIPB; saved when abort or access size mismatch occurs" "8 bits,16 bits,32 bits,32 bits"
|
|
bitfld.word 0x0c 4.--5. " DBG_MAS ,Memory access size on TIPB; saved when abort or access size mismatch occurs" "8 bits,16 bits,32 bits,32 bits"
|
|
textline " "
|
|
bitfld.word 0x0c 3. " DBG_NSUPV ,Indicates supervisor mode status of MPU; saved when abort or access size mismatch occurs" "Yes,No"
|
|
bitfld.word 0x0c 2. " DBG_RNW ,Indicates read or write transaction on the TIPB; saved when abort or access size mismatch occurs" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x0c 1. " WR_SIZE_FLAG ,Mismatch between memory access size and peripheral memory access size" "No,Yes"
|
|
bitfld.word 0x0c 0. " ABORT_FLAG ,TIPB access is aborted" "No,Yes"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "ACCESS_CNTL,Private Access Control Register"
|
|
bitfld.word 0x00 3. " DPS_EN ,Dynamic power-saving mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MASK_OCPI_NABORT ,Mask OCPI abort before sending it back" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 1. " MASK_DMA_NABORT ,Mask DMA abort before sending it back" "No,Yes"
|
|
bitfld.word 0x00 0. " DMA_ENABLE ,DMA can access peripherals on the TIPB bridge" "Denied,Granted"
|
|
if (1==1)
|
|
group.word 0xA80++0x1
|
|
line.word 0x0 "SECURE_COND_REG,Security Condition Register"
|
|
bitfld.word 0x0 4. " IT_MASK ,Inactivate global mask" "Active,Inactive"
|
|
bitfld.word 0x0 3. " ETM_IF_EN ,Disable ETM interface" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 2. " OCPI_BLOCK ,Disable OCPI access on TIPB private" "Enabled,Disabled"
|
|
bitfld.word 0x0 1. " DMA_BLOCK ,Disable DMA access on TIPB private" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 0. " TRACE_DIS ,Disable TRACE operations" "Enabled,Disabled"
|
|
endif
|
|
tree.end
|
|
base AD:0xFFFECC00
|
|
tree "Traffic Controller OCP-T1/OCP-T2 Registers"
|
|
width 22.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "OCP_T1_PRIO,OCP-T1 LRU Priority Register"
|
|
hexmask.long.byte 0x00 12.--15. 1. " OCP_PRIORITY ,Number of consecutive accesses allowed for OCP-I"
|
|
hexmask.long.byte 0x00 8.--11. 1. " DMA_PRIORITY ,Number of consecutive accesses allowed for DMA"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--6. 1. " DSP_PRIORITY ,Number of consecutive accesses allowed for DSP"
|
|
hexmask.long.byte 0x00 0.--2. 1. " ARM_PRIORITY ,Number of consecutive access allowed for MPU"
|
|
group.long 0xA0++0xF
|
|
line.long 0x00 "OCP_T1_TIMEOUT1,OCP-T1 Dynamic Priority Time-out Register 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DMA ,Number of TC_CK cycles that DMA must wait in low-priority queue before going to high-priority queue"
|
|
line.long 0x04 "OCP_T1_TIMEOUT2,OCP-T1 Dynamic Priority Time-out Register 2"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DSP ,Number of TC_CK cycles that DSP must wait in low-priority queue before going to high-priority queue"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LCD ,Number of TC_CK cycles that LCD must wait in low-priority queue before going to high-priority queue"
|
|
line.long 0x08 "OCP_T1_TIMEOUT3,OCP-T1 Dynamic Priority Time-out Register 3"
|
|
hexmask.long.byte 0x08 0.--7. 1. " OCP-I ,Number of TC_CK cycles that OCP-I must wait in low-priority queue before going to high-priority queue"
|
|
line.long 0x0C "OCP_T1_ABORT_TIMEOUT,OCP-T1 Abort Time-out Register"
|
|
bitfld.long 0x0C 8. " TIMEOUT_EN ,Enable time-out bit" "No,Yes"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " TIMEOUT ,Number of counted-down clock cycles before sending out abort signal if there is no response from the slave"
|
|
rgroup.long 0xB0++0x7
|
|
line.long 0x00 "OCP_T1_ABORT_ADDR,OCP-T1 Abort Address"
|
|
line.long 0x04 "OCP_T1_ABORT_TYPE,OCP-T1 Abort Type"
|
|
bitfld.long 0x04 4. " TIMEOUT_ERR ,Abort generated by time-out register" "No,Yes"
|
|
bitfld.long 0x04 3. " BUS_ERR ,Abort generated by error coming from external peripherals" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1.--2. " HOST_ID ,Host ID of request that causes memory fault" "MPU,DSP,DMA,OCPI"
|
|
bitfld.long 0x04 0. " ABORT_FLAG ," "No abort,Abort"
|
|
group.long 0xB8++0x3
|
|
line.long 0x00 "CONFIG_REG,OCP Target Configuration Register"
|
|
bitfld.long 0x00 1. " PIPELN_RD_EN ,Pipeline read operation" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTO_GATED_CLK ,Autogating clock feature to save power" "Disabled,Enabled"
|
|
group.long 0xD0++0x13
|
|
line.long 0x00 "OCP_T2_PRIO,OCP-T2 LRU Priority Register"
|
|
hexmask.long.byte 0x00 12.--15. 1. " OCP_PRIORITY ,Number of consecutive accesses allowed for OCP-I"
|
|
hexmask.long.byte 0x00 8.--11. 1. " DMA_PRIORITY ,Number of consecutive accesses allowed for DMA"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--6. 1. " DSP_PRIORITY ,Number of consecutive accesses allowed for DSP"
|
|
hexmask.long.byte 0x00 0.--2. 1. " ARM_PRIORITY ,Number of consecutive access allowed for MPU"
|
|
line.long 0x04 "OCP_T2_TIMEOUT1,OCP-T2 Dynamic Priority Time-out Register 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DMA ,Number of TC_CK cycles that DMA must wait in low-priority queue before going to high-priority queue"
|
|
line.long 0x08 "OCP_T2_TIMEOUT2,OCP-T2 Dynamic Priority Time-out Register 2"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DSP ,Number of TC_CK cycles that DSP must wait in low-priority queue before going to high-priority queue"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LCD ,Number of TC_CK cycles that LCD must wait in low-priority queue before going to high-priority queue"
|
|
line.long 0x0C "OCP_T2_TIMEOUT3,OCP-T2 Dynamic Priority Time-out Register 3"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " OCP-I ,Number of TC_CK cycles that OCP-I must wait in low-priority queue before going to high-priority queue"
|
|
line.long 0x10 "OCP_T2_ABORT_TIMEOUT,OCP-T2 Abort Time Out"
|
|
bitfld.long 0x10 8. " TIMEOUT_EN ,Enable time-out bit" "No,Yes"
|
|
hexmask.long.byte 0x10 0.--7. 1. " TIMEOUT ,Number of counted-down clock cycles before sending out abort signal if there is no response from the slave"
|
|
rgroup.long 0xE4++0x7
|
|
line.long 0x00 "OCP_T2_ABORT_ADDR,OCP-T2 Abort Address Register"
|
|
line.long 0x04 "OCP_T2_ABORT_TYPE,OCP-T2 Abort Aype Register"
|
|
bitfld.long 0x04 4. " TIMEOUT_ERR ,Abort generated by time-out register" "No,Yes"
|
|
bitfld.long 0x04 3. " BUS_ERR ,Abort generated by error coming from external peripherals" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1.--2. " HOST_ID ,Host ID of request that causes memory fault" "MPU,DSP,DMA,OCPI"
|
|
bitfld.long 0x04 0. " ABORT_FLAG ,Abort flag" "No abort,Abort"
|
|
tree.end
|
|
tree "Traffic Controler EMIFS Register"
|
|
width 18.
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "EMIFS_PRIOR,EMIFS LRU priority register"
|
|
bitfld.long 0x00 12.--15. " OCPI ,OCPI consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
bitfld.long 0x00 8.--11. " DMA ,DMA consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DSP ,DSP consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7"
|
|
bitfld.long 0x00 0.--2. " MPU ,MPU consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7"
|
|
group.long 0xC++0x13
|
|
line.long 0x0 "EMIFS_CONFIG_REG,EMIFS Configuration Register"
|
|
bitfld.long 0x0 4. " FR ,Ready signal. This bit is a copy of the Ready input pin sample by TC_CK (2 TC_CK cycles delay from input pin to register update)" "Low,High"
|
|
bitfld.long 0x0 3. " PDE ,System power-down acknowledge" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 2. " PWD_EN ,Dynamic auto idle" "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " BM ,Boot mode. Enables CS0 and CS3 address decoding swapping" "Not swapped,Swapped"
|
|
textline " "
|
|
bitfld.long 0x0 0. " WP ,Write protect out pin control" "Low,High"
|
|
line.long 0x4 "EMIFS_CCS0,EMIFS Chip-select Configuration CS0 Register"
|
|
bitfld.long 0x4 31. " PGWSTEN ,PGWST is specified by" "WELEN,PGWST"
|
|
bitfld.long 0x4 27.--30. " PGWST ,Controls the wait states cycle number between accesses in a page for asychronous page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 23.--26. " BTWST ,Control the IDLE cycle number for bus turn-around and CS high-pulse-width timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 22. " MAD ,Enables EMIFS multiplexed address and data bus protocol" "Non-multiplexed,Multiplexed"
|
|
textline " "
|
|
bitfld.long 0x4 20. " BW ,Controls the data bus width used for this CS" "16b,32b"
|
|
bitfld.long 0x4 16.--18. " RDMODE ,Read mode select" "Asynchronous,Page ROM - 4 words,Page ROM - 8 words,Page ROM - 16 words,Synchronous burst,Synchronous burst,Reserved,Synchronous burst"
|
|
textline " "
|
|
bitfld.long 0x4 12.--15. " WELEN ,Controls the WE pulse length during a write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 8.--11. " WRWST ,Controls the wait states cycle number for write operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x4 4.--7. " RDWST ,Controls the wait states cycle number for asychronous read operation and the initial idle time for asynchronous read page mode and synchronous read mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x4 2. " RT ,Enable the read retimed protocol" "Non retimed,Retimed"
|
|
textline " "
|
|
bitfld.long 0x4 0.--1. " FCLKDIV ,Controls the TC_CK divider REF_CLK" "1,2,4,6"
|
|
line.long 0x8 "EMIFS_CCS1,EMIFS Chip-select Configuration CS1 Register"
|
|
bitfld.long 0x8 31. " PGWSTEN ,PGWST is specified by" "WELEN,PGWST"
|
|
bitfld.long 0x8 27.--30. " PGWST ,Controls the wait states cycle number between accesses in a page for asychronous page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 23.--26. " BTWST ,Control the IDLE cycle number for bus turn-around and CS high-pulse-width timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 22. " MAD ,Enables EMIFS multiplexed address and data bus protocol" "Non-multiplexed,Multiplexed"
|
|
textline " "
|
|
bitfld.long 0x8 20. " BW ,Controls the data bus width used for this CS" "16b,32b"
|
|
bitfld.long 0x8 16.--18. " RDMODE ,Read mode select" "Asynchronous,Page ROM - 4 words,Page ROM - 8 words,Page ROM - 16 words,Synchronous burst,Synchronous burst,Reserved,Synchronous burst"
|
|
textline " "
|
|
bitfld.long 0x8 12.--15. " WELEN ,Controls the WE pulse length during a write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 8.--11. " WRWST ,Controls the wait states cycle number for write operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x8 4.--7. " RDWST ,Controls the wait states cycle number for asychronous read operation and the initial idle time for asynchronous read page mode and synchronous read mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x8 2. " RT ,Enable the read retimed protocol" "Non retimed,Retimed"
|
|
textline " "
|
|
bitfld.long 0x8 0.--1. " FCLKDIV ,Controls the TC_CK divider REF_CLK" "1,2,4,6"
|
|
line.long 0xC "EMIFS_CCS2,EMIFS Chip-select Configuration CS2 Register"
|
|
bitfld.long 0xC 31. " PGWSTEN ,PGWST is specified by" "WELEN,PGWST"
|
|
bitfld.long 0xC 27.--30. " PGWST ,Controls the wait states cycle number between accesses in a page for asychronous page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 23.--26. " BTWST ,Control the IDLE cycle number for bus turn-around and CS high-pulse-width timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 22. " MAD ,Enables EMIFS multiplexed address and data bus protocol" "Non-multiplexed,Multiplexed"
|
|
textline " "
|
|
bitfld.long 0xC 20. " BW ,Controls the data bus width used for this CS" "16b,32b"
|
|
bitfld.long 0xC 16.--18. " RDMODE ,Read mode select" "Asynchronous,Page ROM - 4 words,Page ROM - 8 words,Page ROM - 16 words,Synchronous burst,Synchronous burst,Reserved,Synchronous burst"
|
|
textline " "
|
|
bitfld.long 0xC 12.--15. " WELEN ,Controls the WE pulse length during a write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 8.--11. " WRWST ,Controls the wait states cycle number for write operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0xC 4.--7. " RDWST ,Controls the wait states cycle number for asychronous read operation and the initial idle time for asynchronous read page mode and synchronous read mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0xC 2. " RT ,Enable the read retimed protocol" "Non retimed,Retimed"
|
|
textline " "
|
|
bitfld.long 0xC 0.--1. " FCLKDIV ,Controls the TC_CK divider REF_CLK" "1,2,4,6"
|
|
line.long 0x10 "EMIFS_CCS3,EMIFS Chip-select Configuration CS3 Register"
|
|
bitfld.long 0x10 31. " PGWSTEN ,PGWST is specified by" "WELEN,PGWST"
|
|
bitfld.long 0x10 27.--30. " PGWST ,Controls the wait states cycle number between accesses in a page for asychronous page mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 23.--26. " BTWST ,Control the IDLE cycle number for bus turn-around and CS high-pulse-width timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 22. " MAD ,Enables EMIFS multiplexed address and data bus protocol" "Non-multiplexed,Multiplexed"
|
|
textline " "
|
|
bitfld.long 0x10 20. " BW ,Controls the data bus width used for this CS" "16b,32b"
|
|
bitfld.long 0x10 16.--18. " RDMODE ,Read mode select" "Asynchronous,Page ROM - 4 words,Page ROM - 8 words,Page ROM - 16 words,Synchronous burst,Synchronous burst,Reserved,Synchronous burst"
|
|
textline " "
|
|
bitfld.long 0x10 12.--15. " WELEN ,Controls the WE pulse length during a write access" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 8.--11. " WRWST ,Controls the wait states cycle number for write operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x10 4.--7. " RDWST ,Controls the wait states cycle number for asychronous read operation and the initial idle time for asynchronous read page mode and synchronous read mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 2. " RT ,Enable the read retimed protocol" "Non retimed,Retimed"
|
|
textline " "
|
|
bitfld.long 0x10 0.--1. " FCLKDIV ,Controls the TC_CK divider REF_CLK" "1,2,4,6"
|
|
group.long 0x28++0xF
|
|
line.long 0x0 "EMIFS_TIMEOUT1,EMIFS Dynamic Priority Timeout 1 Register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " DMA ,Number of TC_CK cycles"
|
|
line.long 0x4 "EMIFS_TIMEOUT2,EMIFS Dynamic Priority Timeout 2 Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " DSP ,Number of TC_CK cycles"
|
|
line.long 0x8 "EMIFS_TIMEOUT3,EMIFS Dynamic Priority Timeout 3 Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " OCPI ,Number of TC_CK cycles"
|
|
line.long 0xC "ENDIANISM,DSP Endianism Register"
|
|
bitfld.long 0xC 1. " SWAP ,Byte/Word Swap" "Byte,Word"
|
|
bitfld.long 0xC 0. " EN ,Enable DSP Endianism Conversion" "Disabled,Enabled"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "EMIFS_DWS,EMIFS Dynamic Wait-States Register"
|
|
bitfld.long 0x0 7. " CS3_HNDSHK ,Full handshaking mode for CS3" "Full,Non-full"
|
|
bitfld.long 0x0 6. " CS2_HNDSHK ,Full handshaking mode for CS2" "Full,Non-full"
|
|
textline " "
|
|
bitfld.long 0x0 5. " CS1_HNDSHK ,Full handshaking mode for CS1" "Full,Non-full"
|
|
bitfld.long 0x0 4. " CS0_HNDSHK ,Full handshaking mode for CS0" "Full,Non-full"
|
|
textline " "
|
|
bitfld.long 0x0 3. " CS3_DYN_WS ,Dynamic wait states mode for CS3" "Disabled,Enabled"
|
|
bitfld.long 0x0 2. " CS2_DYN_WS ,Dynamic wait states mode for CS2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0 1. " CS1_DYN_WS ,Dynamic wait states mode for CS1" "Disabled,Enabled"
|
|
bitfld.long 0x0 0. " CS0_DYN_WS ,Dynamic wait states mode for CS0" "Disabled,Enabled"
|
|
rgroup.long 0x44++0x7
|
|
line.long 0x00 "EMIFS_AADDR,EMIFS Abort Address Register"
|
|
line.long 0x04 "EMIFS_ATYPER,EMIFS Abort Type Register"
|
|
bitfld.long 0x04 4. " TOE ,Time out error" "No,Yes"
|
|
bitfld.long 0x04 3. " RAE ,Restricted access error" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 1.--2. " HID ,Host ID" "MPU,DSP,DMA,OCP-I"
|
|
bitfld.long 0x04 0. " ABORT_FLAG ,Abort status" "No abort,Abort"
|
|
group.long 0x4C++0x13
|
|
line.long 0x00 "EMIFS_ATOR,EMIFS Abort Timeout Register"
|
|
bitfld.long 0x00 8. " TIMEOUT_EN ,Enable the time-out timer" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TIMEOUT ,Time out counter value in REF_CLK clock cycles"
|
|
line.long 0x04 "EMIFS_ACS0,Advanced EMIFS Chip Select Configuration Register nCS0"
|
|
bitfld.long 0x04 9. " BTMODE ,Enables extended BTWST usage" "RD to RD/WR, RD/WR to RD/WR"
|
|
bitfld.long 0x04 8. " ADVHOLD ,Controls the ADV pulse width low" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " OEHOLD ,Controls the number of cycles from OE high to CS high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x04 0.--3. " OESETUP ,Controls the number of cycles inserted from CS low OE low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x08 "EMIFS_ACS1,Advanced EMIFS Chip Select Configuration Register nCS1"
|
|
bitfld.long 0x08 9. " BTMODE ,Enables extended BTWST usage" "RD to RD/WR, RD/WR to RD/WR"
|
|
bitfld.long 0x08 8. " ADVHOLD ,Controls the ADV pulse width low" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 4.--7. " OEHOLD ,Controls the number of cycles from OE high to CS high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x08 0.--3. " OESETUP ,Controls the number of cycles inserted from CS low OE low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x0c "EMIFS_ACS2,Advanced EMIFS Chip Select Configuration Register nCS2"
|
|
bitfld.long 0x0c 9. " BTMODE ,Enables extended BTWST usage" "RD to RD/WR, RD/WR to RD/WR"
|
|
bitfld.long 0x0c 8. " ADVHOLD ,Controls the ADV pulse width low" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0c 4.--7. " OEHOLD ,Controls the number of cycles from OE high to CS high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x0c 0.--3. " OESETUP ,Controls the number of cycles inserted from CS low OE low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.long 0x10 "EMIFS_ACS3,Advanced EMIFS Chip Select Configuration Register nCS3"
|
|
bitfld.long 0x10 9. " BTMODE ,Enables extended BTWST usage" "RD to RD/WR, RD/WR to RD/WR"
|
|
bitfld.long 0x10 8. " ADVHOLD ,Controls the ADV pulse width low" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x10 4.--7. " OEHOLD ,Controls the number of cycles from OE high to CS high" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 0.--3. " OESETUP ,Controls the number of cycles inserted from CS low OE low" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
tree "Traffic Controller EMIFF Registers"
|
|
width 22.
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "EMIFF_PRIOR,EMIFF Priority Register"
|
|
bitfld.long 0x00 12.--15. " OCPI ,OCPI consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
bitfld.long 0x00 8.--11. " DMA ,DMA consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7,0x8,0x9,0xA,0xB,0xC,0xD,0xE,0xF"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " DSP ,DSP consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7"
|
|
bitfld.long 0x00 0.--2. " MPU ,MPU consecutive access" "0x0,0x1,0x2,0x3,0x4,0x5,0x6,0x7"
|
|
group.long 0x20++0x7
|
|
line.long 0x0 "EMIFF_SDRAM_CONFIG,EMIFF SDRAM Configuration Register"
|
|
bitfld.long 0x0 28.--29. " LG_SDRAM ,Used to define the larger SDRAM memories" "00,01,10,11"
|
|
bitfld.long 0x0 27. " CLK ,Disable SDRAM closk" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 26. " PWD ,Power down enable" "No,Yes"
|
|
bitfld.long 0x0 24.--25. " SDRAM_FREQ ,SDRAM frequency range" "SDF0,SDF1,SDF2,SDF3"
|
|
textline " "
|
|
hexmask.long.word 0x0 8.--23. 1. " ARCV ,Autorefresh counter register value"
|
|
bitfld.long 0x0 4.--7. " SDRAM_TYPE ,Set the SDRAM internal organization" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " ARE ,Autorefresh enable" "Disabled,Enabled,Burst of 4 cmds,Burst of 8 cmds"
|
|
bitfld.long 0x0 0. " SLRF ,Self-refresh" "Disabled,Enabled"
|
|
line.long 0x4 "EMIFF_MRS,EMIFF SDRAM MRS Register"
|
|
bitfld.long 0x4 9. " WBST ,Write burst" "Proper,Erratic"
|
|
bitfld.long 0x4 4.--6. " CASL ,CAS idle time" "0,Reserved,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x4 3. " S/I ,Serial/Interleave" "Serial,Interleave"
|
|
bitfld.long 0x4 0.--2. " PGBL ,Page burst length" "000,001,010,011,100,101,110,111"
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "EMIFF_SDRAM_CONFIG_2,EMIFF SDRAM Configuration Register 2"
|
|
bitfld.long 0x0 2. " SD_AUTO_CLK ,Allow controller to suspend its internal clocks when idle." "Disabled,Enabled"
|
|
bitfld.long 0x0 1. " RFRSH_RESET ,Place the SDRAM into self_refresh when in reset (active high)" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 0. " RFRSH_STBY ,Place the SDRAM into self_refresh when in standby mode (active high" "No,Yes"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "DLL_WRT_CTL,DLL WRT Control Register (write byte)"
|
|
bitfld.long 0x0 20.--25. " WO ,Write offset" "-32,-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x0 8.--15. 1. " DLY ,Delay"
|
|
textline " "
|
|
bitfld.long 0x0 3. " LDLL ,Load DLL" "No action,Load"
|
|
bitfld.long 0x0 2. " DLLP ,DLLPhase" "72 deg,90 deg"
|
|
textline " "
|
|
bitfld.long 0x0 1. " ENADLL ,Enable DLL" "No,Yes"
|
|
rgroup.long 0x68++0x3
|
|
line.long 0x00 "DLL_WRT_STAT,DLL WRT Status Register (read lower byte)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " CNT ,DLL Count. Current DLL counter value"
|
|
bitfld.long 0x00 2. " LOCK ,DLL lock status" "Not locked,Property locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UDF ,DLL counter underflow status" "OK,Underflow"
|
|
bitfld.long 0x00 0. " OVF ,DLL counter overflow status" "OK,Overflow"
|
|
group.long 0x70++0xB
|
|
line.long 0x00 "EMIFF_MRS_NEW,EMIFF SDRAM MRS Register (duplicate)"
|
|
bitfld.long 0x00 9. " WBST ,Write burst" "Proper,Erratic"
|
|
bitfld.long 0x00 8. " RESET_DLL ,Reset the memory device DLL" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " CASL ,CAS idle time" "0,Reserved,2,3,4,5,6,7"
|
|
bitfld.long 0x00 3. " S/I ,Serial/Interleave" "Serial,Interleave"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " PGBL ,Page burst length" "000,001,010,011,100,101,110,111"
|
|
line.long 0x04 "EMIFF_EMRS0,EMIFF SDRAM EMRS 0 Register"
|
|
bitfld.long 0x04 2. " QFC ,QFC enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " DS ,DS driver strength bit" "Normal,Reduced"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DLL ,DLL enable bit" "Enabled,Disabled"
|
|
line.long 0x08 "EMIFF_EMRS1,EMIFF SDRAM EMRS 1 Register"
|
|
bitfld.long 0x08 3.--4. " TCSR ,Temperature-compensated self-refresh" "70 C max,45 C max,15 C max,85 C max"
|
|
bitfld.long 0x08 0.--2. " PASR ,Partial-array self-refresh" "All banks,1/2 array,1/4 array,Reserved,Reserved,1/8 array,1/16 array,?..."
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "EMIFF_OP,EMIFF SDRAM Operation Register"
|
|
hexmask.long.byte 0x0 25.--31. 1. " TIME_OUT_B3 ,Time-out value for Bank3, in TC clock cycles"
|
|
hexmask.long.byte 0x0 18.--24. 1. " TIME_OUT_B2 ,Time-out value for Bank2, in TC clock cycles"
|
|
textline " "
|
|
hexmask.long.byte 0x0 11.--17. 1. " TIME_OUT_B1 ,Time-out value for Bank1, in TC clock cycles"
|
|
hexmask.long.byte 0x0 4.--10. 1. " TIME_OUT_B0 ,Time-out value for Bank0, in TC clock cycles"
|
|
textline " "
|
|
bitfld.long 0x0 2.--3. " OP_MODE ,Operation Mode" "LPLB,HPHB,POM0,?..."
|
|
bitfld.long 0x0 0.--1. " SDRAM_TYPE ,The type of SDRAM" "Regular SDR,Regular DDR,Low-power SDR,Mobile DDR"
|
|
line.long 0x4 "EMIFF_MCMD,EMIFF SDRAM Manual Command Register"
|
|
bitfld.long 0x4 0.--3. " SDRAM ,Manual command" "NOP,Precharge,Autorefresh,Enter deep sleep,Exit deep sleep,Set CKE high,Set CKE low,?..."
|
|
group.long 0x8C++0xB
|
|
line.long 0x0 "EMIFF_TIMEOUT1,EMIFF Dynamic Arb. Timeout 1"
|
|
hexmask.long.byte 0x0 0.--7. 1. " DMA ,Number of clock cycles before DMA requests"
|
|
line.long 0x4 "EMIFF_TIMEOUT2,EMIFF Dynamic Arb. Timeout 2"
|
|
hexmask.long.byte 0x4 16.--23. 1. " DSP ,Number of clock cycles before DSP requests"
|
|
hexmask.long.byte 0x4 0.--7. 1. " LCD ,Number of clock cycles before LCD requests"
|
|
line.long 0x8 "EMIFF_TIMEOUT3,EMIFF Dynamic Arb. Timeout 3"
|
|
hexmask.long.byte 0x8 0.--7. 1. " L3 ,Number of clock cycles before L3 OCP initiator requests"
|
|
rgroup.long 0x98++0x7
|
|
line.long 0x00 "EMIFF_AADDR,EMIFF Abort Address Register"
|
|
line.long 0x04 "EMIFF_ATYPER,EMIFF Abort Type Register"
|
|
bitfld.long 0x04 1.--2. " HOSTID ,ID of the host whose transaction was aborted" "MPU,DSP,DMA,OCP-I"
|
|
bitfld.long 0x04 0. " ABORT_FLAG ,Set when an abort accurs; reset when this register is read" "No,Yes"
|
|
rgroup.long 0xBC++0x03
|
|
line.long 0x00 "EMIFF_DLL_LRD_STAT,DLLS LRD Status Register (Reserved)"
|
|
group.long 0xC0++0x3
|
|
line.long 0x00 "DLL_URD_CTL,DLL URD Control Register (read upper byte)"
|
|
bitfld.long 0x00 20.--25. " RO ,Read offset" "-32,-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DELAY "
|
|
textline " "
|
|
bitfld.long 0x00 3. " LOADDLL ,Allows loading the delay value into the DLL" "No action,Load DLL"
|
|
bitfld.long 0x00 2. " DLLPHASE " "72 deg,90 deg"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ENADLL ,Enable DLL" "No,Yes"
|
|
rgroup.long 0xC4++0x7
|
|
line.long 0x00 "DLL_URD_STAT,DLL Status Register (read upper byte)"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DLLCOUNT ,Current DLL counter value"
|
|
bitfld.long 0x00 2. " LOCK ,DLL Lock status" "Not locked,Properly locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UDF ,DLL counter underflow status" "OK,Underflow"
|
|
bitfld.long 0x00 0. " OVF ,DLL counter overflow status" "OK,Overflow"
|
|
line.long 0x04 "EMIFF_EMRS2,EMIFF SDRAM EMRS 2 Register (Reserved)"
|
|
group.long 0xCC++0x3
|
|
line.long 0x00 "DLL_LRD_CTL,DLL LRD Control Register (read lower byte)"
|
|
bitfld.long 0x00 20.--25. " RO ,Read offset" "-32,-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,-3,-2,-1,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
base AD:0xFFFEC320
|
|
tree "Traffic Controller OCPI Registers"
|
|
width 13.
|
|
rgroup.long 0x00++0x7
|
|
line.long 0x00 "OCPI_AFR,OCPI Address Fault Register"
|
|
line.long 0x04 "OCPI_MCFR,OCP Master Command Fault Register"
|
|
bitfld.long 0x04 0.--2. " MCMD ,Command that causes an abort or error" "Idle,Write,Read,ReadEX,?..."
|
|
;group.long 0x08++0x3
|
|
; line.long 0x00 "OCP_SINT0,OCP Sinterrupt 0 Register"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "OCPI_ATYPER,OCP Abort Type Register"
|
|
bitfld.long 0x0 3. " BURST_ERROR ,Burst access to the MPUI or TIPB was requested" "No,Yes"
|
|
bitfld.long 0x0 2. " PROTECT ,Address hit a protected area" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 1. " TRGABORT ,Abort coming from the accessed target" "No,Yes"
|
|
bitfld.long 0x0 0. " ADDDEC ,Address decoding error (initiator sent unknown address)" "No,Yes"
|
|
;group.long 0x10++0x3
|
|
;line.long 0x0 "OCPI_SINT1,OCP Sinterrupt 1 Register"
|
|
group.long 0x14++0x7
|
|
line.long 0x0 "OCPI_PR,OCP Protection Register"
|
|
bitfld.long 0x0 7. " API ,Access to MPUI is prohibited" "No,Yes"
|
|
bitfld.long 0x0 6. " RHEA_PUB ,Access to MPU public TIPB is prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 5. " RHEA_PRIV ,Access to MPU private TIPB is prohibited" "No,Yes"
|
|
bitfld.long 0x0 4. " OCPMULT ,Access to OCPT multibank is prohibited " "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 3. " OCPT2 ,Access to OCPT2 is prohibited" "No,Yes"
|
|
bitfld.long 0x0 2. " OCPT1 ,Access to OCPT1 is prohibited" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x0 1. " EMIFF ,Access to EMIFF is prohibited" "No,Yes"
|
|
bitfld.long 0x0 0. " EMIFS ,Access to EMIFS is prohibited" "No,Yes"
|
|
line.long 0x4 "OCPI_SMR,OCPI Secure Mode Register"
|
|
bitfld.long 0x4 6. " API ,Access to API in secure mode" "Allowed,Prohibited"
|
|
bitfld.long 0x4 5. " RHEA_PRIV ,Access to MPU_TIPB public in secure mode" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x4 4. " OCP_MULT ,Access to OCP multibank in secure mode" "Allowed,Prohibited"
|
|
bitfld.long 0x4 3. " OCPT2 ,Access to OCPT2 in secure mode" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x4 2. " OCPT1 ,Access to OCPT1 in secure mode" "Allowed,Prohibited"
|
|
bitfld.long 0x4 1. " EMIFF ,Access to EMIFF in secure mode" "Allowed,Prohibited"
|
|
textline " "
|
|
bitfld.long 0x4 0. " EMIFS ,Access to EMIFS CS1-CS3 in secure mode" "Allowed,Prohibited"
|
|
tree.end
|
|
base AD:0xFFFECE00
|
|
tree "MPU Clock/Reset/Power Mode Control Registers"
|
|
width 13.
|
|
group.long 0x00++0x27
|
|
line.long 0x00 "ARM_CKCTL,MPU Clock Control Register"
|
|
bitfld.long 0x00 14. " ARM_INTHCK_SEL ,This bit controls which clock is used for the ARM_INTH_CK" "Full freq ARM_CK,Half freq ARM_CK"
|
|
bitfld.long 0x00 13. " EN_DSPCK ,Turns on DSP_CK while the DSP is still in reset state" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ARM_TIMXO ,Select a subfrequency to supply internal MPU timers" "CK_REF,CK_GEN1"
|
|
bitfld.long 0x00 10.--11. " DSPMMUDIV ,Define prescaler value from the frequency of CK_GEN2 to DSPMMU clock domain" "CK_GEN2,CK_GEN2/2,CK_GEN2/4,CK_GEN2/8"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " TCDIV ,Define prescaler value from the frequency of CK_GEN3 to TC clock domain" "CK_GEN3,CK_GEN3/2,CK_GEN3/4,CK_GEN3/8"
|
|
bitfld.long 0x00 6.--7. " DSPDIV ,Define prescaler value from the frequency of CK_GEN2 to DSP clock domain" "CK_GEN2,CK_GEN2/2,CK_GEN2/4,CK_GEN2/8"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ARMDIV ,Define prescaler value from the frequency of CK_GEN1 to MPU clock domain" "CK_GEN1,CK_GEN1/2,CK_GEN1/4,CK_GEN1/8"
|
|
bitfld.long 0x00 2.--3. " LCDDIV ,Define prescaler value from the frequency of CK_GEN3 to LCD controller clock signal" "CK_GEN3,CK_GEN3/2,CK_GEN3/4,CK_GEN3/8"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " ARM_PERDIV ,Define prescaler value from the frequency of CK_GEN1 to MPU external peripheral clock domain" "CK_GEN1,CK_GEN1/2,CK_GEN1/4,CK_GEN1/8"
|
|
line.long 0x04 "ARM_IDLECT1,MPU Idle Control 1 Register"
|
|
bitfld.long 0x04 12. " IDL_CLKOUT_ARM ,Idle entry mode for the external DPLL output clock" "Active,Stopped"
|
|
bitfld.long 0x04 10. " WKUP_MODE ,Controls how the MPU can exit the CHIP_IDLE state (CHIP_nWKUP dependence)" "Dependent,Independent"
|
|
textline " "
|
|
bitfld.long 0x04 9. " IDLTIM_ARM ,Selects the idle entry mode for the internal MPU timer clock" "Active,Stopped"
|
|
bitfld.long 0x04 8. " IDLAPI_ARM ,Selects the idle entry mode for MPUI clock" "EN_APICK control,On on request"
|
|
textline " "
|
|
bitfld.long 0x04 7. " IDLDPLL_ARM ,Enables the DPLL macro to enter idle mode when DSP is set to global_idle mode; MPU is in idle mode; no active DMA transaction or TCLB_EN pin is asserted low; no TIPB posted write is queued; and the peripheral clocks are stopped" "Active,Idle"
|
|
bitfld.long 0x04 6. " IDLIF_ARM ,Enables the TIPB bridge; the system DMA controller; and the TC to enter idle mode when the MPU processor executes the wait-for-interrupt instruction (the clocks)" "Active,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 2. " IDLPER_ARM ,Selects idle entry mode for external peripheral clock (ARMPER_CK)" "Active,Stopped"
|
|
bitfld.long 0x04 1. " IDLXORP_ARM ,Selects idle entry mode for external reference peripheral clock ARMXOR_CK" "Active,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 0. " IDLWDT_ARM ,Selects the idle entry mode for internal timer/watchdog connected to MPU TIPB (if not watchdog)" "Active,Stopped"
|
|
line.long 0x08 "ARM_IDLECT2,MPU Idle Control 2 Register"
|
|
bitfld.long 0x08 11. " EN_CKOUT_ARM ,Enable the free running clock from DPLL1 output" "No,Yes"
|
|
bitfld.long 0x08 8. " DMACK_REQ ,Disables the permanently-supplied-clock to the system DMA controller to function on a clock request basis" "Shutdown,On on DMA request"
|
|
textline " "
|
|
bitfld.long 0x08 7. " EN_TIMCK ,Enable the MPU internal timer clock connected to the MPU TIPB" "No,Yes"
|
|
bitfld.long 0x08 6. " EN_APICK ,Enable the clock of the MPUI" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 3. " EN_LCDCK ,Enable the clock of the LCD controller connected to MPU TIPB" "No,Yes"
|
|
bitfld.long 0x08 2. " EN_PERCK ,Enable the external peripheral clock" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 1. " EN_XORCK ,Enable the clock of the OS timer connected to MPU TIPB and the external reference peripheral clock" "No,Yes"
|
|
bitfld.long 0x08 0. " EN_WDTCK ,Enable the clock of the timer/watchdog connected to MPU TIPB (if watchdog - always on)" "Disabled,Enabled"
|
|
line.long 0x0c "ARM_EWUPCT,MPU External Wake-up Control Register"
|
|
bitfld.long 0x0c 5. " REPWR_EN ,Enable the external power control feature (state of /FLASH.RP when TC in idle mode)" "Low,High"
|
|
hexmask.long.byte 0x0c 0.--4. 1. " EXTPWR ,Define the delay from /FLASH.RP pin going high to the clocks restarting. Reference clock is the EMIFS CK_REF"
|
|
line.long 0x10 "ARM_RSTCT1,MPU Reset Control 1 Register"
|
|
bitfld.long 0x10 3. " SW_RST ,Global system reset" "No reset,Reset"
|
|
bitfld.long 0x10 2. " DSP_RST ,Resets the priority registers (TIPB module); the EMIF configuration registers; and the MPUI control logic in the DSP" "Reset,No reset"
|
|
textline " "
|
|
bitfld.long 0x10 1. " DSP_EN ,Reset/Enable the DSP" "Reset,Enabled"
|
|
bitfld.long 0x10 0. " ARM_RST ,Reset/Enable the MPU" "Enabled,Reset"
|
|
line.long 0x14 "ARM_RSTCT2,MPU Reset Control 2 Register"
|
|
bitfld.long 0x14 0. " PER_EN ,MPU peripheral reset/enable" "Reset,Enabled"
|
|
line.long 0x18 "ARM_SYSST,MPU System Status Register"
|
|
bitfld.long 0x18 11.--13. " CLOCK_SELECT , Clock select " "Full sync,Reserved,Sync scalable,Reserved,Reserved,Bypass,Mix mode #3,Mix mode #4"
|
|
bitfld.long 0x18 6. " IDLE_DSP ,Indicates the DSP state" "Active,Global idle"
|
|
textline " "
|
|
bitfld.long 0x18 5. " POR ,Indicates whether or not a power-on-reset (cold start) has occured" "Not occured,Occured"
|
|
bitfld.long 0x18 4. " EXT_RST ,An external reset has been asserted" "Not occured,Occured"
|
|
textline " "
|
|
bitfld.long 0x18 3. " ARM_MCRST ,An MPU reset has occured" "Not occured,Occured"
|
|
bitfld.long 0x18 2. " ARM_WDRST ,A reset has been asserted due to an MPU timer/watchdog underflow" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 1. " GLOB_SWRST ,A reset has been asserted due to global software reset" "No,Yes"
|
|
bitfld.long 0x18 0. " DSP_WDRST ,A reset has been asserted due to DSP timer/watchdog underflow" "No,Yes"
|
|
line.long 0x1c "ARM_CKOUT1,MPU Clock Out Definition Register 1"
|
|
bitfld.long 0x1c 4.--5. " TCLKOUT ,POCLKOUT3 pin function" "Reserved,CK_GEN3 output,TC_CK output,?..."
|
|
bitfld.long 0x1c 2.--3. " DCLKOUT ,POCLKOUT2 pin function" "DSPMMU_CK output,CK_GEN2 output,DSP_CK output,CK_REF/14 output"
|
|
textline " "
|
|
bitfld.long 0x1c 0.--1. " ACLKOUT ,POCLKOUT1 pin function" "Reserved,CK_GEN1 output,ARM_CK output,CK_REF/14 output"
|
|
line.long 0x20 "ARM_CKOUT2,MPU Clock Out Definition Register 2 (Reserved)"
|
|
line.long 0x24 "ARM_IDLECT3,MPU Idle Enable Control Register 3"
|
|
bitfld.long 0x24 5. " IDLTC2_ARM ,Select the idle entry mode for TC2 clock" "Active,Stopped"
|
|
bitfld.long 0x24 4. " EN_TC2_CK ,Enable the TC2 clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 3. " IDLTC1_ARM ,Select the idle entry mode for TC1 clock" "Active,Stopped"
|
|
bitfld.long 0x24 2. " EN_TC1_CK ,Enable the TC1 clock" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x24 1. " IDLOCPI_ARM ,Select the idle entry mode for the L3 OCP initiator clock" "Active,Stopped"
|
|
bitfld.long 0x24 0. " EN_OCPI_CK ,Enable the L3 OCPI clock" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFECF00
|
|
tree "DPLL Configuration Register"
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "DPLL1_CTL_REG,DPLL1 Control Register"
|
|
bitfld.word 0x00 15. " LS_DISABLE ,Level shifter power-down pin mode" "Transparent,Isolated"
|
|
bitfld.word 0x00 14. " IAI ,Initialize after idle" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 13. " IOB ,Initialize on break" "Bypass mode,Continue the clock"
|
|
bitfld.word 0x00 12. " TEST ,Controls the test output clock on the DPLL_TCLKOUT pin" "DPLL1 (test)/0 (else),DPLL1/32 (test)/0 (else)"
|
|
textline " "
|
|
bitfld.word 0x00 7.--11. " PLL_MULT ,DPLL multiply value" "CLKREF,CLKREF,CLKREFx2,CLKREFx3,CLKREFx4,CLKREFx5,CLKREFx6,CLKREFx7,CLKREFx8,CLKREFx9,CLKREFx10,CLKREFx11,CLKREFx12,CLKREFx13,CLKREFx14,CLKREFx15,CLKREFx16,CLKREFx17,CLKREFx18,CLKREFx19,CLKREFx20,CLKREFx21,CLKREFx22,CLKREFx23,CLKREFx24,CLKREFx25,CLKREFx26,CLKREFx27,CLKREFx28,CLKREFx29,CLKREFx30,CLKREFx31"
|
|
bitfld.word 0x00 5.--6. " PLL_DIV ,DPLL divide value " "CKREF,CKREF/2,CKREF/3,CKREF/4"
|
|
textline " "
|
|
bitfld.word 0x00 4. " PLL_ENABLE ,Request the DPLL to enter the lock mode" "Bypass mode,Lock mode"
|
|
bitfld.word 0x00 2.--3. " BYPASS_DIV ,Determines the clock out frequency when in bypass mode" "CK_REF,CK_REF/2,CK_REF/4,CK_REF/4"
|
|
textline " "
|
|
bitfld.word 0x00 1. " BREAKLN ,Indicates whether DPLL has broken lock for some unknown reason" "Broken lock,OK/Writing to reg."
|
|
bitfld.word 0x00 0. " LOCK ,Indicates if DPLL is in lock mode and the clock out has the desired synthesized frequency" "Bypass mode,Lock mode"
|
|
group.word 0x100++0x1
|
|
line.word 0x00 "DPLL2_CTL_REG,DPLL2 Control Register (Reserved)"
|
|
tree.end
|
|
base AD:0xFFFED200
|
|
tree "DSP MMU Registers"
|
|
width 25.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "DSP_MMU_PREFETCH_REG,DSP MMU Prefetch Register"
|
|
hexmask.long.word 0x00 0.--13. 1. " PREF_ADDR ,MSB of virtual address of the TLB entry to be prefetched"
|
|
rgroup.long 0x04++0x3
|
|
line.long 0x00 "DSP_MMU_WALKING_ST_REG,DSP MMU Prefetch Status Register"
|
|
bitfld.long 0x00 1. " WALK_WORKING ,The table walking logic is handling a page miss" "No,Yes"
|
|
bitfld.long 0x00 0. " PREFETCH_ON ,The prefetch register" "Acknowledged,Written"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "DSP_MMU_CNTL_REG,DSP MMU Control Register"
|
|
bitfld.long 0x00 2. " WTL_EN ,Enables the table walking logic" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MMU_EN ,Enables the MMU" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RESET_SW ,Resets the module" "No,Yes"
|
|
rgroup.long 0x0C++0xb
|
|
line.long 0x00 "DSP_MMU_FAULT_AD_H_REG,DSP MMU Fault Address Register MSB"
|
|
hexmask.long.byte 0x00 0.--7. 1. " FAULT_ADDRESS_MSB ,MSB of logical address of the access that generated a permission fault"
|
|
line.long 0x04 "DSP_MMU_FAULT_AD_L_REG,DSP MMU Fault Address Register LSB"
|
|
hexmask.long.word 0x04 0.--7. 1. " FAULT_ADDRESS_LSB ,LSB of logical address of the access that generated a permission fault"
|
|
line.long 0x08 "DSP_MMU_F_ST_REG,DSP MMU Fault Status Register"
|
|
bitfld.long 0x08 3. " PREFETCH_ERR ,This error occurs during a prefetch" "No,Yes"
|
|
bitfld.long 0x08 2. " PERM_FAULT ,Permission fault" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x08 1. " TLB_MISS ,TLB miss (when WIB is disabled)" "No,Yes"
|
|
bitfld.long 0x08 0. " TRANS_FAULT ,Translation fault (invalid descriptor)" "No,Yes"
|
|
wgroup.long 0x18++0x3
|
|
line.long 0x00 "DSP_MMU_IT_ACK_REG,DSP MMU IT Acknowledge Register"
|
|
bitfld.long 0x00 0. " IT_ACK ,Acknowledge the interrupt" "No,Yes"
|
|
group.long 0x1C++0x27
|
|
line.long 0x00 "DSP_MMU_TTB_H_REG,DSP MMU TTB Register MSB"
|
|
hexmask.long.word 0x00 0.--7. 1. " TTB_H_REG ,MSB of TTB"
|
|
line.long 0x04 "DSP_MMU_TTB_L_REG,DSP MMU TTB Register LSB"
|
|
hexmask.long.word 0x04 7.--15. 1. " TTB_L_REG ,LSB of TTB"
|
|
line.long 0x08 "DSP_MMU_LOCK_REG,DSP MMU Lock Counter Register"
|
|
hexmask.long.byte 0x08 10.--15. 1. " BASE_VALUE ,Locked entries base value"
|
|
hexmask.long.byte 0x08 4.--9. 1. " CURRENT_VICTIM ,Current entry pointed by the hardware table walk logic"
|
|
line.long 0x0c "DSP_MMU_LD_TLB_REG,DSP MMU Load Entry TLB Register"
|
|
bitfld.long 0x0c 0. " LD_TLB_ITEM ,Load data in TLB" "No,Yes"
|
|
line.long 0x10 "DSP_MMU_CAM_H_REG,DSP MMU CAM Entry Register MSB"
|
|
hexmask.long.word 0x10 0.--7. 1. " VA_TAB_L1_H ,Table index level 1 MSB"
|
|
line.long 0x14 "DSP_MMU_CAM_L_REG,DSP MMU CAM Entry Register LSB"
|
|
hexmask.long.byte 0x14 14.--15. 1. " VA_TAG_L1_L ,Table index level 1 LSB which means bits (21:20) of logical address"
|
|
hexmask.long.word 0x14 4.--13. 1. " VA_TAB_L2 ,Table index level 2"
|
|
textline " "
|
|
bitfld.long 0x14 3. " P ,Preserved bit" "No,Yes"
|
|
bitfld.long 0x14 2. " V ,Valid bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x14 0.--1. " SLST ,SLST" "1MB,64KB,4KB,1KB"
|
|
line.long 0x18 "DSP_MMU_RAM_H_REG,DSP MMU RAM Entry Register MSB"
|
|
hexmask.long.word 0x18 0.--7. 1. " RAM_MSB ,MSB physical address"
|
|
line.long 0x1c "DSP_MMU_RAM_L_REG,DSP MMU RAM Entry Register LSB"
|
|
hexmask.long.byte 0x1c 10.--15. 1. " RAM_LSB ,LSB physical address"
|
|
hexmask.long.byte 0x1c 8.--9. 1. " AP ,Access permission bits"
|
|
line.long 0x20 "DSP_MMU_GFLUSH_REG,DSP MMU Global Flush Register"
|
|
bitfld.long 0x20 0. " GLOBAL_FLUSH ,Flush all the nonprotected TLB entries" "No,Yes"
|
|
line.long 0x24 "DSP_MMU_FLUSH_ENTRY_REG,DSP MMU Individual Flush Register"
|
|
bitfld.long 0x24 0. " FLUSH_ENTRY ,Flush the TLB entry pointed by the logical address in CAM_H_REG and CAM_L_REG registers (even if this entry is set protected)" "No,Yes"
|
|
rgroup.long 0x44++0x0F
|
|
line.long 0x00 "DSP_MMU_READ_CAM_H_REG,MMU Read CAM Register MSB"
|
|
hexmask.long.byte 0x00 0.--2. 1. " VA_TAG_L1_H ,Table index level 1 MSB"
|
|
line.long 0x04 "DSP_MMU_READ_CAM_L_REG,MMU Read CAM Register LSB"
|
|
hexmask.long.byte 0x04 14.--15. 1. " VA_TAG_L1_L ,Table index level 1 LSB which means bits (21:20) of logical address"
|
|
hexmask.long.word 0x04 4.--13. 1. " VA_TAG_L2 ,Table index level 2"
|
|
textline " "
|
|
bitfld.long 0x04 3. " P ,Preserved bit" "No,Yes"
|
|
bitfld.long 0x04 2. " V ,Valid bit" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SLST ,SLST" "1MB,64KB,4KB,1KB"
|
|
line.long 0x08 "DSP_MMU_READ_RAM_H_REG,MMU Read RAM Register MSB"
|
|
hexmask.long.word 0x08 0.--7. 1. " RAM_MSB ,MSB psychical address"
|
|
line.long 0x0c "DSP_MMU_READ_RAM_L_REG,MMU Read RAM Register LSB"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " RAM_LSB ,LSB physical address"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "DSP_MMU_IDLE_CTRL,Idle control register"
|
|
bitfld.long 0x00 1. " GL_PDE ,Global power-down enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " AUTOGATING_EN ,Enables autogating" "Disabled,Enabled"
|
|
tree.end
|
|
base AD:0xFFFED300
|
|
tree "TIPB Public Bridge 2 Configuration Registers"
|
|
width 20.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIPB_CNTL,Public TIPB Control Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TIMEOUT ,TIPB bus access time-out"
|
|
bitfld.word 0x00 4.--7. " ACCESS_FACTOR1 ,Clock period multiplication factor for TIPB strobe 1" "x2,x2,x4,x6,x8,x10,x12,x14,x16,x18,x20,x22,x24,x26,x28,x30"
|
|
textline " "
|
|
bitfld.word 0x00 0.--3. " ACCESS_FACTOR0 ,Clock period multiplication factor for TIPB strobe 0" "x2,x2,x4,x6,x8,x10,x12,x14,x16,x18,x20,x22,x24,x26,x28,x30"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "TIPB_BUS_ALLOC,Public TIPB Bus Allocation Register"
|
|
bitfld.word 0x0 5. " EXTNINT_PRIORITY ,Priority between DMA and OCP-I when fixed priority scheme is selected" "DMA,OCP-I"
|
|
bitfld.word 0x0 4. " FIXNROUND_PRIORITY ,Type of priority scheme used in DMA and OCP-I arbitration" "Round-robin,Fixed"
|
|
textline " "
|
|
bitfld.word 0x0 3. " PRIORITY_ENABLE " "RHEA_PRIORITY,MPU=OCP-I"
|
|
bitfld.word 0x0 0.--2. " RHEA_PRIORITY ,Defines TIPB priority between MPU and DMA/OCP-I" "MPU > DMA/OCP-I,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU,DMA/OCP-I > MPU"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "MPU_TIPB_CNTL,Public MPU TIPB Control Register"
|
|
bitfld.word 0x0 1. " W_BUF_EN_1 ,Posted write buffer enable for TIPB strobe 1" "Bypassed,Enabled"
|
|
bitfld.word 0x0 0. " W_BUF_EN_0 ,Posted write buffer enable for TIPB strobe 0" "Bypassed,Enabled"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "ENHANCED_TIPB_CNTL,Public Enhanced TIPB Control Register"
|
|
bitfld.word 0x0 3. " MASK_ABORT ,Do not send the abort signal to the MPU whenever an MPU to TIPB access is aborted" "No mask,Mask"
|
|
bitfld.word 0x0 1. " MASK_IT ,Do not send the interrupt to the MPU whenever a TIPB write access (from MPU/DMA/OCP-I) is aborted or any TIPB access has a size mismatch" "No mask,Mask"
|
|
textline " "
|
|
bitfld.word 0x0 0. " TIMEOUT_EN ,Enable the TIMEOUT feature" "No,Yes"
|
|
rgroup.word 0x10++0xF
|
|
line.word 0x00 "ADDRESS_DBG,Public Debug Address Register"
|
|
line.word 0x04 "DATA_DEBUG_LOW,Public Debug Data LSB Register"
|
|
line.word 0x08 "DATA_DEBUG_HIGH,Public Debug Data MSB Register"
|
|
line.word 0x0c "DEBUG_CNTR_SIG,Public Debug Control Signals Register"
|
|
bitfld.word 0x0c 9.--10. " HOST_ID ,Host-ID that caused the abort" "MPU,DMA,OCP-I,?..."
|
|
bitfld.word 0x0c 8. " BURST_ACC ,Indicates single or burst access on the TIPB; saved when abort or access size mismatch occurs" "Single,Burst"
|
|
textline " "
|
|
bitfld.word 0x0c 6.--7. " DBG_PERHMAS ,Peripheral memory access size on TIPB; saved when abort or access size mismatch occurs" "8 bits,16 bits,32 bits,32 bits"
|
|
bitfld.word 0x0c 4.--5. " DBG_MAS ,Memory access size on TIPB; saved when abort or access size mismatch occurs" "8 bits,16 bits,32 bits,32 bits"
|
|
textline " "
|
|
bitfld.word 0x0c 3. " DBG_NSUPV ,Indicates supervisor mode status of MPU; saved when abort or access size mismatch occurs" "Yes,No"
|
|
bitfld.word 0x0c 2. " DBG_RNW ,Indicates read or write transaction on the TIPB; saved when abort or access size mismatch occurs" "Write,Read"
|
|
textline " "
|
|
bitfld.word 0x0c 1. " WR_SIZE_FLAG ,Mismatch between memory access size and peripheral memory access size" "No,Yes"
|
|
bitfld.word 0x0c 0. " ABORT_FLAG ,TIPB access is aborted" "No,Yes"
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "ACCESS_CNTL,Private Access Control Register"
|
|
bitfld.word 0x00 3. " DPS_EN ,Dynamic power-saving mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " MASK_OCPI_NABORT ,Mask OCPI abort before sending it back" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 1. " MASK_DMA_NABORT ,Mask DMA abort before sending it back" "No,Yes"
|
|
bitfld.word 0x00 0. " DMA_ENABLE ,DMA can access peripherals on the TIPB bridge" "Denied,Granted"
|
|
if (2==1)
|
|
group.word 0xA80++0x1
|
|
line.word 0x0 "SECURE_COND_REG,Security Condition Register"
|
|
bitfld.word 0x0 4. " IT_MASK ,Inactivate global mask" "Active,Inactive"
|
|
bitfld.word 0x0 3. " ETM_IF_EN ,Disable ETM interface" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 2. " OCPI_BLOCK ,Disable OCPI access on TIPB private" "Enabled,Disabled"
|
|
bitfld.word 0x0 1. " DMA_BLOCK ,Disable DMA access on TIPB private" "Enabled,Disabled"
|
|
textline " "
|
|
bitfld.word 0x0 0. " TRACE_DIS ,Disable TRACE operations" "Enabled,Disabled"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "L3 OCP T2 Registers"
|
|
base AD:0x30001000
|
|
tree "GDD Global Registers"
|
|
width 14.
|
|
rgroup 0x000++0x3
|
|
line.long 0x000 "GDD_HW_ID,GDD version ID"
|
|
rgroup 0x10++0x7
|
|
line.long 0x00 "GDD_PPORT_ID,Peripheral port version ID"
|
|
line.long 0x04 "GDD_MPORT_ID,Memory port version ID"
|
|
rgroup 0x20++0x7
|
|
line.long 0x00 "GDD_PPORT_SR,Peripheral port status register"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PPORT_ACT_LCh_NUM ,Channel ID number currently active in the peripheral port"
|
|
line.long 0x04 "GDD_MPORT_SR,Memory port status register"
|
|
hexmask.long.byte 0x4 0.--7. 1. " MPORT_ACT_LCh_NUM ,Channel ID number currently active in the memory port"
|
|
group 0x040++0x3
|
|
line.long 0x00 "GDD_TEST,GDD test register"
|
|
bitfld.long 0x00 0. " TEST ,Memory core functioinal test control bit" "Disabled,Enabled"
|
|
group 0x100++0x3
|
|
line.long 0x00 "GDD_GCR,GDD global control register"
|
|
bitfld.long 0x00 3. " CLK_AUTOGATING_ON ,GDD clock autogating enabled" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWITCH_OFF ,GDD global clock control" "No control,Under control"
|
|
group 0x200++0x3
|
|
line.long 0x00 "GDD_GRST,GDD software reset control register"
|
|
bitfld.long 0x00 0. " SW_RESET ,GDD software reset control bit" "No reset,Reset"
|
|
tree.end
|
|
tree "GDD Logical Channel Registers"
|
|
tree "Channel 0"
|
|
width 15.
|
|
group.word (0x800+(0.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(0.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(0.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(0.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(0.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 15.
|
|
group.word (0x800+(1.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(1.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(1.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(1.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(1.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 15.
|
|
group.word (0x800+(2.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(2.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(2.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(2.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(2.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 3"
|
|
width 15.
|
|
group.word (0x800+(3.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(3.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(3.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(3.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(3.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 4"
|
|
width 15.
|
|
group.word (0x800+(4.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(4.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(4.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(4.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(4.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 5"
|
|
width 15.
|
|
group.word (0x800+(5.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(5.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(5.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(5.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(5.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 6"
|
|
width 15.
|
|
group.word (0x800+(6.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(6.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(6.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(6.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(6.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree "Channel 7"
|
|
width 15.
|
|
group.word (0x800+(7.*0x40))++0x5
|
|
line.word 0x00 "GDD_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
hexmask.word.byte 0x00 9.--12. 1. " DST ,Transfer destination"
|
|
textline " "
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single access,Single access,Burst 4x32b,Burst 8x32b"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Memory port (OCPI),Peripheral port (OCP),?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,The type of data moved into the channel" "Reserved,Reserved,32b scalar,?..."
|
|
line.word 0x02 "GDD_CCR,Channel control"
|
|
bitfld.word 0x02 14.--15. " DST_AMODE ,Destination addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE ,Source addressing mode bit" "Constant,Post-incremented,Not supported,Not supported"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Logical channel enable" "Stopped,Enabled"
|
|
hexmask.word.byte 0x02 0.--4. 1. " SYNC ,Synchronization control"
|
|
line.word 0x04 "GDD_CICR,Channel interrupt control"
|
|
bitfld.word 0x04 5. " BLOCK_IE ,End of block interrupt enable" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 2. " HALF_IE ,Half-block interrupt enable" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 0. " TOUT_IE ,Time-out interrupt enable" "No interrupt,Interrupt"
|
|
rgroup.word (0x806+(7.*0x40))++0x1
|
|
line.word 0x00 "GDD_CSR,Channel status"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status: A DMA request has occured" "Not occured,Occured"
|
|
bitfld.word 0x00 5. " BLOCK ,End of block" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half-block reached" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUTE ,Time-out event" "Not occured,Occured"
|
|
group.word (0x808+(7.*0x40))++0x9
|
|
line.word 0x00 "GDD_CSSA_L,Channel source start address LSW"
|
|
line.word 0x02 "GDD_CSSA_U,Channel source start address MSW"
|
|
line.word 0x04 "GDD_CDSA_L,Channel destination start address LSW"
|
|
line.word 0x06 "GDD_CDSA_U,Channel destination start address MSW"
|
|
line.word 0x08 "GDD_CEN,Channel element number"
|
|
rgroup.word (0x818+(7.*0x40))++0x3
|
|
line.word 0x00 "GDD_CSAC,Channel source address counter"
|
|
line.word 0x02 "GDD_CDAC,Channel destination address counter"
|
|
group.word (0x828+(7.*0x40))++0x1
|
|
line.word 0x00 "GDD_CLNK_CTRL,Channel link control"
|
|
bitfld.word 0x00 15. " ENABLE_LINK ,Enables the channel linking" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " STOP_LNK ," "Not disabled,Disabled"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--4. 1. " NEXTLCH_ID ,Next logical channel ID"
|
|
tree.end
|
|
tree.end
|
|
base AD:0x30000800
|
|
tree "SSR Registers"
|
|
width 16.
|
|
rgroup 0x00++0x3
|
|
line.long 0x00 "ID,Identification"
|
|
group 0x04++0xf
|
|
line.long 0x00 "MODE,Mode of operation"
|
|
bitfld.long 0x00 0.--2. " MODE_VAL , " "Sleep,Stream,Frame,Two-wire,Real-time,?..."
|
|
line.long 0x04 "FRAMESIZE,Frame size"
|
|
bitfld.long 0x04 0.--4. " FRAMESIZE_VAL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "RXSTATE,Receiver state"
|
|
bitfld.long 0x08 0.--2. " RXSTATE_VAL ," "Idle,Receiving,Finished,Error,Halt,Time-out,?..."
|
|
line.long 0x0c "BUFSTATE,Receiver buffer state"
|
|
bitfld.long 0x0c 7. " BUFSTATE_VAL7 ,Gives the state of the 7th buffer" "Empty,Not empty"
|
|
bitfld.long 0x0c 6. " BUFSTATE_VAL6 ,Gives the state of the 6th buffer" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " BUFSTATE_VAL5 ,Gives the state of the 5th buffer" "Empty,Not empty"
|
|
bitfld.long 0x0c 4. " BUFSTATE_VAL4 ,Gives the state of the 4th buffer" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " BUFSTATE_VAL3 ,Gives the state of the 3rd buffer" "Empty,Not empty"
|
|
bitfld.long 0x0c 2. " BUFSTATE_VAL2 ,Gives the state of the 2nd buffer" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " BUFSTATE_VAL1 ,Gives the state of the 1st buffer" "Empty,Not empty"
|
|
bitfld.long 0x0c 0. " BUFSTATE_VAL0 ,Gives the state of the 0th buffer" "Empty,Not empty"
|
|
group 0x1c++0x1b
|
|
line.long 0x0 "BREAK,Break detection state"
|
|
bitfld.long 0x0 0. " BREAK_VAL ," "Not detected,Detected"
|
|
line.long 0x4 "ERROR,Error detection state"
|
|
bitfld.long 0x4 0.--1. " ERROR_VAL ," "None,Signal,Time-out,?..."
|
|
line.long 0x8 "ERRORACK,Error acknowledge"
|
|
bitfld.long 0x8 0.--1. " ERRORACK_VAL ,Error acknowledge register" "0,1,2,3"
|
|
line.long 0xc "CHANNELS,Channels"
|
|
bitfld.long 0xc 0.--3. " CHANNEL_VAL ,Number of channels" "Reserved,1,2,Reserved,4,Reserved,Reserved,Reserved,8,?..."
|
|
line.long 0x10 "OVERRUN,Overrun"
|
|
bitfld.long 0x10 7. " OVERRUN_VAL7 ,Overrun detected on channel 7" "Normal,Detected"
|
|
bitfld.long 0x10 6. " OVERRUN_VAL6 ,Overrun detected on channel 6" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x10 5. " OVERRUN_VAL5 ,Overrun detected on channel 5" "Normal,Detected"
|
|
bitfld.long 0x10 4. " OVERRUN_VAL4 ,Overrun detected on channel 4" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x10 3. " OVERRUN_VAL3 ,Overrun detected on channel 3" "Normal,Detected"
|
|
bitfld.long 0x10 2. " OVERRUN_VAL2 ,Overrun detected on channel 2" "Normal,Detected"
|
|
textline " "
|
|
bitfld.long 0x10 1. " OVERRUN_VAL1 ,Overrun detected on channel 1" "Normal,Detected"
|
|
bitfld.long 0x10 0. " OVERRUN_VAL0 ,Overrun detected on channel 0" "Normal,Detected"
|
|
line.long 0x14 "OVERRUNACK,Overrun acknowkedge"
|
|
line.long 0x18 "TIMEOUT,Timeout period"
|
|
group 0x80++0x1F
|
|
line.long 0x00 "BUFFER_CH0,Channel reception buffer channel 0"
|
|
line.long 0x04 "BUFFER_CH1,Channel reception buffer channel 1"
|
|
line.long 0x08 "BUFFER_CH2,Channel reception buffer channel 2"
|
|
line.long 0x0c "BUFFER_CH3,Channel reception buffer channel 3"
|
|
line.long 0x10 "BUFFER_CH4,Channel reception buffer channel 4"
|
|
line.long 0x14 "BUFFER_CH5,Channel reception buffer channel 5"
|
|
line.long 0x18 "BUFFER_CH6,Channel reception buffer channel 6"
|
|
line.long 0x1c "BUFFER_CH7,Channel reception buffer channel 7"
|
|
group 0xC0++0x1F
|
|
line.long 0x00 "SWAPBUFFER_CH0,Receiver buffer with byte swapping channel 0"
|
|
line.long 0x04 "SWAPBUFFER_CH1,Receiver buffer with byte swapping channel 1"
|
|
line.long 0x08 "SWAPBUFFER_CH2,Receiver buffer with byte swapping channel 2"
|
|
line.long 0x0c "SWAPBUFFER_CH3,Receiver buffer with byte swapping channel 3"
|
|
line.long 0x10 "SWAPBUFFER_CH4,Receiver buffer with byte swapping channel 4"
|
|
line.long 0x14 "SWAPBUFFER_CH5,Receiver buffer with byte swapping channel 5"
|
|
line.long 0x18 "SWAPBUFFER_CH6,Receiver buffer with byte swapping channel 6"
|
|
line.long 0x1c "SWAPBUFFER_CH7,Receiver buffer with byte swapping channel 7"
|
|
tree.end
|
|
base AD:0x30000000
|
|
tree "SST Registers"
|
|
width 16.
|
|
rgroup 0x00++0x3
|
|
line.long 0x00 "ID,Identification"
|
|
group 0x04++0x27
|
|
line.long 0x00 "MODE,Mode of operation"
|
|
bitfld.long 0x00 0.--1. " MODE_VAL ," "Sleep,Stream,Frame,Multipoint"
|
|
line.long 0x04 "FRAMESIZE,Frame size"
|
|
bitfld.long 0x04 0.--4. " FRAMESIZE_VAL ," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.long 0x08 "TXSTATE,Transmitter state"
|
|
bitfld.long 0x08 0.--2. " TXSTATE_VAL ," "Idle,Wait,Transmit,Star,Break,Collision,?..."
|
|
line.long 0x0c "BUFSTATE,Transmitter buffer state"
|
|
bitfld.long 0x0c 7. " BUFSTATE_VAL7 ,Gives the state of the 7th buffer" "Not full,Full"
|
|
bitfld.long 0x0c 6. " BUFSTATE_VAL6 ,Gives the state of the 6th buffer" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x0c 5. " BUFSTATE_VAL5 ,Gives the state of the 5th buffer" "Not full,Full"
|
|
bitfld.long 0x0c 4. " BUFSTATE_VAL4 ,Gives the state of the 4th buffer" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x0c 3. " BUFSTATE_VAL3 ,Gives the state of the 3rd buffer" "Not full,Full"
|
|
bitfld.long 0x0c 2. " BUFSTATE_VAL2 ,Gives the state of the 2nd buffer" "Not full,Full"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " BUFSTATE_VAL2 ,Gives the state of the 1st buffer" "Not full,Full"
|
|
bitfld.long 0x0c 0. " BUFSTATE_VAL1 ,Gives the state of the 0th buffer" "Not full,Full"
|
|
group 0x18++0x3
|
|
line.long 0x0 "DIVISOR,Transmitter bit rate divisor"
|
|
hexmask.long.byte 0x0 0.--6. 1. " DIVISOR_VAL ,Transmission bit rate divisor"
|
|
group 0x20++0xb
|
|
line.long 0x0 "BREAK,Transmitter break strobe"
|
|
bitfld.long 0x0 0. " BREAK_VAL ,Number of break to be transmitted" "0,1"
|
|
line.long 0x4 "CHANNELS,Number of channels"
|
|
bitfld.long 0x4 0.--3. " CHANNEL_VAL ,Number of channels" "Reserved,1,2,Reserved,4,Reserved,Reserved,Reserved,8,?..."
|
|
line.long 0x8 "ARBMODE,Arbitration mode"
|
|
bitfld.long 0x8 0. " ARBMODE_VAL ," "Round robin,Priority"
|
|
group 0x80++0x1F
|
|
line.long 0x00 "BUFFER_CH0,Buffer for channel 0"
|
|
line.long 0x04 "BUFFER_CH1,Buffer for channel 1"
|
|
line.long 0x08 "BUFFER_CH2,Buffer for channel 2"
|
|
line.long 0x0c "BUFFER_CH3,Buffer for channel 3"
|
|
line.long 0x10 "BUFFER_CH4,Buffer for channel 4"
|
|
line.long 0x14 "BUFFER_CH5,Buffer for channel 5"
|
|
line.long 0x18 "BUFFER_CH6,Buffer for channel 6"
|
|
line.long 0x1c "BUFFER_CH7,Buffer for channel 7"
|
|
group 0xC0++0x1F
|
|
line.long 0x00 "SWAPBUFFER_CH0,Buffer write byte swap for channel 0"
|
|
line.long 0x04 "SWAPBUFFER_CH1,Buffer write byte swap for channel 1"
|
|
line.long 0x08 "SWAPBUFFER_CH2,Buffer write byte swap for channel 2"
|
|
line.long 0x0c "SWAPBUFFER_CH3,Buffer write byte swap for channel 3"
|
|
line.long 0x10 "SWAPBUFFER_CH4,Buffer write byte swap for channel 4"
|
|
line.long 0x14 "SWAPBUFFER_CH5,Buffer write byte swap for channel 5"
|
|
line.long 0x18 "SWAPBUFFER_CH6,Buffer write byte swap for channel 6"
|
|
line.long 0x1c "SWAPBUFFER_CH7,Buffer write byte swap for channel 7"
|
|
tree.end
|
|
base AD:0x30002000
|
|
tree "VLYNQ Registers"
|
|
width 23.
|
|
rgroup 0x00++0x3
|
|
line.long 0x00 "VLYNQ_REV_ID,Revision/ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Major revision"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision"
|
|
group 0x04++0x3b
|
|
line.long 0x00 "VLYNQ_CNTL,Control"
|
|
bitfld.long 0x00 16.--18. " CLKDIV ,Division factor for the VLYNQ.CLK pin when CLKDIR=1" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 15. " CLKDIR ,Serial clock direction bit" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INTLOC ,Interrupt local bit" "Forwarded,Posted"
|
|
bitfld.long 0x00 13. " INTENABLE ,Interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " INTVEC ,Interrupt vector field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " INT2CFG ,Interrupt to configuration register bit; VLYNQ_INT_PENDING is written directly with the status contained in interrupt packets" "Not write,Write"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ILOOP ,Internal loop back bit" "Disabled,Enabled"
|
|
line.long 0x04 "VLYNQ_STAT,Status"
|
|
bitfld.long 0x04 29.--31. " DEBUG ,Reserved for manufacturing test" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 24.--26. " SWIDTH ,Size of the interface" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " MODESUP ,Mode supported field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 10. " IFLOW ,Inbound flow control bit; a flow control enable request has been received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFLOW ,Outbound flow control bit; the internal flow control threshold has been reached" "Not reached,Reached"
|
|
bitfld.long 0x04 8. " RERROR ,Remote error bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LERROR ,Local error bit" "No error,Error"
|
|
bitfld.long 0x04 6. " NFEMPTY3 ,FIFO 3 not empty; slave command not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x04 5. " NFEMPTY2 ,FIFO 2 not empty; slave data not empty" "Empty,Not empty"
|
|
bitfld.long 0x04 4. " NFEMPTY1 ,FIFO 1 not empty; master command not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x04 3. " NFEMPTY0 ,FIFO 0 not empty; master data not empty" "Empty,Not empty"
|
|
bitfld.long 0x04 2. " SPEND ,Pending slave request bit" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MPEND ,Pending master request bit" "No request,Request"
|
|
bitfld.long 0x04 0. " LINK ,Serial initialization sequence has completed succesfully" "Not successful,Successful"
|
|
group 0x10++0x2f
|
|
line.long 0x0 "VLYNQ_INT_STAT,Interrupt status/clear"
|
|
bitfld.long 0x0 31. " INTCLR31 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 30. " INTCLR30 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 29. " INTCLR29 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 28. " INTCLR28 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 27. " INTCLR27 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 26. " INTCLR26 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 25. " INTCLR25 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 24. " INTCLR24 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 23. " INTCLR23 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 22. " INTCLR22 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 21. " INTCLR21 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 20. " INTCLR20 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 19. " INTCLR19 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 18. " INTCLR18 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 17. " INTCLR17 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 16. " INTCLR16 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 15. " INTCLR15 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 14. " INTCLR14 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 13. " INTCLR13 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 12. " INTCLR12 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 11. " INTCLR11 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 10. " INTCLR10 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 9. " INTCLR9 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 8. " INTCLR8 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 7. " INTCLR7 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 6. " INTCLR6 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 5. " INTCLR5 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 4. " INTCLR4 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 3. " INTCLR3 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 2. " INTCLR2 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " INTCLR1 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 0. " INTCLR0 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
line.long 0x4 "VLYNQ_INT_PENDING,Interrupt pending/set"
|
|
bitfld.long 0x4 31. " INTSET31 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 30. " INTSET30 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 29. " INTSET29 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 28. " INTSET28 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 27. " INTSET27 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 26. " INTSET26 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 25. " INTSET25 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 24. " INTSET24 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 23. " INTSET23 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 22. " INTSET22 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 21. " INTSET21 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 20. " INTSET20 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 19. " INTSET19 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 18. " INTSET18 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 17. " INTSET17 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 16. " INTSET16 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 15. " INTSET15 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 14. " INTSET14 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 13. " INTSET13 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 12. " INTSET12 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 11. " INTSET11 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 10. " INTSET10 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 9. " INTSET9 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 8. " INTSET8 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 7. " INTSET7 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 6. " INTSET6 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 5. " INTSET5 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 4. " INTSET4 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 3. " INTSET3 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 2. " INTSET2 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 1. " INTSET1 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 0. " INTSET0 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
line.long 0x8 "VLYNQ_INT_PTR,Interrupt pointer"
|
|
hexmask.long 0x8 2.--31. 1. " INTPTR ,Interrupt pointer field; address of the VLYNQ_INT_PENDING register"
|
|
line.long 0xc "VLYNQ_TX_ADDR,TX address map"
|
|
hexmask.long 0xc 2.--31. 1. " TXADDRMAP ,Transmit address map is substracted from the local bus address"
|
|
line.long 0x10 "VLYNQ_RX_SIZE1,RX address map size 1"
|
|
hexmask.long 0x10 2.--31. 1. " RXADDRSIZE1 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x14 "VLYNQ_RX_OFFSET1,RX address map offset 1"
|
|
hexmask.long 0x14 2.--31. 1. " RXADDROFFSET1 ,Determines the translated address for serial data"
|
|
line.long 0x18 "VLYNQ_RX_SIZE2,RX address map size 2"
|
|
hexmask.long 0x18 2.--31. 1. " RXADDRSIZE2 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x1c "VLYNQ_RX_OFFSET2,RX address map offset 2"
|
|
hexmask.long 0x1c 2.--31. 1. " RXADDROFFSET2 ,Determines the translated address for serial data"
|
|
line.long 0x20 "VLYNQ_RX_SIZE3,RX address map size 3"
|
|
hexmask.long 0x20 2.--31. 1. " RXADDRSIZE3 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x24 "VLYNQ_RX_OFFSET3,RX address map offset 3"
|
|
hexmask.long 0x24 2.--31. 1. " RXADDROFFSET3 ,Determines the translated address for serial data"
|
|
line.long 0x28 "VLYNQ_RX_SIZE4,RX address map size 4"
|
|
hexmask.long 0x28 2.--31. 1. " RXADDRSIZE4 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x2c "VLYNQ_RX_OFFSET4,RX address map offset 4"
|
|
hexmask.long 0x2c 2.--31. 1. " RXADDROFFSET4 ,Determines the translated address for serial data"
|
|
rgroup 0x40++0x3
|
|
line.long 0x00 "VLYNQ_CHIP_VERSION,Chip version"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVREV ,Device revision field; reflects the value of the DEVICE_REV pins"
|
|
hexmask.long.word 0x00 0.--15. 1. " DEVID ,Device ID field; reflects the value of the DEVICE_ID pins"
|
|
rgroup 0x80++0x3
|
|
line.long 0x00 "VLYNQ_REM_REV_ID,Revision/ID"
|
|
hexmask.long.byte 0x00 8.--15. 1. " REVMAJ ,Major revision"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REVMIN ,Minor revision"
|
|
group 0x84++0x7
|
|
line.long 0x00 "VLYNQ_REM_CNTL,Control"
|
|
bitfld.long 0x00 16.--18. " CLKDIV ,Division factor for the VLYNQ.CLK pin when CLKDIR=1" "1,2,3,4,5,6,7,8"
|
|
bitfld.long 0x00 15. " CLKDIR ,Serial clock direction bit" "External,Internal"
|
|
textline " "
|
|
bitfld.long 0x00 14. " INTLOC ,Interrupt local bit" "Forwarded,Posted"
|
|
bitfld.long 0x00 13. " INTENABLE ,Interrupt enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " INTVEC ,Interrupt vector field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 7. " INT2CFG ,Interrupt to configuration register bit; VLYNQ_INT_PENDING is written directly with the status contained in interrupt packets" "Not write,Write"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ILOOP ,Internal loop back bit" "Disabled,Enabled"
|
|
line.long 0x04 "VLYNQ_REM_STAT"
|
|
bitfld.long 0x04 29.--31. " DEBUG ,Reserved for manufacturing test" "000,001,010,011,100,101,110,111"
|
|
bitfld.long 0x04 24.--26. " SWIDTH ,Size of the interface" "1,2,3,4,5,6,7,8"
|
|
textline " "
|
|
bitfld.long 0x04 21.--23. " MODESUP ,Mode supported field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x04 10. " IFLOW ,Inbound flow control bit; a flow control enable request has been received" "Not received,Received"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OFLOW ,Outbound flow control bit; the internal flow control threshold has been reached" "Not reached,Reached"
|
|
bitfld.long 0x04 8. " RERROR ,Remote error bit" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LERROR ,Local error bit" "No error,Error"
|
|
bitfld.long 0x04 6. " NFEMPTY3 ,FIFO 3 not empty; slave command not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x04 5. " NFEMPTY2 ,FIFO 2 not empty; slave data not empty" "Empty,Not empty"
|
|
bitfld.long 0x04 4. " NFEMPTY1 ,FIFO 1 not empty; master command not empty" "Empty,Not empty"
|
|
textline " "
|
|
bitfld.long 0x04 3. " NFEMPTY0 ,FIFO 0 not empty; master data not empty" "Empty,Not empty"
|
|
bitfld.long 0x04 2. " SPEND ,Pending slave request bit" "No request,Request"
|
|
textline " "
|
|
bitfld.long 0x04 1. " MPEND ,Pending master request bit" "No request,Request"
|
|
bitfld.long 0x04 0. " LINK ,Serial initialization sequence has completed succesfully" "Not successful,Successful"
|
|
group 0x90++0x2f
|
|
line.long 0x0 "VLYNQ_REM_INT_STAT,Interrupt status/clear"
|
|
bitfld.long 0x0 31. " INTCLR31 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 30. " INTCLR30 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 29. " INTCLR29 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 28. " INTCLR28 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 27. " INTCLR27 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 26. " INTCLR26 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 25. " INTCLR25 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 24. " INTCLR24 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 23. " INTCLR23 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 22. " INTCLR22 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 21. " INTCLR21 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 20. " INTCLR20 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 19. " INTCLR19 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 18. " INTCLR18 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 17. " INTCLR17 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 16. " INTCLR16 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 15. " INTCLR15 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 14. " INTCLR14 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 13. " INTCLR13 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 12. " INTCLR12 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 11. " INTCLR11 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 10. " INTCLR10 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 9. " INTCLR9 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 8. " INTCLR8 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 7. " INTCLR7 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 6. " INTCLR6 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 5. " INTCLR5 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 4. " INTCLR4 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 3. " INTCLR3 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 2. " INTCLR2 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
textline " "
|
|
bitfld.long 0x0 1. " INTCLR1 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
bitfld.long 0x0 0. " INTCLR0 ,Unmasked status of interrupt" "No interrupt,Interrupt/Clear"
|
|
line.long 0x4 "VLYNQ_REM_INT_PENDING,Interrupt pending/set"
|
|
bitfld.long 0x4 31. " INTSET31 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 30. " INTSET30 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 29. " INTSET29 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 28. " INTSET28 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 27. " INTSET27 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 26. " INTSET26 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 25. " INTSET25 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 24. " INTSET24 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 23. " INTSET23 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 22. " INTSET22 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 21. " INTSET21 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 20. " INTSET20 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 19. " INTSET19 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 18. " INTSET18 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 17. " INTSET17 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 16. " INTSET16 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 15. " INTSET15 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 14. " INTSET14 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 13. " INTSET13 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 12. " INTSET12 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 11. " INTSET11 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 10. " INTSET10 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 9. " INTSET9 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 8. " INTSET8 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 7. " INTSET7 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 6. " INTSET6 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 5. " INTSET5 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 4. " INTSET4 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 3. " INTSET3 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 2. " INTSET2 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
textline " "
|
|
bitfld.long 0x4 1. " INTSET1 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
bitfld.long 0x4 0. " INTSET0 ,Unmasked status of pending interrupt" "No interrupt,Interrupt/Set"
|
|
line.long 0x8 "VLYNQ_REM_INT_PTR,Interrupt pointer"
|
|
hexmask.long 0x8 2.--31. 1. " INTPTR ,Interrupt pointer field; address of the VLYNQ_INT_PENDING register"
|
|
line.long 0xc "VLYNQ_REM_TX_ADDR,TX address map"
|
|
hexmask.long 0xc 2.--31. 1. " TXADDRMAP ,Transmit address map is substracted from the local bus address"
|
|
line.long 0x10 "VLYNQ_REM_RX_SIZE1,RX address map size 1"
|
|
hexmask.long 0x10 2.--31. 1. " RXADDRSIZE1 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x14 "VLYNQ_REM_RX_OFFSET1,RX address map offset 1"
|
|
hexmask.long 0x14 2.--31. 1. " RXADDROFFSET1 ,Determines the translated address for serial data"
|
|
line.long 0x18 "VLYNQ_REM_RX_SIZE2,RX address map size 2"
|
|
hexmask.long 0x18 2.--31. 1. " RXADDRSIZE2 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x1c "VLYNQ_REM_RX_OFFSET2,RX address map offset 2"
|
|
hexmask.long 0x1c 2.--31. 1. " RXADDROFFSET2 ,Determines the translated address for serial data"
|
|
line.long 0x20 "VLYNQ_REM_RX_SIZE3,RX address map size 3"
|
|
hexmask.long 0x20 2.--31. 1. " RXADDRSIZE3 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x24 "VLYNQ_REM_RX_OFFSET3,RX address map offset 3"
|
|
hexmask.long 0x24 2.--31. 1. " RXADDROFFSET3 ,Determines the translated address for serial data"
|
|
line.long 0x28 "VLYNQ_REM_RX_SIZE4,RX address map size 4"
|
|
hexmask.long 0x28 2.--31. 1. " RXADDRSIZE4 ,Determines if receive packets are destined for this mapped address region"
|
|
line.long 0x2c "VLYNQ_REM_RX_OFFSET4,RX address map offset 4"
|
|
hexmask.long 0x2c 2.--31. 1. " RXADDROFFSET4 ,Determines the translated address for serial data"
|
|
rgroup 0xC0++0x3
|
|
line.long 0x00 "VLYNQ_REM_CHIP_VER,Chip version"
|
|
hexmask.long.word 0x00 16.--31. 1. " DEVREV ,Device revision field; reflects the value of the DEVICE_REV pins"
|
|
hexmask.long.word 0x00 0.--15. 1. " DEVID ,Device ID field; reflects the value of the DEVICE_ID pins"
|
|
group 0x100++0xF
|
|
line.long 0x00 "VLYNQ_CONFIG,VLYNQ configuration"
|
|
bitfld.long 0x00 4. " IE ,Address fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSWTH ,Serial bus width" "CLK TX0 RX0,CLK TX0 TX1 RX0 RX1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SW_RST ,VLYNQ module software reset" "No reset,Reset"
|
|
line.long 0x04 "VLYNQ_ADDR_FAULT,VLYNQ address fault"
|
|
hexmask.long 0x04 2.--31. 1. " ADDR ,Word address of error transfer"
|
|
bitfld.long 0x04 1. " ET ,Type of error" "Write error,Read error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " ERR ,An error" "No error,Error"
|
|
line.long 0x08 "VLYNQ_BUSY,VLYNQ busy"
|
|
bitfld.long 0x08 0. " PD ,VLYNQ has data in pipeline" "No data,Data"
|
|
line.long 0x0c "VLYNQ_DMAREQ_EN,VLYNQ DMA request enable"
|
|
bitfld.long 0x0c 0. " DR ,DMA request" "Disabled,Initially triggered"
|
|
tree.end
|
|
tree.end
|
|
tree "System DMA Registers"
|
|
base AD:0xFFFEDC00
|
|
tree "DMA Global Control Registers"
|
|
width 15.
|
|
group.word 0x00++0x9
|
|
line.word 0x00 "DMA_GCR,DMA global control"
|
|
bitfld.word 0x00 4. " ROUND_ROBIN_DISABLE ,DMA physical channel scheduler round robin scheduling disable" "Round robin,Fixed weighted"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CLK_AUTOGATING_ON ,DMA Clock autogating on" "Always on,Activity dependent"
|
|
textline " "
|
|
bitfld.word 0x00 2. " FREE ,DMA reaction to the suspend signal" "Suspend,Continue"
|
|
line.word 0x04 "DMA_GSCR,DMA software compatible"
|
|
bitfld.word 0x04 3. " OMAP3_1_MAPPING_DISABLE ,OMAP3.1 mapping disable" "3.0/3.1 compatible,3.2 compatible"
|
|
line.word 0x08 "DMA_GRST,Software reset control"
|
|
bitfld.word 0x08 0. " SW_RESET ,DMA software reset control" "No reset,Reset"
|
|
rgroup.word 0x42++0x19
|
|
line.word 0x00 "DMA_HW_ID,DMA version ID"
|
|
line.word 0x02 "DMA_PCh2_ID,Physical channel 2 version ID"
|
|
line.word 0x04 "DMA_PCh0_ID,Physical channel 0 version ID"
|
|
line.word 0x06 "DMA_PCh1_ID,Physical channel 1 version ID"
|
|
line.word 0x08 "DMA_PChG_ID,Physical channel G version ID"
|
|
line.word 0x0a "DMA_PChD_ID,Physical channel D version ID"
|
|
line.word 0x0c "DMA_CAPS_0_U,Global DMA capability 0 upper"
|
|
bitfld.word 0x0c 3. " CFC ,Constant fill capability for PCh-G/PCh-0/PCh-1" "Disabled,Enabled"
|
|
bitfld.word 0x0c 2. " TBLTC ,Transparent BLT capability PCh-G/PCh-0/PCh-1" "Disabled,Enabled"
|
|
bitfld.word 0x0c 1. " OD ,Overlap detection capability PCh-G" "Disabled,Enabled"
|
|
bitfld.word 0x0c 0. " DBLTC ,Directional BLT capability PCh-G" "Disabled,Enabled"
|
|
line.word 0x0e "DMA_CAPS_0_L,Global DMA capability 0 lower"
|
|
bitfld.word 0x0e 2. " SBDC ,Sub-byte destination capability for PCh-G" "Disabled,Enabled"
|
|
bitfld.word 0x0e 0. " OCC ,Origin coordinate capability for PCh-G" "Disabled,Enabled"
|
|
line.word 0x10 "DMA_CAPS_1_U,Global DMA capability 1 upper (Reserved)"
|
|
line.word 0x12 "DMA_CAPS_1_L,Global DMA capability 1 lower"
|
|
bitfld.word 0x12 1. " CE ,1-bit palletized capability (not available in OMAP 3.2) for PCh-G" "Disabled,Enabled"
|
|
line.word 0x14 "DMA_CAPS_2,Global DMA capability 2"
|
|
bitfld.word 0x14 8. " SSDIC ,Separate source/double-index capability" "Disabled,Enabled"
|
|
bitfld.word 0x14 7. " DDIAC ,Destination double-index address capability" "Disabled,Enabled"
|
|
bitfld.word 0x14 6. " DSIAC ,Destination single-index address capability" "Disabled,Enabled"
|
|
bitfld.word 0x14 5. " DPIAC ,Destination post-increment address capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x14 4. " DCAC ,Destination constant address capability" "Disabled,Enabled"
|
|
bitfld.word 0x14 3. " SDIAC ,Source double-index address capability" "Disabled,Enabled"
|
|
bitfld.word 0x14 2. " SSIAC ,Source single-index address capability" "Disabled,Enabled"
|
|
bitfld.word 0x14 1. " SPIAC ,Source post-increment address capability" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x14 0. " SCAC ,Source constant address capability" "Disabled,Enabled"
|
|
line.word 0x16 "DMA_CAPS_3,Global DMA capability 3"
|
|
bitfld.word 0x16 5. " CCC ,Channel chaining capability" "Disabled,Enabled"
|
|
bitfld.word 0x16 4. " IC ,LCh interleave capability" "Disabled,Enabled"
|
|
bitfld.word 0x16 3. " ARC ,Autoinit and repeat capability" "Disabled,Enabled"
|
|
bitfld.word 0x16 2. " AEC ,Autoinit and End_prog" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x16 1. " FSC ,Frame synchronization capability" "Disabled,Enabled"
|
|
bitfld.word 0x16 0. " ESC ,Element synchronization capability" "Disabled,Enabled"
|
|
line.word 0x18 "DMA_CAPS_4,Global DMA capability 4"
|
|
bitfld.word 0x18 6. " SSC ,Sync status capability" "Disabled,Enabled"
|
|
bitfld.word 0x18 5. " BIC ,Block interrupt capability (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x18 4. " LFIC ,Last frame interrupt capability (starts of last frame)" "Disabled,Enabled"
|
|
bitfld.word 0x18 3. " FIC ,Frame interrupt capability (end of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x18 2. " HFIC ,Halt frame interrupt capability" "Disabled,Enabled"
|
|
bitfld.word 0x18 1. " EDIC ,Event drop interrupt capability" "Disabled,Enabled"
|
|
bitfld.word 0x18 0. " TOIC ,Time-out interrupt capability (time-out error)" "Disabled,Enabled"
|
|
group.word 0x60++0x1
|
|
line.word 0x0 "DMA_PCh2_SR,Physical channel 2 status"
|
|
hexmask.word.byte 0x0 0.--7. 1. " ALCN ,Active logical channel number for associated physical channel"
|
|
group.word 0x80++0x1
|
|
line.word 0x0 "DMA_PCh0_SR,Physical channel 0 status"
|
|
hexmask.word.byte 0x0 0.--7. 1. " ALCN ,Active logical channel number for associated physical channel"
|
|
group.word 0x82++0x1
|
|
line.word 0x0 "DMA_PCh1_SR,Physical channel 1 status"
|
|
hexmask.word.byte 0x0 0.--7. 1. " ALCN ,Active logical channel number for associated physical channel"
|
|
group.word 0xc0++0x1
|
|
line.word 0x0 "DMA_PChD_SR_0,Physical channel D status"
|
|
hexmask.word.byte 0x0 0.--7. 1. " ALCN ,Active logical channel number for associated physical channel"
|
|
tree.end
|
|
tree "DMA Logical Channel Configuration Registers"
|
|
base AD:0xFFFED800
|
|
tree "Channel 0"
|
|
width 15.
|
|
group.word (0x00+(0.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(0.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(0.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(0.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(0.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(0.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(0.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(0.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(0.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(0.*0x40))&0x20)==0x0
|
|
group.word (0x24+(0.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(0.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(0.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 1"
|
|
width 15.
|
|
group.word (0x00+(1.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(1.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(1.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(1.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(1.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(1.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(1.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(1.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(1.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(1.*0x40))&0x20)==0x0
|
|
group.word (0x24+(1.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(1.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(1.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 2"
|
|
width 15.
|
|
group.word (0x00+(2.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(2.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(2.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(2.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(2.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(2.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(2.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(2.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(2.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(2.*0x40))&0x20)==0x0
|
|
group.word (0x24+(2.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(2.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(2.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 3"
|
|
width 15.
|
|
group.word (0x00+(3.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(3.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(3.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(3.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(3.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(3.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(3.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(3.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(3.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(3.*0x40))&0x20)==0x0
|
|
group.word (0x24+(3.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(3.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(3.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 4"
|
|
width 15.
|
|
group.word (0x00+(4.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(4.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(4.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(4.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(4.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(4.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(4.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(4.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(4.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(4.*0x40))&0x20)==0x0
|
|
group.word (0x24+(4.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(4.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(4.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 5"
|
|
width 15.
|
|
group.word (0x00+(5.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(5.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(5.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(5.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(5.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(5.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(5.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(5.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(5.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(5.*0x40))&0x20)==0x0
|
|
group.word (0x24+(5.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(5.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(5.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 6"
|
|
width 15.
|
|
group.word (0x00+(6.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(6.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(6.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(6.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(6.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(6.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(6.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(6.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(6.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(6.*0x40))&0x20)==0x0
|
|
group.word (0x24+(6.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(6.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(6.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 7"
|
|
width 15.
|
|
group.word (0x00+(7.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(7.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(7.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(7.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(7.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(7.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(7.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(7.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(7.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(7.*0x40))&0x20)==0x0
|
|
group.word (0x24+(7.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(7.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(7.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 8"
|
|
width 15.
|
|
group.word (0x00+(8.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(8.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(8.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(8.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(8.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(8.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(8.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(8.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(8.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(8.*0x40))&0x20)==0x0
|
|
group.word (0x24+(8.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(8.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(8.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 9"
|
|
width 15.
|
|
group.word (0x00+(9.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(9.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(9.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(9.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(9.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(9.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(9.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(9.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(9.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(9.*0x40))&0x20)==0x0
|
|
group.word (0x24+(9.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(9.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(9.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 10"
|
|
width 15.
|
|
group.word (0x00+(10.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(10.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(10.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(10.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(10.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(10.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(10.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(10.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(10.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(10.*0x40))&0x20)==0x0
|
|
group.word (0x24+(10.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(10.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(10.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 11"
|
|
width 15.
|
|
group.word (0x00+(11.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(11.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(11.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(11.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(11.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(11.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(11.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(11.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(11.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(11.*0x40))&0x20)==0x0
|
|
group.word (0x24+(11.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(11.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(11.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 12"
|
|
width 15.
|
|
group.word (0x00+(12.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(12.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(12.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(12.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(12.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(12.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(12.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(12.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(12.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(12.*0x40))&0x20)==0x0
|
|
group.word (0x24+(12.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(12.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(12.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 13"
|
|
width 15.
|
|
group.word (0x00+(13.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(13.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(13.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(13.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(13.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(13.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(13.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(13.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(13.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(13.*0x40))&0x20)==0x0
|
|
group.word (0x24+(13.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(13.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(13.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 14"
|
|
width 15.
|
|
group.word (0x00+(14.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(14.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(14.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(14.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(14.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(14.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(14.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(14.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(14.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(14.*0x40))&0x20)==0x0
|
|
group.word (0x24+(14.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(14.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(14.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree "Channel 15"
|
|
width 15.
|
|
group.word (0x00+(15.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSDP,Channel source destination parameters"
|
|
bitfld.word 0x00 14.--15. " DST_BURST_EN ,Destination burst enable" "Single,Single,4x,8x"
|
|
bitfld.word 0x00 13. " DST_PACK ,Destination packing" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9.--12. " DST ,Transfer destination" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
bitfld.word 0x00 7.--8. " SRC_BURST_EN ,Source burst enable" "Single,Single,4x,8x"
|
|
textline " "
|
|
bitfld.word 0x00 6. " SRC_PACK ,Source packing" "Disabled,Enabled"
|
|
bitfld.word 0x00 2.--5. " SRC ,Transfer source" "EMIFF,EMIFS,OCP_T1,TIPB,OCP_T2,MPUI,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE ,Defines the type of the data moved in the channel" "8b scalar,16b scalar,32b scalar,?..."
|
|
if (d.w(ad:(0xFFFED824+(15.*0x40)))&0x4)==0x0
|
|
group.word (0x02+(15.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization (depends on DMA_CCR2[BS])" "Element,Frame"
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
group.word (0x02+(15.*0x40))++0x1
|
|
line.word 0x00 "DMA_CCR,Channel control register"
|
|
bitfld.word 0x00 14.--15. " DST_AMODE ,Destination addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x00 12.--13. " SRC_AMODE ,Source addressing mode" "Constant,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x00 11. " END_PROG ,End of programming status bit" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OMAP_3_1_COMPATIBLE_DISABLE ,OMAP 3.0/3.1 channel compatibility control" "3.0/3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x00 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " AUTO_INIT ,Autoinitialization at the end of the transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " ENABLE ,Logical channel enable" "TX stops,TX startx"
|
|
bitfld.word 0x00 6. " PRIO ,Channel priority" "Lowest,Highest"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FS ,Frame synchronization" "Block,?..."
|
|
bitfld.word 0x00 0.--4. " SYNC ,Synchronization control" "Disabled,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word (0x04+(15.*0x40))++0x1
|
|
line.word 0x00 "DMA_CICR,Channel interrupt control register"
|
|
bitfld.word 0x00 5. " BLOCK_IE ,End block interrupt enable (end of block)" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " LAST_IE ,End block interrupt enable (start of last frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " FRAME_IE ,Frame interrupt enable (end of frame)" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " HALF_IE ,Half-frame interrupt enable (half of frame)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " DROP_IE ,Synchronization event drop interrupt enable (request collision)" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " TOUT_IE ,Time-out interrupt enable (time-out error)" "Disabled,Enabled"
|
|
rgroup.word (0x06+(15.*0x40))++0x1
|
|
line.word 0x00 "DMA_CSR,Channel status register"
|
|
bitfld.word 0x00 6. " SYNC ,Synchronization status" "No,Yes"
|
|
bitfld.word 0x00 5. " BLOCK ,End block (end of block)" "No,Yes"
|
|
bitfld.word 0x00 4. " LAST ,Last frame (start of last frame)" "No,Yes"
|
|
bitfld.word 0x00 3. " FRAME ,Frame (end of frame)" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 2. " HALF ,Half frame (half of frame)" "No,Yes"
|
|
bitfld.word 0x00 1. " DROP ,Event drop (request collision)" "No,Yes"
|
|
bitfld.word 0x00 0. " TOUT ,Time-out in the channel" "No,Yes"
|
|
group.word (0x08+(15.*0x40))++0xF
|
|
line.word 0x00 "DMA_CSSA_L,Channel source start address - lower bits"
|
|
line.word 0x02 "DMA_CSSA_U,Channel source start address - upper bits"
|
|
line.word 0x04 "DMA_CDSA_L,Channel destination start address - lower bits"
|
|
line.word 0x06 "DMA_CDSA_U,Channel destination start address - upper bits"
|
|
line.word 0x08 "DMA_CEN,Channel element number"
|
|
line.word 0x0a "DMA_CFN,Channel frame number"
|
|
line.word 0x0c "DMA_CSFI,Channel source frame index"
|
|
line.word 0x0e "DMA_CSEI,Channel source element index"
|
|
rgroup.word (0x18+(15.*0x40))++0x3
|
|
line.word 0x00 "DMA_CSAC,Channel source addr counter"
|
|
line.word 0x02 "DMA_CDAC,Channel destination address counter"
|
|
group.word (0x1C+(15.*0x40))++0x07
|
|
line.word 0x00 "DMA_CDEI,Channel destination element index"
|
|
line.word 0x02 "DMA_CDFI,Channel destination frame index"
|
|
line.word 0x04 "DMA_COLOR_L,Color parameter register - lower bits"
|
|
line.word 0x06 "DMA_COLOR_U,Color parameter register - upper bits"
|
|
if (d.w(ad:0xFFFED802+(15.*0x40))&0x20)==0x0
|
|
group.word (0x24+(15.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization (depends on DMA_CCR[FS])" "Element,Block"
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
else
|
|
group.word (0x24+(15.*0x40))++0x01
|
|
line.word 0x00 "DMA_CCR2,Channel control register 2"
|
|
bitfld.word 0x00 2. " BS ,Block Synchronization" "Frame,?..."
|
|
bitfld.word 0x00 1. " TCE ,Transparent copy enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CFE ,Constant fill enable" "Disabled,Enabled"
|
|
endif
|
|
group.word (0x28+(15.*0x40))++0x03
|
|
line.word 0x00 "DMA_CLNK_CTRL,Channel link control register"
|
|
bitfld.word 0x00 15. " EL ,Enable_Lnk" "No chain,Enable"
|
|
bitfld.word 0x00 14. " SL ,Stop_Lnk" "No disable,Disable"
|
|
bitfld.word 0x00 4. " NID ,Next LCh_ID" "0,1"
|
|
bitfld.word 0x00 0.--3. " NID ,Next LCh_ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.word 0x02 "DMA_LCH_CTRL,Logical channel control register"
|
|
bitfld.word 0x02 15. " LID ,LCH Interleave Disable" "Enabled,Disabled"
|
|
bitfld.word 0x02 0.--3. " LT ,LCH Type" "LCh-2D -> PCh-0 & -1,LCh-G -> PCh0 & -1,LCh-P -> PCh-0 & -1,Reserved,Reserved,Reserved,Reserved,LCh-PD -> PCh-2,?..."
|
|
tree.end
|
|
tree.end
|
|
base AD:0xFFFEEC00
|
|
tree "LCD Channel Dedicated Registers"
|
|
width 21.
|
|
group.word 0xC0++0x5
|
|
line.word 0x00 "DMA_LCD_CSDP,DMA LCD channel source destination"
|
|
bitfld.word 0x00 14.--15. " BURST_EN_B2 ,Burst enable for block 2" "Single,Reserved,4x,?..."
|
|
bitfld.word 0x00 13. " PACK_EN_B2 ,Pack enable for block 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11.--12. " DATA_TYPE_B2 ,Data type for block 2" "8b scalar,16b scalar,32b scalar,?..."
|
|
bitfld.word 0x00 7.--8. " BURST_EN_B1 ,Burst enable for block 1" "Single,Reserved,4x,?..."
|
|
textline " "
|
|
bitfld.word 0x00 6. " PACK_EN_B1 ,Pack enable for block 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " DATA_TYPE_B1 ,Data type for block 1" "8b scalar,16b scalar,32b scalar,?..."
|
|
line.word 0x02 "DMA_LCD_CCR,DMA LCD channel control"
|
|
bitfld.word 0x02 14.--15. " SRC_AMODE_B2 ,Source addressing mode for block 2" "Reserved,Post-incremented,Single index,Double index"
|
|
bitfld.word 0x02 12.--13. " SRC_AMODE_B1 ,Source addressing mode for block 1" "Reserved,Post-incremented,Single index,Double index"
|
|
textline " "
|
|
bitfld.word 0x02 11. " END_PROG ,End of programming status bit" "Disabled,Enabled"
|
|
bitfld.word 0x02 10. " OMAP3_1_COMPATIBLE_DISABLE ,OMAP3.1 channel compatibility control" "3.1 compatible,3.2 compatible"
|
|
textline " "
|
|
bitfld.word 0x02 9. " REPEAT ,Repetitive operation" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " AUTOINIT ,Autoinitialize at the end of transfer" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 7. " ENABLE ,Enable transfer" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " PRIO ,Channel priority" "Low,High"
|
|
textline " "
|
|
bitfld.word 0x02 4. " BS ,Block synchronize" "Software,Hardware"
|
|
line.word 0x04 "DMA_LCD_CTRL,DMA LCD control"
|
|
bitfld.word 0x04 8. " LDP ,LCD destination port (OMAP or external LCD controller)" "OMAP,External"
|
|
bitfld.word 0x04 6.--7. " LSP ,LCD source port. Memory source for the LCD channel" "SDRAM,L3_OCP_T1,L3_OCP_T2,?..."
|
|
textline " "
|
|
bitfld.word 0x04 5. " BUS_ERROR_IT_COND ,Bus error interrupt condition" "No error,Error"
|
|
bitfld.word 0x04 4. " BLOCK_2_IT_COND ,Block 2 interrupt condition" "No end of block,End of block"
|
|
textline " "
|
|
bitfld.word 0x04 3. " BLOCK_1_IT_COND ,Block 1 interrupt condition" "No end of block,End of block"
|
|
bitfld.word 0x04 2. " BUS_ERROR_IT_IE ,bus error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 1. " BLOCK_IT_IE ,Block interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " BLOCK_MODE ,Type of block used for the LCD transfer" "1 block,2 block"
|
|
group.word 0xc8++0x1
|
|
line.word 0x0 "TOP_B1_L,DMA LCD top address B1 L"
|
|
hexmask.word 0x0 1.--15. 1. " LCD_TOP_LSB ,LCD TOP addrress for block buffer 1 lower bits"
|
|
group.word 0xca++0x1
|
|
line.word 0x0 "TOP_B1_U,DMA LCD top address B1 U"
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hexmask.word 0x0 0.--15. 1. " LCD_TOP_MSB ,LCD TOP addrress for block buffer 1 upper bits"
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group.word 0xcc++0x1
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line.word 0x0 "BOT_B1_L,DMA LCD bottom address B1 L"
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hexmask.word 0x0 1.--15. 1. " LCD_BOT_LSB ,LCD BOT addrress for block buffer 1 lower bits"
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group.word 0xce++0x1
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line.word 0x0 "BOT_B1_U,DMA LCD bottom address B1 U"
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hexmask.word 0x0 0.--15. 1. " LCD_BOT_MSB ,LCD BOT addrress for block buffer 1 upper bits"
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group.word 0xd0++0x1
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line.word 0x0 "TOP_B2_L,DMA LCD top address B2 L"
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hexmask.word 0x0 1.--15. 1. " LCD_TOP_LSB ,LCD TOP addrress for block buffer 2 lower bits"
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group.word 0xd2++0x1
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line.word 0x0 "TOP_B2_U,DMA LCD top address B2 U"
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hexmask.word 0x0 0.--15. 1. " LCD_TOP_MSB ,LCD TOP addrress for block buffer 2 upper bits"
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group.word 0xd4++0x1
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line.word 0x0 "BOT_B2_L,DMA LCD bottom address B2 L"
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hexmask.word 0x0 1.--15. 1. " LCD_BOT_LSB ,LCD BOT addrress for block buffer 2 lower bits"
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|
group.word 0xd6++0x1
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|
line.word 0x0 "BOT_B2_U,DMA LCD bottom address B2 U"
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|
hexmask.word 0x0 0.--15. 1. " LCD_BOT_MSB ,LCD BOT addrress for block buffer 2 upper bits"
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group.word 0xd8++0x1
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line.word 0x0 "DMA_LCD_SRC_EI_B1,DMA LCD source element index B1"
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group.word 0xda++0x1
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line.word 0x0 "DMA_LCD_SRC_FI_B1_L,DMA LCD source frame index B1 L"
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group.word 0xf4++0x1
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line.word 0x0 "DMA_LCD_SRC_FI_B1_U,DMA LCD source frame index B1 U"
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|
group.word 0xdc++0x1
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|
line.word 0x0 "DMA_LCD_SRC_EI_B2,DMA LCD source element index B2"
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|
group.word 0xde++0x1
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|
line.word 0x0 "DMA_LCD_SRC_FI_B2_L,DMA LCD source frame index B2 L"
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|
group.word 0xf6++0x1
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line.word 0x0 "DMA_LCD_SRC_FI_B2_U,DMA LCD source frame index B2 U"
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group.word 0xe0++0x1
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line.word 0x0 "DMA_LCD_SRC_EN_B1,DMA LCD source element number B1"
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group.word 0xe4++0x1
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line.word 0x0 "DMA_LCD_SRC_FN_B1,DMA LCD source frame number B1"
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|
group.word 0xe2++0x1
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|
line.word 0x0 "DMA_LCD_SRC_EN_B2,DMA LCD source element number B2"
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|
group.word 0xe6++0x1
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|
line.word 0x0 "DMA_LCD_SRC_FN_B2,DMA LCD source frame number B2"
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|
group.word 0xea++01
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line.word 0x0 "DMA_LCD_LCH_CTRL,DMA LCD logical channel control"
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bitfld.word 0x0 0.--3. " LCH_TYPE ,Logical channel type" "Reserved,Reserved,Reserved,Reserved,LCh-D PCh-D,?..."
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tree.end
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tree.end
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textline ""
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