9659 lines
1.2 MiB
9659 lines
1.2 MiB
; --------------------------------------------------------------------------------
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; @Title: NUC1262 On-Chip Peripherals
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; @Props: Released
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; @Author: JDU, NEJ
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; @Changelog: 2023-02-09 JDU
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; 2023-11-08 NEJ
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; @Manufacturer: NUVOTON - Nuvoton Technology Corp.
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; @Doc: Generated (TRACE32, build: 164352.), based on:
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; NUC1262AE_fixed.svd (Ver. 1.0)
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; @Core: Cortex-M23
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; @Chip: NUC1262LE4AE, NUC1262NE4AE, NUC1262SE4AE
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pernuc1262.per 16971 2023-11-09 16:09:22Z kwisniewski $
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AUTOINDENT.ON CENTER TREE
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ENUMDELIMITER ","
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base ad:0x0
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main extension,Reserved,Reserved,ARMv8-M w/ Main extension"
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newline
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
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bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "ADC (Analog to Digital Converter)"
|
|
base ad:0x400E0000
|
|
rgroup.long 0x0++0x1F
|
|
line.long 0x0 "ADC_ADDR0,ADC Data Register 0"
|
|
bitfld.long 0x0 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
|
|
bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
|
|
newline
|
|
hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x4 "ADC_ADDR1,ADC Data Register 1"
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bitfld.long 0x4 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x8 "ADC_ADDR2,ADC Data Register 2"
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bitfld.long 0x8 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x8 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x8 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0xC "ADC_ADDR3,ADC Data Register 3"
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bitfld.long 0xC 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0xC 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0xC 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x10 "ADC_ADDR4,ADC Data Register 4"
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bitfld.long 0x10 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x10 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x10 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x14 "ADC_ADDR5,ADC Data Register 5"
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bitfld.long 0x14 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x14 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x14 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x18 "ADC_ADDR6,ADC Data Register 6"
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bitfld.long 0x18 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x18 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x18 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x1C "ADC_ADDR7,ADC Data Register 7"
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bitfld.long 0x1C 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x1C 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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newline
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hexmask.long.word 0x1C 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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rgroup.long 0x74++0x7
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line.long 0x0 "ADC_ADDR29,ADC Data Register 29"
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bitfld.long 0x0 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x0 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x0 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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line.long 0x4 "ADC_ADDR30,ADC Data Register 30"
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bitfld.long 0x4 17. "VALID,Valid Flag (Read Only). This bit will be set to 1 when the conversion of the corresponding channel is completed. This bit will be cleared to 0 by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid"
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bitfld.long 0x4 16. "OVERRUN,Overrun Flag (Read Only). If converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1. It is cleared by hardware after ADC_ADDR register is read." "0: Data in RSLT bits is not overwritten,1: Data in RSLT bits is overwritten"
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hexmask.long.word 0x4 0.--15. 1. "RSLT,A/D Conversion Result (Read Only). This field contains conversion result of ADC."
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group.long 0x80++0x13
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line.long 0x0 "ADC_ADCR,ADC Control Register"
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bitfld.long 0x0 31. "DMOF,Differential Input Mode Output Format. If user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)." "0: A/D Conversion result will be filled in RSLT at..,1: A/D Conversion result will be filled in RSLT at.."
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bitfld.long 0x0 16.--18. "SMPTSEL,ADC Internal Sampling Time Selection" "0: 4 ADC clock for sampling; 16 ADC clock for..,1: 5 ADC clock for sampling; 17 ADC clock for..,?,?,?,?,?,?"
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bitfld.long 0x0 11. "ADST,A/D Conversion Start. ADST bit can be set to 1 from four sources: software external pin STADC PWM trigger and Timer trigger. ADST bit will be cleared to 0 by hardware automatically at the ends of Single mode and Single-cycle Scan mode. In.." "0: Conversion stops and A/D converter enters idle..,1: Conversion starts"
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bitfld.long 0x0 10. "DIFFEN,Differential Input Mode Control. Note 1: In Differential Input mode only the even number of the two corresponding channels needs to be enabled in ADC_ADCHER register. The conversion result will be placed to the corresponding data register of the.." "0: Single-end analog input mode,1: In Differential Input mode"
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bitfld.long 0x0 9. "PTEN,PDMA Transfer Enable Bit. When A/D conversion is completed the converted data is loaded into ADC_ADDR0~7 ADC_ADDR29~ADC_ADDR30 registers. Software can enable this bit to generate a PDMA data transfer request." "0: PDMA data transfer Disabled,1: PDMA data transfer in ADC_ADDR0~7.."
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bitfld.long 0x0 8. "TRGEN,External Trigger Enable Bit. Enable or disable triggering of A/D conversion by external STADC pin PWM trigger and Timer trigger. If external trigger is enabled the ADST bit can be set to 1 by the selected hardware trigger source.. Note: The ADC.." "0: External trigger Disabled,1: External trigger Enabled"
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bitfld.long 0x0 6.--7. "TRGCOND,External Trigger Condition. These two bits decide external pin STADC trigger event is level or edge. The signal must be kept at stable state at least 8 PCLKs for level trigger. If edge trigger condition is selected the STADC pin must be kept.." "0: Low level,1: High level,?,?"
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bitfld.long 0x0 4.--5. "TRGS,Hardware Trigger Source. Note: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits." "0: A/D conversion is started by external STADC pin,1: Timer0 ~ Timer3 overflow pulse trigger,?,?"
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bitfld.long 0x0 2.--3. "ADMD,A/D Converter Operation Mode Control. Note 1: When changing the operation mode software should clear ADST bit first.. Note 2: In Burst mode the A/D result data is always at ADC Data Register 0." "0: Single conversion,1: When changing the operation mode,2: In Burst mode,?"
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bitfld.long 0x0 1. "ADIE,A/D Interrupt Enable Bit. A/D conversion end interrupt request is generated if ADIE bit is set to 1." "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled"
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bitfld.long 0x0 0. "ADEN,A/D Converter Enable Bit. Note: Before starting A/D conversion function this bit should be set to 1. Clear it to 0 to disable A/D converter analog circuit to save power consumption." "0: A/D converter Disabled,1: A/D converter Enabled"
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line.long 0x4 "ADC_ADCHER,ADC Channel Enable Register"
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hexmask.long 0x4 0.--31. 1. "CHEN,Analog Input Channel Enable Control. Set ADC_ADCHER[7:0] bits to enable the corresponding analog input channel 7 ~ 0. If DIFFEN (ADC_ADCR[10]) bit is set to 1 only the even number channel needs to be enabled.. Besides setting ADC_ADCHER[29] to.."
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line.long 0x8 "ADC_ADCMPR0,ADC Compare Register 0"
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hexmask.long.word 0x8 16.--27. 1. "CMPD,Comparison Data. The 12-bit data is used to compare with conversion result of specified channel.. Note: CMPD bits should be filled in unsigned format (straight binary format)."
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bitfld.long 0x8 15. "CMPWEN,Compare Window Mode Enable Bit. Note: This bit is only presented in ADC_ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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hexmask.long.byte 0x8 8.--11. 1. "CMPMATCNT,Compare Match Count"
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hexmask.long.byte 0x8 3.--7. 1. "CMPCH,Compare Channel Selection"
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bitfld.long 0x8 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0x8 1. "CMPIE,Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0x8 0. "CMPEN,Compare Enable Bit. Set this bit to 1 to enable ADC controller to compare CMPD with specified channel conversion result when converted data is loaded into ADC_ADDRx register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0xC "ADC_ADCMPR1,ADC Compare Register 1"
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hexmask.long.word 0xC 16.--27. 1. "CMPD,Comparison Data. The 12-bit data is used to compare with conversion result of specified channel.. Note: CMPD bits should be filled in unsigned format (straight binary format)."
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bitfld.long 0xC 15. "CMPWEN,Compare Window Mode Enable Bit. Note: This bit is only presented in ADC_ADCMPR0 register." "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled"
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newline
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hexmask.long.byte 0xC 8.--11. 1. "CMPMATCNT,Compare Match Count"
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hexmask.long.byte 0xC 3.--7. 1. "CMPCH,Compare Channel Selection"
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newline
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bitfld.long 0xC 2. "CMPCOND,Compare Condition" "0: Set the compare condition as that when a 12-bit..,1: Set the compare condition as that when a 12-bit.."
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bitfld.long 0xC 1. "CMPIE,Compare Interrupt Enable Bit" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled"
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newline
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bitfld.long 0xC 0. "CMPEN,Compare Enable Bit. Set this bit to 1 to enable ADC controller to compare CMPD with specified channel conversion result when converted data is loaded into ADC_ADDRx register." "0: Compare function Disabled,1: Compare function Enabled"
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line.long 0x10 "ADC_ADSR0,ADC Status Register0"
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hexmask.long.byte 0x10 27.--31. 1. "CHANNEL,Current Conversion Channel (Read Only)"
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rbitfld.long 0x10 16. "OVERRUNF,Overrun Flag (Read Only). If any of OVERRUN (ADC_ADDRx[16]) is set this flag will be set to 1.. Note: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1." "0,1"
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newline
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rbitfld.long 0x10 8. "VALIDF,Data Valid Flag (Read Only). If any of VALID (ADC_ADDRx[17]) is set this flag will be set to 1.. Note: When ADC is in burst mode and any conversion result is valid this flag will be set to 1." "0,1"
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rbitfld.long 0x10 7. "BUSY,BUSY/IDLE (Read Only). This bit is a mirror of ADST bit in ADC_ADCR register." "0: A/D converter is in idle state,1: A/D converter is busy at conversion"
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bitfld.long 0x10 2. "CMPF1,Compare Flag 1. When the A/D conversion result of the selected channel meets setting condition in ADC_ADCMPR1 register then this bit is set to 1; it is cleared by writing 1 to it" "0: Conversion result in ADC_ADDRx did not meet..,1: Conversion result in ADC_ADDRx met ADC_ADCMPR1.."
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bitfld.long 0x10 1. "CMPF0,Compare Flag 0. When the A/D conversion result of the selected channel meets setting condition in ADC_ADCMPR0 register then this bit is set to 1. This bit is cleared by writing 1 to it." "0: Conversion result in ADC_ADDRx did not meet..,1: Conversion result in ADC_ADDRx met ADC_ADCMPR0.."
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newline
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bitfld.long 0x10 0. "ADF,A/D Conversion End Flag. A status flag that indicates the end of A/D conversion. Software can write 1 to clear this bit.. ADF bit is set to 1 at the following three conditions:. When A/D conversion ends in Single mode.. When A/D conversion ends on.." "0,1"
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rgroup.long 0x94++0x7
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line.long 0x0 "ADC_ADSR1,ADC Status Register1"
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hexmask.long 0x0 0.--31. 1. "VALID,Data Valid Flag (Read Only). VALID[30:29] VALID[7:0] are the mirror of the VALID bits in ADC_ADDR30[17] ~ ADC_ADDR29[17] ADC_ADDR7[17]~ ADC_ADDR0[17]. The other bits are reserved. . Note: When ADC is in burst mode and any conversion result is.."
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line.long 0x4 "ADC_ADSR2,ADC Status Register2"
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hexmask.long 0x4 0.--31. 1. "OVERRUN,Overrun Flag (Read Only). OVERRUN[30:29] VALID[7:0] are the mirror of the OVERRUN bit in ADC_ADDR30[16] ~ADC_ADDR29[16] ADC_ADDR7[16] ~ ADC_ADDR0[16]. The other bits are reserved. . Note: When ADC is in burst mode and the FIFO is overrun .."
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group.long 0x9C++0x3
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line.long 0x0 "ADC_ADTDCR,ADC Trigger Delay Control Register"
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hexmask.long.byte 0x0 0.--7. 1. "PTDT,BPWM Trigger Delay Time. Set this field will delay ADC start conversion time after BPWM trigger.. BPWM trigger delay time is (4 * PTDT) * system clock"
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rgroup.long 0x100++0x3
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line.long 0x0 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register"
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hexmask.long.tbyte 0x0 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only). When PDMA transferring reading this register can monitor current PDMA transfer data.. The current PDMA transfer data could be the content of ADC_ADDR0 ~ ADC_ADDR7 and ADC_ADDR29 ~ ADC_ADDR30.."
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tree.end
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tree "BPWM (Basic PWM Generator and Capture Timer)"
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base ad:0x0
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tree "BPWM0"
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base ad:0x40040000
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group.long 0x0++0x7
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line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect). BPWM pin will keep output no matter ICE debug mode acknowledged or not.. Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect). If counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. . Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 5. "CTRLD5,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 1. "CTRLD1,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0. Each bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
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group.long 0x10++0x7
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line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 3,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale . The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
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group.long 0x20++0x7
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line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0. It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register. Up-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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rgroup.long 0x90++0x3
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line.long 0x0 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down counting,1: Counter is UP counting"
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hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only). Monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0xF
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line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x7
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line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x3
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line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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newline
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit. Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x3
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line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0." "0,1"
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group.long 0xF8++0x7
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line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
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bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0: BPWM_CH3 Trigger ADC function Disabled,1: BPWM_CH3 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select. Others reserved."
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0: BPWM_CH2 Trigger ADC function Disabled,1: BPWM_CH2 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select. Others reserved"
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0: BPWM_CH1 Trigger ADC function Disabled,1: BPWM_CH1 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select. Others reserved"
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0: BPWM_CH0 Trigger ADC function Disabled,1: BPWM_CH0 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select. Others reserved"
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line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
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bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0: BPWM_CH5 Trigger ADC function Disabled,1: BPWM_CH5 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select. Others reserved"
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0: BPWM_CH4 Trigger ADC function Disabled,1: BPWM_CH4 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select. Others reserved"
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group.long 0x110++0x3
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line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,?,?"
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bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit. When synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only). BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.. Writing this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag" "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value."
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group.long 0x200++0x7
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line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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group.long 0x250++0x7
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line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x3
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line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only). Used as PERIOD active register."
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rgroup.long 0x31C++0x17
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line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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tree.end
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tree "BPWM1"
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base ad:0x40140000
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group.long 0x0++0x7
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line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect). BPWM pin will keep output no matter ICE debug mode acknowledged or not.. Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect). If counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. . Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 5. "CTRLD5,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 3. "CTRLD3,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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newline
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bitfld.long 0x0 1. "CTRLD1,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0. Each bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
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group.long 0x10++0x7
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line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 3,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale . The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
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group.long 0x20++0x7
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line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0. It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register. Up-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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rgroup.long 0x90++0x3
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line.long 0x0 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down counting,1: Counter is UP counting"
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hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only). Monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0xF
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line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x7
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line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x3
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line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit. Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x3
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line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0." "0,1"
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group.long 0xF8++0x7
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line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
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bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0: BPWM_CH3 Trigger ADC function Disabled,1: BPWM_CH3 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select. Others reserved."
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0: BPWM_CH2 Trigger ADC function Disabled,1: BPWM_CH2 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select. Others reserved"
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0: BPWM_CH1 Trigger ADC function Disabled,1: BPWM_CH1 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select. Others reserved"
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0: BPWM_CH0 Trigger ADC function Disabled,1: BPWM_CH0 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select. Others reserved"
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line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
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bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0: BPWM_CH5 Trigger ADC function Disabled,1: BPWM_CH5 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0: BPWM_CH4 Trigger ADC function Disabled,1: BPWM_CH4 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select. Others reserved"
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group.long 0x110++0x3
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line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,?,?"
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bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit. When synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only). BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.. Writing this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag" "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value."
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group.long 0x200++0x7
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line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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group.long 0x250++0x7
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line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x3
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line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only). Used as PERIOD active register."
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rgroup.long 0x31C++0x17
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line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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tree.end
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tree "BPWM2"
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base ad:0x40044000
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group.long 0x0++0x7
|
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line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect). BPWM pin will keep output no matter ICE debug mode acknowledged or not.. Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect). If counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. . Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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newline
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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newline
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bitfld.long 0x0 5. "CTRLD5,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0. Each bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
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group.long 0x10++0x7
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line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 3,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale . The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
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group.long 0x20++0x7
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line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0. It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register. Up-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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rgroup.long 0x90++0x3
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line.long 0x0 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down counting,1: Counter is UP counting"
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hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only). Monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0xF
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line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x7
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line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x3
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line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit. Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x3
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line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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newline
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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newline
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0." "0,1"
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group.long 0xF8++0x7
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line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
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bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0: BPWM_CH3 Trigger ADC function Disabled,1: BPWM_CH3 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select. Others reserved."
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newline
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0: BPWM_CH2 Trigger ADC function Disabled,1: BPWM_CH2 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0: BPWM_CH1 Trigger ADC function Disabled,1: BPWM_CH1 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0: BPWM_CH0 Trigger ADC function Disabled,1: BPWM_CH0 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select. Others reserved"
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line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
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bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0: BPWM_CH5 Trigger ADC function Disabled,1: BPWM_CH5 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0: BPWM_CH4 Trigger ADC function Disabled,1: BPWM_CH4 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select. Others reserved"
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group.long 0x110++0x3
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line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,?,?"
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bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit. When synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only). BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.. Writing this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag" "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value."
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group.long 0x200++0x7
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line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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group.long 0x250++0x7
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line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x3
|
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line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
|
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hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only). Used as PERIOD active register."
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rgroup.long 0x31C++0x17
|
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line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
|
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hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
|
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line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
|
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line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
|
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line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
|
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line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
|
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line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
|
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hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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tree.end
|
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tree "BPWM3"
|
|
base ad:0x40144000
|
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group.long 0x0++0x7
|
|
line.long 0x0 "BPWM_CTL0,BPWM Control Register 0"
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bitfld.long 0x0 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable (Write Protect). BPWM pin will keep output no matter ICE debug mode acknowledged or not.. Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects BPWM output,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect). If counter halt is enabled BPWM all counters will keep current value until exit ICE debug mode. . Note: This bit is write protected. Refer to SYS_REGLCTL register." "0: ICE debug mode counter halt Disabled,1: ICE debug mode counter halt Enabled"
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bitfld.long 0x0 21. "IMMLDEN5,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 20. "IMMLDEN4,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 19. "IMMLDEN3,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 18. "IMMLDEN2,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 17. "IMMLDEN1,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 16. "IMMLDEN0,Immediately Load Enable Bit(S). Each bit n controls the corresponding BPWM channel n.. Note: If IMMLDENn is enabled CTRLDn will be invalid." "0: PERIOD will be loaded to PBUF at the end point..,1: PERIOD/CMPDAT will be loaded to PBUF and CMPBUF.."
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bitfld.long 0x0 5. "CTRLD5,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 4. "CTRLD4,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 3. "CTRLD3,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 2. "CTRLD2,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 1. "CTRLD1,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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bitfld.long 0x0 0. "CTRLD0,Center Re-load. Each bit n controls the corresponding BPWM channel n.. In up-down counter type PERIOD will be loaded to PBUF at the end point of each period. CMPDAT will be loaded to CMPBUF at the center point of a period." "0,1"
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line.long 0x4 "BPWM_CTL1,BPWM Control Register 1"
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bitfld.long 0x4 0.--1. "CNTTYPE0,BPWM Counter Behavior Type 0. Each bit n controls corresponding BPWM channel n." "0: Up counter type (supports in capture mode),1: Down count type (supports in capture mode),?,?"
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group.long 0x10++0x7
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line.long 0x0 "BPWM_CLKSRC,BPWM Clock Source Register"
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bitfld.long 0x0 0.--2. "ECLKSRC0,BPWM_CH01 External Clock Source Select" "0: BPWMx_CLK x denotes 0 or 3,1: TIMER0 overflow,?,?,?,?,?,?"
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line.long 0x4 "BPWM_CLKPSC,BPWM Clock Prescale Register"
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hexmask.long.word 0x4 0.--11. 1. "CLKPSC,BPWM Counter Clock Prescale . The clock of BPWM counter is decided by clock prescaler. The clock of BPWM counter is divided by (CLKPSC+ 1)."
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group.long 0x20++0x7
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line.long 0x0 "BPWM_CNTEN,BPWM Counter Enable Register"
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bitfld.long 0x0 0. "CNTEN0,BPWM Counter 0 Enable Bit" "0: BPWM Counter and clock prescaler stop running,1: BPWM Counter and clock prescaler start running"
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line.long 0x4 "BPWM_CNTCLR,BPWM Clear Counter Register"
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bitfld.long 0x4 0. "CNTCLR0,Clear BPWM Counter Control Bit 0. It is automatically cleared by hardware." "0: No effect,1: Clear 16-bit BPWM counter to 0000H"
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group.long 0x30++0x3
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line.long 0x0 "BPWM_PERIOD,BPWM Period Register"
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hexmask.long.word 0x0 0.--15. 1. "PERIOD,BPWM Period Register. Up-Count mode: In this mode BPWM counter counts from 0 to PERIOD and restarts from 0.. Down-Count mode: In this mode BPWM counter counts from PERIOD to 0 and restarts from PERIOD."
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group.long 0x50++0x17
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line.long 0x0 "BPWM_CMPDAT0,BPWM Comparator Register 0"
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hexmask.long.word 0x0 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x4 "BPWM_CMPDAT1,BPWM Comparator Register 1"
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hexmask.long.word 0x4 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x8 "BPWM_CMPDAT2,BPWM Comparator Register 2"
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hexmask.long.word 0x8 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0xC "BPWM_CMPDAT3,BPWM Comparator Register 3"
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hexmask.long.word 0xC 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x10 "BPWM_CMPDAT4,BPWM Comparator Register 4"
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hexmask.long.word 0x10 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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line.long 0x14 "BPWM_CMPDAT5,BPWM Comparator Register 5"
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hexmask.long.word 0x14 0.--15. 1. "CMPDAT,BPWM Comparator Register. CMPDAT use to compare with CNT to generate BPWM waveform interrupt and trigger ADC."
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rgroup.long 0x90++0x3
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line.long 0x0 "BPWM_CNT,BPWM Counter Register"
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bitfld.long 0x0 16. "DIRF,BPWM Direction Indicator Flag (Read Only)" "0: Counter is Down counting,1: Counter is UP counting"
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hexmask.long.word 0x0 0.--15. 1. "CNT,BPWM Data Register (Read Only). Monitor CNT to know the current value in 16-bit period counter."
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group.long 0xB0++0xF
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line.long 0x0 "BPWM_WGCTL0,BPWM Generation Register 0"
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bitfld.long 0x0 26.--27. "PRDPCTL5,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 24.--25. "PRDPCTL4,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 22.--23. "PRDPCTL3,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 20.--21. "PRDPCTL2,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 18.--19. "PRDPCTL1,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 16.--17. "PRDPCTL0,BPWM Period (Center) Point Control. Each bit n controls the corresponding BPWM channel n.. BPWM can control output level when BPWM counter count to (PERIOD+1).. Note: This bit is center point control when BPWM counter operating in up-down.." "0: Do nothing,1: BPWM period (center) point output Low,?,?"
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bitfld.long 0x0 10.--11. "ZPCTL5,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 8.--9. "ZPCTL4,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 6.--7. "ZPCTL3,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 4.--5. "ZPCTL2,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 2.--3. "ZPCTL1,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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bitfld.long 0x0 0.--1. "ZPCTL0,BPWM Zero Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter counts to 0." "0: Do nothing,1: BPWM zero point output Low,?,?"
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line.long 0x4 "BPWM_WGCTL1,BPWM Generation Register 1"
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bitfld.long 0x4 26.--27. "CMPDCTL5,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 24.--25. "CMPDCTL4,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 22.--23. "CMPDCTL3,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 20.--21. "CMPDCTL2,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 18.--19. "CMPDCTL1,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 16.--17. "CMPDCTL0,BPWM Compare Down Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter down counts to CMPDAT." "0: Do nothing,1: BPWM compare down point output Low,?,?"
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bitfld.long 0x4 10.--11. "CMPUCTL5,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 8.--9. "CMPUCTL4,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 6.--7. "CMPUCTL3,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 4.--5. "CMPUCTL2,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 2.--3. "CMPUCTL1,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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bitfld.long 0x4 0.--1. "CMPUCTL0,BPWM Compare Up Point Control. Each bit n controls the corresponding BPWM channel n.. Note: BPWM can control output level when BPWM counter up counts to CMPDAT." "0: Do nothing,1: BPWM compare up point output Low,?,?"
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line.long 0x8 "BPWM_MSKEN,BPWM Mask Enable Register"
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bitfld.long 0x8 5. "MSKEN5,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 4. "MSKEN4,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 3. "MSKEN3,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 2. "MSKEN2,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 1. "MSKEN1,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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bitfld.long 0x8 0. "MSKEN0,BPWM Mask Enable Bits. Each bit n controls the corresponding BPWM channel n.. The BPWM output signal will be masked when this bit is enabled. The corresponding BPWM channel n will output MSKDATn (BPWM_MSK[5:0]) data." "0: BPWM output signal is non-masked,1: BPWM output signal is masked and output MSKDATn.."
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line.long 0xC "BPWM_MSK,BPWM Mask Data Register"
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bitfld.long 0xC 5. "MSKDAT5,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 4. "MSKDAT4,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 3. "MSKDAT3,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 2. "MSKDAT2,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 1. "MSKDAT1,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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bitfld.long 0xC 0. "MSKDAT0,BPWM Mask Data Bit. This data bit controls the state of BPWMn output pin if the corresponding mask function is enabled. Each bit n controls the corresponding BPWM channel n." "0: Output logic low to BPWMn,1: Output logic high to BPWMn"
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group.long 0xD4++0x7
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line.long 0x0 "BPWM_POLCTL,BPWM Pin Polar Inverse Register"
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bitfld.long 0x0 5. "PINV5,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 4. "PINV4,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 3. "PINV3,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 2. "PINV2,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 1. "PINV1,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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bitfld.long 0x0 0. "PINV0,BPWM PIN Polar Inverse Control. The register controls polarity state of BPWMx_CHn output. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn output polar inverse Disabled,1: BPWMx_CHn output polar inverse Enabled"
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line.long 0x4 "BPWM_POEN,BPWM Output Enable Register"
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bitfld.long 0x4 5. "POEN5,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 4. "POEN4,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 3. "POEN3,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 2. "POEN2,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 1. "POEN1,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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bitfld.long 0x4 0. "POEN0,BPWM Pin Output Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWMx_CHn pin at tri-state,1: BPWMx_CHn pin in output mode"
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group.long 0xE0++0x3
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line.long 0x0 "BPWM_INTEN,BPWM Interrupt Enable Register"
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bitfld.long 0x0 29. "CMPDIEN5,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 28. "CMPDIEN4,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 27. "CMPDIEN3,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 26. "CMPDIEN2,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 25. "CMPDIEN1,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 24. "CMPDIEN0,BPWM Compare Down Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled"
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bitfld.long 0x0 21. "CMPUIEN5,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 20. "CMPUIEN4,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 19. "CMPUIEN3,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 18. "CMPUIEN2,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 17. "CMPUIEN1,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 16. "CMPUIEN0,BPWM Compare Up Count Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled"
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bitfld.long 0x0 8. "PIEN0,BPWM Period Point Interrupt 0 Enable Bit. Note: When up-down counter type period point means center point." "0: Period point interrupt Disabled,1: Period point interrupt Enabled"
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bitfld.long 0x0 0. "ZIEN0,BPWM Zero Point Interrupt 0 Enable Bit" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled"
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group.long 0xE8++0x3
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line.long 0x0 "BPWM_INTSTS,BPWM Interrupt Flag Register"
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bitfld.long 0x0 29. "CMPDIF5,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 28. "CMPDIF4,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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newline
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bitfld.long 0x0 27. "CMPDIF3,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 26. "CMPDIF2,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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newline
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bitfld.long 0x0 25. "CMPDIF1,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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bitfld.long 0x0 24. "CMPDIF0,BPWM Compare Down Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter down count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal.." "0,1"
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newline
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bitfld.long 0x0 21. "CMPUIF5,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 20. "CMPUIF4,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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newline
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bitfld.long 0x0 19. "CMPUIF3,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 18. "CMPUIF2,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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newline
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bitfld.long 0x0 17. "CMPUIF1,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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bitfld.long 0x0 16. "CMPUIF0,BPWM Compare Up Count Interrupt Flag. Each bit controls the corresponding BPWM channel n.. Flag is set by hardware when BPWM counter up count and reaches BPWM_CMPDATn. Software can clear this bit by writing 1 to it.. Note: If CMPDAT is equal to.." "0,1"
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newline
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bitfld.long 0x0 8. "PIF0,BPWM Period Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches BPWM_PERIOD0. Software can write 1 to clear this bit to 0." "0,1"
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bitfld.long 0x0 0. "ZIF0,BPWM Zero Point Interrupt Flag 0. This bit is set by hardware when BPWM_CH0 counter reaches 0. Software can write 1 to clear this bit to 0." "0,1"
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group.long 0xF8++0x7
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line.long 0x0 "BPWM_ADCTS0,BPWM Trigger ADC Source Select Register 0"
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bitfld.long 0x0 31. "TRGEN3,BPWM_CH3 Trigger ADC Enable Bit" "0: BPWM_CH3 Trigger ADC function Disabled,1: BPWM_CH3 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 24.--27. 1. "TRGSEL3,BPWM_CH3 Trigger ADC Source Select. Others reserved."
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newline
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bitfld.long 0x0 23. "TRGEN2,BPWM_CH2 Trigger ADC Enable Bit" "0: BPWM_CH2 Trigger ADC function Disabled,1: BPWM_CH2 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 16.--19. 1. "TRGSEL2,BPWM_CH2 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x0 15. "TRGEN1,BPWM_CH1 Trigger ADC Enable Bit" "0: BPWM_CH1 Trigger ADC function Disabled,1: BPWM_CH1 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 8.--11. 1. "TRGSEL1,BPWM_CH1 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x0 7. "TRGEN0,BPWM_CH0 Trigger ADC Enable Bit" "0: BPWM_CH0 Trigger ADC function Disabled,1: BPWM_CH0 Trigger ADC function Enabled"
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hexmask.long.byte 0x0 0.--3. 1. "TRGSEL0,BPWM_CH0 Trigger ADC Source Select. Others reserved"
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line.long 0x4 "BPWM_ADCTS1,BPWM Trigger ADC Source Select Register 1"
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bitfld.long 0x4 15. "TRGEN5,BPWM_CH5 Trigger ADC Enable Bit" "0: BPWM_CH5 Trigger ADC function Disabled,1: BPWM_CH5 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 8.--11. 1. "TRGSEL5,BPWM_CH5 Trigger ADC Source Select. Others reserved"
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newline
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bitfld.long 0x4 7. "TRGEN4,BPWM_CH4 Trigger ADC Enable Bit" "0: BPWM_CH4 Trigger ADC function Disabled,1: BPWM_CH4 Trigger ADC function Enabled"
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hexmask.long.byte 0x4 0.--3. 1. "TRGSEL4,BPWM_CH4 Trigger ADC Source Select. Others reserved"
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group.long 0x110++0x3
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line.long 0x0 "BPWM_SSCTL,BPWM Synchronous Start Control Register"
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bitfld.long 0x0 8.--9. "SSRC,BPWM Synchronous Start Source Select" "0: Synchronous start source come from BPWM0,1: Synchronous start source come from BPWM1,?,?"
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bitfld.long 0x0 0. "SSEN0,BPWM Synchronous Start Function 0 Enable Bit. When synchronous start function is enabled the BPWM_CH0 counter enable bit (CNTEN0) can be enabled by writing BPWM synchronous start trigger bit (CNTSEN)." "0: BPWM synchronous start function Disabled,1: BPWM synchronous start function Enabled"
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wgroup.long 0x114++0x3
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line.long 0x0 "BPWM_SSTRG,BPWM Synchronous Start Trigger Register"
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bitfld.long 0x0 0. "CNTSEN,BPWM Counter Synchronous Start Enable Bit (Write Only). BPMW counter synchronous enable function is used to make all BPWM channels start counting at the same time.. Writing this bit to 1 will also set the counter enable bit if correlated BPWM.." "0,1"
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group.long 0x120++0x3
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line.long 0x0 "BPWM_STATUS,BPWM Status Register"
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bitfld.long 0x0 21. "ADCTRG5,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 20. "ADCTRG4,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 19. "ADCTRG3,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 18. "ADCTRG2,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 17. "ADCTRG1,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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bitfld.long 0x0 16. "ADCTRG0,ADC Start of Conversion Status. Each bit n controls the corresponding BPWM channel n." "0: No ADC start of conversion trigger event occurred,1: An ADC start of conversion trigger event.."
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newline
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bitfld.long 0x0 0. "CNTMAXF0,Time-base Counter 0 Equal to 0xFFFF Latched Flag" "0: The time-base counter never reached its maximum..,1: The time-base counter reached its maximum value."
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group.long 0x200++0x7
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line.long 0x0 "BPWM_CAPINEN,BPWM Capture Input Enable Register"
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bitfld.long 0x0 5. "CAPINEN5,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 4. "CAPINEN4,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 3. "CAPINEN3,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 2. "CAPINEN2,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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newline
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bitfld.long 0x0 1. "CAPINEN1,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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bitfld.long 0x0 0. "CAPINEN0,Capture Input Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: BPWM Channel capture input path Disabled. The..,1: BPWM Channel capture input path Enabled. The.."
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line.long 0x4 "BPWM_CAPCTL,BPWM Capture Control Register"
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bitfld.long 0x4 29. "FCRLDEN5,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 28. "FCRLDEN4,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 27. "FCRLDEN3,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 26. "FCRLDEN2,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 25. "FCRLDEN1,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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bitfld.long 0x4 24. "FCRLDEN0,Falling Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled"
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newline
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bitfld.long 0x4 21. "RCRLDEN5,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 20. "RCRLDEN4,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 19. "RCRLDEN3,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 18. "RCRLDEN2,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 17. "RCRLDEN1,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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bitfld.long 0x4 16. "RCRLDEN0,Rising Capture Reload Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled"
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newline
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bitfld.long 0x4 13. "CAPINV5,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 12. "CAPINV4,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 11. "CAPINV3,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 10. "CAPINV2,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 9. "CAPINV1,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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bitfld.long 0x4 8. "CAPINV0,Capture Inverter Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture source inverter Disabled,1: Capture source inverter Enabled. Reverse the.."
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newline
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bitfld.long 0x4 5. "CAPEN5,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 4. "CAPEN4,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 3. "CAPEN3,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 2. "CAPEN2,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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newline
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bitfld.long 0x4 1. "CAPEN1,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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bitfld.long 0x4 0. "CAPEN0,Capture Function Enable Bits. Each bit n controls the corresponding BPWM channel n." "0: Capture function Disabled.,1: Capture function Enabled. Capture latched the.."
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rgroup.long 0x208++0x33
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line.long 0x0 "BPWM_CAPSTS,BPWM Capture Status Register"
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bitfld.long 0x0 13. "CFIFOV5,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 12. "CFIFOV4,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 11. "CFIFOV3,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 10. "CFIFOV2,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 9. "CFIFOV1,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 8. "CFIFOV0,Capture Falling Interrupt Flag Overrun Status (Read Only). Each bit controls the corresponding BPWM channel n.. This flag indicates if falling latch happened when the corresponding CAPFIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 5. "CRIFOV5,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 4. "CRIFOV4,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 3. "CRIFOV3,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 2. "CRIFOV2,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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newline
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bitfld.long 0x0 1. "CRIFOV1,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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bitfld.long 0x0 0. "CRIFOV0,Capture Rising Interrupt Flag Overrun Status (Read Only). Each bit n controls the corresponding BPWM channel n.. This flag indicates if rising latch happened when the corresponding CAPRIF is 1. . Note: This bit will be cleared automatically when.." "0,1"
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line.long 0x4 "BPWM_RCAPDAT0,BPWM Rising Capture Data Register 0"
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hexmask.long.word 0x4 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x8 "BPWM_FCAPDAT0,BPWM Falling Capture Data Register 0"
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hexmask.long.word 0x8 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0xC "BPWM_RCAPDAT1,BPWM Rising Capture Data Register 1"
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hexmask.long.word 0xC 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x10 "BPWM_FCAPDAT1,BPWM Falling Capture Data Register 1"
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hexmask.long.word 0x10 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x14 "BPWM_RCAPDAT2,BPWM Rising Capture Data Register 2"
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hexmask.long.word 0x14 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x18 "BPWM_FCAPDAT2,BPWM Falling Capture Data Register 2"
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hexmask.long.word 0x18 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x1C "BPWM_RCAPDAT3,BPWM Rising Capture Data Register 3"
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hexmask.long.word 0x1C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x20 "BPWM_FCAPDAT3,BPWM Falling Capture Data Register 3"
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hexmask.long.word 0x20 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x24 "BPWM_RCAPDAT4,BPWM Rising Capture Data Register 4"
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hexmask.long.word 0x24 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x28 "BPWM_FCAPDAT4,BPWM Falling Capture Data Register 4"
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hexmask.long.word 0x28 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x2C "BPWM_RCAPDAT5,BPWM Rising Capture Data Register 5"
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hexmask.long.word 0x2C 0.--15. 1. "RCAPDAT,BPWM Rising Capture Data (Read Only). When rising capture condition happened the BPWM counter value will be saved in this register."
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line.long 0x30 "BPWM_FCAPDAT5,BPWM Falling Capture Data Register 5"
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hexmask.long.word 0x30 0.--15. 1. "FCAPDAT,BPWM Falling Capture Data (Read Only). When falling capture condition happened the BPWM counter value will be saved in this register."
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group.long 0x250++0x7
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line.long 0x0 "BPWM_CAPIEN,BPWM Capture Interrupt Enable Register"
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hexmask.long.byte 0x0 8.--13. 1. "CAPFIENn,BPWM Capture Falling Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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hexmask.long.byte 0x0 0.--5. 1. "CAPRIENn,BPWM Capture Rising Latch Interrupt Enable Bits. Each bit n controls the corresponding BPWM channel n."
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line.long 0x4 "BPWM_CAPIF,BPWM Capture Interrupt Flag Register"
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bitfld.long 0x4 13. "CAPFIF5,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 12. "CAPFIF4,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 11. "CAPFIF3,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 10. "CAPFIF2,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 9. "CAPFIF1,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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bitfld.long 0x4 8. "CAPFIF0,BPWM Capture Falling Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.."
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newline
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bitfld.long 0x4 5. "CAPRIF5,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 4. "CAPRIF4,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 3. "CAPRIF3,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 2. "CAPRIF2,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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newline
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bitfld.long 0x4 1. "CAPRIF1,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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bitfld.long 0x4 0. "CAPRIF0,BPWM Capture Rising Latch Interrupt Flag. Each bit n controls the corresponding BPWM channel n.. Note: This bit is cleared by writing 1 to it." "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.."
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rgroup.long 0x304++0x3
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line.long 0x0 "BPWM_PBUF,BPWM PERIOD Buffer"
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hexmask.long.word 0x0 0.--15. 1. "PBUF,BPWM Period Buffer (Read Only). Used as PERIOD active register."
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rgroup.long 0x31C++0x17
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line.long 0x0 "BPWM_CMPBUF0,BPWM CMPDAT 0 Buffer"
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hexmask.long.word 0x0 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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|
line.long 0x4 "BPWM_CMPBUF1,BPWM CMPDAT 1 Buffer"
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hexmask.long.word 0x4 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x8 "BPWM_CMPBUF2,BPWM CMPDAT 2 Buffer"
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hexmask.long.word 0x8 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0xC "BPWM_CMPBUF3,BPWM CMPDAT 3 Buffer"
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hexmask.long.word 0xC 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x10 "BPWM_CMPBUF4,BPWM CMPDAT 4 Buffer"
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hexmask.long.word 0x10 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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line.long 0x14 "BPWM_CMPBUF5,BPWM CMPDAT 5 Buffer"
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hexmask.long.word 0x14 0.--15. 1. "CMPBUF,BPWM Comparator Buffer (Read Only). Used as CMPDAT active register."
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tree.end
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tree.end
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|
tree "CLK (Clock Controller)"
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base ad:0x50000200
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group.long 0x0++0xB
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line.long 0x0 "CLK_PWRCTL,System Power-down Control Register"
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bitfld.long 0x0 31. "HXTMD,HXT Bypass Mode (Write Protect). Note 2: This bit is write protected. Refer to the SYS_REGCTL register." "0: HXT work as crystal mode. PF.2 and PF.3 are..,1: HXT works as external clock mode. PF.3 is.."
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bitfld.long 0x0 10.--12. "HXTGAIN,HXT Gain Control Bit (Write Protect). Gain control is used to enlarge the gain of crystal to make sure crystal work normally. If gain control is enabled crystal will consume more power than gain control off. . Note: These bits are write.." "0: HXT frequency is from 4 MHz to 8 MHz,1: HXT frequency is from 8 MHz to 12 MHz,?,?,?,?,?,?"
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newline
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bitfld.long 0x0 7. "PDEN,System Power-down Enable (Write Protect). When this bit is set to 1 Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode.. When chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip waits CPU sleep command WFI and then enters.."
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bitfld.long 0x0 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status. Set by 'Power-down wake-up event' which indicates that resume from Power-down mode' . The flag is set if the EINT0~5 VDET GPIO USBD UART0~1 WDT BOD TMR0~3 or I2C0~1 wake-up occurred.. Note 1: This.." "?,1: This bit can be cleared by software writing 1"
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newline
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bitfld.long 0x0 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect). Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high.. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up interrupt Disabled,1: The interrupt will occur when both PDWKIF and.."
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bitfld.long 0x0 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect). When the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.. The delayed clock cycle is 4096 clock cycles when chip work at 4~24 MHz.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled"
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newline
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bitfld.long 0x0 3. "LIRCEN,LIRC Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "HIRCEN,HIRC Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 48 MHz internal high speed RC oscillator (HIRC)..,1: 48 MHz internal high speed RC oscillator (HIRC).."
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newline
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bitfld.long 0x0 1. "LXTEN,LXT Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz External Low Speed Crystal (LXT)..,1: 32.768 kHz External Low Speed Crystal (LXT).."
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bitfld.long 0x0 0. "HXTEN,HXT Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz External High Speed Crystal (HXT)..,1: 4~24 MHz External High Speed Crystal (HXT) Enabled"
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line.long 0x4 "CLK_AHBCLK,AHB Devices Clock Enable Control Register"
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bitfld.long 0x4 21. "GPIOFCKEN,General Purpose I/O PF Group Clock Enable Bit" "0: GPIO PF group clock Disabled,1: GPIO PF group clock Enabled"
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bitfld.long 0x4 19. "GPIODCKEN,General Purpose I/O PD Group Clock Enable Bit" "0: GPIO PD group clock Disabled,1: GPIO PD group clock Enabled"
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newline
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bitfld.long 0x4 18. "GPIOCCKEN,General Purpose I/O PC Group Clock Enable Bit" "0: GPIO PC group clock Disabled,1: GPIO PC group clock Enabled"
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bitfld.long 0x4 17. "GPIOBCKEN,General Purpose I/O PB Group Clock Enable Bit" "0: GPIO PB group clock Disabled,1: GPIO PB group clock Enabled"
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newline
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bitfld.long 0x4 16. "GPIOACKEN,General Purpose I/O PA Group Clock Enable Bit" "0: GPIO PA group clock Disabled,1: GPIO PA group clock Enabled"
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bitfld.long 0x4 15. "FMCIDLE,Flash Memory Controller Clock Enable Bit in IDLE Mode" "0: FMC peripheral clock Disabled when chip..,1: FMC peripheral clock Enabled when chip operating.."
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newline
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bitfld.long 0x4 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled"
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bitfld.long 0x4 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled"
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newline
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bitfld.long 0x4 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled"
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line.long 0x8 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0"
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bitfld.long 0x8 28. "ADCCKEN,Analog-digital-converter Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled"
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bitfld.long 0x8 27. "USBDCKEN,USB Device Clock Enable Bit" "0: USB Device clock Disabled,1: USB Device clock Enabled"
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newline
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bitfld.long 0x8 23. "BPWM3CKEN,BPWM3 Clock Enable Bit" "0: BPWM3 clock Disabled,1: BPWM3 clock Enabled"
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bitfld.long 0x8 22. "BPWM2CKEN,BPWM2 Clock Enable Bit" "0: BPWM2 clock Disabled,1: BPWM2 clock Enabled"
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newline
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bitfld.long 0x8 21. "BPWM1CKEN,BPWM1 Clock Enable Bit" "0: BPWM1 clock Disabled,1: BPWM1 clock Enabled"
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bitfld.long 0x8 20. "BPWM0CKEN,BPWM0 Clock Enable Bit" "0: BPWM0 clock Disabled,1: BPWM0 clock Enabled"
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newline
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bitfld.long 0x8 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled"
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bitfld.long 0x8 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled"
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newline
|
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bitfld.long 0x8 13. "SPI1CKEN,SPI1 Clock Enable Bit" "0: SPI1 Clock Disabled,1: SPI1 Clock Enabled"
|
|
bitfld.long 0x8 12. "SPI0CKEN,SPI0 Clock Enable Bit" "0: SPI0 Clock Disabled,1: SPI0 Clock Enabled"
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newline
|
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bitfld.long 0x8 9. "I2C1CKEN,I2C1 Clock Enable Bit" "0: I2C1 Clock Disabled,1: I2C1 Clock Enabled"
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bitfld.long 0x8 8. "I2C0CKEN,I2C0 Clock Enable Bit" "0: I2C0 Clock Disabled,1: I2C0 Clock Enabled"
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newline
|
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bitfld.long 0x8 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO Clock Disabled,1: CLKO Clock Enabled"
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|
bitfld.long 0x8 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 Clock Disabled,1: Timer3 Clock Enabled"
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newline
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bitfld.long 0x8 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 Clock Disabled,1: Timer2 Clock Enabled"
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bitfld.long 0x8 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 Clock Disabled,1: Timer1 Clock Enabled"
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newline
|
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bitfld.long 0x8 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 Clock Disabled,1: Timer0 Clock Enabled"
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|
bitfld.long 0x8 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Watchdog Timer Clock Disabled,1: Watchdog Timer Clock Enabled"
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rgroup.long 0xC++0x3
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|
line.long 0x0 "CLK_STATUS,Clock Status Monitor Register"
|
|
bitfld.long 0x0 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) . This bit is updated when software switches system clock source. If switch target clock is stable this bit will be set to 0. If switch target clock is not stable this bit will be set to 1.. Note: After.." "0: Clock switching success,1: Clock switching failure"
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bitfld.long 0x0 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: HIRC clock is not stable or disabled,1: HIRC clock is stable and enabled"
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newline
|
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bitfld.long 0x0 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: 10 kHz internal low speed RC oscillator (LIRC)..,1: 10 kHz internal low speed RC oscillator (LIRC).."
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bitfld.long 0x0 2. "PLLSTB,Internal PLL Clock Source Stable Flag (Read Only)" "0: Internal PLL clock is not stable or disabled,1: Internal PLL clock is stable and enabled"
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newline
|
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bitfld.long 0x0 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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bitfld.long 0x0 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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group.long 0x10++0x17
|
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line.long 0x0 "CLK_CLKSEL0,Clock Source Select Control Register 0"
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bitfld.long 0x0 7. "PCLK1SEL,PCLK1 Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APB1 BUS clock source from HCLK,1: APB1 BUS clock source from HCLK/2"
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bitfld.long 0x0 6. "PCLK0SEL,PCLK0 Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: APB0 BUS clock source from HCLK,1: APB0 BUS clock source from HCLK/2"
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newline
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bitfld.long 0x0 3.--5. "STCLKSEL,Cortex-M23 SysTick Clock Source Selection (Write Protect). Note 2: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,2: These bits are write protected,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect). Before clock switching the related clock sources (both pre-select and new-select) must be turned on.. Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HXT,1: Clock source from LXT,?,?,?,?,?,?"
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line.long 0x4 "CLK_CLKSEL1,Clock Source Select Control Register 1"
|
|
bitfld.long 0x4 26.--27. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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bitfld.long 0x4 24.--25. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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newline
|
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bitfld.long 0x4 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x4 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x4 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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bitfld.long 0x4 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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newline
|
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bitfld.long 0x4 2.--3. "ADCSEL,ADC Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL,?,?"
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bitfld.long 0x4 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect). Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Reserved.,1: Clock source from 32.768 kHz external low speed..,?,?"
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line.long 0x8 "CLK_CLKDIV0,Clock Divider Number Register 0"
|
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hexmask.long.byte 0x8 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source"
|
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hexmask.long.byte 0x8 12.--15. 1. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source"
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newline
|
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hexmask.long.byte 0x8 8.--11. 1. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source"
|
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hexmask.long.byte 0x8 4.--7. 1. "USBDIV,USB Clock Divide Number From PLL Source. Note: If the HIRC is selected it is delivery to USB clock directly."
|
|
newline
|
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hexmask.long.byte 0x8 0.--3. 1. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source"
|
|
line.long 0xC "CLK_CLKSEL2,Clock Source Select Control Register 2"
|
|
bitfld.long 0xC 26.--27. "SPI1SEL,SPI1 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
|
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bitfld.long 0xC 24.--25. "SPI0SEL,SPI0 Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from PLL/2 clock,?,?"
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newline
|
|
bitfld.long 0xC 16.--17. "WWDTSEL,Window Watchdog Timer Clock Source Selection" "?,?,?,?"
|
|
bitfld.long 0xC 2.--4. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from 4~24 MHz external high speed..,1: Clock source from 32.768 kHz external low speed..,?,?,?,?,?,?"
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line.long 0x10 "CLK_PLLCTL,PLL Control Register"
|
|
bitfld.long 0x10 23. "STBSEL,PLL Stable Counter Selection" "0: PLL stable time is 6144 PLL source clock..,1: PLL stable time is 12288 PLL source clock.."
|
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bitfld.long 0x10 19. "PLLSRC,PLL Source Clock Selection" "0: PLL source clock from external 4~24 MHz..,1: PLL source clock from 48 MHz internal high-speed.."
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newline
|
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bitfld.long 0x10 18. "OE,PLL OUT Enable Control" "0: PLL FOUT Enabled,1: PLL FOUT is fixed low"
|
|
bitfld.long 0x10 17. "BP,PLL Bypass Control" "0: PLL is in normal mode (default),1: PLL clock output is same as PLL input clock FIN"
|
|
newline
|
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bitfld.long 0x10 16. "PD,Power-down Mode . If set PDEN(CLK_PWRCTL[7]) bit to 1 the PLL will enter Power-down mode too." "0: PLL is in normal mode,1: PLL is in Power-down mode (default)"
|
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bitfld.long 0x10 14.--15. "OUTDIV,PLL Output Divider Control . Refer to the formulas below the table." "0,1,2,3"
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newline
|
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hexmask.long.byte 0x10 9.--13. 1. "INDIV,PLL Input Divider Control . Refer to the formulas below the table."
|
|
hexmask.long.word 0x10 0.--8. 1. "FBDIV,PLL Feedback Divider Control . Refer to the formulas below the table."
|
|
line.long 0x14 "CLK_CLKOCTL,Clock Output Control Register"
|
|
bitfld.long 0x14 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.."
|
|
bitfld.long 0x14 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled"
|
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newline
|
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hexmask.long.byte 0x14 0.--3. 1. "FREQSEL,Clock Output Frequency Selection. The formula of output frequency is. Fin is the input clock frequency.. Fout is the frequency of divider output clock.. N is the 4-bit value of FREQSEL[3:0]."
|
|
group.long 0x30++0x7
|
|
line.long 0x0 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1"
|
|
bitfld.long 0x0 25. "LLSI9CKEN,LLSI9 Clock Enable Bit" "0: LLSI9 clock Disabled,1: LLSI9 clock Enabled"
|
|
bitfld.long 0x0 24. "LLSI8CKEN,LLSI8 Clock Enable Bit" "0: LLSI8 clock Disabled,1: LLSI8 clock Enabled"
|
|
newline
|
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bitfld.long 0x0 23. "LLSI7CKEN,LLSI7 Clock Enable Bit" "0: LLSI7 clock Disabled,1: LLSI7 clock Enabled"
|
|
bitfld.long 0x0 22. "LLSI6CKEN,LLSI6 Clock Enable Bit" "0: LLSI6 clock Disabled,1: LLSI6 clock Enabled"
|
|
newline
|
|
bitfld.long 0x0 21. "LLSI5CKEN,LLSI5 Clock Enable Bit" "0: LLSI5 clock Disabled,1: LLSI5 clock Enabled"
|
|
bitfld.long 0x0 20. "LLSI4CKEN,LLSI4 Clock Enable Bit" "0: LLSI4 clock Disabled,1: LLSI4 clock Enabled"
|
|
newline
|
|
bitfld.long 0x0 19. "LLSI3CKEN,LLSI3 Clock Enable Bit" "0: LLSI3 clock Disabled,1: LLSI3 clock Enabled"
|
|
bitfld.long 0x0 18. "LLSI2CKEN,LLSI2 Clock Enable Bit" "0: LLSI2 clock Disabled,1: LLSI2 clock Enabled"
|
|
newline
|
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bitfld.long 0x0 17. "LLSI1CKEN,LLSI1 Clock Enable Bit" "0: LLSI1 clock Disabled,1: LLSI1 clock Enabled"
|
|
bitfld.long 0x0 16. "LLSI0CKEN,LLSI0 Clock Enable Bit" "0: LLSI0 clock Disabled,1: LLSI0 clock Enabled"
|
|
line.long 0x4 "CLK_CLKSEL3,Clock Source Select Control Register 3"
|
|
bitfld.long 0x4 8. "USBDSEL,USBD Clock Source Selection (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock source from HIRC clock,1: Clock source from PLL clock"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "CLK_BODCLK,Clock Source Select for BOD Control Register"
|
|
bitfld.long 0x0 0. "VDETCKSEL,Clock Source Selection for Voltage Detector . The Voltage Detector clock source for detecting external input voltage is defined by VDETCKSEL.. Note 1: If LIRC is selected LIRCEN (CLK_PWRCTL[3]) must be enabled.. Note 2: If LXT is selected .." "0: Clock source is from 10 kHz internal low speed..,1: If LIRC is selected"
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "CLK_LXTCTL,LXT Control Register"
|
|
bitfld.long 0x0 1.--3. "GAIN,Oscillator Gain Option. User can select oscillator gain according to crystal external loading and operating temperature range. The greater gain value corresponding to stronger driving capability and higher power consumption." "0: L0 mode (ESR=35K; CL =25pF),1: L1 mode (ESR=35K; CL =25pF),?,?,?,?,?,?"
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|
group.long 0x70++0xF
|
|
line.long 0x0 "CLK_CLKDCTL,Clock Fail Detector Control Register"
|
|
bitfld.long 0x0 17. "HXTFQIEN,HXT Clock Frequency Monitor Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
|
|
bitfld.long 0x0 16. "HXTFQDEN,HXT Clock Frequency Monitor Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
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|
newline
|
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bitfld.long 0x0 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
|
|
bitfld.long 0x0 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: 32.768 kHz external low speed crystal oscillator..,1: 32.768 kHz external low speed crystal oscillator.."
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newline
|
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bitfld.long 0x0 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
|
|
bitfld.long 0x0 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: 4~24 MHz external high speed crystal oscillator..,1: 4~24 MHz external high speed crystal oscillator.."
|
|
line.long 0x4 "CLK_CLKDSTS,Clock Fail Detector Status Register"
|
|
bitfld.long 0x4 8. "HXTFQIF,HXT Clock Frequency Monitor Interrupt Flag (Write Protect). Note 1: This bit can be cleared to 0 by software writing 1.. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: This bit can be cleared to 0 by software writing 1"
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|
bitfld.long 0x4 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect). Note 1: This bit can be cleared to 0 by software writing 1. . Note 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 32.768 kHz external low speed crystal oscillator..,1: This bit can be cleared to 0 by software writing 1"
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|
newline
|
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bitfld.long 0x4 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect). Note 1: This bit can be cleared to 0 by software writing 1.. Note 2: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 4~24 MHz external high speed crystal oscillator..,1: This bit can be cleared to 0 by software writing 1"
|
|
line.long 0x8 "CLK_CDUPB,Clock Frequency Detector Upper Boundary Register"
|
|
hexmask.long.word 0x8 0.--9. 1. "UPERBD,HXT Clock Frequency Detector Upper Boundary. The bits define the high value of frequency monitor window.. When HXT frequency monitor value higher than this register the HXT frequency detect fail interrupt flag will be set to 1.. Note: The.."
|
|
line.long 0xC "CLK_CDLOWB,Clock Frequency Detector Low Boundary Register"
|
|
hexmask.long.word 0xC 0.--9. 1. "LOWERBD,HXT Clock Frequency Detector Low Boundary. The bits define the low value of frequency monitor window.. When HXT frequency monitor value lower than this register the HXT frequency detect fail interrupt flag will be set to 1.. Note: The frequency.."
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x50018000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "CRC_CTL,CRC Control Register"
|
|
bitfld.long 0x0 30.--31. "CRCMODE,CRC Polynomial Mode. This field indicates the CRC operation polynomial mode." "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,?,?"
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bitfld.long 0x0 28.--29. "DATLEN,CPU Write Data Length. This field indicates the valid write data length of DATA (CRC_DAT[31:0]).. Note: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if the write data length is 16-bit mode .." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.. Data length is..,?,?"
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bitfld.long 0x0 27. "CHKSFMT,Checksum 1's Complement Enable Bit. This bit is used to enable the 1's complement function for checksum result CHECKSUM (CRC_CHECKSUM[31:0])." "0: 1's complement for CRC CHECKSUM Disabled,1: 1's complement for CRC CHECKSUM Enabled"
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bitfld.long 0x0 26. "DATFMT,Write Data 1's Complement Enable Bit. This bit is used to enable the 1's complement function for write data value DATA (CRC_DATA[31:0])." "0: 1's complement for CRC DATA Disabled,1: 1's complement for CRC DATA Enabled"
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bitfld.long 0x0 25. "CHKSREV,Checksum Bit Order Reverse Enable Bit. This bit is used to enable the bit order reverse function for checksum result CHECKSUM (CRC_CHECKSUM[31:0]).. Note: If the checksum result is 0xDD7B0F2E the bit order reverse result for CRC checksum is.." "0: Bit order reverse for CRC CHECKSUM Disabled,1: Bit order reverse for CRC CHECKSUM Enabled"
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bitfld.long 0x0 24. "DATREV,Write Data Bit Order Reverse Enable Bit. This bit is used to enable the bit order reverse function per byte for write data value DATA (CRC_DATA[31:0]).. Note: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is.." "0: Bit order reversed for CRC DATA Disabled,1: Bit order reversed for CRC DATA Enabled (per byte)"
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bitfld.long 0x0 1. "CHKSINIT,Checksum Initialization. Set this bit will auto reload SEED (CRC_SEED [31:0]) to CHECKSUM (CRC_CHECKSUM[31:0]) as CRC operation initial value.. Note: This bit will be cleared automatically." "0: No effect,1: Reload SEED value to CHECKSUM as CRC operation.."
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bitfld.long 0x0 0. "CRCEN,CRC Generator Enable Bit. Set this bit 1 to enable CRC generator for CRC operation." "0: No effect,1: CRC generator is active"
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line.long 0x4 "CRC_DAT,CRC Write Data Register"
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hexmask.long 0x4 0.--31. 1. "DATA,CRC Write Data Bits. User can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.. Note: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits; if.."
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line.long 0x8 "CRC_SEED,CRC Seed Register"
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hexmask.long 0x8 0.--31. 1. "SEED,CRC Seed Value. This field indicates the CRC seed value.. Note 1: This SEED value will be loaded to checksum initial value CHECKSUM (CRC_CHECKSUM[31:0]) after set CHKSINIT (CRC_CTL[1]) to 1.. Note 2: The valid bits of CRC_SEED[31:0] are correlated.."
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rgroup.long 0xC++0x3
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line.long 0x0 "CRC_CHECKSUM,CRC Checksum Register"
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hexmask.long 0x0 0.--31. 1. "CHECKSUM,CRC Checksum Results. This field indicates the CRC checksum result.. Note: The valid bits of CRC_CHECKSUM[31:0] are correlated to CRCMODE (CRC_CTL[31:30])."
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tree.end
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tree "FMC (Flash Memory Controller)"
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base ad:0x5000C000
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group.long 0x0++0x13
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line.long 0x0 "FMC_ISPCTL,ISP Control Register"
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect). This bit is set by hardware when a triggered ISP meets any of the following conditions:. (1) APROM writes to itself if APUEN is set to 0.. (2) LDROM writes to itself if LDUEN is set to 0.. (3) CONFIG is.." "0,1"
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bitfld.long 0x0 5. "LDUEN,LDROM Update Enable Bit (Write Protect). LDROM update enable bit.. Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: LDROM cannot be updated,1: LDROM can be updated"
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bitfld.long 0x0 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect). Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: CONFIG cannot be updated,1: CONFIG can be updated"
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bitfld.long 0x0 3. "APUEN,APROM Update Enable Bit (Write Protect). Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in APROM"
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bitfld.long 0x0 2. "SPUEN,SPROM Update Enable Bit (Write Protect). Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: SPROM cannot be updated,1: SPROM can be updated"
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bitfld.long 0x0 1. "BS,Boot Select (Write Protect). Set/clear this bit to select next booting from LDROM/APROM respectively. This bit also functions as chip booting status flag which can be used to check where chip booted from. This bit is initiated with the inversed.." "0: Boot from APROM,1: Boot from LDROM"
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bitfld.long 0x0 0. "ISPEN,ISP Enable Bit (Write Protect). ISP function enable bit. Set this bit to enable ISP function.. Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: ISP function Disabled,1: ISP function Enabled"
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line.long 0x4 "FMC_ISPADDR,ISP Address Register"
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hexmask.long 0x4 0.--31. 1. "ISPADDR,ISP Address. The NuMicro NUC1261 series is equipped with embedded Flash. ISPADDR[1:0] must be kept 00 for ISP 32-bit operation. ISPADDR[2:0] must be kept 000 for ISP 64-bit operation.. For Checksum Calculation command this field is the Flash.."
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line.long 0x8 "FMC_ISPDAT,ISP Data Register"
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hexmask.long 0x8 0.--31. 1. "ISPDAT,ISP Data. Write data to this register before ISP program operation.. Read data from this register after ISP read operation."
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line.long 0xC "FMC_ISPCMD,ISP CMD Register"
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hexmask.long.byte 0xC 0.--6. 1. "CMD,ISP CMD. ISP command table is shown below:. The other commands are invalid."
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line.long 0x10 "FMC_ISPTRG,ISP Trigger Control Register"
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bitfld.long 0x10 0. "ISPGO,ISP Start Trigger (Write Protect). Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.. Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: ISP operation is finished,1: ISP is progressed"
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rgroup.long 0x14++0x3
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line.long 0x0 "FMC_DFBA,Data Flash Base Address"
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hexmask.long 0x0 0.--31. 1. "DFBA,Data Flash Base Address. This register indicates Data Flash start address. It is a read only register.. The Data Flash is shared with APROM. the content of this register is loaded from CONFIG1"
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group.long 0x18++0x3
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line.long 0x0 "FMC_FTCTL,Flash Access Time Control Register"
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bitfld.long 0x0 4.--6. "FOM,Frequency Optimization Mode (Write Protect). This chip supports adjustable Flash access timing to optimize the Flash access cycles in different working frequency.. Note: This bit is write-protected. Refer to the SYS_REGLCTL register." "0: Frequency is less than or equal to 72 MHz,1: Frequency is less than or equal to 24 MHz,?,?,?,?,?,?"
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group.long 0x40++0x3
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line.long 0x0 "FMC_ISPSTS,ISP Status Register"
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bitfld.long 0x0 31. "SCODE,Security Code Active Flag. This bit is set by hardware when detecting SPROM secured code is active at Flash initiation or software writes 1 to this bit to make secured code active; this bit is clear by SPROM page erase operation." "0: Secured code is inactive,1: Secured code is active"
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hexmask.long.tbyte 0x0 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only). All access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF} except SPROM.. VECMAP [18:12] should be 0."
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bitfld.long 0x0 7. "ALLONE,Flash All-one Verification Flag . This bit is set by hardware if all of Flash bits are 1 and clear if Flash bits are not all 1 after 'Run Flash All-One Verification' complete; this bit can also be cleared by writing 1" "0: Flash bits are not all 1 after 'Run Flash..,1: All of Flash bits are 1 after 'Run Flash All-One.."
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bitfld.long 0x0 6. "ISPFF,ISP Fail Flag (Write Protect). This bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:. (1).." "0,1"
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rbitfld.long 0x0 1.--2. "CBS,Boot Selection of CONFIG (Read Only). This bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (CPU is 1) or system reset (SYS) is happened." "0: LDROM with IAP mode,1: LDROM without IAP mode,?,?"
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rbitfld.long 0x0 0. "ISPBUSY,ISP Busy Flag (Read Only). Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.. This bit is the mirror of ISPGO(FMC_ISPTRG[0])." "0: ISP operation is finished,1: ISP is progressed"
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group.long 0x80++0xF
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line.long 0x0 "FMC_MPDAT0,ISP Data0 Register"
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hexmask.long 0x0 0.--31. 1. "ISPDAT0,ISP Data 0. This register is the first 32-bit data for 32-bit/64-bit/multi-word programming and it is also the mirror of FMC_ISPDAT both registers keep the same data."
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line.long 0x4 "FMC_MPDAT1,ISP Data1 Register"
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hexmask.long 0x4 0.--31. 1. "ISPDAT1,ISP Data 1. This register is the second 32-bit data for 64-bit/multi-word programming."
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line.long 0x8 "FMC_MPDAT2,ISP Data2 Register"
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hexmask.long 0x8 0.--31. 1. "ISPDAT2,ISP Data 2. This register is the third 32-bit data for multi-word programming."
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line.long 0xC "FMC_MPDAT3,ISP Data3 Register"
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hexmask.long 0xC 0.--31. 1. "ISPDAT3,ISP Data 3. This register is the fourth 32-bit data for multi-word programming."
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rgroup.long 0xC0++0x7
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line.long 0x0 "FMC_MPSTS,ISP Multi-program Status Register"
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bitfld.long 0x0 7. "D3,ISP DATA 3 Flag (Read Only). This bit is set when FMC_MPDAT3 is written and auto-cleared to 0 when the FMC_MPDAT3 data is programmed to Flash complete." "0: FMC_MPDAT3 register is empty or program to Flash..,1: FMC_MPDAT3 register has been written and not.."
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bitfld.long 0x0 6. "D2,ISP DATA 2 Flag (Read Only). This bit is set when FMC_MPDAT2 is written and auto-cleared to 0 when the FMC_MPDAT2 data is programmed to Flash complete." "0: FMC_MPDAT2 register is empty or program to Flash..,1: FMC_MPDAT2 register has been written and not.."
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bitfld.long 0x0 5. "D1,ISP DATA 1 Flag (Read Only). This bit is set when FMC_MPDAT1 is written and auto-cleared to 0 when the FMC_MPDAT1 data is programmed to Flash complete." "0: FMC_MPDAT1 register is empty or program to Flash..,1: FMC_MPDAT1 register has been written and not.."
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bitfld.long 0x0 4. "D0,ISP DATA 0 Flag (Read Only). This bit is set when FMC_MPDAT0 is written and auto-cleared to 0 when the FMC_MPDAT0 data is programmed to Flash complete." "0: FMC_MPDAT0 register is empty or program to Flash..,1: FMC_MPDAT0 register has been written and not.."
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bitfld.long 0x0 2. "ISPFF,ISP Fail Flag (Read Only). This bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]. This bit is set by hardware when a triggered ISP meets any of the following conditions:. (1) APROM.." "0,1"
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bitfld.long 0x0 1. "PPGO,ISP Multi-program Status (Read Only)" "0: ISP multi-word program operation is not active,1: ISP multi-word program operation is in progress"
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newline
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bitfld.long 0x0 0. "MPBUSY,ISP Multi-word Program Busy Flag (Read Only). Write 1 to start ISP Multi-Word program operation and this bit will be cleared to 0 by hardware automatically when ISP Multi-Word program operation is finished.. This bit is the mirror of.." "0: ISP Multi-Word program operation is finished,1: ISP Multi-Word program operation is progressed"
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line.long 0x4 "FMC_MPADDR,ISP Multi-program Address Register"
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hexmask.long 0x4 0.--31. 1. "MPADDR,ISP Multi-word Program Address. MPADDR is the address of ISP multi-word program operation when ISPGO flag is 1.. MPADDR will keep the final ISP address when ISP multi-word program is complete."
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tree.end
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tree "GPIO (General Purpose I/Os)"
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base ad:0x50004000
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group.long 0x0++0xF
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line.long 0x0 "PA_MODE,PA I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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line.long 0x4 "PA_DINOFF,PA Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PA_DOUT,PA Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PA_DATMSK,PA Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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rgroup.long 0x10++0x3
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line.long 0x0 "PA_PIN,PA Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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group.long 0x14++0x1F
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line.long 0x0 "PA_DBEN,PA De-bounce Enable Control"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PA_INTTYPE,PA Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PA_INTEN,PA Interrupt Enable Control"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PA_INTSRC,PA Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PA_SMTEN,PA Input Schmitt Trigger Enable"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PA_SLEWCTL,PA High Slew Rate Control"
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bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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line.long 0x18 "PA_DRVCTL,PA High Drive Strength Control"
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bitfld.long 0x18 15. "HDRVEN15,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 14. "HDRVEN14,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 13. "HDRVEN13,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 12. "HDRVEN12,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 11. "HDRVEN11,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 10. "HDRVEN10,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 9. "HDRVEN9,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 8. "HDRVEN8,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 7. "HDRVEN7,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 6. "HDRVEN6,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 5. "HDRVEN5,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 4. "HDRVEN4,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 3. "HDRVEN3,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 2. "HDRVEN2,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 1. "HDRVEN1,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 0. "HDRVEN0,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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line.long 0x1C "PA_PUSEL,PA Pull-up Selection Register"
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bitfld.long 0x1C 30. "PUSEL15,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 28. "PUSEL14,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 26. "PUSEL13,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 24. "PUSEL12,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 22. "PUSEL11,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 20. "PUSEL10,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 18. "PUSEL9,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 16. "PUSEL8,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 14. "PUSEL7,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 12. "PUSEL6,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 10. "PUSEL5,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 8. "PUSEL4,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 6. "PUSEL3,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 4. "PUSEL2,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 2. "PUSEL1,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 0. "PUSEL0,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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group.long 0x40++0xF
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line.long 0x0 "PB_MODE,PB I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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line.long 0x4 "PB_DINOFF,PB Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PB_DOUT,PB Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PB_DATMSK,PB Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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rgroup.long 0x50++0x3
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line.long 0x0 "PB_PIN,PB Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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group.long 0x54++0x17
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line.long 0x0 "PB_DBEN,PB De-bounce Enable Control"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PB_INTTYPE,PB Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PB_INTEN,PB Interrupt Enable Control"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PB_INTSRC,PB Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PB_SMTEN,PB Input Schmitt Trigger Enable"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PB_SLEWCTL,PB High Slew Rate Control"
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bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0x70++0x3
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line.long 0x0 "PB_PUSEL,PB Pull-up Selection Register"
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bitfld.long 0x0 30. "PUSEL15,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 28. "PUSEL14,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 26. "PUSEL13,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 24. "PUSEL12,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 22. "PUSEL11,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 20. "PUSEL10,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 18. "PUSEL9,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 16. "PUSEL8,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 14. "PUSEL7,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 12. "PUSEL6,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 10. "PUSEL5,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 8. "PUSEL4,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 6. "PUSEL3,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 4. "PUSEL2,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 2. "PUSEL1,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 0. "PUSEL0,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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group.long 0x80++0xF
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line.long 0x0 "PC_MODE,PC I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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line.long 0x4 "PC_DINOFF,PC Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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newline
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PC_DOUT,PC Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PC_DATMSK,PC Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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rgroup.long 0x90++0x3
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line.long 0x0 "PC_PIN,PC Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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group.long 0x94++0x17
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line.long 0x0 "PC_DBEN,PC De-bounce Enable Control"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PC_INTTYPE,PC Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PC_INTEN,PC Interrupt Enable Control"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PC_INTSRC,PC Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PC_SMTEN,PC Input Schmitt Trigger Enable"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PC_SLEWCTL,PC High Slew Rate Control"
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bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0xB0++0x3
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line.long 0x0 "PC_PUSEL,PC Pull-up Selection Register"
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bitfld.long 0x0 30. "PUSEL15,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 28. "PUSEL14,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 26. "PUSEL13,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 24. "PUSEL12,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 22. "PUSEL11,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 20. "PUSEL10,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 18. "PUSEL9,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 16. "PUSEL8,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 14. "PUSEL7,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 12. "PUSEL6,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 10. "PUSEL5,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 8. "PUSEL4,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 6. "PUSEL3,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 4. "PUSEL2,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 2. "PUSEL1,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 0. "PUSEL0,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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group.long 0xC0++0xF
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line.long 0x0 "PD_MODE,PD I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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line.long 0x4 "PD_DINOFF,PD Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PD_DOUT,PD Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PD_DATMSK,PD Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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rgroup.long 0xD0++0x3
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line.long 0x0 "PD_PIN,PD Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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group.long 0xD4++0x17
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line.long 0x0 "PD_DBEN,PD De-bounce Enable Control"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PD_INTTYPE,PD Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PD_INTEN,PD Interrupt Enable Control"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PD_INTSRC,PD Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PD_SMTEN,PD Input Schmitt Trigger Enable"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PD_SLEWCTL,PD High Slew Rate Control"
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bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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group.long 0xF0++0x3
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line.long 0x0 "PD_PUSEL,PD Pull-up Selection Register"
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bitfld.long 0x0 30. "PUSEL15,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 28. "PUSEL14,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 26. "PUSEL13,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 24. "PUSEL12,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 22. "PUSEL11,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 20. "PUSEL10,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 18. "PUSEL9,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 16. "PUSEL8,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 14. "PUSEL7,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 12. "PUSEL6,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 10. "PUSEL5,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 8. "PUSEL4,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 6. "PUSEL3,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 4. "PUSEL2,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x0 2. "PUSEL1,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x0 0. "PUSEL0,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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group.long 0x140++0xF
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line.long 0x0 "PF_MODE,PF I/O Mode Control"
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bitfld.long 0x0 30.--31. "MODE15,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 28.--29. "MODE14,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 26.--27. "MODE13,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 24.--25. "MODE12,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 22.--23. "MODE11,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 20.--21. "MODE10,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 18.--19. "MODE9,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 16.--17. "MODE8,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 14.--15. "MODE7,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 12.--13. "MODE6,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 10.--11. "MODE5,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 8.--9. "MODE4,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 6.--7. "MODE3,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 4.--5. "MODE2,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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newline
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bitfld.long 0x0 2.--3. "MODE1,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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bitfld.long 0x0 0.--1. "MODE0,Port A-F I/O Pin[n] Mode Control. Determine each I/O mode of Px.n pins.. Note 1: The initial value of this field is defined by CIOINI (CONFIG0 [10]).If CIOINI is set to 1 the default value is 0xFFFF_FFFF and all pins will be quasi-bidirectional.." "0: Px.n is in Input mode,1: The initial value of this field is defined by..,2: The PA,?"
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line.long 0x4 "PF_DINOFF,PF Digital Input Path Disable Control"
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bitfld.long 0x4 31. "DINOFF15,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 30. "DINOFF14,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 29. "DINOFF13,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 28. "DINOFF12,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 27. "DINOFF11,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 26. "DINOFF10,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 25. "DINOFF9,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 24. "DINOFF8,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 23. "DINOFF7,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 22. "DINOFF6,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 21. "DINOFF5,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 20. "DINOFF4,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 19. "DINOFF3,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 18. "DINOFF2,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 17. "DINOFF1,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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bitfld.long 0x4 16. "DINOFF0,Port A-F Pin[n] Digital Input Path Disable Control. Each of these bits is used to control if the digital input path of corresponding Px.n pin is disabled. If input is analog signal users can disable Px.n digital input path to avoid input current.." "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital input.."
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line.long 0x8 "PF_DOUT,PF Data Output Value"
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bitfld.long 0x8 15. "DOUT15,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 14. "DOUT14,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 13. "DOUT13,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 12. "DOUT12,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 11. "DOUT11,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 10. "DOUT10,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 9. "DOUT9,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 8. "DOUT8,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 7. "DOUT7,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 6. "DOUT6,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 5. "DOUT5,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 4. "DOUT4,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 3. "DOUT3,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 2. "DOUT2,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 1. "DOUT1,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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bitfld.long 0x8 0. "DOUT0,Port A-F Pin[n] Output Value. Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.. Note: The.." "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.."
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line.long 0xC "PF_DATMSK,PF Data Output Write Mask"
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bitfld.long 0xC 15. "DATMSK15,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 14. "DATMSK14,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 13. "DATMSK13,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 12. "DATMSK12,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 11. "DATMSK11,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 10. "DATMSK10,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 9. "DATMSK9,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 8. "DATMSK8,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 7. "DATMSK7,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 6. "DATMSK6,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 5. "DATMSK5,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 4. "DATMSK4,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 3. "DATMSK3,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 2. "DATMSK2,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 1. "DATMSK1,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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bitfld.long 0xC 0. "DATMSK0,Port A-F Pin[n] Data Output Write Mask. These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit. When the DATMSK (Px_DATMSK[n]) bit is set to 1 the corresponding DOUT (Px_DOUT[n]) bit is protected. If the write signal is masked .." "0: Corresponding DOUT (Px_DOUT[n]) bit can be updated,1: This function only protects the corresponding.."
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rgroup.long 0x150++0x3
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line.long 0x0 "PF_PIN,PF Pin Value"
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bitfld.long 0x0 15. "PIN15,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 14. "PIN14,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 13. "PIN13,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 12. "PIN12,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 11. "PIN11,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 10. "PIN10,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 9. "PIN9,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 8. "PIN8,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 7. "PIN7,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 6. "PIN6,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 5. "PIN5,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 4. "PIN4,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 3. "PIN3,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 2. "PIN2,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 1. "PIN1,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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bitfld.long 0x0 0. "PIN0,Port A-F Pin[n] Pin Value. Each bit of the register reflects the actual status of the respective Px.n pin. If the bit is 1 it indicates the corresponding pin status is high; else the pin status is low.. Note: The.." "0,1"
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group.long 0x154++0x1F
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line.long 0x0 "PF_DBEN,PF De-bounce Enable Control"
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bitfld.long 0x0 15. "DBEN15,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 14. "DBEN14,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 13. "DBEN13,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 12. "DBEN12,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 11. "DBEN11,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 10. "DBEN10,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 9. "DBEN9,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 8. "DBEN8,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 7. "DBEN7,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 6. "DBEN6,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 5. "DBEN5,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 4. "DBEN4,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 3. "DBEN3,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 2. "DBEN2,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 1. "DBEN1,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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bitfld.long 0x0 0. "DBEN0,Port A-F Pin[n] Input Signal De-bounce Enable Bit. The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit. If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle the input signal.." "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled"
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line.long 0x4 "PF_INTTYPE,PF Interrupt Trigger Type Control"
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bitfld.long 0x4 15. "TYPE15,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 14. "TYPE14,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 13. "TYPE13,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 12. "TYPE12,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 11. "TYPE11,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 10. "TYPE10,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 9. "TYPE9,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 8. "TYPE8,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 7. "TYPE7,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 6. "TYPE6,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 5. "TYPE5,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 4. "TYPE4,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 3. "TYPE3,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 2. "TYPE2,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 1. "TYPE1,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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bitfld.long 0x4 0. "TYPE0,Port A-F Pin[n] Edge or Level Detection Interrupt Trigger Type Control. TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger. If the interrupt is by edge trigger the trigger source can be.." "0: Edge trigger interrupt,1: Level trigger interrupt"
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line.long 0x8 "PF_INTEN,PF Interrupt Enable Control"
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bitfld.long 0x8 31. "RHIEN15,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 30. "RHIEN14,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 29. "RHIEN13,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 28. "RHIEN12,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 27. "RHIEN11,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 26. "RHIEN10,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 25. "RHIEN9,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 24. "RHIEN8,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 23. "RHIEN7,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 22. "RHIEN6,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 21. "RHIEN5,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 20. "RHIEN4,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 19. "RHIEN3,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 18. "RHIEN2,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 17. "RHIEN1,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 16. "RHIEN0,Port A-F Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit. The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function. . When.." "0: Px.n level high or low to high interrupt Disabled,1: Px.n level high or low to high interrupt Enabled"
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bitfld.long 0x8 15. "FLIEN15,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 14. "FLIEN14,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 13. "FLIEN13,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 12. "FLIEN12,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 11. "FLIEN11,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 10. "FLIEN10,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 9. "FLIEN9,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 8. "FLIEN8,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 7. "FLIEN7,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 6. "FLIEN6,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 5. "FLIEN5,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 4. "FLIEN4,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 3. "FLIEN3,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 2. "FLIEN2,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 1. "FLIEN1,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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bitfld.long 0x8 0. "FLIEN0,Port A-F Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit. The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.. When setting.." "0: Px.n level low or high to low interrupt Disabled,1: Px.n level low or high to low interrupt Enabled"
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line.long 0xC "PF_INTSRC,PF Interrupt Source Flag"
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bitfld.long 0xC 15. "INTSRC15,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 14. "INTSRC14,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 13. "INTSRC13,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 12. "INTSRC12,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 11. "INTSRC11,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 10. "INTSRC10,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 9. "INTSRC9,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 8. "INTSRC8,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 7. "INTSRC7,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 6. "INTSRC6,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 5. "INTSRC5,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 4. "INTSRC4,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 3. "INTSRC3,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 2. "INTSRC2,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 1. "INTSRC1,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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bitfld.long 0xC 0. "INTSRC0,Port A-F Pin[n] Interrupt Source Flag. Write Operation:. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are.." "0: No action.. No interrupt at Px.n,1: Clear the corresponding pending interrupt.. Px.n.."
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line.long 0x10 "PF_SMTEN,PF Input Schmitt Trigger Enable"
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bitfld.long 0x10 15. "SMTEN15,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 14. "SMTEN14,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 13. "SMTEN13,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 12. "SMTEN12,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 11. "SMTEN11,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 10. "SMTEN10,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 9. "SMTEN9,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 8. "SMTEN8,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 7. "SMTEN7,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 6. "SMTEN6,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 5. "SMTEN5,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 4. "SMTEN4,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 3. "SMTEN3,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 2. "SMTEN2,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 1. "SMTEN1,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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bitfld.long 0x10 0. "SMTEN0,Port A-F Pin[n] Input Schmitt Trigger Enable Bit. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled"
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line.long 0x14 "PF_SLEWCTL,PF High Slew Rate Control"
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bitfld.long 0x14 15. "HSREN15,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 14. "HSREN14,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 13. "HSREN13,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 12. "HSREN12,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 11. "HSREN11,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 10. "HSREN10,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 9. "HSREN9,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 8. "HSREN8,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 7. "HSREN7,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 6. "HSREN6,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 5. "HSREN5,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 4. "HSREN4,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 3. "HSREN3,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 2. "HSREN2,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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newline
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bitfld.long 0x14 1. "HSREN1,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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bitfld.long 0x14 0. "HSREN0,Port A-F Pin[n] High Slew Rate Control. Note: The PA.4/PA.12/PA.13/PA.14/PA.15/PC.8/PC.9/PC.10/PC.11/PC.12/PC.13/PC.15/PD.4/PD.5/PD.6/PD.7/PD.8/PD.9/PD.10/PD.11/PD.12/PD.13/PD.14/PF.7/PF.8/PF.9/PF.10/PF.11/PF.12/PF.13 pin are ignored." "0: Px.n output with basic slew rate,1: Px.n output with higher slew rate"
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line.long 0x18 "PF_DRVCTL,PF High Drive Strength Control"
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bitfld.long 0x18 15. "HDRVEN15,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 14. "HDRVEN14,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 13. "HDRVEN13,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 12. "HDRVEN12,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 11. "HDRVEN11,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 10. "HDRVEN10,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 9. "HDRVEN9,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 8. "HDRVEN8,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 7. "HDRVEN7,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 6. "HDRVEN6,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 5. "HDRVEN5,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 4. "HDRVEN4,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 3. "HDRVEN3,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 2. "HDRVEN2,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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newline
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bitfld.long 0x18 1. "HDRVEN1,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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bitfld.long 0x18 0. "HDRVEN0,Port A and F Pin[n] Driving Strength Control" "0: Px.n output with basic driving and sink strength,1: Px.n output with high driving and sink strength"
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line.long 0x1C "PF_PUSEL,PF Pull-up Selection Register"
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bitfld.long 0x1C 30. "PUSEL15,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 28. "PUSEL14,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 26. "PUSEL13,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 24. "PUSEL12,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 22. "PUSEL11,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 20. "PUSEL10,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 18. "PUSEL9,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 16. "PUSEL8,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 14. "PUSEL7,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 12. "PUSEL6,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 10. "PUSEL5,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 8. "PUSEL4,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 6. "PUSEL3,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 4. "PUSEL2,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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newline
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bitfld.long 0x1C 2. "PUSEL1,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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bitfld.long 0x1C 0. "PUSEL0,Port A-F Pin[n] Pull-up Enable Register. Determine each I/O Pull-up of Px.n pins.. Note 1: Basically the pull-up control has following behavior limitation.. The independent pull-up control register only valid when MODEn is set as tri-state and.." "0: Px.n pull-up disable,1: Basically"
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group.long 0x180++0x3
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line.long 0x0 "GPIO_DBCTL,Interrupt De-bounce Control"
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bitfld.long 0x0 5. "ICLKON,Interrupt Clock on Mode. Note: It is recommended to disable this bit to save system power if no special application concern." "0: Edge detection circuit is active only if I/O pin..,1: All I/O pins edge detection circuit is always.."
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bitfld.long 0x0 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the internal.."
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newline
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hexmask.long.byte 0x0 0.--3. 1. "DBCLKSEL,De-bounce Sampling Cycle Selection"
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group.long 0x200++0xFF
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line.long 0x0 "PA0_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PA1_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PA2_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PA3_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PA4_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PA5_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PA6_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PA7_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x20 "PA8_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x24 "PA9_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x28 "PA10_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x2C "PA11_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x30 "PA12_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x34 "PA13_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x38 "PA14_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x3C "PA15_PDIO,GPIO PA.n Pin Data Input/Output"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x40 "PB0_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x40 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x44 "PB1_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x44 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x48 "PB2_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x48 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4C "PB3_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x4C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x50 "PB4_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x50 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x54 "PB5_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x54 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x58 "PB6_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x58 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x5C "PB7_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x5C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x60 "PB8_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x60 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x64 "PB9_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x64 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x68 "PB10_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x68 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x6C "PB11_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x6C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x70 "PB12_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x70 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x74 "PB13_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x74 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x78 "PB14_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x78 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x7C "PB15_PDIO,GPIO PB.n Pin Data Input/Output"
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bitfld.long 0x7C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x80 "PC0_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x80 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x84 "PC1_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x84 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x88 "PC2_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x88 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x8C "PC3_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0x8C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x90 "PC4_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0x90 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x94 "PC5_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0x94 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0x98 "PC6_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x98 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x9C "PC7_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0x9C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xA0 "PC8_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0xA0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xA4 "PC9_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xA4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xA8 "PC10_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0xA8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xAC "PC11_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0xAC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB0 "PC12_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xB0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xB4 "PC13_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xB4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xB8 "PC14_PDIO,GPIO PC.n Pin Data Input/Output"
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bitfld.long 0xB8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xBC "PC15_PDIO,GPIO PC.n Pin Data Input/Output"
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|
bitfld.long 0xBC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC0 "PD0_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xC0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xC4 "PD1_PDIO,GPIO PD.n Pin Data Input/Output"
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|
bitfld.long 0xC4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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|
line.long 0xC8 "PD2_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xC8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xCC "PD3_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xCC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xD0 "PD4_PDIO,GPIO PD.n Pin Data Input/Output"
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|
bitfld.long 0xD0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xD4 "PD5_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xD4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xD8 "PD6_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xD8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xDC "PD7_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xDC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xE0 "PD8_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xE0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xE4 "PD9_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xE4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xE8 "PD10_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xE8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xEC "PD11_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xEC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xF0 "PD12_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xF0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xF4 "PD13_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xF4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xF8 "PD14_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xF8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xFC "PD15_PDIO,GPIO PD.n Pin Data Input/Output"
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bitfld.long 0xFC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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group.long 0x340++0x3F
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line.long 0x0 "PF0_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x0 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x4 "PF1_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x4 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x8 "PF2_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x8 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0xC "PF3_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0xC 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x10 "PF4_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x10 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x14 "PF5_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x14 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x18 "PF6_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x18 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x1C "PF7_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x1C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x20 "PF8_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x20 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x24 "PF9_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x24 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x28 "PF10_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x28 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x2C "PF11_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x2C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x30 "PF12_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x30 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x34 "PF13_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x34 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x38 "PF14_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x38 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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line.long 0x3C "PF15_PDIO,GPIO PF.n Pin Data Input/Output"
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bitfld.long 0x3C 0. "PDIO,GPIO Px.n Pin Data Input/Output. Writing this bit can control one GPIO pin output value.. Read this register to get GPIO pin status.. For example writing PA0_PDIO will reflect the written value to bit DOUT (PA_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: The writing operation will not be affected by.."
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tree.end
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tree "I2C (Inter-Integrated Circuit Serial Interface Controller)"
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base ad:0x0
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tree "I2C0"
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base ad:0x40020000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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newline
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bitfld.long 0x0 5. "STA,I2C START Control. Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or Repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control. In Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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newline
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag. When a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
|
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
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line.long 0x8 "I2C_DAT,I2C Data Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data . Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
|
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
|
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
|
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
|
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count . The register bits control the input filter width.. Note: Filter width Min :3*PCLK Max : 18*PCLK"
|
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided . Note: The minimum value of I2C_CLKDIV is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
|
|
bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit. When enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4. When enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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|
newline
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bitfld.long 0x4 0. "TOIF,Time-out Flag. This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.. Note: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
|
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
|
|
bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
|
|
line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit. Note: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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rbitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame (Read Only). Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done. Note: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag. When chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only). Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status. When address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status. When address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status. When address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status. When address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control . This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control. This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.. Note: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat . The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State. The BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.. Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit. Note: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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newline
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit. Note: When I2C enters Power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual. In order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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newline
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.. Bus IDLE..,1: SCL low time-out interrupt Enabled.. Bus IDLE.."
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bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit. For Master it calculates the period from START to ACK.. For Slave it calculates the period from START to STOP." "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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newline
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done . Note: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status . Note: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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newline
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status . In bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.. Note: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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rbitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status (Read Only)" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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newline
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status . Note: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.. No SMBALERT event,1: SMBALERT pin state is high.. There is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception . Note: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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newline
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done . Note: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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rbitfld.long 0x1C 0. "BUSY,Bus Busy (Read Only). Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number. The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.. Note: The byte number counting includes address command code and data frame."
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rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value. Indicates the bus time-out value in bus is IDLE or SCL low.. Note: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first in the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer. The field is used to configure the cumulative clock extension time-out.. Note: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first in the BUSEN is set."
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tree.end
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tree "I2C1"
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base ad:0x40120000
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group.long 0x0++0xB
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line.long 0x0 "I2C_CTL0,I2C Control Register 0"
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bitfld.long 0x0 7. "INTEN,Enable Interrupt" "0: I2C interrupt Disabled,1: I2C interrupt Enabled"
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bitfld.long 0x0 6. "I2CEN,I2C Controller Enable Bit" "0: I2C controller Disabled,1: I2C controller Enabled"
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newline
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bitfld.long 0x0 5. "STA,I2C START Control. Setting STA to logic 1 to enter Master mode the I2C hardware sends a START or Repeat START condition to bus when the bus is free." "0,1"
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bitfld.long 0x0 4. "STO,I2C STOP Control. In Master mode setting STO to transmit a STOP condition to bus then I2C controller will check the bus condition if a STOP condition is detected. This bit will be cleared by hardware automatically." "0,1"
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newline
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bitfld.long 0x0 3. "SI,I2C Interrupt Flag. When a new I2C state is present in the I2C_STATUS0 register the SI flag is set by hardware. If bit INTEN (I2C_CTL0 [7]) is set the I2C interrupt is requested. SI must be cleared by software. Clear SI by writing 1 to this bit.." "0,1"
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bitfld.long 0x0 2. "AA,Assert Acknowledge Control" "0,1"
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line.long 0x4 "I2C_ADDR0,I2C Slave Address Register0"
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hexmask.long.word 0x4 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0x4 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x8 "I2C_DAT,I2C Data Register"
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hexmask.long.byte 0x8 0.--7. 1. "DAT,I2C Data . Bit [7:0] is located with the 8-bit transferred/received data of I2C serial port."
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rgroup.long 0xC++0x3
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line.long 0x0 "I2C_STATUS0,I2C Status Register 0"
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hexmask.long.byte 0x0 0.--7. 1. "STATUS,I2C Status"
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group.long 0x10++0x23
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line.long 0x0 "I2C_CLKDIV,I2C Clock Divided Register"
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hexmask.long.byte 0x0 12.--15. 1. "NFCNT,Noise Filter Count . The register bits control the input filter width.. Note: Filter width Min :3*PCLK Max : 18*PCLK"
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hexmask.long.word 0x0 0.--9. 1. "DIVIDER,I2C Clock Divided . Note: The minimum value of I2C_CLKDIV is 4."
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line.long 0x4 "I2C_TOCTL,I2C Time-out Control Register"
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bitfld.long 0x4 2. "TOCEN,Time-out Counter Enable Bit. When enabled the 14-bit time-out counter will start counting when SI is cleared. Setting flag SI to '1' will reset counter and re-start up counting after SI is cleared." "0: Time-out counter Disabled,1: Time-out counter Enabled"
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bitfld.long 0x4 1. "TOCDIV4,Time-out Counter Input Clock Divided by 4. When enabled the time-out period is extended 4 times." "0: Time-out period is extend 4 times Disabled,1: Time-out period is extend 4 times Enabled"
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newline
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bitfld.long 0x4 0. "TOIF,Time-out Flag. This bit is set by hardware when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (INTEN) is set to 1.. Note: Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_ADDR1,I2C Slave Address Register1"
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hexmask.long.word 0x8 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0x8 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0xC "I2C_ADDR2,I2C Slave Address Register2"
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hexmask.long.word 0xC 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0xC 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x10 "I2C_ADDR3,I2C Slave Address Register3"
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hexmask.long.word 0x10 1.--10. 1. "ADDR,I2C Address . The content of this register is irrelevant when I2C is in Master mode. In the slave mode the seven most significant bits must be loaded with the chip's own address. The I2C hardware will react if either of the address is matched.."
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bitfld.long 0x10 0. "GC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled"
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line.long 0x14 "I2C_ADDRMSK0,I2C Slave Address Mask Register0"
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hexmask.long.word 0x14 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x18 "I2C_ADDRMSK1,I2C Slave Address Mask Register1"
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hexmask.long.word 0x18 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x1C "I2C_ADDRMSK2,I2C Slave Address Mask Register2"
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hexmask.long.word 0x1C 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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line.long 0x20 "I2C_ADDRMSK3,I2C Slave Address Mask Register3"
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hexmask.long.word 0x20 1.--10. 1. "ADDRMSK,I2C Address Mask. I2C bus controllers support multiple address recognition with four address mask register. When the bit in the address mask register is set to one it means the received corresponding address bit is don't-care. If the bit is set.."
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group.long 0x3C++0x23
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line.long 0x0 "I2C_WKCTL,I2C Wake-up Control Register"
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bitfld.long 0x0 7. "NHDBUSEN,I2C No Hold BUS Enable Bit. Note: The I2C controller could respond when WKIF event is not clear it may cause error data transmitted or received. If data transmitted or received when WKIF event is not clear user must reset I2C controller and.." "0: I2C hold bus after wake-up,1: I2C don't hold bus after wake-up"
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bitfld.long 0x0 0. "WKEN,I2C Wake-up Enable Bit" "0: I2C wake-up function Disabled,1: I2C wake-up function Enabled"
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line.long 0x4 "I2C_WKSTS,I2C Wake-up Status Register"
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rbitfld.long 0x4 2. "WRSTSWK,Read/Write Status Bit in Address Wakeup Frame (Read Only). Note: This bit will be cleared when software can write 1 to WKAKDONE (I2C_WKSTS[1]) bit." "0: Write command be record on the address match..,1: Read command be record on the address match.."
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bitfld.long 0x4 1. "WKAKDONE,Wakeup Address Frame Acknowledge Bit Done. Note: This bit can't release WKIF. Software can write 1 to clear this bit." "0: The ACK bit cycle of address match frame isn't..,1: The ACK bit cycle of address match frame is done.."
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newline
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bitfld.long 0x4 0. "WKIF,I2C Wake-up Flag. When chip is woken up from Power-down mode by I2C this bit is set to 1. Software can write 1 to clear this bit." "0,1"
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line.long 0x8 "I2C_CTL1,I2C Control Register 1"
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bitfld.long 0x8 9. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10-bit function Disabled,1: Address match 10-bit function Enabled"
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bitfld.long 0x8 8. "PDMASTR,PDMA Stretch Bit" "0: I2C send STOP automatically after PDMA transfer..,1: I2C SCL bus is stretched by hardware after PDMA.."
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newline
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bitfld.long 0x8 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the I2C request to PDMA"
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bitfld.long 0x8 1. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0x8 0. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0xC "I2C_STATUS1,I2C Status Register 1"
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rbitfld.long 0xC 8. "ONBUSY,On Bus Busy (Read Only). Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected." "0: The bus is IDLE (both SCL and SDA High),1: The bus is busy"
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bitfld.long 0xC 3. "ADMAT3,I2C Address 3 Match Status. When address 3 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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newline
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bitfld.long 0xC 2. "ADMAT2,I2C Address 2 Match Status. When address 2 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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bitfld.long 0xC 1. "ADMAT1,I2C Address 1 Match Status. When address 1 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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newline
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bitfld.long 0xC 0. "ADMAT0,I2C Address 0 Match Status. When address 0 is matched hardware will inform which address used. This bit will set to 1 and software can write 1 to clear this bit." "0,1"
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line.long 0x10 "I2C_TMCTL,I2C Timing Configure Control Register"
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hexmask.long.word 0x10 16.--24. 1. "HTCTL,Hold Time Configure Control . This field is used to generate the delay timing between SCL falling edge and SDA rising edge in transmission mode."
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hexmask.long.word 0x10 0.--8. 1. "STCTL,Setup Time Configure Control. This field is used to generate a delay timing between SDA falling edge and SCL rising edge in transmission mode.. Note: Setup time setting should not make SCL output less than three PCLKs."
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line.long 0x14 "I2C_BUSCTL,I2C Bus Management Control Register"
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bitfld.long 0x14 13. "PECDIEN,Packet Error Checking Byte Transfer Done Interrupt Enable Bit" "0: PEC transfer done interrupt Disabled,1: PEC transfer done interrupt Enabled"
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bitfld.long 0x14 12. "BCDIEN,Packet Error Checking Byte Count Done Interrupt Enable Bit" "0: Byte count done interrupt Disabled,1: Byte count done interrupt Enabled"
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newline
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bitfld.long 0x14 11. "ACKM9SI,Acknowledge Manual Enable Extra SI Interrupt" "0: There is no SI interrupt in the 9th clock cycle..,1: There is SI interrupt in the 9th clock cycle.."
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bitfld.long 0x14 10. "PECCLR,PEC Clear at Repeat . The calculation of PEC starts when PECEN is set to 1 and it is cleared when the STA or STO bit is detected. This PECCLR bit used to enable the condition of Repeat START can clear the PEC calculation." "0: PEC calculation is cleared by 'Repeat START'..,1: PEC calculation is cleared by 'Repeat START'.."
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bitfld.long 0x14 9. "BUSTOCHK,Timer Check in Idle State. The BUSTOCHK is used to calculate the time-out of clock low in bus active and the idle period in bus Idle. This bit is used to define which condition is enabled.. Note: The BUSY (I2C_BUSSTS[0]) indicate the current bus.." "0: BUSTOCHK is used to calculate the clock low..,1: BUSTOCHK is used to calculate the IDLE period in.."
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bitfld.long 0x14 8. "PECTXEN,Packet Error Checking Byte Transmission/Reception" "0: No PEC transfer,1: PEC transmission is requested"
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bitfld.long 0x14 7. "BUSEN,BUS Enable Bit. Note: When the bit is enabled the internal 14-bit counter is used to calculate the time out event of clock low condition." "0: The system management function Disabled,1: The system management function Enabled"
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bitfld.long 0x14 6. "SCTLOEN,Suspend or Control Pin Output Enable Bit" "0: The SUSCON pin in input,1: The output enable is active on the SUSCON pin"
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bitfld.long 0x14 5. "SCTLOSTS,Suspend/Control Data Output Status" "0: The output of SUSCON pin is low,1: The output of SUSCON pin is high"
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bitfld.long 0x14 4. "ALERTEN,Bus Management Alert Enable Bit" "0: Release the BM_ALERT pin high and Alert Response..,1: Drive BM_ALERT pin low and Alert Response.."
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bitfld.long 0x14 3. "BMHEN,Bus Management Host Enable Bit" "0: Host function Disabled,1: Host function Enabled"
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bitfld.long 0x14 2. "BMDEN,Bus Management Device Default Address Enable Bit" "0: Device default address Disable. When the address..,1: Device default address Enabled. When the address.."
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bitfld.long 0x14 1. "PECEN,Packet Error Checking Calculation Enable Bit. Note: When I2C enters Power-down mode the bit should be enabled after wake-up if needed PEC calculation." "0: Packet Error Checking Calculation Disabled,1: Packet Error Checking Calculation Enabled"
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bitfld.long 0x14 0. "ACKMEN,Acknowledge Control by Manual. In order to allow ACK control in slave reception including the command and data slave byte control mode must be enabled by setting the ACKMEN bit." "0: Slave byte control Disabled,1: Slave byte control Enabled. The 9th bit can.."
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line.long 0x18 "I2C_BUSTCTL,I2C Bus Management Timer Control Register"
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bitfld.long 0x18 4. "TORSTEN,Time Out Reset Enable Bit" "0: I2C state machine reset Disabled,1: I2C state machine reset Enabled. (The clock and.."
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bitfld.long 0x18 3. "CLKTOIEN,Extended Clock Time Out Interrupt Enable Bit" "0: Clock time out interrupt Disabled,1: Clock time out interrupt Enabled"
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bitfld.long 0x18 2. "BUSTOIEN,Time-out Interrupt Enable Bit" "0: SCL low time-out interrupt Disabled.. Bus IDLE..,1: SCL low time-out interrupt Enabled.. Bus IDLE.."
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bitfld.long 0x18 1. "CLKTOEN,Cumulative Clock Low Time Out Enable Bit. For Master it calculates the period from START to ACK.. For Slave it calculates the period from START to STOP." "0: Cumulative clock low time-out detection Disabled,1: Cumulative clock low time-out detection Enabled"
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bitfld.long 0x18 0. "BUSTOEN,Bus Time Out Enable Bit" "0: Bus clock low time-out detection Disabled,1: Bus clock low time-out detection Enabled (bus.."
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line.long 0x1C "I2C_BUSSTS,I2C Bus Management Status Register"
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bitfld.long 0x1C 7. "PECDONE,PEC Byte Transmission/Receive Done . Note: Software can write 1 to clear this bit." "0: PEC transmission/ receive is not finished when..,1: PEC transmission/ receive is finished when the.."
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bitfld.long 0x1C 6. "CLKTO,Clock Low Cumulate Time-out Status . Note: Software can write 1 to clear this bit." "0: Cumulative clock low is no any time-out,1: Cumulative clock low time-out occurred"
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bitfld.long 0x1C 5. "BUSTO,Bus Time-out Status . In bus busy the bit indicates the total clock low time-out event occurred; otherwise it indicates the bus idle time-out event occurred.. Note: Software can write 1 to clear this bit." "0: There is no any time-out or external clock..,1: A time-out or external clock time-out occurred"
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rbitfld.long 0x1C 4. "SCTLDIN,Bus Suspend or Control Signal Input Status (Read Only)" "0: The input status of SUSCON pin is 0,1: The input status of SUSCON pin is 1"
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bitfld.long 0x1C 3. "ALERT,SMBus Alert Status . Note: 1. The SMBALERT pin is an open-drain pin the pull-high resistor is must in the system. 2. Software can write 1 to clear this bit." "0: SMBALERT pin state is low.. No SMBALERT event,1: SMBALERT pin state is high.. There is SMBALERT.."
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bitfld.long 0x1C 2. "PECERR,PEC Error in Reception . Note: Software can write 1 to clear this bit." "0: PEC value equal the received PEC data packet,1: PEC value doesn't match the receive PEC data.."
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bitfld.long 0x1C 1. "BCDONE,Byte Count Transmission/Receive Done . Note: Software can write 1 to clear this bit." "0: Byte count transmission/ receive is not finished..,1: Byte count transmission/ receive is finished.."
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rbitfld.long 0x1C 0. "BUSY,Bus Busy (Read Only). Indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a STOP condition is detected" "0: Bus is IDLE (both SCL and SDA High),1: Bus is busy"
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line.long 0x20 "I2C_PKTSIZE,I2C Packet Error Checking Byte Number Register"
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hexmask.long.word 0x20 0.--8. 1. "PLDSIZE,Transfer Byte Number. The transmission or receive byte number in one transaction when the PECEN is set. The maximum transaction or receive byte is 256 Bytes.. Note: The byte number counting includes address command code and data frame."
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rgroup.long 0x60++0x3
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line.long 0x0 "I2C_PKTCRC,I2C Packet Error Checking Byte Value Register"
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hexmask.long.byte 0x0 0.--7. 1. "PECCRC,Packet Error Checking Byte Value"
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group.long 0x64++0x7
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line.long 0x0 "I2C_BUSTOUT,I2C Bus Management Timer Register"
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hexmask.long.byte 0x0 0.--7. 1. "BUSTO,Bus Management Time-out Value. Indicates the bus time-out value in bus is IDLE or SCL low.. Note: If the user wants to revise the value of BUSTOUT the TORSTEN (I2C_BUSTCTL[4]) bit shall be set to 1 and cleared to 0 first in the.."
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line.long 0x4 "I2C_CLKTOUT,I2C Bus Management Clock Low Timer Register"
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hexmask.long.byte 0x4 0.--7. 1. "CLKTO,Bus Clock Low Timer. The field is used to configure the cumulative clock extension time-out.. Note: If the user wants to revise the value of CLKLTOUT the TORSTEN bit shall be set to 1 and cleared to 0 first in the BUSEN is set."
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tree.end
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tree.end
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tree "LLSI (LED Lighting Strip Interface)"
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base ad:0x0
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tree "LLSI0"
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base ad:0x40054000
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group.long 0x0++0xF
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line.long 0x0 "LLSI_CTL,LLSI Control Register"
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bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
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bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
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bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
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bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
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bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
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bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
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bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
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bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
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line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
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hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
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line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
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hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
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line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
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hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
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hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
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wgroup.long 0x10++0x3
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line.long 0x0 "LLSI_DATA,LLSI Data Register"
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hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
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group.long 0x14++0xF
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line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
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hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
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line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
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line.long 0x8 "LLSI_STATUS,LLSI Status Register"
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bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
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bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
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bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
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line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
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bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
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tree.end
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tree "LLSI1"
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base ad:0x40154000
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group.long 0x0++0xF
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line.long 0x0 "LLSI_CTL,LLSI Control Register"
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bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
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bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
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bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
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bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
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bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
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bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
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bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
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newline
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bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
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line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
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hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
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line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
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hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
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line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
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hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
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hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
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wgroup.long 0x10++0x3
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line.long 0x0 "LLSI_DATA,LLSI Data Register"
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hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
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group.long 0x14++0xF
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line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
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hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
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line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
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line.long 0x8 "LLSI_STATUS,LLSI Status Register"
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bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
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bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
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newline
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bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
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bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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newline
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bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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newline
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bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
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line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
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bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
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tree.end
|
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tree "LLSI2"
|
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base ad:0x40054200
|
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group.long 0x0++0xF
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line.long 0x0 "LLSI_CTL,LLSI Control Register"
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bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
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newline
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bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
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bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
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bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
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newline
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bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
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bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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newline
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bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
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bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
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newline
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bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
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line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
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hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
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line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
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hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
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line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
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hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
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hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
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line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
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hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
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line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
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newline
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bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
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|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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newline
|
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bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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newline
|
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bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
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line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI3"
|
|
base ad:0x40154200
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
|
|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
|
|
bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI4"
|
|
base ad:0x40054400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
|
|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
|
|
bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI5"
|
|
base ad:0x40154400
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
|
|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
|
|
bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI6"
|
|
base ad:0x40054600
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
|
|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
|
|
bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI7"
|
|
base ad:0x40154600
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
|
|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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|
newline
|
|
bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
|
|
bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
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|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI8"
|
|
base ad:0x40054800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
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|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
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|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
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|
newline
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bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
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bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
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|
newline
|
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bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
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|
newline
|
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bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree "LLSI9"
|
|
base ad:0x40154800
|
|
group.long 0x0++0xF
|
|
line.long 0x0 "LLSI_CTL,LLSI Control Register"
|
|
bitfld.long 0x0 16.--17. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
|
|
bitfld.long 0x0 12. "OFDEF,Output Format Define" "0: Output RGB format,1: Output GRB format"
|
|
newline
|
|
bitfld.long 0x0 8. "LLSIMODE,LLSI Mode Select" "0: Software mode,1: PDMA mode"
|
|
bitfld.long 0x0 7. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit. Note: This bit is only supported in software mode." "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 6. "FULINTEN,FIFO FULL Interrupt Enable Bit. Note: If this bit is enabled when the FULIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO full interrupt Disabled,1: FIFO full interrupt Enabled"
|
|
bitfld.long 0x0 5. "EMPINTEN,FIFO Empty Interrupt Enable Bit. Note: If this bit is enabled when the EMPIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: FIFO empty interrupt Disabled,1: FIFO empty interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 4. "RSTCINTEN,Reset Command Interrupt Enable Bit. Note: If this bit is enabled when the RSTCIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Reset command interrupt Disabled,1: Reset command interrupt Enabled"
|
|
bitfld.long 0x0 3. "FENDINTEN,Frame End Interrupt Enable Bit. Note: If this bit is enabled when the FENDIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Frame end interrupt Disabled,1: Frame end interrupt Enabled"
|
|
newline
|
|
bitfld.long 0x0 2. "UNDFLINTEN,Underflow Interrupt Enable Bit. Note: If this bit is enabled when the UNDFLIF interrupt flag is set to 1 the LLSI interrupt signal is generated and inform to CPU." "0: Underflow interrupt Disabled,1: Underflow interrupt Enabled"
|
|
bitfld.long 0x0 1. "RSTCEN,Reset Command Function Enable Bit. Note: If this bit is enabled when FIFO and shift register are both empty LLSI will send reset command out." "0: Reset command function Disabled,1: Reset command function Enabled"
|
|
newline
|
|
bitfld.long 0x0 0. "LLSIEN,LLSI Enable Bit" "0: LLSI Disabled,1: LLSI Enabled"
|
|
line.long 0x4 "LLSI_RSTPERIOD,LLSI Reset Period Control Register"
|
|
hexmask.long.word 0x4 0.--15. 1. "RSTPERIOD,Reset Command Period. This field is used to adjust the time of reset command."
|
|
line.long 0x8 "LLSI_PERIOD,LLSI Period Control Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. "PERIOD,LLSI Period Register. This field is used to define data transfer time (TH+TL)."
|
|
line.long 0xC "LLSI_DUTY,LLSI Duty Control Register"
|
|
hexmask.long.byte 0xC 16.--23. 1. "T1H,T1H Data Register. This field is used to define the time of T1H."
|
|
hexmask.long.byte 0xC 0.--7. 1. "T0H,T0H Data Register. This field is used to define the time of T0H."
|
|
wgroup.long 0x10++0x3
|
|
line.long 0x0 "LLSI_DATA,LLSI Data Register"
|
|
hexmask.long 0x0 0.--31. 1. "DATA,Data Transmit Register . The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers."
|
|
group.long 0x14++0xF
|
|
line.long 0x0 "LLSI_PCNT,LLSI Pixel Count Register"
|
|
hexmask.long.word 0x0 0.--11. 1. "PCNT,Pixel Count Register. User should write a frame size to this register before transfer.. For example if there are a total of 5 LED (5 pixels) in frame user should write 5 to this control register."
|
|
line.long 0x4 "LLSI_CLKDIV,LLSI Clock Divider Register"
|
|
hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,LLSI Clock Divider. It indicates the LLSI clock "
|
|
line.long 0x8 "LLSI_STATUS,LLSI Status Register"
|
|
bitfld.long 0x8 8. "LDT,Last Data Transmit" "0,1"
|
|
bitfld.long 0x8 5. "FENDIF,Frame End Interrupt Flag. This bit indicates that LLSI has finished data transmission (FIFO empty shift register empty). When LLSI transfer finish (FIFO empty shift register empty) this bit is set to 1.. User can use this flag to prepare data in.." "0,1"
|
|
newline
|
|
bitfld.long 0x8 4. "UNDFLIF,Under Flow Interrupt Flag. Each transmission LLSI reads 3 bytes data from the FIFO. This bit is set to 1 when LLSI reads the FIFO and the valid data in FIFO is less than 3 bytes.. Software can write 1 to clear this bit." "0,1"
|
|
bitfld.long 0x8 3. "TXTHIF,Transmit FIFO Threshold Interrupt Flag" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
|
|
newline
|
|
bitfld.long 0x8 2. "FULIF,FIFO Full Interrupt Flag" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
|
|
bitfld.long 0x8 1. "EMPIF,FIFO Empty Interrupt Flag" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
|
|
newline
|
|
bitfld.long 0x8 0. "RSTCIF,Reset Command Interrupt Flag. This bit indicates that LLSI has finished reset command transmission." "0,1"
|
|
line.long 0xC "LLSI_OCTL,LLSI Output Control Register"
|
|
bitfld.long 0xC 0. "IDOS,Idle Output Control" "0: Idle will output 0,1: Idle will output 1"
|
|
tree.end
|
|
tree.end
|
|
tree "NMI (Non-maskable Interrupt)"
|
|
base ad:0x50000300
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "NMIEN,NMI Source Interrupt Enable Register"
|
|
bitfld.long 0x0 15. "UART1_INT,UART1 NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled"
|
|
bitfld.long 0x0 14. "UART0_INT,UART0 NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x0 13. "EINT5,External Interrupt From INT5 Pin NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT5 pin NMI source..,1: External interrupt from INT5 pin NMI source.."
|
|
bitfld.long 0x0 12. "EINT4,External Interrupt From INT4 Pin NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT4 pin NMI source..,1: External interrupt from INT4 pin NMI source.."
|
|
newline
|
|
bitfld.long 0x0 11. "EINT3,External Interrupt From INT3 Pin NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT3 pin NMI source..,1: External interrupt from INT3 pin NMI source.."
|
|
bitfld.long 0x0 10. "EINT2,External Interrupt From INT2 Pin NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT2 pin NMI source..,1: External interrupt from INT2 pin NMI source.."
|
|
newline
|
|
bitfld.long 0x0 9. "EINT1,External Interrupt From INT1 Pin NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT1 pin NMI source..,1: External interrupt from INT1 pin NMI source.."
|
|
bitfld.long 0x0 8. "EINT0,External Interrupt From INT0 Pin NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: External interrupt from INT0 pin NMI source..,1: External interrupt from INT0 pin NMI source.."
|
|
newline
|
|
bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Clock fail detected interrupt NMI source Disabled,1: Clock fail detected interrupt NMI source Enabled"
|
|
bitfld.long 0x0 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "IRC_INT,IRC TRIM NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled"
|
|
bitfld.long 0x0 0. "BODOUT,BOD NMI Source Enable Bit (Write Protect). Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: BOD NMI source Disabled,1: BOD NMI source Enabled"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "NMISTS,NMI Source Interrupt Status Register"
|
|
bitfld.long 0x0 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
bitfld.long 0x0 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 13. "EINT5,External Interrupt From INT5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT5 pin interrupt is..,1: External Interrupt from INT5 pin interrupt is.."
|
|
bitfld.long 0x0 12. "EINT4,External Interrupt From INT4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT4 pin interrupt is..,1: External Interrupt from INT4 pin interrupt is.."
|
|
newline
|
|
bitfld.long 0x0 11. "EINT3,External Interrupt From INT3 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT3 pin interrupt is..,1: External Interrupt from INT3 pin interrupt is.."
|
|
bitfld.long 0x0 10. "EINT2,External Interrupt From INT2 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT2 pin interrupt is..,1: External Interrupt from INT2 pin interrupt is.."
|
|
newline
|
|
bitfld.long 0x0 9. "EINT1,External Interrupt From INT1 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT1 pin interrupt is..,1: External Interrupt from INT1 pin interrupt is.."
|
|
bitfld.long 0x0 8. "EINT0,External Interrupt From INT0 Pin Interrupt Flag (Read Only)" "0: External Interrupt from INT0 pin interrupt is..,1: External Interrupt from INT0 pin interrupt is.."
|
|
newline
|
|
bitfld.long 0x0 4. "CLKFAIL,Clock Fail Detected Interrupt Flag (Read Only)" "0: Clock fail detected interrupt is deasserted,1: Clock fail detected interrupt is asserted"
|
|
bitfld.long 0x0 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted"
|
|
newline
|
|
bitfld.long 0x0 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted"
|
|
bitfld.long 0x0 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted"
|
|
tree.end
|
|
tree "NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
group.long 0x0++0x7
|
|
line.long 0x0 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETENA,Interrupt Set Enable Bit. The NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled. Write Operation:"
|
|
line.long 0x4 "NVIC_ISER1,IRQ32 ~ IRQ41 Set-enable Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETENA,Interrupt Set Enable Bit. The NVIC_ISER0-NVIC_ISER1 registers enable interrupts and show which interrupts are enabled. Write Operation:"
|
|
group.long 0x80++0x7
|
|
line.long 0x0 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CALENA,Interrupt Clear Enable Bit. The NVIC_ICER0-NVIC_ICER1 registers disable interrupts and show which interrupts are enabled.. Write Operation:"
|
|
line.long 0x4 "NVIC_ICER1,IRQ32 ~ IRQ41 Clear-enable Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "CALENA,Interrupt Clear Enable Bit. The NVIC_ICER0-NVIC_ICER2 registers disable interrupts and show which interrupts are enabled.. Write Operation:"
|
|
group.long 0x100++0x7
|
|
line.long 0x0 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "SETPEND,Interrupt Set-pending . The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending. Write Operation:"
|
|
line.long 0x4 "NVIC_ISPR1,IRQ32 ~ IRQ41 Set-pending Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "SETPEND,Interrupt Set-pending . The NVIC_ISPR0-NVIC_ISPR1 registers force interrupts into the pending state and show which interrupts are pending. Write Operation:"
|
|
group.long 0x180++0x7
|
|
line.long 0x0 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register"
|
|
hexmask.long 0x0 0.--31. 1. "CALPEND,Interrupt Clear-pending. The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending. Write Operation:"
|
|
line.long 0x4 "NVIC_ICPR1,IRQ32 ~ IRQ41 Clear-pending Control Register"
|
|
hexmask.long 0x4 0.--31. 1. "CALPEND,Interrupt Clear-pending. The NVIC_ICPR0-NVIC_ICPR1 registers remove the pending state from interrupts and show which interrupts are pending. Write Operation:"
|
|
group.long 0x200++0x7
|
|
line.long 0x0 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register"
|
|
hexmask.long 0x0 0.--31. 1. "ACTIVE,Interrupt Active Flags. The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active."
|
|
line.long 0x4 "NVIC_IABR1,IRQ32 ~ IRQ41 Active Bit Register"
|
|
hexmask.long 0x4 0.--31. 1. "ACTIVE,Interrupt Active Flags. The NVIC_IABR0-NVIC_IABR1 registers indicate which interrupts are active."
|
|
tree.end
|
|
tree "PDMA (Peripheral Direct Memory Access)"
|
|
base ad:0x50008000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x40++0x3
|
|
line.long 0x0 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x50++0x3
|
|
line.long 0x0 "PDMA_DSCT5_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "PDMA_DSCT6_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x70++0x3
|
|
line.long 0x0 "PDMA_DSCT7_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "PDMA_DSCT8_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x90++0x3
|
|
line.long 0x0 "PDMA_DSCT9_CTL,Descriptor Table Control Register of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--29. 1. "TXCNT,Transfer Count. The TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.. Note: When.."
|
|
bitfld.long 0x0 12.--13. "TXWIDTH,Transfer Width Selection. This field is used for transfer width.. Note: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection. For example if source.." "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for every..,?,?"
|
|
newline
|
|
bitfld.long 0x0 10.--11. "DAINC,Destination Address Increment. This field is used to set the destination address increment size." "?,?,?,?"
|
|
bitfld.long 0x0 8.--9. "SAINC,Source Address Increment. This Field Is Used To Set The Source Address Increment Size." "?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 7. "TBINTDIS,Table Interrupt Disable Bit. This field can be used to decide whether to enable table interrupt or not. If the TBINTDIS bit is enabled when PDMA controller finishes transfer task it will not generates transfer done interrupt.. Note: If this bit.." "0: Table interrupt Enabled,1: Table interrupt Disabled"
|
|
bitfld.long 0x0 4.--6. "BURSIZE,Burst Size. This field is used for peripheral to determine the burst size or used to determine the re-arbitration size.. Note: This field is only useful in burst transfer type." "0: 128 Transfers,1: 64 Transfers,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type"
|
|
bitfld.long 0x0 0.--1. "OPMODE,PDMA Operation Mode Selection. Note: Before filling transfer task in the Descriptor Table user must check if the descriptor table is complete." "0: Idle state: Channel is stopped or this table is..,1: Basic mode: The descriptor table only has one..,?,?"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x24++0x3
|
|
line.long 0x0 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x34++0x3
|
|
line.long 0x0 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x44++0x3
|
|
line.long 0x0 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x54++0x3
|
|
line.long 0x0 "PDMA_DSCT5_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "PDMA_DSCT6_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x74++0x3
|
|
line.long 0x0 "PDMA_DSCT7_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "PDMA_DSCT8_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x94++0x3
|
|
line.long 0x0 "PDMA_DSCT9_SA,Source Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "SA,PDMA Transfer Source Address Register. This field indicates a 32-bit source address of PDMA controller."
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x38++0x3
|
|
line.long 0x0 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x48++0x3
|
|
line.long 0x0 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x58++0x3
|
|
line.long 0x0 "PDMA_DSCT5_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x68++0x3
|
|
line.long 0x0 "PDMA_DSCT6_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x78++0x3
|
|
line.long 0x0 "PDMA_DSCT7_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x88++0x3
|
|
line.long 0x0 "PDMA_DSCT8_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "PDMA_DSCT9_DA,Destination Address Register of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "DA,PDMA Transfer Destination Address Register. This field indicates a 32-bit destination address of PDMA controller."
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PDMA_DSCT0_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "PDMA_DSCT1_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "PDMA_DSCT2_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x3C++0x3
|
|
line.long 0x0 "PDMA_DSCT3_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x4C++0x3
|
|
line.long 0x0 "PDMA_DSCT4_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x5C++0x3
|
|
line.long 0x0 "PDMA_DSCT5_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x6C++0x3
|
|
line.long 0x0 "PDMA_DSCT6_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x7C++0x3
|
|
line.long 0x0 "PDMA_DSCT7_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x8C++0x3
|
|
line.long 0x0 "PDMA_DSCT8_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
group.long 0x9C++0x3
|
|
line.long 0x0 "PDMA_DSCT9_FIRST,First Scatter-gather Descriptor Table Offset of PDMA Channel n"
|
|
hexmask.long.word 0x0 16.--31. 1. "NEXT,PDMA Next Descriptor Table Offset. This field indicates the offset of next descriptor table address in system memory. . Note: write operation is useless in this field."
|
|
hexmask.long.word 0x0 0.--15. 1. "FIRST,PDMA First Descriptor Table Offset. This field indicates the offset of the first descriptor table address in system memory. . Write Operation:. If the system memory based address is 0x2000_0000 (PDMA_SCATBA) and the first descriptor table is.."
|
|
rgroup.long 0xA0++0x27
|
|
line.long 0x0 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x0 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x4 "PDMA_CURSCAT1,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x4 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x8 "PDMA_CURSCAT2,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x8 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0xC "PDMA_CURSCAT3,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0xC 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x10 "PDMA_CURSCAT4,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x10 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x14 "PDMA_CURSCAT5,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x14 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x18 "PDMA_CURSCAT6,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x18 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x1C "PDMA_CURSCAT7,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x1C 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x20 "PDMA_CURSCAT8,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x20 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
line.long 0x24 "PDMA_CURSCAT9,Current Scatter-gather Descriptor Table Address of PDMA Channel n"
|
|
hexmask.long 0x24 0.--31. 1. "CURADDR,PDMA Current Description Address Register (Read Only). This field indicates a 32-bit current external description address of PDMA controller.. Note: This field is read only and only used for Scatter-Gather mode to indicate the current external.."
|
|
group.long 0x400++0x3
|
|
line.long 0x0 "PDMA_CHCTL,PDMA Channel Control Register"
|
|
bitfld.long 0x0 9. "CHEN9,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 8. "CHEN8,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 7. "CHEN7,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 6. "CHEN6,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 5. "CHEN5,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 4. "CHEN4,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 3. "CHEN3,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 2. "CHEN2,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
newline
|
|
bitfld.long 0x0 1. "CHEN1,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
bitfld.long 0x0 0. "CHEN0,PDMA Channel n Enable Bit. Set this bit to 1 to enable PDMAn operation. Channel cannot be active if it is not set as enabled.. Note: Set PDMA_PAUSE or PDMA_RESET register will also clear this bit." "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled"
|
|
wgroup.long 0x404++0x7
|
|
line.long 0x0 "PDMA_PAUSE,PDMA Transfer Pause Control Register"
|
|
bitfld.long 0x0 9. "PAUSE9,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 8. "PAUSE8,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 7. "PAUSE7,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 6. "PAUSE6,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 5. "PAUSE5,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 4. "PAUSE4,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 3. "PAUSE3,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 2. "PAUSE2,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
newline
|
|
bitfld.long 0x0 1. "PAUSE1,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
bitfld.long 0x0 0. "PAUSE0,PDMA Channel n Transfer Pause Control Register (Write Only)" "0: No effect,1: Pause PDMA channel n transfer"
|
|
line.long 0x4 "PDMA_SWREQ,PDMA Software Request Register"
|
|
bitfld.long 0x4 9. "SWREQ9,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
bitfld.long 0x4 8. "SWREQ8,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
newline
|
|
bitfld.long 0x4 7. "SWREQ7,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
bitfld.long 0x4 6. "SWREQ6,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
newline
|
|
bitfld.long 0x4 5. "SWREQ5,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
bitfld.long 0x4 4. "SWREQ4,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
newline
|
|
bitfld.long 0x4 3. "SWREQ3,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
bitfld.long 0x4 2. "SWREQ2,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
newline
|
|
bitfld.long 0x4 1. "SWREQ1,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
bitfld.long 0x4 0. "SWREQ0,PDMA Channel n Software Request Register (Write Only). Set this bit to 1 to generate a software request to PDMA [n].. Note 1: User can read PDMA_TRGSTS register to know which channel is on active. Active flag may be triggered by software request.." "0: No effect,1: User can read PDMA_TRGSTS register to know which.."
|
|
rgroup.long 0x40C++0x3
|
|
line.long 0x0 "PDMA_TRGSTS,PDMA Channel Request Status Register"
|
|
bitfld.long 0x0 9. "REQSTS9,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x0 8. "REQSTS8,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x0 7. "REQSTS7,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x0 6. "REQSTS6,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x0 5. "REQSTS5,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x0 4. "REQSTS4,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x0 3. "REQSTS3,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x0 2. "REQSTS2,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
newline
|
|
bitfld.long 0x0 1. "REQSTS1,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
bitfld.long 0x0 0. "REQSTS0,PDMA Channel n Request Status (Read Only). This flag indicates whether channel[n] have a request or not no matter request from software or peripheral. When the PDMA controller finishes channel transfer this bit will be cleared automatically. ." "0: PDMA Channel n has no request,1: PDMA Channel n has a request"
|
|
group.long 0x410++0x3
|
|
line.long 0x0 "PDMA_PRISET,PDMA Fixed Priority Setting Register"
|
|
bitfld.long 0x0 9. "FPRISET9,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
|
|
bitfld.long 0x0 8. "FPRISET8,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
|
|
newline
|
|
bitfld.long 0x0 7. "FPRISET7,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
|
|
bitfld.long 0x0 6. "FPRISET6,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
|
|
newline
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bitfld.long 0x0 5. "FPRISET5,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
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bitfld.long 0x0 4. "FPRISET4,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
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bitfld.long 0x0 3. "FPRISET3,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
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bitfld.long 0x0 2. "FPRISET2,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
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bitfld.long 0x0 1. "FPRISET1,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
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bitfld.long 0x0 0. "FPRISET0,PDMA Channel n Fixed Priority Setting Register. Set this bit to 1 to enable fixed priority level. The fixed priority channel has higher priority than round-robin priority channel. If multiple channels are set as the same priority the higher.." "0: No effect.. Corresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority channel.."
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wgroup.long 0x414++0x3
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line.long 0x0 "PDMA_PRICLR,PDMA Fixed Priority Clear Register"
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bitfld.long 0x0 9. "FPRICLR9,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 8. "FPRICLR8,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 7. "FPRICLR7,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 6. "FPRICLR6,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 5. "FPRICLR5,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 4. "FPRICLR4,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 3. "FPRICLR3,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 2. "FPRICLR2,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 1. "FPRICLR1,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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bitfld.long 0x0 0. "FPRICLR0,PDMA Channel n Fixed Priority Clear Register (Write Only). Set this bit to 1 to clear fixed priority level.. Note: User can read PDMA_PRISET register to know the channel priority." "0: No effect,1: Clear PDMA channel [n] fixed priority setting"
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group.long 0x418++0x13
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line.long 0x0 "PDMA_INTEN,PDMA Interrupt Enable Register"
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bitfld.long 0x0 9. "INTEN9,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 8. "INTEN8,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 7. "INTEN7,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 6. "INTEN6,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 5. "INTEN5,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 4. "INTEN4,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 3. "INTEN3,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 2. "INTEN2,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 1. "INTEN1,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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bitfld.long 0x0 0. "INTEN0,PDMA Channel n Interrupt Enable Register. This field is used for enabling PDMA channel[n] interrupt." "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled"
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line.long 0x4 "PDMA_INTSTS,PDMA Interrupt Status Register"
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bitfld.long 0x4 9. "REQTOF1,PDMA Channel n Request Time-out Flag. This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits." "0: No request time-out,1: Peripheral request time-out"
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bitfld.long 0x4 8. "REQTOF0,PDMA Channel n Request Time-out Flag. This flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOCn user can write 1 to clear these bits." "0: No request time-out,1: Peripheral request time-out"
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rbitfld.long 0x4 2. "TEIF,Table Empty Interrupt Flag (Read Only). This bit indicates PDMA channel scatter-gather table is empty. User can read PDMA_SCATSTS register to indicate which channel scatter-gather table is empty." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty"
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rbitfld.long 0x4 1. "TDIF,Transfer Done Interrupt Flag (Read Only). This bit indicates that PDMA controller has finished transmission; User can read PDMA_TDSTS register to indicate which channel finished transfer." "0: Not finished yet,1: PDMA channel has finished transmission"
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rbitfld.long 0x4 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only). This bit indicates that PDMA has target abort error; Software can read PDMA_ABTSTS register to find which channel has target abort error." "0: No AHB bus ERROR response received,1: AHB bus ERROR response received"
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line.long 0x8 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register"
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bitfld.long 0x8 9. "ABTIF9,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 8. "ABTIF8,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 7. "ABTIF7,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 6. "ABTIF6,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 5. "ABTIF5,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 4. "ABTIF4,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 3. "ABTIF3,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 2. "ABTIF2,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 1. "ABTIF1,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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bitfld.long 0x8 0. "ABTIF0,PDMA Channel n Read/Write Target Abort Interrupt Status Flag. This bit indicates which PDMA controller has target abort error; User can write 1 to clear these bits." "0: No AHB bus ERROR response received when channel..,1: AHB bus ERROR response received when channel n.."
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line.long 0xC "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register"
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bitfld.long 0xC 9. "TDIF9,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 8. "TDIF8,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 7. "TDIF7,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 6. "TDIF6,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 5. "TDIF5,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 4. "TDIF4,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 3. "TDIF3,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 2. "TDIF2,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 1. "TDIF1,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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bitfld.long 0xC 0. "TDIF0,PDMA Channel n Transfer Done Flag Register. This bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits." "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission"
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line.long 0x10 "PDMA_SCATSTS,PDMA Scatter-gather Table Empty Status Register"
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bitfld.long 0x10 9. "TEMPTYF9,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 8. "TEMPTYF8,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 7. "TEMPTYF7,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 6. "TEMPTYF6,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 5. "TEMPTYF5,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 4. "TEMPTYF4,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 3. "TEMPTYF3,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 2. "TEMPTYF2,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 1. "TEMPTYF1,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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bitfld.long 0x10 0. "TEMPTYF0,Table Empty Flag Register. T This bit indicates which PDMA channel table is empty when channel has a request no matter request from software or peripheral but operation mode of channel descriptor table is idle state or channel has finished.." "0: PDMA channel scatter-gather table is not empty,1: PDMA channel scatter-gather table is empty and.."
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rgroup.long 0x42C++0x3
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line.long 0x0 "PDMA_TACTSTS,PDMA Transfer Active Flag Register"
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bitfld.long 0x0 9. "TXACTF9,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 8. "TXACTF8,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 7. "TXACTF7,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 6. "TXACTF6,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 5. "TXACTF5,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 4. "TXACTF4,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 3. "TXACTF3,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 2. "TXACTF2,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 1. "TXACTF1,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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bitfld.long 0x0 0. "TXACTF0,PDMA Channel n Transfer on Active Flag Register (Read Only). This bit indicates which PDMA channel is in active." "0: PDMA channel is not finished,1: PDMA channel is active"
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group.long 0x430++0x13
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line.long 0x0 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register"
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bitfld.long 0x0 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,?,?,?,?,?,?"
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bitfld.long 0x0 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,?,?,?,?,?,?"
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line.long 0x4 "PDMA_TOUTEN,PDMA Time-out Enable Register"
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bitfld.long 0x4 1. "TOUTEN1,PDMA Channel n Time-out Enable Bit" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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bitfld.long 0x4 0. "TOUTEN0,PDMA Channel n Time-out Enable Bit" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled"
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line.long 0x8 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register"
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bitfld.long 0x8 1. "TOUTIEN1,PDMA Channel n Time-out Interrupt Enable Bit" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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bitfld.long 0x8 0. "TOUTIEN0,PDMA Channel n Time-out Interrupt Enable Bit" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled"
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line.long 0xC "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register"
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hexmask.long.word 0xC 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address Register. In Scatter-Gather mode this is the base address for calculating the next link - list address. The next link address equation is . Note: Only useful in Scatter-Gather mode."
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line.long 0x10 "PDMA_TOC0_1,PDMA Channel 0 and Channel 1 Time-out Counter Register"
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hexmask.long.word 0x10 16.--31. 1. "TOC1,Time-out Counter for Channel 1. This controls the period of time-out function for channel 1. The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock. The example of time-out period can refer TOC0 bit description."
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hexmask.long.word 0x10 0.--15. 1. "TOC0,Time-out Counter for Channel 0. This controls the period of time-out function for channel 0. The calculation unit is based on TOUTPSC0 (PDMA_TOUTPSC[2:0]) clock."
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group.long 0x460++0x3
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line.long 0x0 "PDMA_RESET,PDMA Channel Reset Control Register"
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bitfld.long 0x0 9. "RESET9,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 8. "RESET8,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 7. "RESET7,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 6. "RESET6,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 5. "RESET5,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 4. "RESET4,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 3. "RESET3,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 2. "RESET2,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 1. "RESET1,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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bitfld.long 0x0 0. "RESET0,PDMA Channel n Reset Control Register . Note: This bit will be cleared automatically after finishing reset process." "0: No effect,1: Reset PDMA channel n"
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group.long 0x480++0xB
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line.long 0x0 "PDMA_REQSEL0_3,PDMA Channel 0 to Channel 3 Request Source Select Register"
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hexmask.long.byte 0x0 24.--29. 1. "REQSRC3,Channel 3 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 3. User can configure the peripheral setting by REQSRC3. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 16.--21. 1. "REQSRC2,Channel 2 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 2. User can configure the peripheral setting by REQSRC2. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 8.--13. 1. "REQSRC1,Channel 1 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 1. User can configure the peripheral setting by REQSRC1. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x0 0.--5. 1. "REQSRC0,Channel 0 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 0. User can configure the peripheral by setting REQSRC0.. Note 1: A request source can't assign to two channels at the same time.. Note 2: This.."
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line.long 0x4 "PDMA_REQSEL4_7,PDMA Channel 4 to Channel 7 Request Source Select Register"
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|
hexmask.long.byte 0x4 24.--29. 1. "REQSRC7,Channel 7 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 7. User can configure the peripheral setting by REQSRC7. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 16.--21. 1. "REQSRC6,Channel 6 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 6. User can configure the peripheral setting by REQSRC6. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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|
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hexmask.long.byte 0x4 8.--13. 1. "REQSRC5,Channel 5 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 5. User can configure the peripheral setting by REQSRC5. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x4 0.--5. 1. "REQSRC4,Channel 4 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 4. User can configure the peripheral setting by REQSRC4. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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line.long 0x8 "PDMA_REQSEL8_9,PDMA Channel 8 to Channel 9 Request Source Select Register"
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hexmask.long.byte 0x8 8.--13. 1. "REQSRC9,Channel 9 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 9. User can configure the peripheral setting by REQSRC9. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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hexmask.long.byte 0x8 0.--5. 1. "REQSRC8,Channel 8 Request Source Selection. This filed defines which peripheral is connected to PDMA channel 8. User can configure the peripheral setting by REQSRC8. . Note: The channel configuration is the same as REQSRC0 field. Please refer to the.."
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tree.end
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tree "SCS (System Controller Space)"
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base ad:0xE000E000
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|
group.long 0x10++0xB
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|
line.long 0x0 "SYST_CSR,SysTick Control and Status Register"
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|
bitfld.long 0x0 16. "COUNTFLAG,System Tick Counter Flag. Returns 1 if timer counted to 0 since last time this register is read.. COUNTFLAG is set by a count transition from 1 to 0.. COUNTFLAG is cleared on read or by a write to the Current Value register." "0,1"
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bitfld.long 0x0 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick"
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bitfld.long 0x0 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.."
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bitfld.long 0x0 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner"
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line.long 0x4 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "RELOAD,System Tick Reload Value. Value to load into the Current Value register when the counter reaches 0."
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|
line.long 0x8 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x8 0.--23. 1. "CURRENT,System Tick Current Value. Current counter value. This is the value of the counter at the time it is sampled. The counter does not provide read-modify-write protection. The register is write-clear. A software write of any value will clear the.."
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|
rgroup.long 0xD00++0x3
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|
line.long 0x0 "CPUID,CPUID Register"
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|
hexmask.long.byte 0x0 24.--31. 1. "IMPLEMENTER,Implementer Code Assigned by Arm"
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|
hexmask.long.byte 0x0 16.--19. 1. "PART,Architecture of the Processor. Read as 0xC for Armv6-M parts."
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|
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hexmask.long.word 0x0 4.--15. 1. "PARTNO,Part Number of the Processor. Read as 0xC20."
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|
hexmask.long.byte 0x0 0.--3. 1. "REVISION,Revision Number. Read as 0x0."
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|
group.long 0xD04++0x3
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line.long 0x0 "ICSR,Interrupt Control and State Register"
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bitfld.long 0x0 31. "NMIPENDSET,NMI Set-pending Bit. Write Operation:. Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears this bit to 0. This.." "0: No effect.. NMI exception not pending,1: Changes NMI exception state to pending.. NMI.."
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bitfld.long 0x0 28. "PENDSVSET,PendSV Set-pending Bit. Write Operation:. Note: Writing 1 to this bit is the only way to set the PendSV exception state to pending." "0: No effect.. PendSV exception is not pending,1: Changes PendSV exception state to pending.."
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bitfld.long 0x0 27. "PENDSVCLR,PendSV Clear-pending Bit. Write Operation:. This is a write only bit. When you want to clear PENDSV bit you must 'write 0 to PENDSVSET and write 1 to PENDSVCLR' at the same time." "0: No effect,1: Removes the pending state from the PendSV.."
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bitfld.long 0x0 26. "PENDSTSET,SysTick Exception Set-pending Bit. Write Operation:" "0: No effect.. SysTick exception is not pending,1: Changes SysTick exception state to pending.."
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bitfld.long 0x0 25. "PENDSTCLR,SysTick Exception Clear-pending Bit. Write Operation:. This is a write only bit. When you want to clear PENDST bit you must 'write 0 to PENDSTSET and write 1 to PENDSTCLR' at the same time." "0: No effect,1: Removes the pending state from the SysTick.."
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rbitfld.long 0x0 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only). If Set a Pending Exception Will Be Serviced on Exit From the Debug Halt State" "0,1"
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rbitfld.long 0x0 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending"
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hexmask.long.byte 0x0 12.--17. 1. "VECTPENDING,Number of the Highest Pended Exception"
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hexmask.long.byte 0x0 0.--5. 1. "VECTACTIVE,Number of the Current Active Exception"
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|
group.long 0xD0C++0x7
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line.long 0x0 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x0 16.--31. 1. "VECTORKEY,Register Access Key. Write Operation:. When writing to this register the VECTORKEY field need to be set to 0x05FA otherwise the write operation would be ignored. The VECTORKEY filed is used to prevent accidental write to this register from.."
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bitfld.long 0x0 2. "SYSRESETREQ,System Reset Request. Writing this bit 1 will cause a reset signal to be asserted to the chip to indicate a reset is requested.. The bit is a write only bit and self-clears as part of the reset sequence." "0,1"
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bitfld.long 0x0 1. "VECTCLRACTIVE,Exception Active Status Clear Bit. Reserved for debug use. When writing to the register user must write 0 to this bit otherwise behavior is unpredictable." "0,1"
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line.long 0x4 "SCR,System Control Register"
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bitfld.long 0x4 4. "SEVONPEND,Send Event on Pending Bit. When an event or interrupt enters pending state the event signal wakes up the processor from WFE. If the processor is not waiting for an event the event is registered and affects the next WFE.. The processor also.." "0: Only enabled interrupts or events can wake-up..,1: Enabled events and all interrupts including.."
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bitfld.long 0x4 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection. Controls whether the processor uses sleep or deep sleep as its low power mode:" "0: Sleep mode,1: Deep Sleep mode"
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bitfld.long 0x4 1. "SLEEPONEXIT,Sleep-on-exit Enable Bit. This bit indicates sleep-on-exit when returning from Handler mode to Thread mode.. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application." "0: Do not sleep when returning to Thread mode,1: Enter Sleep or Deep Sleep when returning from.."
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group.long 0xD1C++0x7
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line.long 0x0 "SHPR2,System Handler Priority Register 2"
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|
bitfld.long 0x0 30.--31. "PRI_11,Priority of System Handler 11 - SVCall. '0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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line.long 0x4 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x4 30.--31. "PRI_15,Priority of System Handler 15 - SysTick. '0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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bitfld.long 0x4 22.--23. "PRI_14,Priority of System Handler 14 - PendSV. '0' denotes the highest priority and '3' denotes the lowest priority" "0,1,2,3"
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tree.end
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tree "SPI (Serial Peripheral Interface)"
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|
base ad:0x0
|
|
tree "SPI0"
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base ad:0x40030000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control. This bit is used to select the data input/output direction in half-duplex transfer." "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit. Note: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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newline
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit. This bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. . Note: This bit is.." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit. This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width. This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval. The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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newline
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit. In Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.. Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider. The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.. . where . is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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newline
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit. Note: This bit is for Master mode only." "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity. This bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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newline
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bitfld.long 0x8 0. "SS,Slave Selection Control. If AUTOSS bit is cleared to 0 . Note: This bit is for Master mode only." "0: set the SPIx_SS line to inactive state.. Keep..,1: set the SPIx_SS line to active state.. SPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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newline
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit. Note: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--29. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x10 24.--25. "RXTH,Receive FIFO Threshold. If the valid data count of the receive FIFO buffer is greater than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear. Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear. Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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newline
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity. Note:. 1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.. 2. This bit should be set as 0 in I2S mode.. 3. When TX underflow event occurs SPIx_MISO pin state.." "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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newline
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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newline
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bitfld.long 0x10 1. "TXRST,Transmit Reset. Note: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer."
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newline
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag. When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.. Note 1: This bit will be cleared by writing 1 to it.. Note 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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newline
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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newline
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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newline
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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newline
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag. In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs"
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newline
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag. In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.. Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only). Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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newline
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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newline
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.."
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group.long 0x60++0xB
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line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit. If MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode. I2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
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newline
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: Data size is 8-bit,1: Data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit. Note:. 1. If this bit is enabled I2Sx_BCLK will start to output in Master mode.. 2. Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: I2S mode Enabled"
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line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider. The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:. . where . is the frequency of I2S peripheral clock source which is defined in.."
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hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider. If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:. where. is the frequency of I2S peripheral clock.."
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line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag. When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled"
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only). This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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tree.end
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tree "SPI1"
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base ad:0x40034000
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group.long 0x0++0x17
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line.long 0x0 "SPIx_CTL,SPI Control Register"
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bitfld.long 0x0 20. "DATDIR,Data Port Direction Control. This bit is used to select the data input/output direction in half-duplex transfer." "0: SPI data is input direction,1: SPI data is output direction"
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bitfld.long 0x0 19. "REORDER,Byte Reorder Function Enable Bit. Note: Byte Reorder function is only available if DWIDTH is defined as 16 24 and 32 bits." "0: Byte Reorder function Disabled,1: Byte Reorder function Enabled. A byte suspend.."
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bitfld.long 0x0 18. "SLAVE,Slave Mode Control" "0: Master mode,1: Slave mode"
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bitfld.long 0x0 17. "UNITIEN,Unit Transfer Interrupt Enable Bit" "0: SPI unit transfer interrupt Disabled,1: SPI unit transfer interrupt Enabled"
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bitfld.long 0x0 15. "RXONLY,Receive-only Mode Enable Bit. This bit field is only available in Master mode. In receive-only mode SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. . Note: This bit is.." "0: Receive-only mode Disabled,1: Receive-only mode Enabled"
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bitfld.long 0x0 14. "HALFDPX,SPI Half-duplex Transfer Enable Bit. This bit is used to select full-duplex or half-duplex for SPI transfer. The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer." "0: SPI operates in full-duplex transfer,1: SPI operates in half-duplex transfer"
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bitfld.long 0x0 13. "LSB,Send LSB First" "0: The MSB which bit of transmit/receive register..,1: The LSB bit 0 of the SPI TX register is sent.."
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hexmask.long.byte 0x0 8.--12. 1. "DWIDTH,Data Width. This field specifies how many bits can be transmitted / received in one transaction. The minimum bit length is 8 bits and can up to 32 bits."
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hexmask.long.byte 0x0 4.--7. 1. "SUSPITV,Suspend Interval. The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer. The definition of the suspend interval is the interval between the last clock edge of the preceding.."
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bitfld.long 0x0 3. "CLKPOL,Clock Polarity" "0: SPI bus clock is idle low,1: SPI bus clock is idle high"
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bitfld.long 0x0 2. "TXNEG,Transmit on Negative Edge" "0: Transmitted data output signal is changed on the..,1: Transmitted data output signal is changed on the.."
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bitfld.long 0x0 1. "RXNEG,Receive on Negative Edge" "0: Received data input signal is latched on the..,1: Received data input signal is latched on the.."
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bitfld.long 0x0 0. "SPIEN,SPI Transfer Control Enable Bit. In Master mode the transfer will start when there is data in the FIFO buffer after this bit is set to 1. In Slave mode this device is ready to receive data when this bit is set to 1.. Note: Before changing the.." "0: Transfer control Disabled,1: Transfer control Enabled"
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line.long 0x4 "SPIx_CLKDIV,SPI Clock Divider Register"
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hexmask.long.byte 0x4 0.--7. 1. "DIVIDER,Clock Divider. The value in this field is the frequency divider for generating the peripheral clock fspi_eclk and the SPI bus clock of SPI Master. The frequency is obtained according to the following equation.. . where . is the peripheral.."
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line.long 0x8 "SPIx_SSCTL,SPI Slave Select Control Register"
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bitfld.long 0x8 13. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit" "0: Slave select inactive interrupt Disabled,1: Slave select inactive interrupt Enabled"
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bitfld.long 0x8 12. "SSACTIEN,Slave Select Active Interrupt Enable Bit" "0: Slave select active interrupt Disabled,1: Slave select active interrupt Enabled"
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bitfld.long 0x8 9. "SLVURIEN,Slave Mode TX Under Run Interrupt Enable Bit" "0: Slave mode TX under run interrupt Disabled,1: Slave mode TX under run interrupt Enabled"
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bitfld.long 0x8 8. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit" "0: Slave mode bit count error interrupt Disabled,1: Slave mode bit count error interrupt Enabled"
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bitfld.long 0x8 3. "AUTOSS,Automatic Slave Selection Function Enable Bit. Note: This bit is for Master mode only." "0: Automatic slave selection function Disabled.,1: Automatic slave selection function Enabled"
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bitfld.long 0x8 2. "SSACTPOL,Slave Selection Active Polarity. This bit defines the active polarity of slave selection signal (SPIx_SS)." "0: The slave selection signal SPIx_SS is active low,1: The slave selection signal SPIx_SS is active high"
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bitfld.long 0x8 0. "SS,Slave Selection Control. If AUTOSS bit is cleared to 0 . Note: This bit is for Master mode only." "0: set the SPIx_SS line to inactive state.. Keep..,1: set the SPIx_SS line to active state.. SPIx_SS.."
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line.long 0xC "SPIx_PDMACTL,SPI PDMA Control Register"
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bitfld.long 0xC 2. "PDMARST,PDMA Reset" "0: No effect,1: Reset the PDMA control logic of the SPI.."
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bitfld.long 0xC 1. "RXPDMAEN,Receive PDMA Enable Bit" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled"
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bitfld.long 0xC 0. "TXPDMAEN,Transmit PDMA Enable Bit. Note: In SPI Master mode with full duplex transfer if both TX and RX PDMA functions are enabled RX PDMA function cannot be enabled prior to TX PDMA function. User can enable TX PDMA function firstly or enable both.." "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled"
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line.long 0x10 "SPIx_FIFOCTL,SPI FIFO Control Register"
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bitfld.long 0x10 28.--29. "TXTH,Transmit FIFO Threshold. If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting the TXTHIF bit will be set to 1 else the TXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x10 24.--25. "RXTH,Receive FIFO Threshold. If the valid data count of the receive FIFO buffer is greater than the RXTH setting the RXTHIF bit will be set to 1 else the RXTHIF bit will be cleared to 0." "0,1,2,3"
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bitfld.long 0x10 9. "TXFBCLR,Transmit FIFO Buffer Clear. Note: The TX shift register will not be cleared." "0: No effect,1: Clear transmit FIFO pointer. The TXFULL bit will.."
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bitfld.long 0x10 8. "RXFBCLR,Receive FIFO Buffer Clear. Note: The RX shift register will not be cleared." "0: No effect,1: Clear receive FIFO pointer. The RXFULL bit will.."
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bitfld.long 0x10 7. "TXUFIEN,TX Underflow Interrupt Enable Bit" "0: Slave TX underflow interrupt Disabled,1: Slave TX underflow interrupt Enabled"
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bitfld.long 0x10 6. "TXUFPOL,TX Underflow Data Polarity. Note:. 1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active.. 2. This bit should be set as 0 in I2S mode.. 3. When TX underflow event occurs SPIx_MISO pin state.." "0: The SPI data out is keep 0 if there is TX..,1: The SPI data out is keep 1 if there is TX.."
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bitfld.long 0x10 5. "RXOVIEN,Receive FIFO Overrun Interrupt Enable Bit" "0: Receive FIFO overrun interrupt Disabled,1: Receive FIFO overrun interrupt Enabled"
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bitfld.long 0x10 4. "RXTOIEN,Slave Receive Time-out Interrupt Enable Bit" "0: Receive time-out interrupt Disabled,1: Receive time-out interrupt Enabled"
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bitfld.long 0x10 3. "TXTHIEN,Transmit FIFO Threshold Interrupt Enable Bit" "0: TX FIFO threshold interrupt Disabled,1: TX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 2. "RXTHIEN,Receive FIFO Threshold Interrupt Enable Bit" "0: RX FIFO threshold interrupt Disabled,1: RX FIFO threshold interrupt Enabled"
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bitfld.long 0x10 1. "TXRST,Transmit Reset. Note: If TX underflow event occurs in SPI Slave mode this bit can be used to make SPI return to idle state." "0: No effect,1: Reset transmit FIFO pointer and transmit.."
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bitfld.long 0x10 0. "RXRST,Receive Reset" "0: No effect,1: Reset receive FIFO pointer and receive circuit."
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line.long 0x14 "SPIx_STATUS,SPI Status Register"
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hexmask.long.byte 0x14 28.--31. 1. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer."
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hexmask.long.byte 0x14 24.--27. 1. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer."
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rbitfld.long 0x14 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x14 19. "TXUFIF,TX Underflow Interrupt Flag. When the TX underflow event occurs this bit will be set to 1 the state of data output pin depends on the setting of TXUFPOL.. Note 1: This bit will be cleared by writing 1 to it.. Note 2: If reset slave's.." "0: No effect,1: This bit will be cleared by writing 1 to it"
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rbitfld.long 0x14 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x14 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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rbitfld.long 0x14 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x14 15. "SPIENSTS,SPI Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI control logic is disabled this bit indicates the real status of SPI controller." "0: SPI controller Disabled,1: SPI controller Enabled"
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bitfld.long 0x14 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x14 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No FIFO is overrun,1: Receive FIFO is overrun"
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rbitfld.long 0x14 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x14 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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rbitfld.long 0x14 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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bitfld.long 0x14 7. "SLVURIF,Slave Mode TX Under Run Interrupt Flag. In Slave mode if TX underflow event occurs and the slave select line goes to inactive state this interrupt flag will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0: No Slave TX under run event,1: Slave TX under run event occurs"
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bitfld.long 0x14 6. "SLVBEIF,Slave Mode Bit Count Error Interrupt Flag. In Slave mode when the slave select line goes to inactive state if bit counter is mismatch with DWIDTH this interrupt flag will be set to 1.. Note: If the slave select active but there is no any bus.." "0: No Slave mode bit count error event,1: Slave mode bit count error event occurs"
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rbitfld.long 0x14 4. "SSLINE,Slave Select Line Bus Status (Read Only). Note: This bit is only available in Slave mode. If SSACTPOL (SPIx_SSCTL[2]) is set 0 and the SSLINE is 1 the SPI slave select is in inactive status." "0: The slave select line status is 0,1: The slave select line status is 1"
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bitfld.long 0x14 3. "SSINAIF,Slave Select Inactive Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select inactive interrupt was cleared or..,1: Slave select inactive interrupt event occurred"
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bitfld.long 0x14 2. "SSACTIF,Slave Select Active Interrupt Flag. Note: Only available in Slave mode. This bit will be cleared by writing 1 to it." "0: Slave select active interrupt was cleared or not..,1: Slave select active interrupt event occurred"
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newline
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bitfld.long 0x14 1. "UNITIF,Unit Transfer Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No transaction has been finished since this bit..,1: SPI controller has finished one unit transfer"
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rbitfld.long 0x14 0. "BUSY,Busy Status (Read Only)" "0: SPI controller is in idle state,1: SPI controller is in busy state"
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wgroup.long 0x20++0x3
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line.long 0x0 "SPIx_TX,SPI Data Transmit Register"
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hexmask.long 0x0 0.--31. 1. "TX,Data Transmit Register. The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers. The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S.."
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rgroup.long 0x30++0x3
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line.long 0x0 "SPIx_RX,SPI Data Receive Register"
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hexmask.long 0x0 0.--31. 1. "RX,Data Receive Register. There are 4-level FIFO buffers in this controller. The data receive register holds the data received from SPI data input pin. If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1 the receive FIFO buffers can be.."
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group.long 0x60++0xB
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line.long 0x0 "SPIx_I2SCTL,I2S Control Register"
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bitfld.long 0x0 28.--29. "FORMAT,Data Format Selection" "0: I2S data format,1: MSB justified data format,?,?"
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bitfld.long 0x0 25. "LZCIEN,Left Channel Zero Cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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newline
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bitfld.long 0x0 24. "RZCIEN,Right Channel Zero Cross Interrupt Enable Bit. Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs." "0: Interrupt Disabled,1: Interrupt Enabled"
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bitfld.long 0x0 23. "RXLCH,Receive Left Channel Enable Bit" "0: Receive right channel data in Mono mode,1: Receive left channel data in Mono mode"
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newline
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bitfld.long 0x0 17. "LZCEN,Left Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Left channel zero cross detection Disabled,1: Left channel zero cross detection Enabled"
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bitfld.long 0x0 16. "RZCEN,Right Channel Zero Cross Detection Enable Bit. If this bit is set to 1 when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1. This function is only available in transmit.." "0: Right channel zero cross detection Disabled,1: Right channel zero cross detection Enabled"
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newline
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bitfld.long 0x0 15. "MCLKEN,Master Clock Enable Bit. If MCLKEN is set to 1 I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices." "0: Master clock Disabled,1: Master clock Enabled"
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bitfld.long 0x0 8. "SLAVE,Slave Mode. I2S can operate as master or slave. For Master mode I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from this chip to audio CODEC chip. In Slave mode I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and.." "0: Master mode,1: Slave mode"
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bitfld.long 0x0 7. "ORDER,Stereo Data Order in FIFO" "0: Left channel data at high byte,1: Left channel data at low byte"
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bitfld.long 0x0 6. "MONO,Monaural Data" "0: Data is stereo format,1: Data is monaural format"
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newline
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bitfld.long 0x0 4.--5. "WDWIDTH,Word Width" "0: Data size is 8-bit,1: Data size is 16-bit,?,?"
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bitfld.long 0x0 3. "MUTE,Transmit Mute Enable Bit" "0: Transmit data is shifted from buffer,1: Transmit channel zero"
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newline
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bitfld.long 0x0 2. "RXEN,Receive Enable Bit" "0: Data receive Disabled,1: Data receive Enabled"
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bitfld.long 0x0 1. "TXEN,Transmit Enable Bit" "0: Data transmit Disabled,1: Data transmit Enabled"
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newline
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bitfld.long 0x0 0. "I2SEN,I2S Controller Enable Bit. Note:. 1. If this bit is enabled I2Sx_BCLK will start to output in Master mode.. 2. Before changing the configurations of SPIx_I2SCTL SPIx_I2SCLK and SPIx_FIFOCTL registers user shall clear the I2SEN (SPIx_I2SCTL[0]).." "0: I2S mode Disabled,1: I2S mode Enabled"
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line.long 0x4 "SPIx_I2SCLK,I2S Clock Divider Control Register"
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hexmask.long.word 0x4 8.--16. 1. "BCLKDIV,Bit Clock Divider. The I2S controller will generate bit clock in Master mode. The clock frequency of bit clock fBCLK is determined by the following expression:. . where . is the frequency of I2S peripheral clock source which is defined in.."
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hexmask.long.byte 0x4 0.--5. 1. "MCLKDIV,Master Clock Divider. If MCLKEN is set to 1 I2S controller will generate master clock for external audio devices. The frequency of master clock fMCLK is determined by the following expressions:. where. is the frequency of I2S peripheral clock.."
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line.long 0x8 "SPIx_I2SSTS,I2S Status Register"
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rbitfld.long 0x8 28.--30. "TXCNT,Transmit FIFO Data Count (Read Only). This bit field indicates the valid data count of transmit FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 24.--26. "RXCNT,Receive FIFO Data Count (Read Only). This bit field indicates the valid data count of receive FIFO buffer." "0,1,2,3,4,5,6,7"
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rbitfld.long 0x8 23. "TXRXRST,TX or RX Reset Status (Read Only). Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles. User can check the status of this bit to monitor the reset function is doing or done." "0: The reset function of TXRST or RXRST is done,1: Doing the reset function of TXRST or RXRST"
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bitfld.long 0x8 21. "LZCIF,Left Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on left channel,1: Zero cross event occurred on left channel"
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bitfld.long 0x8 20. "RZCIF,Right Channel Zero Cross Interrupt Flag" "0: No zero cross event occurred on right channel,1: Zero cross event occurred on right channel"
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bitfld.long 0x8 19. "TXUFIF,Transmit FIFO Underflow Interrupt Flag. When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer if there is more bus clock input this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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newline
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rbitfld.long 0x8 18. "TXTHIF,Transmit FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the transmit FIFO..,1: The valid data count within the transmit FIFO.."
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rbitfld.long 0x8 17. "TXFULL,Transmit FIFO Buffer Full Indicator (Read Only)" "0: Transmit FIFO buffer is not full,1: Transmit FIFO buffer is full"
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newline
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rbitfld.long 0x8 16. "TXEMPTY,Transmit FIFO Buffer Empty Indicator (Read Only)" "0: Transmit FIFO buffer is not empty,1: Transmit FIFO buffer is empty"
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rbitfld.long 0x8 15. "I2SENSTS,I2S Enable Status (Read Only). Note: The SPI peripheral clock is asynchronous with the system clock. In order to make sure the SPI/I2S control logic is disabled this bit indicates the real status of SPI/I2S control logic for user." "0: SPI/I2S control logic Disabled,1: SPI/I2S control logic Enabled"
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|
newline
|
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bitfld.long 0x8 12. "RXTOIF,Receive Time-out Interrupt Flag. Note: This bit will be cleared by writing 1 to it." "0: No receive FIFO time-out event,1: Receive FIFO buffer is not empty and no read.."
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bitfld.long 0x8 11. "RXOVIF,Receive FIFO Overrun Interrupt Flag. When the receive FIFO buffer is full the follow-up data will be dropped and this bit will be set to 1.. Note: This bit will be cleared by writing 1 to it." "0,1"
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newline
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rbitfld.long 0x8 10. "RXTHIF,Receive FIFO Threshold Interrupt Flag (Read Only)" "0: The valid data count within the receive FIFO..,1: The valid data count within the receive FIFO.."
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rbitfld.long 0x8 9. "RXFULL,Receive FIFO Buffer Full Indicator (Read Only)" "0: Receive FIFO buffer is not full,1: Receive FIFO buffer is full"
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|
newline
|
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rbitfld.long 0x8 8. "RXEMPTY,Receive FIFO Buffer Empty Indicator (Read Only)" "0: Receive FIFO buffer is not empty,1: Receive FIFO buffer is empty"
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|
rbitfld.long 0x8 4. "RIGHT,Right Channel (Read Only). This bit indicates the current transmit data is belong to which channel." "0: Left channel,1: Right channel"
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|
tree.end
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tree.end
|
|
tree "SYS (System Control Registers)"
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|
base ad:0x50000000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "SYS_PDID,Part Device Identification Number Register"
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hexmask.long 0x0 0.--31. 1. "PDID,Part Device Identification Number (Read Only). This register reflects device part number code. Software can read this register to identify which device is used."
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group.long 0x4++0xF
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line.long 0x0 "SYS_RSTSTS,System Reset Status Register"
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bitfld.long 0x0 8. "CPULKRF,CPU Lockup Reset Flag. The CPU lockup reset flag is set by hardware If Cortex-M23 lockup happened.. Note 1: This bit can be cleared by software writing 1.. Note 2: When CPU lockup happened under ICE is connected this flag will be set to 1 but.." "0: No reset from CPU lockup happened,1: This bit can be cleared by software writing 1"
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bitfld.long 0x0 7. "CPURF,CPU Reset Flag. The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC).. Note: This bit can be cleared by software writing 1." "0: No reset from CPU,1: The Cortex-M23 Core and FMC are reset by.."
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newline
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bitfld.long 0x0 5. "MCURF,MCU Reset Flag. The MCU reset flag is set by the 'Reset Signal' from the Cortex-M23 Core to indicate the previous reset source.. Note: This bit can be cleared by software writing 1." "0: No reset from Cortex-M23,1: The Cortex-M23 had issued the reset signal to.."
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bitfld.long 0x0 4. "BODRF,BOD Reset Flag. The BOD reset flag is set by the 'Reset Signal' from the Brown-out Detector to indicate the previous reset source.. Note: This bit can be cleared by software writing 1." "0: No reset from BOD,1: The BOD had issued the reset signal to reset the.."
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newline
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bitfld.long 0x0 3. "LVRF,LVR Reset Flag. The LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.. Note: This bit can be cleared by software writing 1." "0: No reset from LVR,1: LVR controller had issued the reset signal to.."
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bitfld.long 0x0 2. "WDTRF,WDT Reset Flag. The WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.. Note 1: This bit can be cleared by software writing 1.. Note 2: Watchdog Timer register.." "0: No reset from watchdog timer or window watchdog..,1: This bit can be cleared by software writing 1"
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newline
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bitfld.long 0x0 1. "PINRF,nRESET Pin Reset Flag. The nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.. Note: This bit can be cleared by software writing 1." "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to reset.."
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bitfld.long 0x0 0. "PORF,POR Reset Flag. The POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.. Note: This bit can be cleared by software writing 1." "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued the.."
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line.long 0x4 "SYS_IPRST0,Peripheral Reset Control Register 0"
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bitfld.long 0x4 7. "CRCRST,CRC Calculation Controller Reset (Write Protect). Set this bit to 1 will generate a reset signal to the CRC calculation controller. User needs to set this bit to 0 to release from the reset state.. Note: This bit is write protected. Refer to the.." "0: CRC calculation controller normal operation,1: CRC calculation controller reset"
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bitfld.long 0x4 2. "PDMARST,PDMA Controller Reset (Write Protect). Setting this bit to 1 will generate a reset signal to the PDMA. User needs to set this bit to 0 to release from reset state.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: PDMA controller normal operation,1: PDMA controller reset"
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newline
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bitfld.long 0x4 1. "CPURST,Processor Core One-shot Reset (Write Protect). Setting this bit will only reset the processor core and Flash Memory Controller (FMC) and this bit will automatically return to 0 after the 2 clock cycles.. Note: This bit is write protected. Refer.." "0: Processor core normal operation,1: Processor core one-shot reset"
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bitfld.long 0x4 0. "CHIPRST,Chip One-shot Reset (Write Protect). Setting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.. The CHIPRST is same as the POR reset all the.." "0: Chip normal operation,1: Chip one-shot reset"
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line.long 0x8 "SYS_IPRST1,Peripheral Reset Control Register 1"
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bitfld.long 0x8 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset"
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bitfld.long 0x8 27. "USBDRST,USB Device Controller Reset" "0: USB device controller normal operation,1: USB device controller reset"
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newline
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bitfld.long 0x8 23. "BPWM3RST,BPWM3 Controller Reset" "0: BPWM3 controller normal operation,1: BPWM3 controller reset"
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bitfld.long 0x8 22. "BPWM2RST,BPWM2 Controller Reset" "0: BPWM2 controller normal operation,1: BPWM2 controller reset"
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newline
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bitfld.long 0x8 21. "BPWM1RST,BPWM1 Controller Reset" "0: BPWM1 controller normal operation,1: BPWM1 controller reset"
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bitfld.long 0x8 20. "BPWM0RST,BPWM0 Controller Reset" "0: BPWM0 controller normal operation,1: BPWM0 controller reset"
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newline
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bitfld.long 0x8 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset"
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bitfld.long 0x8 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset"
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newline
|
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bitfld.long 0x8 13. "SPI1RST,SPI1 Controller Reset" "0: SPI1 controller normal operation,1: SPI1 controller reset"
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bitfld.long 0x8 12. "SPI0RST,SPI0 Controller Reset" "0: SPI0 controller normal operation,1: SPI0 controller reset"
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newline
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bitfld.long 0x8 9. "I2C1RST,I2C1 Controller Reset" "0: I2C1 controller normal operation,1: I2C1 controller reset"
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bitfld.long 0x8 8. "I2C0RST,I2C0 Controller Reset" "0: I2C0 controller normal operation,1: I2C0 controller reset"
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newline
|
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bitfld.long 0x8 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset"
|
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bitfld.long 0x8 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset"
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newline
|
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bitfld.long 0x8 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset"
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bitfld.long 0x8 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset"
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newline
|
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bitfld.long 0x8 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset"
|
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line.long 0xC "SYS_IPRST2,Peripheral Reset Control Register 2"
|
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bitfld.long 0xC 25. "LLSI9RST,LLSI9 Controller Reset" "0: LED Lighting Strip Interface 9 controller normal..,1: LED Lighting Strip Interface 9 controller reset"
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bitfld.long 0xC 24. "LLSI8RST,LLSI8 Controller Reset" "0: LED Lighting Strip Interface 8 controller normal..,1: LED Lighting Strip Interface 8 controller reset"
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newline
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bitfld.long 0xC 23. "LLSI7RST,LLSI7 Controller Reset" "0: LED Lighting Strip Interface 7 controller normal..,1: LED Lighting Strip Interface 7 controller reset"
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bitfld.long 0xC 22. "LLSI6RST,LLSI6 Controller Reset" "0: LED Lighting Strip Interface 6 controller normal..,1: LED Lighting Strip Interface 6 controller reset"
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newline
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bitfld.long 0xC 21. "LLSI5RST,LLSI5 Controller Reset" "0: LED Lighting Strip Interface 5 controller normal..,1: LED Lighting Strip Interface 5 controller reset"
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|
bitfld.long 0xC 20. "LLSI4RST,LLSI4 Controller Reset" "0: LED Lighting Strip Interface 4 controller normal..,1: LED Lighting Strip Interface 4 controller reset"
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|
newline
|
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bitfld.long 0xC 19. "LLSI3RST,LLSI3 Controller Reset" "0: LED Lighting Strip Interface 3 controller normal..,1: LED Lighting Strip Interface 3 controller reset"
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bitfld.long 0xC 18. "LLSI2RST,LLSI2 Controller Reset" "0: LED Lighting Strip Interface 2 controller normal..,1: LED Lighting Strip Interface 2 controller reset"
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newline
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bitfld.long 0xC 17. "LLSI1RST,LLSI1 Controller Reset" "0: LED Lighting Strip Interface 1 controller normal..,1: LED Lighting Strip Interface 1 controller reset"
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bitfld.long 0xC 16. "LLSI0RST,LLSI0 Controller Reset" "0: LED Lighting Strip Interface 0 controller normal..,1: LED Lighting Strip Interface 0 controller reset"
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group.long 0x18++0x7
|
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line.long 0x0 "SYS_BODCTL,Brown-out Detector Control Register"
|
|
bitfld.long 0x0 25.--27. "VDETDGSEL,Voltage Detector Output De-glitch Time Select (Write Protect). Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: VDET output is sampled by VDET clock,1: 16 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 24. "VDETOUT,Voltage Detector Output Status. It means the detected voltage is lower than Band-gap. If the VDETEN is 0 VDET function is disabled. This bit always responds 0." "0: VDET output status is 0,1: VDET output status is 1"
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newline
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bitfld.long 0x0 19. "VDETIF,Voltage Detector Interrupt Flag. Note: This bit can be cleared by software writing 1." "0: VDET does not detect any voltage draft at..,1: When VDET detects the external pin is dropped.."
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bitfld.long 0x0 18. "VDETIEN,Voltage Detector Interrupt Enable Bit" "0: VDET interrupt Disabled,1: VDET interrupt Enabled"
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newline
|
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bitfld.long 0x0 17. "VDETPINSEL,Voltage Detector External Input Voltage Pin Selection. Note 1: If VDET_P0 is selected multi-function pin must be selected correctly in PB0MFP (SYS_GPB_MFPL[3:0]).. Note 2: If VDET_P1 is selected multi-function pin must be selected correctly.." "0: The input voltage is from VDET_P0 (PB.0),1: If VDET_P0 is selected"
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bitfld.long 0x0 16. "VDETEN,Voltage Detector Enable Bit. Note 1: This function is still active in whole chip Power-down mode.. Note 2: This function need use LIRC or LXT as VDET clock source which is selected in VDETCKSEL (CLK_BODCLK[0]).. Note2: The input pin for VDET.." "0: VDET detect external input voltage function..,1: This function is still active in whole chip.."
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newline
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bitfld.long 0x0 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect). Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Without de-glitch function,1: 4 system clock (HCLK),?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect). Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: BOD output is sampled by RC10K clock,1: 4 system clock (HCLK),?,?,?,?,?,?"
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newline
|
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bitfld.long 0x0 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect). The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. LVR function is enabled by default.. Note 1: After enabling the bit the LVR function will be active with.." "0: Low Voltage Reset function Disabled,1: After enabling the bit"
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bitfld.long 0x0 6. "BODOUT,Brown-out Detector Output Status. It means the detected voltage is lower than BODVL setting. If the BODEN is 0 BOD function is disabled. This bit always responds 0." "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1"
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newline
|
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bitfld.long 0x0 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect). Note 1: The BOD consumes about 100uA in normal mode the low power mode can reduce the current to about 1/10 but slow the BOD response.. Note 2: This bit is write protected. Refer to the.." "0: BOD operated in normal mode (default),1: The BOD consumes about 100uA in normal mode"
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bitfld.long 0x0 4. "BODIF,Brown-out Detector Interrupt Flag. Note: This bit can be cleared by software writing 1." "0: Brown-out Detector does not detect any voltage..,1: When Brown-out Detector detects the VDD is.."
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newline
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bitfld.long 0x0 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect). The default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit.. Note 1: . While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is.." "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled"
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bitfld.long 0x0 1.--2. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect). The default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]).. Note: These bits are write protected. Refer to the SYS_REGLCTL register." "0: Brown-Out Detector threshold voltage is 2.2V,1: Brown-Out Detector threshold voltage is 2.7V,?,?"
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newline
|
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bitfld.long 0x0 0. "BODEN,Brown-out Detector Enable Bit (Write Protect). The default value is set by Flash controller user configuration register CBODEN (CONFIG0 [23]).. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled"
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line.long 0x4 "SYS_IVSCTL,Internal Voltage Source Control Register"
|
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bitfld.long 0x4 1. "VBGUGEN,Band-gap VBG Unity Gain Buffer Enable Bit. This bit is used to enable/disable Band-gap VBG unity gain buffer function.. Note: After this bit is set to 1 the value of VBG unity gain buffer output voltage can be obtained from ADC conversion.." "0: VBG unity gain buffer function Disabled (default),1: VBG unity gain buffer function Enabled"
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bitfld.long 0x4 0. "VTEMPEN,Temperature Sensor Enable Bit. This bit is used to enable/disable temperature sensor function.. Note: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result. Please refer to ADC function.." "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled"
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group.long 0x24++0x3
|
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line.long 0x0 "SYS_PORCTL,Power-on Reset Controller Register"
|
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hexmask.long.word 0x0 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect). When powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again. User can disable internal POR circuit to avoid.."
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group.long 0x30++0x1F
|
|
line.long 0x0 "SYS_GPA_MFPL,GPIOA Low Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x0 28.--31. 1. "PA7MFP,PA.7 Multi-function Pin Selection"
|
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hexmask.long.byte 0x0 24.--27. 1. "PA6MFP,PA.6 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x0 20.--23. 1. "PA5MFP,PA.5 Multi-function Pin Selection"
|
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hexmask.long.byte 0x0 12.--15. 1. "PA3MFP,PA.3 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x0 8.--11. 1. "PA2MFP,PA.2 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x0 4.--7. 1. "PA1MFP,PA.1 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0x0 0.--3. 1. "PA0MFP,PA.0 Multi-function Pin Selection"
|
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line.long 0x4 "SYS_GPA_MFPH,GPIOA High Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x4 12.--15. 1. "PA11MFP,PA.11 Multi-function Pin Selection"
|
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hexmask.long.byte 0x4 8.--11. 1. "PA10MFP,PA.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x4 4.--7. 1. "PA9MFP,PA.9 Multi-function Pin Selection"
|
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hexmask.long.byte 0x4 0.--3. 1. "PA8MFP,PA.8 Multi-function Pin Selection"
|
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line.long 0x8 "SYS_GPB_MFPL,GPIOB Low Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x8 28.--31. 1. "PB7MFP,PB.7 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x8 24.--27. 1. "PB6MFP,PB.6 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x8 20.--23. 1. "PB5MFP,PB.5 Multi-function Pin Selection"
|
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hexmask.long.byte 0x8 16.--19. 1. "PB4MFP,PB.4 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x8 12.--15. 1. "PB3MFP,PB.3 Multi-function Pin Selection"
|
|
hexmask.long.byte 0x8 8.--11. 1. "PB2MFP,PB.2 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x8 4.--7. 1. "PB1MFP,PB.1 Multi-function Pin Selection"
|
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hexmask.long.byte 0x8 0.--3. 1. "PB0MFP,PB.0 Multi-function Pin Selection"
|
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line.long 0xC "SYS_GPB_MFPH,GPIOB High Byte Multiple Function Control Register"
|
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hexmask.long.byte 0xC 28.--31. 1. "PB15MFP,PB.15 Multi-function Pin Selection"
|
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hexmask.long.byte 0xC 24.--27. 1. "PB14MFP,PB.14 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0xC 20.--23. 1. "PB13MFP,PB.13 Multi-function Pin Selection"
|
|
hexmask.long.byte 0xC 16.--19. 1. "PB12MFP,PB.12 Multi-function Pin Selection"
|
|
newline
|
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hexmask.long.byte 0xC 12.--15. 1. "PB11MFP,PB.11 Multi-function Pin Selection"
|
|
hexmask.long.byte 0xC 8.--11. 1. "PB10MFP,PB.10 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0xC 4.--7. 1. "PB9MFP,PB.9 Multi-function Pin Selection"
|
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hexmask.long.byte 0xC 0.--3. 1. "PB8MFP,PB.8 Multi-function Pin Selection"
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line.long 0x10 "SYS_GPC_MFPL,GPIOC Low Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x10 28.--31. 1. "PC7MFP,PC.7 Multi-function Pin Selection"
|
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hexmask.long.byte 0x10 24.--27. 1. "PC6MFP,PC.6 Multi-function Pin Selection"
|
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newline
|
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hexmask.long.byte 0x10 20.--23. 1. "PC5MFP,PC.5 Multi-function Pin Selection"
|
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hexmask.long.byte 0x10 16.--19. 1. "PC4MFP,PC.4 Multi-function Pin Selection"
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newline
|
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hexmask.long.byte 0x10 12.--15. 1. "PC3MFP,PC.3 Multi-function Pin Selection"
|
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hexmask.long.byte 0x10 8.--11. 1. "PC2MFP,PC.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x10 4.--7. 1. "PC1MFP,PC.1 Multi-function Pin Selection"
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hexmask.long.byte 0x10 0.--3. 1. "PC0MFP,PC.0 Multi-function Pin Selection"
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line.long 0x14 "SYS_GPC_MFPH,GPIOC High Byte Multiple Function Control Register"
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hexmask.long.byte 0x14 24.--27. 1. "PC14MFP,PC14 Multi-function Pin Selection"
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line.long 0x18 "SYS_GPD_MFPL,GPIOD Low Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x18 12.--15. 1. "PD3MFP,PD.3 Multi-function Pin Selection"
|
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hexmask.long.byte 0x18 8.--11. 1. "PD2MFP,PD.2 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x18 4.--7. 1. "PD1MFP,PD.1 Multi-function Pin Selection"
|
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hexmask.long.byte 0x18 0.--3. 1. "PD0MFP,PD.0 Multi-function Pin Selection"
|
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line.long 0x1C "SYS_GPD_MFPH,GPIOD High Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x1C 28.--31. 1. "PD15MFP,PD.15 Multi-function Pin Selection"
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group.long 0x58++0x7
|
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line.long 0x0 "SYS_GPF_MFPL,GPIOF Low Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x0 24.--27. 1. "PF6MFP,PF.6 Multi-function Pin Selection"
|
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hexmask.long.byte 0x0 20.--23. 1. "PF5MFP,PF.5 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 16.--19. 1. "PF4MFP,PF.4 Multi-function Pin Selection"
|
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hexmask.long.byte 0x0 12.--15. 1. "PF3MFP,PF.3 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 8.--11. 1. "PF2MFP,PF.2 Multi-function Pin Selection"
|
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hexmask.long.byte 0x0 4.--7. 1. "PF1MFP,PF.1 Multi-function Pin Selection"
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newline
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hexmask.long.byte 0x0 0.--3. 1. "PF0MFP,PF.0 Multi-function Pin Selection"
|
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line.long 0x4 "SYS_GPF_MFPH,GPIOF High Byte Multiple Function Control Register"
|
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hexmask.long.byte 0x4 28.--31. 1. "PF15MFP,PF.15 Multi-function Pin Selection"
|
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hexmask.long.byte 0x4 24.--27. 1. "PF14MFP,PF.14 Multi-function Pin Selection"
|
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group.long 0x80++0xB
|
|
line.long 0x0 "SYS_IRCTCTL,HIRC Trim Control Register"
|
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hexmask.long.byte 0x0 16.--20. 1. "BOUNDARY,Boundary Selection. Fill the boundary range from 0x1 to 0x1F 0x0 is reserved.. Note: This field is effective only when the BOUNDEN(SYS_IRCTCTL[9]) is enabled."
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bitfld.long 0x0 10. "REFCKSEL,Reference Clock Selection" "0: HIRC trim reference clock is from LXT (32.768 kHz),1: HIRC trim reference clock is from USB.."
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newline
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bitfld.long 0x0 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled"
|
|
bitfld.long 0x0 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.."
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newline
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bitfld.long 0x0 6.--7. "RETRYCNT,Trim Value Update Limitation Count. This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.. Once the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,?,?"
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bitfld.long 0x0 4.--5. "LOOPSEL,Trim Calculation Loop Selection. This field defines that trim value calculation is based on how many clocks of reference clock (32.768 kHz LXT).. Note: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,?,?"
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newline
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bitfld.long 0x0 0.--1. "FREQSEL,Trim Frequency Selection. This field indicates the target frequency of internal high speed RC oscillator (HIRC) auto trim.. During auto trim operation if clock error detected with CESTOPEN(SYS_IRCTCTL[8]) is set to 1 or trim retry limitation.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC to..,?,?"
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line.long 0x4 "SYS_IRCTIEN,HIRC Trim Interrupt Enable Register"
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bitfld.long 0x4 2. "CLKEIEN,HIRC Clock Error Interrupt Enable Bit. This bit controls if CPU would get an interrupt while HIRC clock is inaccurate during auto trim operation.. If this bit is set to1 and CLKERRIF(SYS_IRCTSTS[2]) is set during auto trim operation an.." "0: Disable CLKERRIF(SYS_IRCTSTS[2]) status to..,1: Enable CLKERRIF(SYS_IRCTSTS[2]) status to.."
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bitfld.long 0x4 1. "TFAILIEN,HIRC Trim Failure Interrupt Enable Bit. This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_IRCTCTL[1:0]).. If this.." "0: Disable TFAILIF(SYS_IRCTSTS[1]) status to..,1: Enable TFAILIF(SYS_IRCTSTS[1]) status to trigger.."
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line.long 0x8 "SYS_IRCTISTS,HIRC Trim Interrupt Status Register"
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bitfld.long 0x8 2. "CLKERRIF,Clock Error Interrupt Status. When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and indicate that clock.." "0: Clock frequency is accurate,1: Clock frequency is inaccurate"
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bitfld.long 0x8 1. "TFAILIF,Trim Failure Interrupt Status. This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency is still not locked. Once this bit is set the auto trim operation stopped and FREQSEL(SYS_IRCTCTL[1:0]) will be.." "0: Trim value update limitation count not reached,1: Trim value update limitation count reached and.."
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newline
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bitfld.long 0x8 0. "FREQLOCK,HIRC Frequency Lock Status. This bit indicates the HIRC frequency is locked.. This is a status bit and does not trigger any interrupt." "0: The internal high-speed RC oscillator frequency..,1: The internal high-speed RC oscillator frequency.."
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group.long 0xC0++0x3
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line.long 0x0 "SYS_MODCTL,Modulation Control Register"
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bitfld.long 0x0 4.--6. "MODPWMSEL,BPWM0 Channel Select for Modulation. Select the BPWM0 channel to modulate with the UART1_TXD.. Note: These bits are valid while MODEN (SYS_MODCTL[0]) is set to 1." "0: BPWM0 channel 0 modulate with UART1_TXD,1: BPWM0 channel 1 modulate with UART1_TXD,?,?,?,?,?,?"
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bitfld.long 0x0 1. "MODH,Modulation at Data High. Select modulation pulse (BPWM) at UART1_TXD high or low." "0: Modulation pulse at UART1_TXD low,1: Modulation pulse at UART1_TXD high"
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newline
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bitfld.long 0x0 0. "MODEN,Modulation Function Enable Bit. This bit enables modulation function by modulating with BPWM channel output and UART1_TXD." "0: Modulation Function Disabled,1: Modulation Function Enabled"
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group.long 0x100++0x3
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line.long 0x0 "SYS_REGLCTL,Register Lock Control Register"
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hexmask.long.byte 0x0 1.--7. 1. "REGLCTL,Register Lock Control Code. Some registers have write-protection function. Writing these registers have to disable the protected function by writing the sequence value '59h' '16h' '88h' to this field. After this sequence is completed the.."
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bitfld.long 0x0 0. "REGLCTL0,Register Lock Control Disable Index. The Protected registers are:. SYS_IPRST0: address 0x5000_0008. SYS_BODCTL: address 0x5000_0018. SYS_PORCTL: address 0x5000_0024. SYS_SRAM_BISTCTL: address 0x5000_00D0. CLK_PWRCTL: address 0x5000_0200." "0: address 0x4014_4000,1: address 0x5000_0214"
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rgroup.long 0x114++0x3
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line.long 0x0 "SYS_TSOFFSET,Temperature Sensor Offset Register"
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hexmask.long.word 0x0 0.--11. 1. "VTEMP,Temperature Sensor Offset Value (Read Only). This field reflects temperature sensor output voltage offset at 25oC from Flash."
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tree.end
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tree "TIMER (Timer Controller)"
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base ad:0x0
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tree "TMR01"
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base ad:0x40010000
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group.long 0x0++0xB
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line.long 0x0 "TIMER0_CTL,Timer0 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit. Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.. Note: This bit will be auto cleared." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status.. Note: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled. . Note 2: When Timer/Timer INTRGEN is set to 1 this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1 this bit is.." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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newline
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGADC,Trigger ADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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newline
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bitfld.long 0x0 19. "TRGBPWM01,Trigger BPWM01 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM01." "0: Timer interrupt trigger BPWM01 Disabled,1: Timer interrupt trigger BPWM01 Enabled"
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger BPWM.."
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newline
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bitfld.long 0x0 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from LIRC"
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bitfld.long 0x0 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit. Setting this bit will enable the inter-timer trigger capture function.. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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newline
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bitfld.long 0x0 9. "TRGBPWM23,Trigger BPWM23 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM23." "0: Timer interrupt trigger BPWM23 Disabled,1: Timer interrupt trigger BPWM23 Enabled"
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bitfld.long 0x0 8. "TRGPDMA,Trigger PDMA Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter. Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER0_CMP,Timer0 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.. Note 1: Never write 0x0 or 0x1 in CMPDAT.."
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line.long 0x8 "TIMER0_INTSTS,Timer0 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer did not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matched the CMPDAT value"
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rgroup.long 0xC++0x7
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line.long 0x0 "TIMER0_CNT,Timer0 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. Read this register to get CNT value. For example:. If EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.. If EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value for getting.."
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line.long 0x4 "TIMER0_CAP,Timer0 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
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group.long 0x14++0x7
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line.long 0x0 "TIMER0_EXTCTL,Timer0 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce de-bounce Enabled"
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newline
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: Capture Mode Enabled,1: Capture and Reset Mode Enabled"
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newline
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit. This bit enables the capture input function.. Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~3) pin or LIRC..,1: A Rising edge on TMx_EXT (x= 0~3) pin or LIRC..,?,?"
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newline
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag. This bit indicates the timer capture interrupt flag status.. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will keep register.." "0: TMx_EXT (x= 0~3) pin or LIRC capture interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC capture interrupt.."
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group.long 0x20++0xB
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line.long 0x0 "TIMER1_CTL,Timer1 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit. Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.. Note: This bit will be auto cleared." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status.. Note: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled. . Note 2: When Timer/Timer INTRGEN is set to 1 this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1 this bit is.." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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newline
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGADC,Trigger ADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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newline
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bitfld.long 0x0 19. "TRGBPWM01,Trigger BPWM01 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM01." "0: Timer interrupt trigger BPWM01 Disabled,1: Timer interrupt trigger BPWM01 Enabled"
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger BPWM.."
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newline
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bitfld.long 0x0 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from LIRC"
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bitfld.long 0x0 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit. Setting this bit will enable the inter-timer trigger capture function.. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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newline
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bitfld.long 0x0 9. "TRGBPWM23,Trigger BPWM23 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM23." "0: Timer interrupt trigger BPWM23 Disabled,1: Timer interrupt trigger BPWM23 Enabled"
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bitfld.long 0x0 8. "TRGPDMA,Trigger PDMA Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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newline
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter. Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER1_CMP,Timer1 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.. Note 1: Never write 0x0 or 0x1 in CMPDAT.."
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line.long 0x8 "TIMER1_INTSTS,Timer1 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer did not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matched the CMPDAT value"
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rgroup.long 0x2C++0x7
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line.long 0x0 "TIMER1_CNT,Timer1 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. Read this register to get CNT value. For example:. If EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.. If EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value for getting.."
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line.long 0x4 "TIMER1_CAP,Timer1 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
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group.long 0x34++0x7
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line.long 0x0 "TIMER1_EXTCTL,Timer1 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce de-bounce Enabled"
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newline
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: Capture Mode Enabled,1: Capture and Reset Mode Enabled"
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newline
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit. This bit enables the capture input function.. Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~3) pin or LIRC..,1: A Rising edge on TMx_EXT (x= 0~3) pin or LIRC..,?,?"
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newline
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag. This bit indicates the timer capture interrupt flag status.. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will keep register.." "0: TMx_EXT (x= 0~3) pin or LIRC capture interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC capture interrupt.."
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tree.end
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tree "TMR23"
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base ad:0x40110000
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group.long 0x0++0xB
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line.long 0x0 "TIMER2_CTL,Timer2 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit. Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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newline
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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newline
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.. Note: This bit will be auto cleared." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status.. Note: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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newline
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled. . Note 2: When Timer/Timer INTRGEN is set to 1 this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1 this bit is.." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGADC,Trigger ADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x0 19. "TRGBPWM01,Trigger BPWM01 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM01." "0: Timer interrupt trigger BPWM01 Disabled,1: Timer interrupt trigger BPWM01 Enabled"
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger BPWM.."
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bitfld.long 0x0 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from LIRC"
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bitfld.long 0x0 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit. Setting this bit will enable the inter-timer trigger capture function.. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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bitfld.long 0x0 9. "TRGBPWM23,Trigger BPWM23 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM23." "0: Timer interrupt trigger BPWM23 Disabled,1: Timer interrupt trigger BPWM23 Enabled"
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bitfld.long 0x0 8. "TRGPDMA,Trigger PDMA Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter. Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER2_CMP,Timer2 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.. Note 1: Never write 0x0 or 0x1 in CMPDAT.."
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line.long 0x8 "TIMER2_INTSTS,Timer2 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer did not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matched the CMPDAT value"
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rgroup.long 0xC++0x7
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line.long 0x0 "TIMER2_CNT,Timer2 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. Read this register to get CNT value. For example:. If EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.. If EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value for getting.."
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line.long 0x4 "TIMER2_CAP,Timer2 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
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group.long 0x14++0x7
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line.long 0x0 "TIMER2_EXTCTL,Timer2 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce de-bounce Enabled"
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: Capture Mode Enabled,1: Capture and Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit. This bit enables the capture input function.. Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~3) pin or LIRC..,1: A Rising edge on TMx_EXT (x= 0~3) pin or LIRC..,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag. This bit indicates the timer capture interrupt flag status.. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will keep register.." "0: TMx_EXT (x= 0~3) pin or LIRC capture interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC capture interrupt.."
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group.long 0x20++0xB
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line.long 0x0 "TIMER3_CTL,Timer3 Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect). TIMER counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled"
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bitfld.long 0x0 30. "CNTEN,Timer Counting Enable Bit. Note 3: Setting this bit enable/disable needs 2 * TMR_CLK period to become active. User can read ACTSTS (TIMERx_CTL[25]) to check enable/disable command is completed or not." "0: Stops/Suspends counting,1: Starts counting"
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bitfld.long 0x0 29. "INTEN,Timer Interrupt Enable Bit. Note: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU." "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled"
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bitfld.long 0x0 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot mode,1: The timer controller is operated in Periodic mode,?,?"
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bitfld.long 0x0 26. "RSTCNT,Timer Counter Reset Bit. Setting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.. Note: This bit will be auto cleared." "0: No effect,1: Reset internal 8-bit prescale counter 24-bit up.."
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rbitfld.long 0x0 25. "ACTSTS,Timer Active Status Bit (Read Only). This bit indicates the 24-bit up counter status.. Note: This bit may active when CNT 0 transition to CNT 1." "0: 24-bit up counter is not active,1: 24-bit up counter is active"
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bitfld.long 0x0 24. "EXTCNTEN,Event Counter Mode Enable Bit . This bit is for external counting pin function enabled. . Note 2: When Timer/Timer INTRGEN is set to 1 this bit is forced to 1. When INTRGEN is 1 and Timer1/Timer3 CAPIF (TIMERx_EINTSTS[0]) is 1 this bit is.." "0: Event counter mode Disabled,1: Event counter mode Enabled"
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bitfld.long 0x0 23. "WKEN,Wake-up Function Enable Bit. If this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU." "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.."
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bitfld.long 0x0 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to TMx (Timer Event Counter..,1: Toggle mode output to TMx_EXT (Timer External.."
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bitfld.long 0x0 21. "TRGADC,Trigger ADC Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC." "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled"
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bitfld.long 0x0 19. "TRGBPWM01,Trigger BPWM01 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM01." "0: Timer interrupt trigger BPWM01 Disabled,1: Timer interrupt trigger BPWM01 Enabled"
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bitfld.long 0x0 18. "TRGSSEL,Trigger Source Select Bit. This bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal." "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger BPWM.."
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bitfld.long 0x0 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x= 0~3)..,1: Capture Function source is from LIRC"
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bitfld.long 0x0 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit. Setting this bit will enable the inter-timer trigger capture function.. The Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled"
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bitfld.long 0x0 9. "TRGBPWM23,Trigger BPWM23 Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger BPWM23." "0: Timer interrupt trigger BPWM23 Disabled,1: Timer interrupt trigger BPWM23 Enabled"
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bitfld.long 0x0 8. "TRGPDMA,Trigger PDMA Enable Bit. If this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA." "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled"
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hexmask.long.byte 0x0 0.--7. 1. "PSC,Prescale Counter. Note: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value."
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line.long 0x4 "TIMER3_CMP,Timer3 Comparator Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CMPDAT,Timer Comparator Value. CMPDAT is a 24-bit compared value register. When the internal 24-bit up counter value is equal to CMPDAT value the TIF (TIMERx_INTSTS[0] Timer Interrupt Flag) will be set to 1.. Note 1: Never write 0x0 or 0x1 in CMPDAT.."
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line.long 0x8 "TIMER3_INTSTS,Timer3 Interrupt Status Register"
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bitfld.long 0x8 1. "TWKF,Timer Wake-up Flag. This bit indicates the interrupt wake-up flag status of timer.. Note: This bit is cleared by writing 1 to it." "0: Timer did not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.."
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bitfld.long 0x8 0. "TIF,Timer Interrupt Flag. This bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.. Note: This bit is cleared by writing 1 to it." "0: No effect,1: CNT value matched the CMPDAT value"
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rgroup.long 0x2C++0x7
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line.long 0x0 "TIMER3_CNT,Timer3 Data Register"
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hexmask.long.tbyte 0x0 0.--23. 1. "CNT,Timer Data Register. Read this register to get CNT value. For example:. If EXTCNTEN (TIMERx_CTL[24]) is 0 user can read CNT value for getting current 24-bit counter value.. If EXTCNTEN (TIMERx_CTL[24]) is 1 user can read CNT value for getting.."
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line.long 0x4 "TIMER3_CAP,Timer3 Capture Data Register"
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hexmask.long.tbyte 0x4 0.--23. 1. "CAPDAT,Timer Capture Data Register. When CAPEN (TIMERx_EXTCTL[3]) bit is set CAPFUNCS (TIMERx_EXTCTL[4]) bit is 0 and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[2:1]) setting CAPIF (TIMERx_EINTSTS[0]) will be set to 1 and the.."
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group.long 0x34++0x7
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line.long 0x0 "TIMER3_EXTCTL,Timer3 External Control Register"
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bitfld.long 0x0 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit." "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled"
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bitfld.long 0x0 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit. Note: If this bit is enabled the edge detection of TMx_EXT pin output is detected with de-bounce circuit." "0: TMx_EXT (x= 0~3) pin de-bounce de-bounce Disabled,1: TMx_EXT (x= 0~3) pin de-bounce de-bounce Enabled"
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bitfld.long 0x0 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC detection Interrupt.."
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bitfld.long 0x0 4. "CAPFUNCS,Capture Function Selection" "0: Capture Mode Enabled,1: Capture and Reset Mode Enabled"
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bitfld.long 0x0 3. "CAPEN,Timer Capture Enable Bit. This bit enables the capture input function.. Note: Timer1/3 CAPEN will be forced to 1 when Timer0/2 INTRGEN is enabled." "0: Capture source Disabled,1: Capture source Enabled"
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bitfld.long 0x0 1.--2. "CAPEDGE,Timer External Capture Pin Edge Detect" "0: A Falling edge on TMx_EXT (x= 0~3) pin or LIRC..,1: A Rising edge on TMx_EXT (x= 0~3) pin or LIRC..,?,?"
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bitfld.long 0x0 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will be..,1: A rising edge of external counting pin will be.."
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line.long 0x4 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register"
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bitfld.long 0x4 0. "CAPIF,Timer Capture Interrupt Flag. This bit indicates the timer capture interrupt flag status.. Note 3: There is a new incoming capture event detected before CPU clearing the CAPIF status. If the above condition occurred the Timer will keep register.." "0: TMx_EXT (x= 0~3) pin or LIRC capture interrupt..,1: TMx_EXT (x= 0~3) pin or LIRC capture interrupt.."
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tree.end
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tree.end
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tree "UART (Universal Asynchronous Receiver/Transmitter)"
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base ad:0x0
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tree "UART0"
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base ad:0x40050000
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group.long 0x0++0x1B
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer. Write Operation:. By writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer. Write Operation:. By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.. Read.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit. If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit. This bit can enable or disable RX PDMA service.. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit. This bit can enable or disable TX PDMA service." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit. Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit. Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use. Note: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit. The receiver is disabled or not (set 1 to disable receiver).. Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level. When the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset. When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.. Note 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset. When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.. Note 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted. Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.. Note.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted. Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.. Note.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,Parity Bit Source Selection. The parity bit can be selected to be generated and checked automatically or by software.. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.. Note 2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit. Note: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit. Note: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit. Note: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection. This field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only). This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level. This bit defines the active level state of nRTS pin output.. Note 1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode.. Note 2: Refer to Figure 6.1117 and Figure 6.1118 for RS-485 function mode.. Note 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control. This bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.. Note 1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: This nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level. This bit defines the active level state of nCTS pin input.. Note: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only). This bit mirror from nCTS pin input of voltage logic status.. Note: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag. This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.. Note: This bit can be cleared by writing 1 to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only). This bit indicates TX and RX are active or inactive.. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only). This bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only). This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag. If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.. Note: This bit can be cleared by writing 1 to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only). This bit indicates TX FIFO full or not.. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only). This bit indicates TX FIFO empty or not.. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only). This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.. The Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only). This bit initiates RX FIFO full or not.. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only). This bit initiate RX FIFO empty or not.. Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only). This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.. The Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag. This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).. Note: This bit can be cleared by writing 1 to it." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note: This bit can be cleared by writing 1 to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag. Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.. Note 2: This bit can be cleared by writing 1 to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag. This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.. Note: This bit can be cleared by writing 1 to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag. This bit is set to logic '1' when auto-baud rate detect function is finished.. Note: This bit can be cleared by writing 1 to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag. This bit is set when RX FIFO overflow.. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.. Note: This bit can be cleared by writing 1 to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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rgroup.long 0x1C++0x3
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line.long 0x0 "UART_INTSTS,UART Interrupt Status Register"
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bitfld.long 0x0 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only). This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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bitfld.long 0x0 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) . This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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bitfld.long 0x0 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only). This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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bitfld.long 0x0 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only). This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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bitfld.long 0x0 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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bitfld.long 0x0 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only). This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x0 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only). This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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bitfld.long 0x0 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only). This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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bitfld.long 0x0 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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bitfld.long 0x0 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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bitfld.long 0x0 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only). This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x0 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only). This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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bitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only). This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x0 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only). This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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bitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated."
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bitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) . This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only). This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only). This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x0 6. "WKIF,UART Wake-up Interrupt Flag (Read Only). This bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.. Note: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x0 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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bitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only) . This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.. Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.. Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x13
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line.long 0x0 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value . This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x4 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1. This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0. This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1. This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.113."
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider. The field indicates the baud rate divider. This filed is used in baud rate calculation. . Note: The detailed description is shown in Table 6.113."
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line.long 0x8 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal . Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal . Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit. Note: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))." "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value . This field contains the RS-485 address match values.. Note: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length . Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
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bitfld.long 0xC 18. "ABRDEN,Auto-baud Rate Detect Enable Bit. Note: This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0xC 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) . This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. ." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit. This bit is used to enable RS-485 Address Detection mode. . Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Function. Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode. Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode . Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x10 6. "DGE,Deglitch Enable Bit. Note 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x10 3. "TXRXDIS,TX and RX Disable Bit. Setting this bit can disable TX and RX.. Note: The TX and RX will not disable immediately when this bit is set. The TX and RX complete current task before disable TX and RX. When TX and RX disable the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function,1: Reserved.,?,?"
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group.long 0x3C++0xF
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten. These 9-bits are used to define the relative bit is compensated or not. . BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit. Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit. Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1." "0: RS-485 Address Match (AAD mode) wake-up system..,1: RS-485 Address Match (AAD mode) wake-up system.."
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled. When the.."
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag. This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag. This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).. Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag. This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag. This bit is set if chip wake-up from power-down state by data wake-up.. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.. Note 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag. This bit is set if chip wake-up from power-down state by nCTS wake-up.. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.. Note 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,Start Bit Compensation Value. These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.. Note: It is valid only when WKDATEN.."
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tree.end
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tree "UART1"
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base ad:0x40150000
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group.long 0x0++0x1B
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line.long 0x0 "UART_DAT,UART Receive/Transmit Buffer Register"
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bitfld.long 0x0 8. "PARITY,Parity Bit Receive/Transmit Buffer. Write Operation:. By writing to this bit the parity bit will be stored in transmitter FIFO. If PBE (UART_LINE[3]) and PSS (UART_LINE[7]) are set the UART controller will send out this bit follow the DAT.." "0,1"
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hexmask.long.byte 0x0 0.--7. 1. "DAT,Data Receive/Transmit Buffer. Write Operation:. By writing one byte to this register the data byte will be stored in transmitter FIFO. The UART controller will send out the data stored in transmitter FIFO top location through the UART_TXD.. Read.."
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line.long 0x4 "UART_INTEN,UART Interrupt Enable Register"
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bitfld.long 0x4 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit. If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled"
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bitfld.long 0x4 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled"
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bitfld.long 0x4 15. "RXPDMAEN,RX PDMA Enable Bit. This bit can enable or disable RX PDMA service.. Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused. If RLS interrupt is caused by Break.." "0: RX PDMA Disabled,1: RX PDMA Enabled"
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bitfld.long 0x4 14. "TXPDMAEN,TX PDMA Enable Bit. This bit can enable or disable TX PDMA service." "0: TX PDMA Disabled,1: TX PDMA Enabled"
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bitfld.long 0x4 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit. Note: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)." "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled"
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bitfld.long 0x4 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit. Note: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal." "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled"
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bitfld.long 0x4 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled"
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bitfld.long 0x4 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled"
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bitfld.long 0x4 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled"
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bitfld.long 0x4 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled"
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bitfld.long 0x4 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled"
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bitfld.long 0x4 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled"
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bitfld.long 0x4 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt Disabled,1: Transmit holding register empty interrupt Enabled"
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bitfld.long 0x4 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled"
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line.long 0x8 "UART_FIFO,UART FIFO Control Register"
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hexmask.long.byte 0x8 16.--19. 1. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control Use. Note: This field is used for auto nRTS flow control."
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bitfld.long 0x8 8. "RXOFF,Receiver Disable Bit. The receiver is disabled or not (set 1 to disable receiver).. Note: This bit is used for RS-485 Normal Multi-drop mode. It should be programmed before RS485NMM (UART_ALTCTL [8]) is programmed." "0: Receiver Enabled,1: Receiver Disabled"
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hexmask.long.byte 0x8 4.--7. 1. "RFITL,RX FIFO Interrupt Trigger Level. When the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN [0]) enabled and an interrupt will be generated)."
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bitfld.long 0x8 2. "TXRST,TX Field Software Reset. When TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.. Note 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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bitfld.long 0x8 1. "RXRST,RX Field Software Reset. When RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.. Note 1: This bit will automatically clear at least 3 UART peripheral clock cycles.. Note 2: Before setting this.." "0: No effect,1: This bit will automatically clear at least 3.."
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line.long 0xC "UART_LINE,UART Line Control Register"
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bitfld.long 0xC 9. "RXDINV,RX Data Inverted. Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.. Note.." "0: Received data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 8. "TXDINV,TX Data Inverted. Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.. Note.." "0: Transmitted data signal inverted Disabled,1: Before setting this bit"
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bitfld.long 0xC 7. "PSS,Parity Bit Source Selection. The parity bit can be selected to be generated and checked automatically or by software.. Note 1: This bit has effect only when PBE (UART_LINE[3]) is set.. Note 2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: This bit has effect only when PBE"
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bitfld.long 0xC 6. "BCB,Break Control Bit. Note: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0). This bit acts only on TX line and has no effect on the transmitter logic." "0: Break Control Disabled,1: Break Control Enabled"
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bitfld.long 0xC 5. "SPE,Stick Parity Enable Bit. Note: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0. If PBE (UART_LINE[3]) is 1 and EPE (UART_LINE[4]) is 0 then the parity bit is transmitted and checked as 1." "0: Stick parity Disabled,1: Stick parity Enabled"
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bitfld.long 0xC 4. "EPE,Even Parity Enable Bit. Note: This bit has effect only when PBE (UART_LINE[3]) is set." "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.."
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bitfld.long 0xC 3. "PBE,Parity Bit Enable Bit. Note: Parity bit is generated on each outgoing character and is checked on each incoming data." "0: Parity bit generated Disabled,1: Parity bit generated Enabled"
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bitfld.long 0xC 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the transmitted..,1: When select 5-bit word length 1.5 'STOP bit' is.."
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bitfld.long 0xC 0.--1. "WLS,Word Length Selection. This field sets UART word length." "0: 5 bits,1: 6 bits,?,?"
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line.long 0x10 "UART_MODEM,UART Modem Control Register"
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rbitfld.long 0x10 13. "RTSSTS,nRTS Pin Status (Read Only). This bit mirror from nRTS pin output of voltage logic status." "0: nRTS pin output is low level voltage logic state,1: nRTS pin output is high level voltage logic state"
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bitfld.long 0x10 9. "RTSACTLV,nRTS Pin Active Level. This bit defines the active level state of nRTS pin output.. Note 1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode.. Note 2: Refer to Figure 6.1117 and Figure 6.1118 for RS-485 function mode.. Note 3:.." "0: nRTS pin output is high level active,1: Refer to Figure 6"
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bitfld.long 0x10 1. "RTS,nRTS Signal Control. This bit is direct control internal nRTS (Request-to-send) signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.. Note 1: This nRTS signal control bit is not effective when nRTS auto-flow.." "0: nRTS signal is active,1: This nRTS signal control bit is not effective.."
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line.long 0x14 "UART_MODEMSTS,UART Modem Status Register"
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bitfld.long 0x14 8. "CTSACTLV,nCTS Pin Active Level. This bit defines the active level state of nCTS pin input.. Note: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done .." "0: nCTS pin input is high level active,1: nCTS pin input is low level active. (Default)"
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rbitfld.long 0x14 4. "CTSSTS,nCTS Pin Status (Read Only). This bit mirror from nCTS pin input of voltage logic status.. Note: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected." "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic state"
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bitfld.long 0x14 0. "CTSDETF,Detect nCTS State Change Flag. This bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN [3]) is set to 1.. Note: This bit can be cleared by writing 1 to it." "0: nCTS input has not change state,1: nCTS input has change state"
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line.long 0x18 "UART_FIFOSTS,UART FIFO Status Register"
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rbitfld.long 0x18 31. "TXRXACT,TX and RX Active Status (Read Only). This bit indicates TX and RX are active or inactive.. Note: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared. The UART controller cannot transmit or receive data.." "0: TX and RX are inactive,1: TX and RX are active. (Default)"
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rbitfld.long 0x18 29. "RXIDLE,RX Idle Status (Read Only). This bit is set by hardware when RX is idle." "0: RX is busy,1: RX is idle. (Default)"
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rbitfld.long 0x18 28. "TXEMPTYF,Transmitter Empty Flag (Read Only). This bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.. Note: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the last..,1: TX FIFO is empty and the STOP bit of the last.."
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bitfld.long 0x18 24. "TXOVIF,TX Overflow Error Interrupt Flag. If TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.. Note: This bit can be cleared by writing 1 to it." "0: TX FIFO is not overflow,1: TX FIFO is overflow"
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rbitfld.long 0x18 23. "TXFULL,Transmitter FIFO Full (Read Only). This bit indicates TX FIFO full or not.. Note: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: TX FIFO is not full,1: TX FIFO is full"
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rbitfld.long 0x18 22. "TXEMPTY,Transmitter FIFO Empty (Read Only). This bit indicates TX FIFO empty or not.. Note: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high. It will be cleared when writing data into UART_DAT.." "0: TX FIFO is not empty,1: TX FIFO is empty"
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hexmask.long.byte 0x18 16.--21. 1. "TXPTR,TX FIFO Pointer (Read Only). This field indicates the TX FIFO Buffer Pointer. When CPU writes one byte into UART_DAT TXPTR increases one. When one byte of TX FIFO is transferred to Transmitter Shift Register TXPTR decreases one.. The Maximum.."
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rbitfld.long 0x18 15. "RXFULL,Receiver FIFO Full (Read Only). This bit initiates RX FIFO full or not.. Note: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware." "0: RX FIFO is not full,1: RX FIFO is full"
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rbitfld.long 0x18 14. "RXEMPTY,Receiver FIFO Empty (Read Only). This bit initiate RX FIFO empty or not.. Note: When the last byte of RX FIFO has been read by CPU hardware sets this bit high. It will be cleared when UART receives any new data." "0: RX FIFO is not empty,1: RX FIFO is empty"
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hexmask.long.byte 0x18 8.--13. 1. "RXPTR,RX FIFO Pointer (Read Only). This field indicates the RX FIFO Buffer Pointer. When UART receives one byte from external device RXPTR increases one. When one byte of RX FIFO is read by CPU RXPTR decreases one.. The Maximum value shown in RXPTR is.."
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bitfld.long 0x18 6. "BIF,Break Interrupt Flag. This bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).." "0: No Break interrupt is generated,1: Break interrupt is generated"
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bitfld.long 0x18 5. "FEF,Framing Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).. Note: This bit can be cleared by writing 1 to it." "0: No framing error is generated,1: Framing error is generated"
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bitfld.long 0x18 4. "PEF,Parity Error Flag. This bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.. Note: This bit can be cleared by writing 1 to it." "0: No parity error is generated,1: Parity error is generated"
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bitfld.long 0x18 3. "ADDRDETF,RS-485 Address Byte Detect Flag. Note 1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.. Note 2: This bit can be cleared by writing 1 to it." "0: Receiver detects a data that is not an address..,1: This field is used for RS-485 function mode and.."
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bitfld.long 0x18 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag. This bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.. Note: This bit can be cleared by writing 1 to it." "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow"
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bitfld.long 0x18 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag. This bit is set to logic '1' when auto-baud rate detect function is finished.. Note: This bit can be cleared by writing 1 to it." "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished"
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bitfld.long 0x18 0. "RXOVIF,RX Overflow Error Interrupt Flag. This bit is set when RX FIFO overflow.. If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.. Note: This bit can be cleared by writing 1 to it." "0: RX FIFO is not overflow,1: RX FIFO is overflow"
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rgroup.long 0x1C++0x3
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line.long 0x0 "UART_INTSTS,UART Interrupt Status Register"
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bitfld.long 0x0 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only). This bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1." "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated"
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bitfld.long 0x0 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) . This bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF(UART_INTSTS[22]) are both set to 1." "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated"
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bitfld.long 0x0 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only). This bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1." "0: No buffer error interrupt is generated in PDMA..,1: Buffer error interrupt is generated in PDMA mode"
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bitfld.long 0x0 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only). This bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF(UART_INTSTS[20]) are both set to 1." "0: No RX time-out interrupt is generated in PDMA mode,1: RX time-out interrupt is generated in PDMA mode"
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bitfld.long 0x0 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF(UART_INTSTS[19]) are both set to 1." "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode"
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bitfld.long 0x0 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only). This bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF(UART_INTSTS[18]) are both set to 1." "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode"
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bitfld.long 0x0 22. "TXENDIF,Transmitter Empty Interrupt Flag (Read Only). This bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set). If TXENDIEN (UART_INTEN[22]) is enabled the Transmitter.." "0: No transmitter empty interrupt flag is generated,1: Transmitter empty interrupt flag is generated"
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bitfld.long 0x0 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only). This bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS [24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer maybe is not correct. If.." "0: No buffer error interrupt flag is generated in..,1: Buffer error interrupt flag is generated in PDMA.."
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bitfld.long 0x0 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX.." "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in PDMA.."
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bitfld.long 0x0 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS [0])." "0: No Modem interrupt flag is generated in PDMA mode,1: Modem interrupt flag is generated in PDMA mode"
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bitfld.long 0x0 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only). This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set). If.." "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode"
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bitfld.long 0x0 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only). This bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1." "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated"
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bitfld.long 0x0 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only). This bit is set if BUFERRIEN(UART_INTEN[5]) and BUFERRIF(UART_ INTSTS[5]) are both set to 1." "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated"
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bitfld.long 0x0 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only). This bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF(UART_INTSTS[4]) are both set to 1." "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated"
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bitfld.long 0x0 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only). This bit is set if MODEMIEN(UART_INTEN[3]) and MODEMIF(UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated"
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bitfld.long 0x0 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) . This bit is set if RLSIEN (UART_INTEN[2]) and RLSIF(UART_INTSTS[2]) are both set to 1." "0: No RLS interrupt is generated,1: RLS interrupt is generated"
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bitfld.long 0x0 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only). This bit is set if THREIEN (UART_INTEN[1]) and THREIF(UART_INTSTS[1]) are both set to 1." "0: No THRE interrupt is generated,1: THRE interrupt is generated"
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bitfld.long 0x0 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only). This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1." "0: No RDA interrupt is generated,1: RDA interrupt is generated"
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bitfld.long 0x0 6. "WKIF,UART Wake-up Interrupt Flag (Read Only). This bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF(UART_WKSTS[0]) is set to 1.. Note: This bit is cleared if all of TOUTWKF .." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated"
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bitfld.long 0x0 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only). This bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set). When BUFERRIF (UART_INTSTS[5]) is set the transfer is not correct. If BUFERRIEN.." "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated"
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bitfld.long 0x0 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only). This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equals TOIC (UART_TOUT[7:0]). If RXTOIEN (UART_INTEN [4]) is enabled the RX time-out.." "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated"
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bitfld.long 0x0 3. "MODEMIF,MODEM Interrupt Flag (Read Only). Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF(UART_MODEMSTS[0])." "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated"
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bitfld.long 0x0 2. "RLSIF,Receive Line Interrupt Flag (Read Only) . This bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF(UART_FIFOSTS[6]) FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) is set). If RLSIEN.." "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated"
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bitfld.long 0x0 1. "THREIF,Transmit Holding Register Empty Interrupt Flag (Read Only). This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register. If THREIEN (UART_INTEN[1]) is enabled the THRE interrupt will be generated.. Note: This bit is.." "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated"
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bitfld.long 0x0 0. "RDAIF,Receive Data Available Interrupt Flag (Read Only). When the number of bytes in the RX FIFO equals the RFITL then the RDAIF(UART_INTSTS[0]) will be set. If RDAIEN (UART_INTEN [0]) is enabled the RDA interrupt will be generated.. Note: This bit is.." "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated"
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group.long 0x20++0x13
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line.long 0x0 "UART_TOUT,UART Time-out Register"
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hexmask.long.byte 0x0 8.--15. 1. "DLY,TX Delay Time Value . This field is used to programming the transfer delay time between the last stop bit and next start bit. The unit is bit time."
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hexmask.long.byte 0x0 0.--7. 1. "TOIC,Time-out Interrupt Comparator"
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line.long 0x4 "UART_BAUD,UART Baud Rate Divider Register"
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bitfld.long 0x4 29. "BAUDM1,BAUD Rate Mode Selection Bit 1. This bit is baud rate mode selection bit 1. UART provides three baud rate calculation modes. This bit combines with BAUDM0 (UART_BAUD[28]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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bitfld.long 0x4 28. "BAUDM0,BAUD Rate Mode Selection Bit 0. This bit is baud rate mode selection bit 0. UART provides three baud rate calculation modes. This bit combines with BAUDM1 (UART_BAUD[29]) to select baud rate calculation mode. The detailed description is shown in.." "0,1"
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hexmask.long.byte 0x4 24.--27. 1. "EDIVM1,Extra Divider for BAUD Rate Mode 1. This field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2. The detailed description is shown in Table 6.113."
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hexmask.long.word 0x4 0.--15. 1. "BRD,Baud Rate Divider. The field indicates the baud rate divider. This filed is used in baud rate calculation. . Note: The detailed description is shown in Table 6.113."
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line.long 0x8 "UART_IRDA,UART IrDA Control Register"
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bitfld.long 0x8 6. "RXINV,IrDA Inverse Receive Input Signal . Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART.." "0: None inverse receiving input signal,1: Before setting this bit"
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bitfld.long 0x8 5. "TXINV,IrDA Inverse Transmitting Output Signal . Note 1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared. When the configuration is done cleared TXRXDIS (UART_FUNCSEL[3]) to activate.." "0: None inverse transmitting signal. (Default),1: Before setting this bit"
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bitfld.long 0x8 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit. Note: In IrDA mode the BAUDM1 (UART_BAUD [29]) register must be disabled the baud equation must be Clock / (16 * (BRD + 2))." "0: IrDA Transmitter Disabled and Receiver Enabled.,1: IrDA Transmitter Enabled and Receiver Disabled"
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line.long 0xC "UART_ALTCTL,UART Alternate Control/Status Register"
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hexmask.long.byte 0xC 24.--31. 1. "ADDRMV,Address Match Value . This field contains the RS-485 address match values.. Note: This field is used for RS-485 auto address detection mode."
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bitfld.long 0xC 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length . Note: The calculation of bit number includes the START bit." "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,?,?"
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bitfld.long 0xC 18. "ABRDEN,Auto-baud Rate Detect Enable Bit. Note: This bit is cleared automatically after auto-baud detection is finished." "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled"
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rbitfld.long 0xC 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) . This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. ." "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated"
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bitfld.long 0xC 15. "ADDRDEN,RS-485 Address Detection Enable Bit. This bit is used to enable RS-485 Address Detection mode. . Note: This bit is used for RS-485 any operation mode." "0: Address detection mode Disabled,1: Address detection mode Enabled"
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bitfld.long 0xC 10. "RS485AUD,RS-485 Auto Direction Function. Note: It can be active with RS-485_AAD or RS-485_NMM operation mode." "0: RS-485 Auto Direction Operation function (AUD)..,1: RS-485 Auto Direction Operation function (AUD).."
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bitfld.long 0xC 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode. Note: It cannot be active with RS-485_NMM operation mode." "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.."
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bitfld.long 0xC 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode . Note: It cannot be active with RS-485_AAD operation mode." "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).."
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line.long 0x10 "UART_FUNCSEL,UART Function Select Register"
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bitfld.long 0x10 6. "DGE,Deglitch Enable Bit. Note 1: When this bit is set to logic 1 any pulse width less than about 150 ns will be considered a glitch and will be removed in the serial data input (RX). This bit acts only on RX line and has no effect on the transmitter.." "0: Deglitch Disabled,1: When this bit is set to logic 1"
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bitfld.long 0x10 3. "TXRXDIS,TX and RX Disable Bit. Setting this bit can disable TX and RX.. Note: The TX and RX will not disable immediately when this bit is set. The TX and RX complete current task before disable TX and RX. When TX and RX disable the TXRXACT.." "0: TX and RX Enabled,1: TX and RX Disabled"
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bitfld.long 0x10 0.--1. "FUNCSEL,Function Select" "0: UART function,1: Reserved.,?,?"
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group.long 0x3C++0xF
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line.long 0x0 "UART_BRCOMP,UART Baud Rate Compensation Register"
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bitfld.long 0x0 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).."
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hexmask.long.word 0x0 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten. These 9-bits are used to define the relative bit is compensated or not. . BRCOMP[7:0] is used to define the compensation of DAT (UART_DAT[7:0]) and BRCOM[8] is used to define PARITY (UART_DAT[8])."
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line.long 0x4 "UART_WKCTL,UART Wake-up Control Register"
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bitfld.long 0x4 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit. Note: It is suggest the function is enabled when the WKRFRTEN (UART_WKCTL[2]) is set to 1." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.."
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bitfld.long 0x4 3. "WKRS485EN,RS-485 Address Match Wake-up Enable Bit. Note: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1." "0: RS-485 Address Match (AAD mode) wake-up system..,1: RS-485 Address Match (AAD mode) wake-up system.."
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bitfld.long 0x4 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.."
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bitfld.long 0x4 1. "WKDATEN,Incoming Data Wake-up Enable Bit" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled.."
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bitfld.long 0x4 0. "WKCTSEN,nCTS Wake-up Enable Bit" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled. When the.."
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line.long 0x8 "UART_WKSTS,UART Wake-up Status Register"
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bitfld.long 0x8 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag. This bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out wake-up.. Note 1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: If WKTOUTEN"
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bitfld.long 0x8 3. "RS485WKF,RS-485 Address Match Wake-up Flag. This bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).. Note 1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit is set to.." "0: Chip stays in power-down state,1: If WKRS485EN"
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bitfld.long 0x8 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag. This bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up .. Note 1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: If WKRFRTEN"
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bitfld.long 0x8 1. "DATWKF,Incoming Data Wake-up Flag. This bit is set if chip wake-up from power-down state by data wake-up.. Note 1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.. Note 2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: If WKDATEN"
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bitfld.long 0x8 0. "CTSWKF,nCTS Wake-up Flag. This bit is set if chip wake-up from power-down state by nCTS wake-up.. Note 1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.. Note 2: This bit can be cleared by writing '1' to it." "0: Chip stays in power-down state,1: If WKCTSEN"
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line.long 0xC "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register"
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hexmask.long.word 0xC 0.--15. 1. "STCOMP,Start Bit Compensation Value. These bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from power-down mode.. Note: It is valid only when WKDATEN.."
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tree.end
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tree.end
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tree "USBD (USB Device Controller)"
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base ad:0x40060000
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group.long 0x0++0xB
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line.long 0x0 "USBD_INTEN,USB Device Interrupt Enable Register"
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bitfld.long 0x0 15. "INNAKEN,Active NAK Function and Its Status in IN Token" "0: When the device responds NAK after receiving IN..,1: IN NAK status will be updated to USBD_EPSTS.."
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bitfld.long 0x0 8. "WKEN,Wake-up Function Enable Bit. Note: If woken up by any change by VBUS state VBDETIEN must be enabled. If woken up by receiving resume signal BUSIEN must be enabled." "0: USB wake-up function Disabled,1: USB wake-up function Enabled"
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bitfld.long 0x0 4. "SOFIEN,Start of Frame Interrupt Enable Bit" "0: SOF Interrupt Disabled,1: SOF Interrupt Enabled"
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bitfld.long 0x0 3. "NEVWKIEN,USB No-event-wake-up Interrupt Enable Bit" "0: No-event-wake-up Interrupt Disabled,1: No-event-wake-up Interrupt Enabled"
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bitfld.long 0x0 2. "VBDETIEN,VBUS Detection Interrupt Enable Bit" "0: VBUS detection Interrupt Disabled,1: VBUS detection Interrupt Enabled"
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bitfld.long 0x0 1. "USBIEN,USB Event Interrupt Enable Bit" "0: USB event interrupt Disabled,1: USB event interrupt Enabled"
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bitfld.long 0x0 0. "BUSIEN,Bus Event Interrupt Enable Bit" "0: BUS event interrupt Disabled,1: BUS event interrupt Enabled"
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line.long 0x4 "USBD_INTSTS,USB Device Interrupt Event Status Register"
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bitfld.long 0x4 31. "SETUP,Setup Event Status" "0: No Setup event,1: Setup event occurred and it is cleared by.."
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bitfld.long 0x4 23. "EPEVT7,Endpoint 7's USB Event Status" "0: No event occurred in endpoint 7,1: USB event occurred on Endpoint 7 check.."
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bitfld.long 0x4 22. "EPEVT6,Endpoint 6's USB Event Status" "0: No event occurred in endpoint 6,1: USB event occurred on Endpoint 6 check.."
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bitfld.long 0x4 21. "EPEVT5,Endpoint 5's USB Event Status" "0: No event occurred in endpoint 5,1: USB event occurred on Endpoint 5 check.."
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bitfld.long 0x4 20. "EPEVT4,Endpoint 4's USB Event Status" "0: No event occurred in endpoint 4,1: USB event occurred on Endpoint 4 check.."
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bitfld.long 0x4 19. "EPEVT3,Endpoint 3's USB Event Status" "0: No event occurred in endpoint 3,1: USB event occurred on Endpoint 3 check.."
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bitfld.long 0x4 18. "EPEVT2,Endpoint 2's USB Event Status" "0: No event occurred in endpoint 2,1: USB event occurred on Endpoint 2 check.."
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bitfld.long 0x4 17. "EPEVT1,Endpoint 1's USB Event Status" "0: No event occurred in endpoint 1,1: USB event occurred on Endpoint 1 check.."
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bitfld.long 0x4 16. "EPEVT0,Endpoint 0's USB Event Status" "0: No event occurred in endpoint 0,1: USB event occurred on Endpoint 0 check.."
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bitfld.long 0x4 4. "SOFIF,Start of Frame Interrupt Status" "0: SOF event did not occur,1: SOF event occurred and it is cleared by writing.."
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bitfld.long 0x4 3. "NEVWKIF,No-event-wake-up Interrupt Status" "0: NEVWK event did not occur,1: No-event-wake-up event occurred and it is.."
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bitfld.long 0x4 2. "VBDETIF,VBUS Detection Interrupt Status" "0: There is no attached/detached event in the USB,1: There is attached/detached event in the USB bus.."
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bitfld.long 0x4 1. "USBIF,USB Event Interrupt Status. The USB event includes the SETUP Token IN Token OUT ACK ISO IN or ISO OUT events in the bus." "0: No USB event occurred,1: USB event occurred; check EPSTS0~7[2:0] to know.."
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bitfld.long 0x4 0. "BUSIF,BUS Interrupt Status. The BUS event means that there is one of the suspense or the resume function in the bus." "0: No BUS event occurred,1: Bus event occurred; check USBD_ATTR[3:0] to know.."
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line.long 0x8 "USBD_FADDR,USB Device Function Address Register"
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hexmask.long.byte 0x8 0.--6. 1. "FADDR,USB Device Function Address"
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rgroup.long 0xC++0x3
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line.long 0x0 "USBD_EPSTS,USB Device Endpoint Status Register"
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bitfld.long 0x0 29.--31. "EPSTS7,Endpoint 7 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 26.--28. "EPSTS6,Endpoint 6 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 23.--25. "EPSTS5,Endpoint 5 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 20.--22. "EPSTS4,Endpoint 4 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 17.--19. "EPSTS3,Endpoint 3 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 14.--16. "EPSTS2,Endpoint 2 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 11.--13. "EPSTS1,Endpoint 1 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 8.--10. "EPSTS0,Endpoint 0 Status. These bits are used to indicate the current status of this endpoint" "0: In ACK,1: In NAK,?,?,?,?,?,?"
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bitfld.long 0x0 7. "OV,Overrun. It indicates that the received data is more than the maximum payload number or not." "0: No overrun,1: Out Data is more than the Max Payload in MXPLD.."
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group.long 0x10++0x3
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line.long 0x0 "USBD_ATTR,USB Device Bus Status and Attribution Register"
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rbitfld.long 0x0 13. "L1RESUME,LPM L1 Resume (Read Only)" "0: Bus no LPM L1 state resume,1: LPM L1 state resume from LPM L1 state suspend"
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rbitfld.long 0x0 12. "L1SUSPEND,LPM L1 Suspend (Read Only)" "0: Bus no L1 state suspend,1: This bit is set by the hardware when LPM command.."
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bitfld.long 0x0 11. "LPMACK,LPM Token Acknowledge Enable Bit" "0: The valid LPM Token will be NYET,1: The valid LPM Token will be ACK"
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bitfld.long 0x0 10. "BYTEM,CPU Access USB SRAM Size Mode Selection" "0: Word mode: The size of the transfer from CPU to..,1: Byte mode: The size of the transfer from CPU to.."
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bitfld.long 0x0 9. "PWRDN,Power-down PHY Transceiver Low Active" "0: Power-down related circuit of PHY transceiver,1: Turn-on related circuit of PHY transceiver"
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bitfld.long 0x0 8. "DPPUEN,Pull-up Resistor on USB_DP Enable Bit" "0: Pull-up resistor in USB_D+ bus Disabled,1: Pull-up resistor in USB_D+ bus Active"
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bitfld.long 0x0 7. "USBEN,USB Controller Enable Bit" "0: USB Controller Disabled,1: USB Controller Enabled"
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bitfld.long 0x0 5. "RWAKEUP,Remote Wake-up" "0: Release the USB bus from K state,1: Force USB bus to K (USB_D+ low USB_D-: high).."
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bitfld.long 0x0 4. "PHYEN,PHY Transceiver Function Enable Bit" "0: PHY transceiver function Disabled,1: PHY transceiver function Enabled"
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rbitfld.long 0x0 3. "TOUT,Time-out Status (Read Only)" "0: No time-out,1: No Bus response more than 18 bits time("
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rbitfld.long 0x0 2. "RESUME,Resume Status (Read Only)" "0: No bus resume,1: Resume from suspend"
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rbitfld.long 0x0 1. "SUSPEND,Suspend Status (Read Only)" "0: Bus no suspend,1: Bus idle more than 3ms either cable is plugged.."
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rbitfld.long 0x0 0. "USBRST,USB Reset Status (Read Only)" "0: Bus no reset,1: Bus reset when SE0 (single-ended 0) more than.."
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rgroup.long 0x14++0x3
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line.long 0x0 "USBD_VBUSDET,USB Device VBUS Detection Register"
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bitfld.long 0x0 0. "VBUSDET,Device VBUS Detection" "0: Controller is not attached to the USB host,1: Controller is attached to the USB host"
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group.long 0x18++0x3
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line.long 0x0 "USBD_STBUFSEG,SETUP Token Buffer Segmentation Register"
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hexmask.long.byte 0x0 3.--8. 1. "STBUFSEG,SETUP Token Buffer Segmentation. It is used to indicate the offset address for the SETUP token with the USB Device SRAM starting address The effective starting address is. USBD_SRAM address + {STBUFSEG 3'b000} . Note: It is used for SETUP token.."
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rgroup.long 0x88++0x7
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line.long 0x0 "USBD_LPMATTR,USB LPM Attribution Register"
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bitfld.long 0x0 8. "LPMRWAKUP,LPM Remote Wake-up. This bit contains the bRemoteWake value received with last ACK LPM Token" "0,1"
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hexmask.long.byte 0x0 4.--7. 1. "LPMBESL,LPM Best Effort Service Latency. These bits contain the BESL value received with last ACK LPM Token"
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hexmask.long.byte 0x0 0.--3. 1. "LPMLINKSTS,LPM Link State. These bits contain the bLinkState received with last ACK LPM Token"
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line.long 0x4 "USBD_FN,USB Frame Number Register"
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hexmask.long.word 0x4 0.--10. 1. "FN,Frame Number. These bits contain the 11-bits frame number in the last received SOF packet."
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group.long 0x90++0x3
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line.long 0x0 "USBD_SE0,USB Device Drive SE0 Control Register"
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bitfld.long 0x0 0. "SE0,Drive Single Ended Zero in USB Bus. The Single Ended Zero (SE0) is when both lines (USB_D+ and USB_D-) are being pulled low." "0: Normal operation,1: Force USB PHY transceiver to drive SE0"
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group.long 0x500++0x7F
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line.long 0x0 "USBD_BUFSEG0,Endpoint 0 Buffer Segmentation Register"
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hexmask.long.byte 0x0 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x4 "USBD_MXPLD0,Endpoint 0 Maximal Payload Register"
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hexmask.long.word 0x4 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x8 "USBD_CFG0,Endpoint 0 Configuration Register"
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bitfld.long 0x8 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x8 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x8 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x8 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x8 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0xC "USBD_CFGP0,Endpoint 0 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0xC 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0xC 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x10 "USBD_BUFSEG1,Endpoint 1 Buffer Segmentation Register"
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hexmask.long.byte 0x10 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x14 "USBD_MXPLD1,Endpoint 1 Maximal Payload Register"
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hexmask.long.word 0x14 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x18 "USBD_CFG1,Endpoint 1 Configuration Register"
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bitfld.long 0x18 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x18 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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bitfld.long 0x18 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x18 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x18 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x1C "USBD_CFGP1,Endpoint 1 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x1C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x1C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x20 "USBD_BUFSEG2,Endpoint 2 Buffer Segmentation Register"
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hexmask.long.byte 0x20 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x24 "USBD_MXPLD2,Endpoint 2 Maximal Payload Register"
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hexmask.long.word 0x24 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x28 "USBD_CFG2,Endpoint 2 Configuration Register"
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bitfld.long 0x28 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x28 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x28 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x28 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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hexmask.long.byte 0x28 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x2C "USBD_CFGP2,Endpoint 2 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x2C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x2C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x30 "USBD_BUFSEG3,Endpoint 3 Buffer Segmentation Register"
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hexmask.long.byte 0x30 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x34 "USBD_MXPLD3,Endpoint 3 Maximal Payload Register"
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hexmask.long.word 0x34 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x38 "USBD_CFG3,Endpoint 3 Configuration Register"
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bitfld.long 0x38 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x38 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x38 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x38 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x38 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x3C "USBD_CFGP3,Endpoint 3 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x3C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x3C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x40 "USBD_BUFSEG4,Endpoint 4 Buffer Segmentation Register"
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hexmask.long.byte 0x40 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x44 "USBD_MXPLD4,Endpoint 4 Maximal Payload Register"
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hexmask.long.word 0x44 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x48 "USBD_CFG4,Endpoint 4 Configuration Register"
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bitfld.long 0x48 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x48 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x48 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x48 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x48 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x4C "USBD_CFGP4,Endpoint 4 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x4C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x4C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x50 "USBD_BUFSEG5,Endpoint 5 Buffer Segmentation Register"
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hexmask.long.byte 0x50 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x54 "USBD_MXPLD5,Endpoint 5 Maximal Payload Register"
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hexmask.long.word 0x54 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x58 "USBD_CFG5,Endpoint 5 Configuration Register"
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bitfld.long 0x58 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x58 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x58 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x58 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x58 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x5C "USBD_CFGP5,Endpoint 5 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x5C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x5C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x60 "USBD_BUFSEG6,Endpoint 6 Buffer Segmentation Register"
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hexmask.long.byte 0x60 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x64 "USBD_MXPLD6,Endpoint 6 Maximal Payload Register"
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hexmask.long.word 0x64 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x68 "USBD_CFG6,Endpoint 6 Configuration Register"
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bitfld.long 0x68 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x68 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x68 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x68 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x68 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x6C "USBD_CFGP6,Endpoint 6 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x6C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x6C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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line.long 0x70 "USBD_BUFSEG7,Endpoint 7 Buffer Segmentation Register"
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hexmask.long.byte 0x70 3.--8. 1. "BUFSEG,Endpoint Buffer Segmentation. It is used to indicate the offset address for each endpoint with the USB SRAM starting address. The effective starting address of the endpoint is:. USBD_SRAM address + { BUFSEG 3'b000}. Refer to the Buffer Control.."
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line.long 0x74 "USBD_MXPLD7,Endpoint 7 Maximal Payload Register"
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hexmask.long.word 0x74 0.--8. 1. "MXPLD,Maximal Payload. Define the data length which is transmitted to host (IN token) or the actual data length which is received from the host (OUT token). It also used to indicate that the endpoint is ready to be transmitted in IN token or received in.."
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line.long 0x78 "USBD_CFG7,Endpoint 7 Configuration Register"
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bitfld.long 0x78 9. "CSTALL,Clear STALL Response" "0: Disable the device to clear the STALL handshake..,1: Clear the device to response STALL handshake in.."
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bitfld.long 0x78 7. "DSQSYNC,Data Sequence Synchronization. Note: It is used to specify the DATA0 or DATA1 PID in the following IN token transaction. Hardware will toggle automatically in IN token base on this bit." "0: DATA0 PID,1: DATA1 PID"
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newline
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bitfld.long 0x78 5.--6. "STATE,Endpoint State" "0: Endpoint is Disabled,1: Out endpoint,?,?"
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bitfld.long 0x78 4. "ISOCH,Isochronous Endpoint. This bit is used to set the endpoint as Isochronous endpoint no handshake." "0: No Isochronous endpoint,1: Isochronous endpoint"
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newline
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hexmask.long.byte 0x78 0.--3. 1. "EPNUM,Endpoint Number. These bits are used to define the endpoint number of the current endpoint."
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line.long 0x7C "USBD_CFGP7,Endpoint 7 Set Stall and Clear In/Out Ready Control Register"
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bitfld.long 0x7C 1. "SSTALL,Set STALL" "0: Disable the device to response STALL,1: Set the device to respond STALL automatically"
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bitfld.long 0x7C 0. "CLRRDY,Clear Ready. When the USBD_MXPLDx register is set by user it means that the endpoint is ready to transmit or receive data. If the user wants to disable this transaction before the transaction start users can set this bit to 1 to disable it and.." "0,1"
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tree.end
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tree "WDT (Watchdog Timer)"
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base ad:0x40004000
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group.long 0x0++0x7
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line.long 0x0 "WDT_CTL,WDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect). WDT up counter will keep going no matter CPU is held by ICE or not.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled"
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rbitfld.long 0x0 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only). If user execute enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.. Note: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.."
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newline
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bitfld.long 0x0 8.--10. "TOUTSEL,WDT Time-out Interval Selection (Write Protect). These three bits select the time-out interval period after WDT starts counting.. Note: This bit is write protected. Refer to the SYS_REGLCTL register." "0: 24 * WDT_CLK,1: 26 * WDT_CLK,?,?,?,?,?,?"
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bitfld.long 0x0 7. "WDTEN,WDT Enable Bit (Write Protect). Note 1: This bit is write protected. Refer to the SYS_REGLCTL register.. Note 2: Perform enable or disable WDTEN bit needs 2 * WDT_CLK period to become active user can read SYNC (WDT_CTL[30]) to check enabe/disable.." "0: Set WDT counter stop and internal up counter..,1: This bit is write protected"
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newline
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bitfld.long 0x0 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect). If this bit is enabled when WDT time-out event occurs the IF (WDT_CTL[3]) will be set to 1 and WDT time-out interrupt signal is generated and inform to CPU. . Note: This bit is write protected." "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled"
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bitfld.long 0x0 5. "WKF,WDT Time-out Wake-up Flag (Write Protect). This bit indicates the WDT time-out event has triggered chip wake-up or not.. Note: This bit is cleared by writing 1 to it." "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode when.."
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newline
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bitfld.long 0x0 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect). If this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will generate a.." "0: Trigger wake-up event function Disabled if WDT..,1: This bit is write protected"
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bitfld.long 0x0 3. "IF,WDT Time-out Interrupt Flag. This bit will be set to 1 while WDT up counter value reaches the selected WDT time-out interval.. Note: This bit is cleared by writing 1 to it." "0: WDT time-out interrupt event did not occur,1: WDT time-out interrupt event occurred"
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newline
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bitfld.long 0x0 2. "RSTF,WDT Time-out Reset Flag. This bit indicates the system has been reset by WDT time-out reset system event or not.. Note: This bit is cleared by writing 1 to it." "0: WDT time-out reset system event did not occur,1: WDT time-out reset system event has been occurred"
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bitfld.long 0x0 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect). Setting this bit will enable the WDT time-out reset system function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.. Note: This bit is write.." "0: WDT time-out reset system function Disabled,1: WDT time-out reset system function Enabled"
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line.long 0x4 "WDT_ALTCTL,WDT Alternative Control Register"
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bitfld.long 0x4 0.--1. "RSTDSEL,WDT Reset Delay Period Selection (Write Protect). When WDT time-out event happened user has a time named WDT Reset Delay Period to execute WDT counter reset to prevent WDT time-out reset system occurred. User can select a suitable setting of.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: This bit is write protected,2: This register will be reset to 0 if WDT time-out..,?"
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wgroup.long 0x8++0x3
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line.long 0x0 "WDT_RSTCNT,WDT Reset Counter Register"
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hexmask.long 0x0 0.--31. 1. "RSTCNT,WDT Reset Counter Register. Writing 0x00005AA5 to this field will reset the internal 18-bit WDT up counter value to 0.. Note: Perform RSTCNT to reset counter needs 2 * WDT_CLK period to become active."
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tree.end
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tree "WWDT (Window Watchdog Timer)"
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base ad:0x40004100
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wgroup.long 0x0++0x3
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line.long 0x0 "WWDT_RLDCNT,WWDT Reload Counter Register"
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hexmask.long 0x0 0.--31. 1. "RLDCNT,WWDT Reload Counter Register. Writing only 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.. Note 1: User can only execute the reload WWDT counter value command when current CNTDAT (WWDT_CNT[5:0]) is between 1 and CMPDAT.."
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group.long 0x4++0x7
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line.long 0x0 "WWDT_CTL,WWDT Control Register"
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bitfld.long 0x0 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit. The WWDT down counter will keep counting no matter CPU is held by ICE or not." "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled"
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hexmask.long.byte 0x0 16.--21. 1. "CMPDAT,WWDT Window Compare Value. Set this field to adjust the valid reload window interval when WWDTIF (WWDT_STATUS[0]) is generated.. Note: User can only write WWDT_RLDCNT register to reload WWDT counter value when current CNTDAT (WWDT_CNT[5:0]) is.."
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newline
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hexmask.long.byte 0x0 8.--11. 1. "PSCSEL,WWDT Counter Prescale Period Selection"
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bitfld.long 0x0 1. "INTEN,WWDT Interrupt Enable Bit. If this bit is enabled when WWDTIF (WWDT_STATUS[0]) is set to 1 the WWDT counter compare match interrupt signal is generated and inform to CPU." "0: WWDT counter compare match interrupt disabled,1: WWDT counter compare match interrupt enabled"
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newline
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bitfld.long 0x0 0. "WWDTEN,WWDT Enable Bit. Set this bit to start WWDT counter counting." "0: WWDT counter is stopped,1: WWDT counter is starting counting"
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line.long 0x4 "WWDT_STATUS,WWDT Status Register"
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bitfld.long 0x4 1. "WWDTRF,WWDT Timer-out Reset System Flag. If this bit is set to 1 it indicates that system has been reset by WWDT counter time-out reset system event.. Note: This bit is cleared by writing 1 to it." "0: WWDT time-out reset system event did not occur,1: WWDT time-out reset system event occurred"
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bitfld.long 0x4 0. "WWDTIF,WWDT Compare Match Interrupt Flag. This bit indicates that current CNTDAT (WWDT_CNT[5:0]) matches the CMPDAT (WWDT_CTL[21:16]).. Note: This bit is cleared by writing 1 to it." "0: No effect,1: WWDT CNTDAT matches the CMPDAT"
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rgroup.long 0xC++0x3
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line.long 0x0 "WWDT_CNT,WWDT Counter Value Register"
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hexmask.long.byte 0x0 0.--5. 1. "CNTDAT,WWDT Counter Value. CNTDAT will be updated continuously."
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tree.end
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AUTOINDENT.OFF
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